Board-level fan-out package structure with high heat dissipation performance and preparation method thereof

Abstract

The present invention discloses a board-level fan-out package structure with high heat dissipation and a preparation method thereof. Among them, the board-level fan-out package structure with high heat dissipation includes: a carrier board, comprising a first encapsulation layer and a heat conduction frame encapsulated in the first encapsulation layer, the first encapsulation layer having a first side surface and a second side surface, and one side surface of the heat conduction frame along its thickness direction being adjacent to the first side surface of the first encapsulation layer; a heat dissipation adhesive, attached to the first side surface; a chip, attached to the heat dissipation adhesive, and the front surface of the chip facing away from the carrier board; an encapsulation structure, located on the heat dissipation adhesive, and the chip being encapsulated in the encapsulation structure. In the present invention, within the size range of several hundred millimeters, a permanent heat dissipation adhesive and a high-strength carrier board can be simultaneously arranged on the back surfaces of multiple chips, greatly improving the warping problem that occurs during chip encapsulation. After the chip is encapsulated and cut, the heat dissipation adhesive and the high-strength carrier board can be used as a heat dissipation structure, realizing both high-efficiency heat dissipation of the chip and reuse of the carrier board.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic packaging, and particularly relates to a board-level fan-out packaging structure with high heat dissipation and a preparation method thereof. Background Art

[0002] High-density chip packaging has received extensive attention in the industry. In recent years, great progress has been made in large-board-level fan-out packaging technology. The large-board-level fan-out packaging has a smaller area, without a substrate and an interposer; the packaged chip has a thinner thickness and a higher pin density; more importantly, the chips of this process have a lower thermal impedance and better electrical performance, and can better meet the requirements of the terminal market for chip miniaturization and high performance.

[0003] With the development of large-board-level fan-out packaging technology, smaller-sized packaging structures have emerged continuously. Chips mainly dissipate heat through a large-area substrate. However, the chips of board-level fan-out packaging do not have a substrate, and the packaging size is smaller, resulting in a smaller heat dissipation surface area of the chips. This requires that the heat conductivity of the packaged chips be sufficiently good. At present, the main methods to transfer the heat of chips to the outside of the packaging more quickly are to use materials with higher thermal conductivity and optimize the packaging structure.

[0004] With the development of large-board-level fan-out packaging technology, the packaging structure has become thinner and thinner. After the packaging structure becomes thinner, the rigidity of the packaging structure is significantly reduced, and the difference in the coefficient of thermal expansion (CTE) of the materials in the packaging body is large, making it easier to deform, resulting in a significant increase in warping, which will affect the yield of chip packaging. To reduce packaging warping, on the one hand, it is manifested in the improvement of material properties, and on the other hand, vertical carriers can be used to avoid contacting the substrate and other ways to slow down the warping problem. For example, the Manz device uses a horizontal transfer method with a double-roller conveying stabilizer to slow down the warping problem. Summary of the Invention

[0005] One object of the present invention is to provide a board-level fan-out packaging structure with high heat dissipation, which can reduce the warping problem and improve the chip heat dissipation efficiency.

[0006] Another object of the present invention is to provide a preparation method of a board-level fan-out packaging structure with high heat dissipation, which can improve the warping problem that occurs during chip packaging, and achieve high-efficiency heat dissipation of the chip and reuse of the carrier board.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] On the one hand, a board-level fan-out packaging structure with high heat dissipation is provided, including:

[0009] A carrier board, the carrier board includes a first encapsulation layer and a heat-conducting frame encapsulated within the first encapsulation layer, the first encapsulation layer has a first side and a second side, and one side of the heat-conducting frame in its thickness direction is adjacent to the first side of the first encapsulation layer;

[0010] A heat-dissipating adhesive, the heat-dissipating adhesive is pasted on the first side;

[0011] A chip, the chip is pasted on the heat-dissipating adhesive, and the front side of the chip faces away from the carrier board;

[0012] An encapsulation structure, the encapsulation structure is located on the heat-dissipating adhesive, and the chip is encapsulated within the encapsulation structure.

[0013] As a preferred solution of a board-level fan-out encapsulation structure with high heat dissipation, the heat-conducting frame is made of one of the materials Cu, Al, iron, or graphene.

[0014] As a preferred solution of a board-level fan-out encapsulation structure with high heat dissipation, the encapsulation structure includes:

[0015] A second encapsulation layer, the chip is encapsulated within the second encapsulation layer;

[0016] A transmission layer and a redistribution layer, located on the side of the second encapsulation layer away from the carrier board, one side of the transmission layer is electrically connected to the I / O interface of the chip, and the other side is electrically connected to the redistribution layer through copper pillars, and the redistribution layer has a pad area and a non-pad area;

[0017] A solder mask layer, the solder mask layer is located on the side of the second encapsulation layer away from the carrier board and covers the non-pad area of the redistribution layer and the area of the transmission layer exposed outside the redistribution layer;

[0018] Metal bumps, the metal bumps are welded to the pad area of the wiring layer.

[0019] As a preferred solution of a board-level fan-out encapsulation structure with high heat dissipation, the transmission layer includes a dielectric layer pasted on the second encapsulation layer and a seed layer attached to the dielectric layer, the dielectric layer has a through hole in its thickness direction for exposing the I / O interface of the chip, and the seed layer extends into the through hole to be electrically connected to the I / O interface.

[0020] On the other hand, a manufacturing method of a board-level fan-out encapsulation structure with high heat dissipation is provided, including the following steps:

[0021] S10. Provide a heat-conducting frame, perform an encapsulation process on the heat-conducting frame with a molding compound to form a first encapsulation layer, and make one side of the heat-conducting frame adjacent to the first side of the first encapsulation layer to obtain a carrier board;

[0022] S20. Provide heat dissipation glue and several chips, make the front side of the chip face away from the side of the carrier board, and attach the chip to the side of the carrier board adjacent to the heat conduction frame through the heat dissipation glue;

[0023] S30. Perform encapsulation processing on the chip, and lead out the I / O interface of the chip and electrically connect it to a metal bump.

[0024] As a preferred solution of the board-level fan-out package structure with high heat dissipation, step S30 specifically includes:

[0025] S31. Perform encapsulation processing on the chip with a molding compound to form a second encapsulation layer;

[0026] S32. Fabricate a transmission layer on the second encapsulation layer, and electrically connect the I / O interface of the chip to the transmission layer;

[0027] S33. Fabricate a redistribution layer on the transmission layer;

[0028] S34. Fabricate a solder mask layer on the side of the second encapsulation layer away from the carrier board, make the solder mask layer cover the non-pad area of the wiring layer and make the pad area of the redistribution layer expose outside the solder mask layer;

[0029] S35. Provide metal bumps, and implant the metal bumps into the pad area.

[0030] As a preferred solution of the board-level fan-out package structure with high heat dissipation, step S32 specifically includes:

[0031] S32a. Provide a dielectric layer, and attach the dielectric layer to the second encapsulation layer;

[0032] S32b. Perform laser drilling on the dielectric layer, so that through holes are formed in the dielectric layer along its thickness direction, so that the I / O interface of the chip is exposed;

[0033] S32c. Form a seed layer in the dielectric layer and the through holes by vacuum sputtering, and the dielectric layer and the seed layer form the transmission layer.

[0034] As a preferred solution of the board-level fan-out package structure with high heat dissipation, step S33 specifically includes:

[0035] S33a. Provide a photosensitive film, and attach the photosensitive film to the transmission layer;

[0036] S33b. Through exposure and development processing, form a pattern on the photosensitive film that exposes the seed layer outside the photosensitive film;

[0037] S33c. Electroplate the pattern and the vias, form copper pillars in the vias, and form the redistribution layer in the pattern. The redistribution layer is electrically connected to the I / O interface of the chip through the copper pillars;

[0038] S33d. Remove the remaining photosensitive film.

[0039] As a preferred solution of the board-level fan-out package structure with high heat dissipation, step S34 specifically includes:

[0040] S34a. Etch the seed layer exposed after the photosensitive film is removed to remove the seed layer;

[0041] S34b. Coat a photosensitive ink on the dielectric layer exposed after the seed layer is removed, and form a solder mask after curing, so that the solder mask covers the non-pad area of the redistribution layer and exposes the pad area of the redistribution layer outside the solder mask.

[0042] As a preferred solution of the board-level fan-out package structure with high heat dissipation, the components of the heat dissipation adhesive include graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, and alumina.

[0043] Advantages of the present invention: In the present invention, the heat-conducting frame is encapsulated in the first encapsulation layer to form a carrier board, the chip is attached to the carrier board through the heat dissipation adhesive and encapsulated, and the carrier board plays a supporting role in the encapsulation of the chip. After the chip is encapsulated and diced, the heat generated during the operation of the chip is transferred to the heat-conducting frame through the heat dissipation adhesive, and the heat of the chip is exported through the heat-conducting frame, improving the heat dissipation efficiency of the chip. During the chip encapsulation process, there is no need to remove the carrier board by debonding, and the high strength of the heat-conducting frame and the characteristic that the thermal expansion coefficients of the first encapsulation layer and the second encapsulation layer match can effectively improve the warping problem that occurs during chip encapsulation. After dicing, the carrier board can be used as the heat dissipation structure of the chip, realizing both high-efficiency heat dissipation of the chip and reuse of the carrier board. Description of the Drawings

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments of the present invention. Obviously, the following described drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0045] Figure 1 is a top view of the carrier board described in the embodiment of the present invention.

[0046] Figure 2 is a cross-sectional view of the carrier board described in the embodiment of the present invention.

[0047] Figure 3 It is a cross-sectional view of the heat dissipation adhesive sticker of the embodiment of the present invention on the carrier board.

[0048] Figure 4 It is a cross-sectional view of the chip of the embodiment of the present invention adhered to the carrier board through the heat dissipation adhesive.

[0049] Figure 5 It is a cross-sectional view of the chip package of the embodiment of the present invention on the carrier board.

[0050] Figure 6 It is a cross-sectional view of the intermediate product after grinding the second encapsulation layer of the embodiment of the present invention.

[0051] Figure 7 It is a cross-sectional view of the intermediate product after the dielectric layer is attached to the second encapsulation layer of the embodiment of the present invention.

[0052] Figure 8 It is a cross-sectional view of the intermediate product after laser drilling of the dielectric layer of the embodiment of the present invention.

[0053] Figure 9 It is a cross-sectional view of the intermediate product after magnetron sputtering of the titanium metal layer on the dielectric layer of the embodiment of the present invention.

[0054] Figure 10 It is a cross-sectional view of the intermediate product after magnetron sputtering of the copper metal layer on the titanium metal layer of the embodiment of the present invention.

[0055] Figure 11 It is a cross-sectional view of the intermediate product after the photosensitive film is attached to the seed layer of the embodiment of the present invention.

[0056] Figure 12 It is a cross-sectional view of the intermediate product after exposure and development of the photosensitive film of the embodiment of the present invention.

[0057] Figure 13 It is a cross-sectional view of the intermediate product after graphic electroplating treatment of the embodiment of the present invention.

[0058] Figure 14 It is a cross-sectional view of the intermediate product after removing the residual photosensitive film of the embodiment of the present invention.

[0059] Figure 15 It is a cross-sectional view of the intermediate product after etching of the seed layer of the embodiment of the present invention.

[0060] Figure 16 It is a cross-sectional view of the product after applying photosensitive ink and implanting metal balls of the embodiment of the present invention.

[0061] In the figure:

[0062] 11. The first encapsulation layer; 12. The heat conduction frame;

[0063] 2. Thermal paste;

[0064] 3. Chip;

[0065] 4. Second encapsulation layer;

[0066] 5. Transmission layer; 51. Dielectric layer; 52. Titanium metal layer; 53. Copper metal layer;

[0067] 6. Redistribution layer;

[0068] 7. Solder mask layer;

[0069] 8. Metal bump;

[0070] 9. Photosensitive film. Detailed implementation manners

[0071] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and through specific implementation manners.

[0072] Among them, the accompanying drawings are only for illustrative purposes, showing only schematic diagrams, rather than physical diagrams, and should not be construed as a limitation of this patent; in order to better illustrate the embodiments of the present invention, some components in the accompanying drawings will be omitted, enlarged or reduced, and do not represent the dimensions of actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0073] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as a limitation of this patent. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0074] In the description of the present invention, unless otherwise clearly specified and limited, if terms such as "connection" are used to indicate the connection relationship between components, this term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0075] Unless otherwise specified, all raw materials used in the preparation method of the board-level fan-out packaging structure with high heat dissipation of the present invention can be commercially available or prepared according to the conventional methods in the technical field.

[0076] As Figure 16 shown, an embodiment of the present invention provides a board-level fan-out packaging structure with high heat dissipation, including:

[0077] A carrier board, the carrier board includes a first encapsulation layer 11 and a heat conduction frame 12 encapsulated in the first encapsulation layer 11. The first encapsulation layer 11 has a first side surface and a second side surface. One side surface of the heat conduction frame 12 along its thickness direction is adjacent to the first side surface of the first encapsulation layer 11;

[0078] A heat dissipation adhesive 2, the heat dissipation adhesive 2 is attached to the first side surface;

[0079] A chip 3, the chip 3 is attached to the heat dissipation adhesive 2, and the front surface of the chip 3 faces away from the carrier board;

[0080] A packaging structure, the packaging structure is located on the heat dissipation adhesive 2, and the chip 3 is encapsulated in the packaging structure.

[0081] In this embodiment, unless otherwise specified, the term "cover" means wrapping the non-contact outer surface of a certain component with other components. For example, the heat dissipation adhesive 2 covers the heat conduction frame 12, which means that the heat dissipation adhesive 2 wraps the non-contact outer surface of the heat conduction frame 12 with the first encapsulation layer 11.

[0082] Among them, one side surface of the heat conduction frame 12 along its thickness direction is adjacent to the first side surface of the first encapsulation layer 11, which means that one side surface of the heat conduction frame 12 along its thickness direction is exposed on the first side surface of the first encapsulation layer 11, or it can be located inside the first encapsulation layer 11, that is, the heat conduction frame 12 is not in direct contact with the heat dissipation adhesive 2.

[0083] Among them, the front surface of the chip 3 refers to the side with I / O interfaces.

[0084] In this embodiment, the heat-conducting frame 12 is encapsulated within the first encapsulation layer 11 to form a carrier board. The chip 3 is attached to the carrier board through the heat-dissipating adhesive 2 and then encapsulated. The carrier board plays a supporting role in the encapsulation of the chip 3. After the chip 3 is encapsulated and diced, the heat generated during the operation of the chip 3 is transferred to the heat-conducting frame 12 through the heat-dissipating adhesive 2, and the heat of the chip 3 is exported through the heat-conducting frame 12, improving the heat dissipation efficiency of the chip 3. In this embodiment, there is no need to remove the bonding to remove the carrier board during the chip 3 encapsulation process, and the high strength of the heat-conducting frame 12 and the characteristic that the thermal expansion coefficients of the first encapsulation layer 11 and the second encapsulation layer 4 match can effectively improve the warping problem that occurs during the chip 3 encapsulation. After dicing, it serves as the heat dissipation structure of the chip 3, realizing both the high-efficiency heat dissipation of the chip 3 and the reuse of the carrier board.

[0085] Optionally, the heat-conducting frame 12 is made of one of the materials Cu, Al, iron, or graphene, and has good heat dissipation effect and high strength.

[0086] In this embodiment, the material of the heat-conducting frame 12 includes but is not limited to Cu, Al, iron, or graphene, and any other material with high strength and high heat dissipation is applicable.

[0087] The heat-conducting frame 12 is composed of several sub-frames, and the sub-frame is any one of the shapes of cross-shaped, diamond-shaped, star-shaped, or square-shaped. Among them, the sub-frame includes but is not limited to the cross-shaped, diamond-shaped, star-shaped, or square-shaped structure. As Figure 2 shown, the heat-conducting frame 12 is composed of four star-shaped frames, which can improve the strength of the heat-conducting frame 12 and the connection stability with the first encapsulation layer 11.

[0088] Preferably, the thickness of the carrier board is 0.5 - 0.8 mm, and the specific thickness can be designed according to the actual situation, which can enable the heat of the heat-conducting frame 12 to be quickly transferred out through the first encapsulation layer 11 while ensuring the stability of the chip encapsulation structure.

[0089] Furthermore, the encapsulation structure includes:

[0090] A second encapsulation layer 4, within which the chip 3 is encapsulated;

[0091] A transmission layer 5 and a redistribution layer 6, located on the side of the second encapsulation layer 4 away from the carrier board. One side of the transmission layer 5 is electrically connected to the I / O interface of the chip, and the other side is electrically connected to the redistribution layer 6 through copper pillars. The redistribution layer 6 has a pad area and a non-pad area;

[0092] A solder mask layer 7, located on the side of the second encapsulation layer 4 away from the carrier board and covering the non-pad area of the redistribution layer 6 and the area where the transmission layer 5 is exposed outside the redistribution layer 6;

[0093] Metal bump 8, and the metal bump 8 is welded to the pad area of the redistribution layer 6.

[0094] Wherein, the thickness of the chip 3 is less than the thickness of the second encapsulation layer 4, and the I / O interface of the chip 3 can be exposed subsequently by laser drilling or other means.

[0095] In this embodiment, the chip 3 is encapsulated and fixed on the carrier board through the second encapsulation layer 4, and then the I / O interface of the chip 3 is electrically led out through the transmission layer 5 and the redistribution layer 6 and welded to the metal bump 8.

[0096] In this embodiment, the materials of the first encapsulation layer 11 and the second encapsulation layer 4 can be exactly the same, and the thermal expansion coefficients of the two are exactly matched to further reduce the warping problem.

[0097] In this embodiment, the solder mask layer 7 is a photosensitive ink layer. Using photosensitive ink as the solder mask layer 7 can not only protect the transmission layer 5 and the redistribution layer 6, but also remove part of the seed layer through exposure, development, and etching, simplifying the process.

[0098] Optionally, the metal bump 8 is a tin solder, a silver solder, or a gold-tin alloy solder. The metal bump 8 in this embodiment is a metal ball structure, and the metal ball is welded and implanted in the pad area to realize the electrical lead-out of the redistribution layer 6.

[0099] Further, the transmission layer 5 includes a dielectric layer 51 attached to the second encapsulation layer 4 and a seed layer attached to the dielectric layer 51. The dielectric layer 51 has a through hole in its thickness direction for exposing the I / O interface of the chip 3, and the seed layer extends into the through hole and is electrically connected to the I / O interface. The dielectric layer 51 is made of ABF (Ajinomoto Build-up Film) or PP (Polypropylene) material and is attached to the second encapsulation layer 4 to play an insulating role. In subsequent steps of this embodiment, a laser drilling method can be used to form a through hole for exposing the I / O interface, and copper is plated in the through hole to form a copper pillar, so that the electrical signal of the chip 3 is connected to the redistribution layer 6 through the copper pillar.

[0100] Further, the seed layer includes a titanium metal layer 52 on the side of the second encapsulation layer 4 away from the carrier board and a copper metal layer 53 on the titanium metal layer 52. Among them, the titanium metal layer 52 has high adhesion, excellent conductivity, and uniform thickness, and the copper metal layer 53 can be stably attached to the second encapsulation layer 4 through the titanium metal layer 52.

[0101] Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer 52, copper metal layer 53), and can also be a single-layer or a structure with more than two layers. The material of the seed layer is not limited to the laminated combination of two single metal materials, and can also be a single metal material or an alloy material, as long as the redistribution layer can be stably attached to the encapsulation structure, which will not be elaborated here.

[0102] Optionally, the materials of the first encapsulation layer 11 and the second encapsulation layer 4 include any one of polyimide, silica gel, and EMC (Epoxy Molding Compound). In this embodiment, EMC is preferably used, that is, the encapsulation layer 4 is an epoxy resin encapsulation layer, which can stably attach the chip 3 to the carrier board and play a role in protecting the chip 3.

[0103] As Figures 1 to 16 shown, the embodiment of the present invention also provides a preparation method for a board-level fan-out encapsulation structure with high heat dissipation performance, including the following steps:

[0104] S10. Provide a heat-conducting frame 12, and perform an encapsulation process on the heat-conducting frame 12 with a molding compound to form a first encapsulation layer 11 with the molding compound, and make one side of the heat-conducting frame 12 adjacent to the first side of the first encapsulation layer 11 to obtain a carrier board, as Figure 1 and Figure 2 shown;

[0105] S20. Provide a heat-dissipating adhesive 2 and a plurality of chips 3, make the front side of the chip 3 face away from the carrier board, and attach the chip 3 to the side of the carrier board adjacent to the heat-conducting frame 12 through the heat-dissipating adhesive 2, as Figure 3 and Figure 4 shown;

[0106] S30. Perform an encapsulation process on the chip 3, and lead out the I / O interface of the chip 3 to be electrically connected to the metal bump 8, as Figures 5 to 16 shown.

[0107] In step S10, after the molding compound encapsulates and cures the heat-conducting frame 12 to form the first encapsulation layer 11, as Figure 5 shown, it is also necessary to perform a grinding and thinning process on at least one side of the first encapsulation layer 11 in the thickness direction to make its surface flat and make one side of the heat-conducting frame 12 adjacent to one side of the first encapsulation layer 11 ( Figure 6 ), so as to facilitate the attachment of the heat-dissipating adhesive 2. Heat can be dissipated between the heat-dissipating adhesive 2 and the heat-conducting frame 12 through the molding compound or by direct contact.

[0108] In this embodiment, a carrier board is obtained by encapsulating the heat-conducting frame 12 with a molding compound, and the chip 3 is attached to the carrier board through a heat-conducting adhesive 2. The heat-conducting frame 12 has high strength and can support the encapsulation of the chip 3. Also, since the molding compound of the heat-conducting frame 12 is the same as that of the chip 3, the thermal expansion coefficients of the two are perfectly matched. Therefore, the generation of warping can be effectively reduced. After cutting, the carrier board also serves as the heat-dissipating structure of the chip, achieving both high-efficiency heat dissipation and the reuse of the carrier board.

[0109] Further, step S30 in this embodiment specifically includes:

[0110] S31. Perform encapsulation processing on the chip 3 with a molding compound so that the molding compound forms a second encapsulation layer 4. Specifically, through grinding treatment on the second encapsulation layer 4, the surface of the second encapsulation layer 4 can be kept flat. In this embodiment, the thickness of the second encapsulation layer 4 after grinding is greater than the thickness of the chip 3.

[0111] S32. Fabricate a transmission layer 5 on the second encapsulation layer 4 to electrically connect the I / O interface of the chip 3 to the transmission layer 5.

[0112] S33. Fabricate a redistribution layer 6 on the transmission layer 5.

[0113] S34. Fabricate a solder mask layer 7 on the side of the second encapsulation layer 4 away from the carrier board so that the solder mask layer 7 covers the non-pad area of the redistribution layer 6 and exposes the pad area of the redistribution layer 6 outside the solder mask layer 7.

[0114] S35. Provide metal bumps 8 and implant the metal bumps 8 into the pad area.

[0115] In this embodiment, the molding compound can be liquid, solid, or sheet-shaped.

[0116] Even further, step S32 specifically includes:

[0117] S32a. Provide a dielectric layer 51 and attach the dielectric layer 51 to the second encapsulation layer 4 to achieve insulation treatment of the second encapsulation layer 4 (as Figure 7 shown).

[0118] S32b. Perform laser drilling treatment (UV laser) on the dielectric layer 51 to form through-holes in the dielectric layer 51 along its thickness direction (as Figure 8 shown) so that the I / O interface of the chip 3 is exposed, facilitating subsequent circuit connection.

[0119] S32c. Form a seed layer on the dielectric layer 51 and inside the through-holes through vacuum sputtering. The dielectric layer 51 and the seed layer constitute the transmission layer 5.

[0120] Specifically, first, the intermediate product obtained in step S32b is heated in a high-vacuum state. After the moisture and contaminants on the intermediate product are removed, a titanium metal layer 52 with high adhesion, excellent electrical conductivity, and uniform thickness is then prepared by magnetron sputtering (as shown in Figure 9 ), and finally, a copper metal layer 53 is prepared by magnetron sputtering (as shown in Figure 10 ). The titanium metal layer 52 and the copper metal layer 53 form the seed layer.

[0121] Furthermore, step S33 specifically includes:

[0122] S33a: Provide a photosensitive film 9 (as shown in Figure 11 ), and attach the photosensitive film 9 to the transmission layer 5; specifically, attach the photosensitive film 9 to the seed layer.

[0123] S33b: Through exposure and development processes, form a pattern on the photosensitive film 9 that exposes the seed layer outside the photosensitive film 9 (as shown in Figure 12 ).

[0124] S33c: Electroplate the pattern and the through holes. Form copper pillars in the through holes and form the redistribution layer 6 in the pattern. The redistribution layer 6 is electrically connected to the I / O interface of the chip 3 through the copper pillars (as shown in Figure 13 ).

[0125] S33d: Remove the remaining photosensitive film 9 (as shown in Figure 14 ).

[0126] Among them, according to actual needs, the redistribution layer 6 can be designed as one layer, two layers, three layers, or even more layers.

[0127] Furthermore, step S34 specifically includes:

[0128] S34a: As shown in Figure 15 , etch the seed layer exposed after the photosensitive film 9 is removed to remove the seed layer.

[0129] S34b: As shown in Figure 16 , coat a photosensitive ink on the dielectric layer 51 exposed after the seed layer is removed, and after curing, form a solder mask layer 7 to make the solder mask layer 7 cover the non-pad area of the redistribution layer 6 and expose the pad area of the redistribution layer 6 outside the solder mask layer 7.

[0130] In this embodiment, the heat dissipation adhesive 2 is a permanent heat dissipation adhesive, and its components include graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, and alumina.

[0131] After implanting metal balls in the pad area of the redistribution layer 6, the production of the plastic package is completed ( Figure 16 ), and the plastic package is cut into individual chip packages to realize the preparation of a board-level fan-out package structure with high heat dissipation.

[0132] In the present invention, in the dimension range of several hundred millimeters, a permanent heat dissipation adhesive 2 and a high-strength carrier plate can be simultaneously arranged on the back surfaces of multiple chips, greatly improving the warping problem that occurs during the packaging of the chip 3. After the chip 3 is packaged and cut, the heat dissipation adhesive 2 and the high-strength carrier plate can be used as a heat dissipation structure, realizing both the high-efficiency heat dissipation of the chip 3 and the reuse of the carrier plate.

[0133] The above embodiments are only used to illustrate the detailed method of the present invention. The present invention is not limited to the above detailed method, that is, it does not mean that the present invention must rely on the above detailed method to be implemented. Those skilled in the art should understand that any improvement to the present invention, the equivalent substitution of each raw material of the product of the present invention, the addition of auxiliary components, the selection of specific methods, etc. all fall within the protection scope and the disclosure scope of the present invention.

Claims

1. A board-level fan-out package structure with high heat dissipation, characterized in that, it includes: A carrier board, the carrier board includes a first encapsulation layer and a heat-conducting frame encapsulated in the first encapsulation layer. The first encapsulation layer has a first side and a second side. One side of the heat-conducting frame along its thickness direction is adjacent to the first side of the first encapsulation layer. The heat-conducting frame is composed of several sub-frames, and the sub-frame is any one of the shapes of cross-shaped, diamond-shaped, cross-in-square-shaped or square-in-square-shaped; the heat-conducting frame is made of one material of Cu, Al, iron or graphene; Thermal paste, the thermal paste is pasted on the first side and is in direct contact with the heat-conducting frame; A chip, the chip is pasted on the thermal paste, and the front side of the chip faces away from the carrier board; An encapsulation structure, the encapsulation structure includes: A second encapsulation layer, the chip is encapsulated in the second encapsulation layer; A transmission layer and a redistribution layer, located on the side of the second encapsulation layer away from the carrier board. One side of the transmission layer is electrically connected to the I / O interface of the chip, and the other side is electrically connected to the redistribution layer through copper pillars. The redistribution layer has a pad area and a non-pad area; A solder mask layer, the solder mask layer is located on the side of the second encapsulation layer away from the carrier board and covers the non-pad area of the redistribution layer and the area where the transmission layer is exposed outside the redistribution layer; Metal bumps, the metal bumps are welded to the pad area of the wiring layer; The thermal expansion coefficients of the first encapsulation layer and the second encapsulation layer are completely matched.

2. The board-level fan-out package structure with high heat dissipation according to claim 1, characterized in that, The transmission layer includes a dielectric layer pasted on the second encapsulation layer and a seed layer attached to the dielectric layer. The dielectric layer has a through hole along its thickness direction for exposing the I / O interface of the chip, and the seed layer extends into the through hole to be electrically connected to the I / O interface.

3. A preparation method of a board-level fan-out package structure with high heat dissipation, characterized in that, it includes the following steps: S10. Provide a heat-conducting frame, perform an encapsulation treatment on the heat-conducting frame with a molding compound to form a first encapsulation layer, and make one side of the heat-conducting frame adjacent to the first side of the first encapsulation layer to obtain a carrier board; S20. Provide thermal paste and several chips, make the front side of the chip face away from the carrier board, paste the chip on the side of the carrier board adjacent to the heat-conducting frame through the thermal paste, and make the thermal paste in direct contact with the heat-conducting frame; S30. Perform an encapsulation treatment on the chip, and lead out the I / O interface of the chip to be electrically connected to the metal bumps to obtain the board-level fan-out package structure with high heat dissipation according to claim 1 or 2.

4. The preparation method of the board-level fan-out package structure with high heat dissipation according to claim 3, characterized in that, Step S30 specifically includes: S31. Perform an encapsulation treatment on the chip with a molding compound to form a second encapsulation layer; S32. Fabricate a transmission layer on the second encapsulation layer to electrically connect the I / O interface of the chip to the transmission layer; S33. Fabricate a redistribution layer on the said transmission layer; S34. Fabricate a solder mask layer on the side of the second encapsulation layer away from the carrier board, such that the solder mask layer covers the non-pad areas of the wiring layer and exposes the pad areas of the redistribution layer outside the solder mask layer; S35. Provide metal bumps and implant the metal bumps into the pad areas.

5. The preparation method of the board-level fan-out package structure with high heat dissipation according to claim 4, characterized in that, step S32 specifically includes: S32a. Provide a dielectric layer and attach the dielectric layer to the second encapsulation layer; S32b. Perform laser drilling on the position of the dielectric layer opposite to the I / O interface of the chip, so that through holes are formed in the dielectric layer along its thickness direction; S32c. Form a seed layer in the dielectric layer and the through holes by vacuum sputtering, and the dielectric layer and the seed layer constitute the transmission layer.

6. The preparation method of the board-level fan-out package structure with high heat dissipation according to claim 5, characterized in that, step S33 specifically includes: S33a. Provide a photosensitive film and attach the photosensitive film to the transmission layer; S33b. Through exposure and development processing, form a pattern on the photosensitive film that exposes the seed layer outside the photosensitive film; S33c. Perform electroplating on the pattern and the through holes, form copper pillars in the through holes, and form the redistribution layer in the pattern, and the redistribution layer is electrically connected to the I / O interface of the chip through the copper pillars; S33d. Remove the remaining photosensitive film.

7. The preparation method of the board-level fan-out package structure with high heat dissipation according to claim 6, characterized in that, step S34 specifically includes: S34a. Etch the seed layer exposed after the photosensitive film is removed to remove the seed layer; S34b. Coat photosensitive ink on the dielectric layer exposed after the seed layer is removed, and form a solder mask layer after curing, such that the solder mask layer covers the non-pad areas of the redistribution layer and exposes the pad areas of the redistribution layer outside the solder mask layer.

8. The preparation method of the board-level fan-out package structure with high heat dissipation according to claim 3, characterized in that, the components of the heat dissipation glue include graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, and alumina.

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