Semiconductor device structure and method of forming the same

Abstract

A semiconductor device structure and a method of forming the same are provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protective cap over a first portion of the first conductive line. The first protective cap and the first conductive line are formed of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protective cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protective cap. The method includes forming a via structure and a second conductive line over the first conductive line. The via structure is located in the first opening and over the first protective cap, and the second conductive line is located over the via structure and the first photosensitive dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor device structures and methods of forming the same, and more particularly, to semiconductor device structures with protective caps and methods of forming the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs having smaller and more complex circuitry. However, these advances have also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, several

[0003] In the course of IC evolution, there has been a continual push to increase functionality at a smaller size, or footprint. This has resulted in the use of smaller and smaller features, or line widths, in the design and manufacture of ICs. This scaling down of features has provided some benefits, such as increased functionality and lower cost.

[0004] However, as the size of the features, such as the size of the conductive via structures, continues to decrease, the manufacturing process becomes more difficult to perform. Thus, as the size of the features continues to decrease, it is a challenge to form reliable semiconductor devices. SUMMARY

[0005] Some embodiments of the present application provide a method of forming a semiconductor device structure. The method includes forming a first conductive line over a substrate, and forming a first protective cap over a first portion of the first conductive line. The first protective cap and the first conductive line are formed of different conductive materials. The method includes forming a first photo dielectric layer over the substrate, the first conductive line, and the first protective cap, and forming a first opening in the first photo dielectric layer. The first opening partially exposes the first protective cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is located in the first opening, and the second conductive line is located over the conductive via structure and the first photo dielectric layer.

[0006] Some embodiments of the present disclosure provide a method of forming a semiconductor device structure. The method includes forming a first conductive line over a substrate, and forming a protective cap over a portion of the first conductive line. The protective cap and the first conductive line are formed of different conductive materials. The method includes forming a first dielectric layer over the substrate, the first conductive line, and the protective cap. The first dielectric layer has a first opening that partially exposes the protective cap, and the first dielectric layer includes sulfur. The method includes forming a magnetic core over the first dielectric layer. The magnetic core extends across the first conductive line. The method includes forming a second dielectric layer over the first dielectric layer and the magnetic core. The second dielectric layer has a second opening that is located over the first opening and connected to the first opening. The method includes forming a via structure and a second conductive line over the first conductive line. The via structure is located in the first opening and the second opening, and the second conductive line is located over the via structure, the second dielectric layer, and the magnetic core.

[0007] Some embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a first conductive line over a substrate, and a protective cap over a first portion of the first conductive line. The protective cap and the first conductive line are formed of different conductive materials. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the protective cap, a via structure through the first photosensitive dielectric layer and connected to the protective cap, and a second conductive line over the via structure and the first photosensitive dielectric layer. The second conductive line is electrically connected to the first conductive line through the via structure and the protective cap. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the present disclosure can be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:

[0009] Figures 1A-1P is a top view schematic diagram of a semiconductor device structure at various stages of a process for forming the semiconductor device structure in accordance with some embodiments;

[0010] Figures 1A-1 to 1K-1 is a cross-sectional schematic diagram showing Figures 1A-1K the semiconductor device structure along the cross-sectional line I-I' in

[0011] Figures 1L-1 to 1P-1 is a cross-sectional schematic diagram showing Figures 1L-1P the semiconductor device structure along the cross-sectional line II-II' in

[0012] Figures 1P-2 is a cross-sectional schematic diagram showing Figures 1PA semiconductor device structure along a cross-sectional line I-I' according to some embodiments;

[0013] Figure 2 A top view schematic of a semiconductor device structure according to some embodiments;

[0014] Figure 3 A top view schematic of a semiconductor device structure according to some embodiments; and

[0015] Figure 4 A cross-sectional schematic of a semiconductor device structure according to some embodiments.

[0016] BRIEF DESCRIPTION OF THE DRAWINGS

[0017] 100: semiconductor device structure

[0018] 110: substrate

[0019] 120: passivation layer

[0020] 130, 226: wire

[0021] 132, 134: end portion

[0022] 132e: edge

[0023] 136: body portion

[0024] 138, 142a, 144a, 226a, 232, 216, 244: top surface

[0025] 139, 142b, 144b, 226b, 234: sidewall

[0026] 140: protection layer

[0027] 142, 144, 230: protection cap

[0028] 142p, 144p, 232p: peripheral portion

[0029] 150: mask layer

[0030] 160, 210, 240: photosensitive dielectric layer

[0031] 170: etch stop layer

[0032] 162, 164, 212, 214, 242: opening

[0033] 162a, 164a, 212a, 214a, 242a: inner wall

[0034] 180: magnetic core

[0035] 180a: magnetic layer

[0036] 190: mask layer

[0037] 222, 224: via structure

[0038] 250: under bump metallization structure

[0039] 260: conductive bump

[0040] C: coil structure

[0041] D: inductor

[0042] T1, T2, T3, T4: thickness

[0043] W1, W2: line width

[0044] W3, W4, W5, W6: width

[0045] Θ1, Θ2: angle DETAILED DESCRIPTION

[0046] The following detailed description is presented to provide a thorough understanding of the application. Numbered embodiments or examples are described below to provide a thorough understanding of the application. Descriptions of well-known methods, devices, and materials can be omitted so as to not unnecessarily obscure the disclosure. Indeed, specific details of the present application are not to be interpreted as limiting, but rather as a representation of embodiments of the application. Embodiments of the present application, however, can be practiced without these specific details. In other instances, well-known methods, devices, and materials have not been described in detail in order to avoid unnecessarily obscuring aspects of the application.

[0047] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one element or component's or portion's relation to another element or component or portion as illustrated in the figures. Such spatially relative terms can be interpreted differently when the devices, objects, or systems are in different positions. For example, if a device in the figure is turned over, the relative position can be reversed. Accordingly, the spatially relative terms can encompass different orientations of the device, objects, or systems in their operation. The devices, objects, or systems depicted in the figures can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. It is to be understood that other process steps can be provided before, during, and after the steps described, and that some of these steps can be replaced by other steps, or eliminated, without departing from the scope of the application.

[0048] Figures 1A-1Pare top-down schematic diagrams of a semiconductor device structure at various stages of a process of forming the semiconductor device structure in accordance with some embodiments. Figures 1A-1 to 1K-1 are cross-sectional schematic diagrams showing Figures 1A-1K a semiconductor device structure along a cross-sectional line I-I' in

[0049] Figures 1L-1 to 1P-1 are cross-sectional schematic diagrams showing Figures 1L-1P a semiconductor device structure along a cross-sectional line II-II' in Figures 1P-2 are cross-sectional schematic diagrams showing Figures 1P a semiconductor device structure along a cross-sectional line I-I' in

[0050] In accordance with some embodiments, as shown in Figure 1A and Figure 1A-1 a substrate 110 is provided. In some embodiments, the substrate 110 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate 110 is a silicon wafer. In some embodiments, the substrate 110 is a chip.

[0051] The substrate 110 can include silicon or other elemental semiconductor material, such as germanium. In other embodiments, the substrate 110 includes a compound semiconductor. The compound semiconductor can include silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, other suitable compound semiconductor, or combinations thereof.

[0052] In some embodiments, the substrate 110 includes a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, other suitable method, or combinations thereof.

[0053] In some embodiments, various different device elements are formed in and / or on the substrate 110. For brevity and clarity, the device elements are not shown in the figures. Examples of the various device elements include transistors, diodes, other suitable elements, or combinations thereof.

[0054] For example, the transistors can be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc. Various processes can be performed to form the various device elements. These processes can include deposition, etching, implantation, lithography, annealing, planarization, one or more other appropriate processes, or combinations thereof.

[0055] In some embodiments, isolation features (not shown) are formed in the substrate 110. The isolation features are used to define active regions, and various device elements are formed in and / or on the substrate 110 in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other appropriate isolation features, or combinations thereof.

[0056] According to some embodiments, as shown in Figure 1A and Figure 1A-1 A passivation layer 120 is formed over the substrate 110. According to some embodiments, the passivation layer 120 is formed of an insulating material. According to some embodiments, the passivation layer 120 is formed of a polymeric material, silicon nitride, or silicon oxide. The passivation layer 120 is formed using a coating process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other appropriate processes.

[0057] According to some embodiments, as shown in Figure 1A and Figure 1A-1 Conducting lines 130 are formed over the passivation layer 120. In some embodiments, the conducting lines 130 are formed of copper. In some other embodiments, the conducting lines 130 are formed of aluminum, cobalt, nickel, tungsten, or other appropriate metals or alloys. According to some embodiments, the conducting lines 130 are formed using a plating process (or deposition process) and an etching process.

[0058] According to some embodiments, each wire 130 has two end portions 132 and 134 and a main portion 136. According to some embodiments, the main portion 136 is connected to the end portions 132 and 134. In some embodiments, the wire width Wl of each end portion 132 and 134 is greater than the wire width W2 of the main portion 136. In other embodiments, the wire width Wl of each end portion 132 and 134 is substantially equal to the wire width W2 of the main portion 136.

[0059] According to some embodiments, as shown in FIG. 1C, a protective layer 140 is formed over the wires 130 and the passivation layer 120. According to some embodiments, the protective layer 140 conformally covers the wires 130 and the passivation layer 120. According to some embodiments, the protective layer 140 and the wires 130 are formed of different conductive materials. Figure 1B and Figure 1B-1 According to some embodiments, as shown in FIG. 1C, a protective layer 140 is formed over the wires 130 and the passivation layer 120. According to some embodiments, the protective layer 140 conformally covers the wires 130 and the passivation layer 120. According to some embodiments, the protective layer 140 and the wires 130 are formed of different conductive materials.

[0060] In some cases, the conductive material of the wires 130 can tend to react with sulfur and oxygen in subsequent processes, and form Cu x O y S z layers over the wires 130, where x, y, and z are positive integers. The Cu x O y S z layers can increase the contact resistance between the wires 130 and a conductive via structure subsequently formed over the wires 130.

[0061] In some embodiments, the protective layer 140 is formed of a conductive material that has a lower reactivity with sulfur and oxygen than the conductive material of the wires 130. Thus, the protective layer 140 can prevent the conductive material of the wires 130 from reacting with sulfur and oxygen in subsequent processes, thus preventing the formation of Cu x O y S z layers over the wires 130. Thus, the protective layer 140 can reduce the contact resistance between the wires 130 and a conductive via structure subsequently formed over the wires 130.

[0062] In some embodiments, the protective layer 140 is formed of titanium (Ti). In other embodiments, the protective layer 140 is formed of gold (Au), silver (Ag), vanadium (V), chromium (Cr), tantalum (Ta), molybdenum (Mo), iron (Fe), palladium (Pd), indium (In), or gallium (Ga). According to some embodiments, the protective layer 140 is formed using a plating process (e.g., an electroplating process) or a deposition process (e.g., a physical vapor deposition process or a chemical vapor deposition process).

[0063] According to some embodiments, as shown in Figure 1C and Figure 1C-1 the mask layer 150 is formed over the protective layer 140. According to some embodiments, the mask layer 150 covers the protective layer 140 directly above the end point portions 132 and 134. According to some embodiments, the mask layer 150 is formed of a photoresist material, such as a polymeric material.

[0064] According to some embodiments, as shown in Figure 1C and Figure 1D the protective layer 140 that is not covered by the mask layer 150 is removed. According to some embodiments, the remaining protective layer 140 forms the protective caps 142 and 144. According to some embodiments, the removal process includes etching, such as a dry etching process or a wet etching process. According to some embodiments, as shown in Figure 1D and Figure 1D-1 the mask layer 150 is then removed.

[0065] According to some embodiments, the thickness Tl of the protective caps 142 and 144 is less than the thickness T2 of the conductive lines 130 underneath the protective caps 142 and 144. According to some embodiments, the thickness Tl ranges from about 5 nanometers (nm) to about 5 micrometers (pm). According to some embodiments, the thickness T2 ranges from about 4 micrometers to about 30 micrometers. According to some embodiments, the protective caps 142 are respectively located directly above the end point portions 132. According to some embodiments, the protective caps 144 are respectively located directly above the end point portions 134.

[0066] According to some embodiments, the size of the protective caps 142 and 144 is less than the size of the end point portions 132 and 134 underneath the protective caps 142 and 144. For example, according to some embodiments, the maximum width W3 of the protective caps 142 and 144 is less than the maximum width W4 of the end point portions 132 and 134 underneath the protective caps 142 and 144.

[0067] According to some embodiments, the protective cap 142 does not cover the edges 132e of the end point portion 132 underneath the protective cap 142. According to some embodiments, the protective cap 142 is spaced apart from all edges 132e of the end point portion 132 underneath the protective cap 142. According to some embodiments, the protective cap 144 does not cover all edges 134e of the end point portion 134 underneath the protective cap 144. According to some embodiments, the protective cap 144 is spaced apart from the edges 134e of the end point portion 134 underneath the protective cap 144.

[0068] According to some embodiments, as shown in FIG. 1F-1, a photoresist layer 160 is formed on the passivation layer 120, the conductive lines 130, and the protective caps 142 and 144. According to some embodiments, the photoresist layer 160 is in direct contact with the conductive lines 130 and the protective caps 142 and 144. Figure 1E and Figure 1E-1 According to some embodiments, as shown in FIG. 1F-1, a photoresist layer 160 is formed on the passivation layer 120, the conductive lines 130, and the protective caps 142 and 144. According to some embodiments, the photoresist layer 160 is in direct contact with the conductive lines 130 and the protective caps 142 and 144.

[0069] According to some embodiments, the photoresist layer 160 is in direct contact with the top surface 138 and the sidewall 139 of the conductive lines 130, the top surface 142a and the sidewall (or edge) 142b of the protective cap 142, and the top surface 144a and the sidewall (or edge) 144b of the protective cap 144.

[0070] According to some embodiments, the photoresist layer 160 is formed of a photoresist polymer material. According to some embodiments, the photoresist polymer material includes polybenzoxazole (PBO). According to some embodiments, the photoresist polymer material includes sulfur. According to some embodiments, the photoresist polymer material includes 2,3,4-Trihydroxybenzophenone tris(1,2-naphthoquinonediazide-5-sulfonate), which includes sulfur. The structure of 2,3,4-Trihydroxybenzophenone tris(1,2-naphthoquinonediazide-5-sulfonate) is shown below.

[0071]

[0072] According to some embodiments, as shown in FIG. 1F and FIG. 1F-1, portions of the photoresist layer 160 that are directly above the protective caps 142 and 144 are removed. According to some embodiments, the removal process includes a photolithography process.

[0073] According to some embodiments, the removal process forms openings 162 and 164 in the photo dielectric layer 160. According to some embodiments, the openings 162 are respectively above the protective caps 142. According to some embodiments, each opening 162 partially exposes the protective cap 142 underneath the opening 162.

[0074] According to some embodiments, the openings 164 are respectively directly above the protective caps 144. According to some embodiments, each opening 164 partially exposes the protective cap 144 underneath the opening 164. According to some embodiments, the photo dielectric layer 160 covers the peripheral portions 142p and 144p of the top surfaces 142a and 144a. According to some embodiments, the peripheral portions 142p and 144p of the top surfaces 142a and 144a have a ring shape.

[0075] According to some embodiments, in some embodiments, the width W5 of the peripheral portion 142p of the top surface 142a ranges from about 1 micron to about 50 microns. According to some embodiments, the width W5 is equal to the distance between the inner wall 162a of the opening 162 and the sidewall 142b of the protective cap 142.

[0076] According to some embodiments, in some embodiments, the width W6 of the peripheral portion 144p of the top surface 144a ranges from about 1 micron to about 50 microns. According to some embodiments, the width W6 is equal to the distance between the inner wall 164a of the opening 164 and the sidewall 144b of the protective cap 144. According to some embodiments, the photo dielectric layer 160 covers the entire sidewalls (or edges) 144a and 144b.

[0077] According to some embodiments, the photo dielectric layer 160 above the conductive lines 130 has a thickness T3. According to some embodiments, the thickness T3 is greater than the thickness T1 of the protective caps 142 and 144. According to some embodiments, the thickness T3 ranges from about 3 microns to about 50 microns. According to some embodiments, the photo dielectric layer 160 above the passivation layer 120 has a thickness T4. According to some embodiments, the thickness T4 ranges from about 7 microns to about 80 microns.

[0078] According to some embodiments, the angle θ1 between the top surface 142a and the inner wall 162a of the opening 162 ranges from about 5° to about 90°. According to some embodiments, the angle θ2 between the top surface 144a and the inner wall 164a of the opening 164 ranges from about 5° to about 90°.

[0079] According to some embodiments, after the aforementioned removal process, a curing process is performed on the photo dielectric layer 160. According to some embodiments, the curing process has a process temperature ranging from about 300 °C to about 350 °C.

[0080] According to some embodiments, because the conductive materials of the protective covers 142 and 144 have lower reactivity with sulfur (from the photosensitive dielectric layer 160) and oxygen (from the environment and / or the photosensitive dielectric layer 160) compared to the conductive material of the conductor 130, the protective covers 142 and 144 prevent the conductor 130 beneath them from reacting with sulfur and oxygen, thus preventing Cu x O y S z It is formed on the conductor 130. Therefore, according to some embodiments, protective covers 142 and 144 are formed to improve the electrical properties of the conductor 130.

[0081] In some embodiments, the protective covers 142 and 144 have a circular shape (e.g. Figure 1F (As shown). In some other embodiments, the protective covers 142 and 144 are polygonal. For example, as Figure 2 As shown, protective covers 142 and 144 are rectangular or square. (As...) Figure 3 As shown, protective covers 142 and 144 are hexagonal.

[0082] According to some embodiments, such as Figure 1G and Figure 1G-1 As shown, an etch stop layer 170 is formed over the photosensitive dielectric layer 160 and protective caps 142 and 144. According to some embodiments, the etch stop layer 170 is formed of a dielectric material. According to some embodiments, the dielectric material comprises silicon nitride. According to some embodiments, the etch stop layer 170 is formed using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0083] According to some embodiments, such as Figure 1G and Figure 1G-1 As shown, a magnetic layer 180a is formed on the etch stop layer 170. In some embodiments, the magnetic layer 180a is formed of a ferromagnetic material. In some embodiments, the magnetic layer 180a is made of Co. x Zr y Ta z (CZT), where x, y, and z represent the atomic percentages of cobalt (Co), zirconium (Zr), and tantalum (Ta), respectively. In some embodiments, x ranges from about 0.85 to about 0.95, y ranges from about 0.025 to about 0.075, and z ranges from about 0.025 to about 0.075. In some embodiments, the CZT material has x = 0.915, y = 0.045, and z = 0.045.

[0084] In some embodiments, the magnetic layer 180a is made of Ni x Zn y Cu zformed, where x, y, and z represent atomic percentages of nickel (Ni), zinc (Zn), and copper (Cu), respectively. In some embodiments, x ranges from about 0.4 to about 0.6, y ranges from about 0.2 to about 0.4, and z ranges from about 0.1 to about 0.2.

[0085] In some embodiments, the magnetic layer 180a is formed of Co x Zr y Nb z formed, where x, y, and z represent atomic percentages of cobalt (Co), zirconium (Zr), and niobium (Nb), respectively. In some embodiments, x ranges from about 0.7 to about 0.9, y ranges from about 0.01 to about 0.05, and z ranges from about 0.01 to about 0.07. In some embodiments, the magnetic layer 180a is formed of Fe x (TaN) y formed, where x and y represent atomic percentages of iron (Fe) and tantalum nitride (TaN), respectively. In some embodiments, x ranges from about 0.7 to about 0.9, and y ranges from about 0.05 to about 0.2.

[0086] In some embodiments, the magnetic layer 180a is formed of Fe x Co y B z formed, where x, y, and z represent atomic percentages of iron (Fe), cobalt (Co), and boron (B), respectively. In some embodiments, x ranges from about 0.1 to about 0.3, y ranges from about 0.1 to about 0.3, and z ranges from about 0.4 to about 0.6.

[0087] In some embodiments, the magnetic layer 180a is formed of Ni x Zn y Fe z O w formed, where x, y, z, and w represent atomic percentages of nickel (Ni), zinc (Zn), iron (Fe), and oxygen (O), respectively. In some embodiments, x ranges from about 0.3 to about 0.4, y ranges from about 0.1 to about 0.2, z ranges from about 0.2 to about 0.5, and w ranges from about 0.15 to about 0.25. In some embodiments, the magnetic layer comprises a multi-layer structure formed of a combination of the aforementioned ferromagnetic materials (e.g., CoZrTa-FeCoB).

[0088] In some embodiments, the magnetic layer 180a is formed using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a combination of the foregoing, or other suitable deposition process.

[0089] In some embodiments, the magnetic layer 180a comprises films stacked together. In some embodiments, the magnetic layer 180a is formed by repeated deposition processes (e.g., physical vapor deposition or chemical vapor deposition) several times.

[0090] According to some embodiments, as shown in Figures 1G and 1G-1, a mask layer 190 is formed over the magnetic layer 180a. According to some embodiments, the mask layer 190 covers the magnetic layer 180a between protective caps 142 and 144 (or openings 162 and 164). According to some embodiments, the mask layer 190 is formed of a photoresist material, such as a polymer material.

[0091] According to some embodiments, such as Figure 1G-1 and Figure 1H-1 As shown, the magnetic layer 180a and etch stop layer 170 not directly beneath the mask layer 190 are removed. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process. According to some embodiments, after the removal process, the remaining magnetic layer 180a forms the magnetic core 180.

[0092] According to some embodiments, such as Figure 1H and Figure 1H-1 As shown, a magnetic core 180 is formed on the photosensitive dielectric layer 160. According to some embodiments, the magnetic core 180 is formed between protective covers 142 and 144 (or openings 162 and 164). According to some embodiments, the magnetic core 180 extends across the conductor 130.

[0093] According to some embodiments, such as Figure 1I and Figure 1I-1 As shown, a photosensitive dielectric layer 210 is formed over the photosensitive dielectric layer 160, protective caps 142 and 144, magnetic core 180, and etch stop layer 170. According to some embodiments, the photosensitive dielectric layer 210 is in direct contact with the photosensitive dielectric layer 160, protective caps 142 and 144, magnetic core 180, and etch stop layer 170. According to some embodiments, the photosensitive dielectric layer 210 covers the entire magnetic core 180.

[0094] According to some embodiments, the photosensitive dielectric layer 210 is formed of a photosensitive polymer material. According to some embodiments, the photosensitive polymer material contains sulfur. According to some embodiments, the photosensitive polymer material contains polybenzoxazole (PBO). According to some embodiments, the photosensitive polymer material contains sulfur. According to some embodiments, the photosensitive polymer material contains 2,3,4-trihydroxybenzophenonetris(1,2-naphthoquinonediazide-5-sulfonate), which contains sulfur.

[0095] According to some embodiments, as shown in Figure 1J and Figure 1J-1 part of the photo dielectric layer 210 is removed directly above the protection caps 142 and 144. According to some embodiments, the removal process includes a photolithography process. According to some embodiments, the removal process forms openings 212 and 214 in the photo dielectric layer 210. According to some embodiments, each of the openings 212 is located above the protection cap 142.

[0096] According to some embodiments, each of the openings 212 partially exposes the protection cap 142 underneath the opening 212. According to some embodiments, each of the openings 212 is connected to the opening 162 underneath the opening 212. According to some embodiments, the opening 212 has an inner wall 212a.

[0097] According to some embodiments, the inner wall 212a is aligned with (or coplanar to) the inner wall 162a of the opening 162 underneath the inner wall 212a. According to some embodiments, the photo dielectric layer 210 covers an annular peripheral portion 142p of the top surface 142a of the protection cap 142.

[0098] According to some embodiments, each of the openings 214 is located above the protection cap 144. According to some embodiments, each of the openings 214 partially exposes the protection cap 144 underneath the opening 214. According to some embodiments, each of the openings 214 is connected to the opening 164 underneath the opening 214. According to some embodiments, the opening 214 has an inner wall 214a. According to some embodiments, the inner wall 214a is aligned with (or coplanar to) the inner wall 164a of the opening 164 underneath the inner wall 214a.

[0099] According to some embodiments, the photo dielectric layer 210 covers an annular peripheral portion 144p of the top surface 144a of the protection cap 144. According to some embodiments, after the removal process, a hardening process is performed on the photo dielectric layer 210. According to some embodiments, the hardening process has a process temperature in a range from about 300 °C to about 350 °C.

[0100] According to some embodiments, because the conductive material of the protection caps 142 and 144 has a lower reactivity with sulfur (from the photo dielectric layer 210) and oxygen (from the environment and / or the photo dielectric layer 210) than the conductive material of the conductive lines 130, the protection caps 142 and 144 prevent the conductive lines 130 underneath the protection caps 142 and 144 from reacting with the sulfur and the oxygen. Thus, according to some embodiments, the formation of the protection caps 142 and 144 improves the electrical properties of the conductive lines 130.

[0101] According to some embodiments, as shown in Figure 1K and Figure 1K-1As shown, conductive via structures 222 are formed in openings 162 and 212. According to some embodiments, conductive via structures 222 fill openings 162 and 212. According to some embodiments, conductive via structures 222 pass through photosensitive dielectric layers 160 and 210.

[0102] According to some embodiments, conductive via structures 222 are positioned above protective cover 142, respectively. According to some embodiments, conductive via structures 222 are electrically connected to wire 130 through protective cover 142. According to some embodiments, protective cover 142 physically separates wire 130 from conductive via structures 222.

[0103] According to some embodiments, as shown in FIG. 2B, Figure 1K and Figure 1K-1 According to some embodiments, conductive via structures 224 are formed in openings 164 and 214. According to some embodiments, conductive via structures 224 fill openings 164 and 214. According to some embodiments, conductive via structures 224 pass through photosensitive dielectric layers 160 and 210.

[0104] According to some embodiments, conductive via structures 224 are positioned above protective cover 144, respectively. According to some embodiments, conductive via structures 224 are electrically connected to wire 130 through protective cover 144. According to some embodiments, protective cover 144 physically separates wire 130 from conductive via structures 224.

[0105] According to some embodiments, protective covers 142 and 144 reduce the electrical resistance between conductive via structures 222 and wire 130, and between conductive via structures 224 and wire 130, because protective covers 142 and 144 prevent wire 130 from reacting with sulfur and oxygen.

[0106] According to some embodiments, as shown in FIG. 2B, Figure 1K and Figure 1K-1 According to some embodiments, wires 226 are formed above conductive via structures 222 and 224. According to some embodiments, wires 226 are electrically connected to conductive via structures 222 and 224, protective covers 142 and 144, and wire 130.

[0107] According to some embodiments, wires 226 are positioned above magnetic core 180. According to some embodiments, wires 226 extend across magnetic core 180. According to some embodiments, wires 130 and 226, conductive via structures 222 and 224, and protective covers 142 and 144 together form a coil structure C.

[0108] According to some embodiments, the coil structure C surrounds the magnetic core 180. The coil structure C and the magnetic core 180 together form an inductor D. According to some embodiments, because the protective caps 142 and 144 reduce the electrical resistance between the via structures 222 and 224 and the conductive lines 130, the electrical resistance of the coil structure C is also reduced. Thus, according to some embodiments, the protective caps 142 and 144 improve the efficiency of the inductor D. According to some embodiments, the photosensitive dielectric layers 160 and 210 separate the magnetic core 180 from the conductive lines 130 and 226, the protective caps 142 and 144, and the vias 130 and 226.

[0109] According to some embodiments, the electrically conductive material of the protective caps 142 and 144 is different from the via structures 222 and 224. According to some embodiments, the via structures 222 and 224 and the conductive lines 130 and 226 are formed of the same electrically conductive material.

[0110] According to some embodiments, the via structures 222 and 224 and the conductive lines 226 are formed of copper (Cu). In other embodiments, the via structures 222 and 224 and the conductive lines 226 are formed of aluminum (Al), cobalt (Co), nickel (Ni), tungsten (W), or other suitable material or alloy.

[0111] According to some embodiments, the formation of the via structures 222 and 224 and the conductive lines 226 includes forming a seed layer in the openings 162, 164, 212, and 214 and on the photosensitive dielectric layer 210, forming a photoresist layer on the seed layer, where the photoresist layer has a trench that exposes a portion of the seed layer, electroplating an electrically conductive layer in the trench, removing the photoresist layer, and removing the seed layer that was previously under the photoresist layer.

[0112] According to some embodiments, as shown in Figure 1L and Figure 1L-1 the protective cap 230 is formed on the conductive lines 226. According to some embodiments, the protective cap 230 and the conductive lines 226 are formed of different electrically conductive materials. In some embodiments, the protective cap 230 is formed of an electrically conductive material that is less reactive with sulfur and oxygen than the electrically conductive material of the conductive lines 226.

[0113] In some embodiments, the protective cap 230 is formed of titanium (Ti). In other embodiments, the protective cap 230 is formed of gold (Au), silver (Ag), vanadium (V), chromium (Cr), tantalum (Ta), molybdenum (Mo), iron (Fe), palladium (Pd), indium (In), or gallium (Ga). According to some embodiments, the protective cap 230 is formed using a plating process (e.g., an electroplating process) or a deposition process (e.g., a physical vapor deposition process or a chemical vapor deposition process).

[0114] According to some embodiments, as shown in Figure 1Mand Figure 1M-1 As shown, a photosensitive dielectric layer 240 is formed on the photosensitive dielectric layer 210, the conductive lines 226, and the protective cap 230. According to some embodiments, the photosensitive dielectric layer 240 is in direct contact with the photosensitive dielectric layer 210, the conductive lines 226, and the protective cap 230.

[0115] According to some embodiments, the photosensitive dielectric layer 240 is in direct contact with the top surface 226a and the sidewalls 226b of the conductive lines 226, the top surface 232 and the sidewalls (or edges) 234 of the protective cap 230, and the top surface 216 of the photosensitive dielectric layer 210.

[0116] According to some embodiments, the photosensitive dielectric layer 240 is formed of a photosensitive polymer material. According to some embodiments, the photosensitive polymer material includes sulfur. According to some embodiments, the photosensitive polymer material includes 2,3,4-Trihydroxybenzophenone tris(l,2-naphthoquinonediazide-5-sulfonate), which includes sulfur. According to some embodiments, the photosensitive polymer material includes polybenzoxazole (PBO).

[0117] According to some embodiments, as shown in FIG. 2B, a portion of the photosensitive dielectric layer 240 that is directly above the protective cap 230 is removed. According to some embodiments, the removal process includes a photolithography process. According to some embodiments, the removal process forms an opening 242 in the photosensitive dielectric layer 240. According to some embodiments, the opening 242 is above the protective cap 230. According to some embodiments, the opening 242 partially exposes the protective cap 230 underneath the opening 242. Figure 1N and Figure 1N-1 According to some embodiments, the photosensitive dielectric layer 240 covers an annular peripheral portion of the top surface 232 of the protective cap 230. According to some embodiments, the photosensitive dielectric layer 240 covers all of the sidewalls (or edges) 234 of the protective cap 230. After the removal process, a hardening process is performed on the photosensitive dielectric layer 240. The process temperature range of the hardening process is between about 300 °C and about 350 °C.

[0118] According to some embodiments, because the conductive material of the protective cap 230 has lower reactivity with sulfur (from the photosensitive dielectric layer 240) and oxygen (from the environment and / or the photosensitive dielectric layer 240) than the conductive material of the conductive lines 226, the protective cap 230 prevents the conductive lines 226 underneath the protective cap 230 from reacting with sulfur and oxygen. Thus, according to some embodiments, the formation of the protective cap 230 improves the electrical properties of the conductive lines 226.

[0119] According to some embodiments, as shown in FIG. 2B, a portion of the photosensitive dielectric layer 240 that is directly above the protective cap 230 is removed. According to some embodiments, the removal process includes a photolithography process. According to some embodiments, the removal process forms an opening 242 in the photosensitive dielectric layer 240. According to some embodiments, the opening 242 is above the protective cap 230. According to some embodiments, the opening 242 partially exposes the protective cap 230 underneath the opening 242.

[0120] According to some embodiments, as shown in FIG. 2B, a portion of the photosensitive dielectric layer 240 that is directly above the protective cap 230 is removed. According to some embodiments, the removal process includes a photolithography process. According to some embodiments, the removal process forms an opening 242 in the photosensitive dielectric layer 240. According to some embodiments, the opening 242 is above the protective cap 230. According to some embodiments, the opening 242 partially exposes the protective cap 230 underneath the opening 242.Figure 1O and Figure 1O-1 As shown, an under-bump metallization (UBM) 250 structure is formed on the protective cover 230. The under-bump metallization structure 250 conformally covers the top surface 232 of the protective cover 230, the inner wall 242a of the opening 242, and the top surface 244 of the photosensitive dielectric 240.

[0121] According to some embodiments, the under-bump metallization structure 250 includes a first metallization layer (not shown), a second metallization layer (not shown), and a third metallization layer (not shown) sequentially stacked on the protective cover 230. According to some embodiments, the first metallization layer comprises copper (Cu) or a copper alloy. According to some embodiments, the first metallization layer is formed using an electroplating process.

[0122] According to some embodiments, the second metallization layer comprises tin (Sn) or a tin alloy. According to some embodiments, the second metallization layer is formed using an electroplating process or an immersion process. According to some embodiments, the third metallization layer comprises nickel (Ni) or a nickel alloy, for example, nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), nickel-palladium (NiPd), or other similar alloys. According to some embodiments, the third metallization layer is formed using an electroplating process or an immersion process.

[0123] According to some embodiments, such as Figure 1P , Figure 1P-1 and Figures 1P-2 As shown, conductive bumps 260 are formed on the under-bump metallization structure 250. The conductive bumps 260 are formed of Sn, SnAg, SnPb, SnAgCu, SnAgZn, SnZn, SnBiIn, SnIn, SnAu, SnPb, SnCu, SnZnIn, SnAgSb, or other suitable conductive materials. In some embodiments, the conductive bumps 260 are formed of lead-free solder. According to some embodiments, in this step, a semiconductor device structure 100 is substantially formed.

[0124] Figure 4 This is a schematic cross-sectional view of a semiconductor device structure 400 according to some embodiments. According to some embodiments, such as... Figure 4 As shown, semiconductor device structure 400 and Figure 1P-1 The semiconductor device structure 100 is similar, except that the semiconductor device structure 400 does not have Figure 1P-1 The semiconductor device structure 100 includes an etch stop layer 170, a magnetic core 180, and a photosensitive dielectric layer 210.

[0125] According to some embodiments, a semiconductor device structure and a method of forming the same are provided. The method (forming the semiconductor device structure) forms a protective cap over a conductive line to prevent the conductive line under the protective cap from reacting with sulfur (from a subsequently formed photo dielectric material) and oxygen (from the environment and / or a subsequently formed photo dielectric material). Thus, the formation of the protective cap improves the electrical properties of the conductive line.

[0126] According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protective cap over a first portion of the first conductive line. The first protective cap and the first conductive line are formed of different conductive materials. The method includes forming a first photo dielectric layer over the substrate, the first conductive line, and the first protective cap. The method includes forming a first opening in the first photo dielectric layer and over the first protective cap. The first opening partially exposes the first protective cap. The method includes forming a via structure and a second conductive line over the first conductive line. The via structure is located in the first opening and over the first protective cap, and the second conductive line is located over the via structure and the first photo dielectric layer. According to some embodiments, after forming the first opening, a remaining portion of the first photo dielectric layer partially covers a top surface of the first protective cap. According to some embodiments, the step of forming the first opening includes performing a lithography process on the first photo dielectric layer to remove the first photo dielectric layer over the first protective cap. According to some embodiments, the first photo dielectric layer is formed of a polymeric material. According to some embodiments, the first photo dielectric layer includes sulfur. According to some embodiments, the first photo dielectric layer is in direct contact with the first conductive line and the first protective cap. According to some embodiments, the method further includes, after forming the via structure and the second conductive line, forming a second protective cap over the second conductive line. The second protective cap and the second conductive line are formed of different conductive materials. The method further includes forming a second photo dielectric layer over the first photo dielectric layer, the second conductive line, and the second protective cap. The method further includes forming a second opening in the second photo dielectric layer. The second opening partially exposes the second protective cap. According to some embodiments, the method further includes, after forming the second opening, forming a conductive bump over the second protective cap, wherein the conductive bump is partially located in the second opening. According to some embodiments, the method further includes, after forming the second opening and before forming the conductive bump over the second protective cap, forming an under bump metallization structure over the second protective cap. The conductive bump is formed over the under bump metallization structure.

[0127] According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a protective cap over a portion of the first conductive line. The protective cap and the first conductive line are formed of different conductive materials. The method includes forming a first dielectric layer over the substrate, the first conductive line, and the protective cap. The first dielectric layer has a first opening that partially exposes the protective cap, and the first dielectric layer includes sulfur. The method includes forming a magnetic core over the first dielectric layer. The magnetic core extends across the first conductive line. The method includes forming a second dielectric layer over the first dielectric layer and the magnetic core. The second dielectric layer has a second opening that is located over the first opening and connected to the first opening. The method includes forming a via structure and a second conductive line over the first conductive line. The via structure is located in the first opening and the second opening and over the protective cap, and the second conductive line is located over the via structure, the second dielectric layer, and the magnetic core. According to some embodiments, the first conductive line, the protective cap, the via structure, and the second conductive line together surround the magnetic core. According to some embodiments, the first dielectric layer and the second dielectric layer separate the magnetic core from the first conductive line, the protective cap, the via structure, and the second conductive line. According to some embodiments, the protective cap separates the first conductive line and the via structure. According to some embodiments, the protective cap and the via structure are formed of different conductive materials. According to some embodiments, the first dielectric layer covers all edges of the protective cap.

[0128] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protective cap over a first portion of the first conductive line. The first protective cap and the first conductive line are formed of different conductive materials. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protective cap. The semiconductor device structure includes a via structure through the first photosensitive dielectric layer and over the first protective cap. The semiconductor device structure includes a second conductive line over the via structure and the first photosensitive dielectric layer. According to some embodiments, the first conductive line includes copper, aluminum, cobalt, nickel, or tungsten, and the protective cap includes titanium, gold, silver, vanadium, chromium, tantalum, molybdenum, iron, palladium, indium, or gallium. According to some embodiments, the first photosensitive dielectric layer includes sulfur. According to some embodiments, the first photosensitive dielectric layer covers a peripheral portion of a top surface of the protective cap. According to some embodiments, the semiconductor device structure further includes a magnetic core over the first photosensitive dielectric layer. The magnetic core extends across the first conductive line. The semiconductor device structure further includes a second photosensitive dielectric layer over the first photosensitive dielectric layer and the magnetic core. The via structure further through the second photosensitive dielectric layer, and the second conductive line is over the second photosensitive dielectric layer.

[0129] The components of the above overview of several embodiments in order that those of ordinary skill in the art can more readily understand the ideas of the embodiments of the present application. Those of ordinary skill in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present application to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those of ordinary skill in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present application, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the scope of the appended claims.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a first conductive line over a substrate; forming a first protective cap over a first portion of the first conductive line, wherein the first protective cap and the first conductive line are formed of different conductive materials; forming a first photo-sensitive dielectric layer over the substrate, the first conductive line, and the first protective cap; forming a first opening in the first photo-sensitive dielectric layer, wherein the first opening partially exposes the first protective cap; forming a via structure and a second conductive line over the first conductive line, wherein the via structure is located in the first opening, and the second conductive line is located over the via structure and the first photo-sensitive dielectric layer; after forming the via structure and the second conductive line, forming a second protective cap over the second conductive line, wherein the second protective cap and the second conductive line are formed of different conductive materials; forming a second photo-sensitive dielectric layer over the first photo-sensitive dielectric layer, the second conductive line, and the second protective cap; and forming a second opening in the second photo-sensitive dielectric layer, wherein the second opening partially exposes the second protective cap.

2. The method for forming a semiconductor device structure of claim 1, wherein after forming the first opening, a remaining portion of the first photo-sensitive dielectric layer partially covers a top surface of the first protective cap.

3. The method for forming a semiconductor device structure of claim 1, wherein forming the first opening comprises performing a photolithography process on the first photo-sensitive dielectric layer to remove the first photo-sensitive dielectric layer over the first protective cap.

4. The method for forming a semiconductor device structure of claim 1, wherein the first photo-sensitive dielectric layer is formed of a polymeric material.

5. The method for forming a semiconductor device structure of claim 4, wherein the first photo-sensitive dielectric layer comprises sulfur.

6. The method for forming a semiconductor device structure of claim 1, wherein the first photo-sensitive dielectric layer is in direct contact with the first conductive line and the first protective cap.

7. The method for forming a semiconductor device structure of claim 1, further comprising: after forming the second opening, forming a conductive bump over the second protective cap, wherein the conductive bump is partially located in the second opening.

8. The method for forming a semiconductor device structure of claim 7, further comprising: after forming the second opening, and before forming the conductive bump over the second protective cap, forming an under-bump metallization structure over the second protective cap, wherein the conductive bump is formed over the under-bump metallization structure.

9. A method for forming a semiconductor device structure, comprising: forming a first conductive line over a substrate; forming a first protective cap over a portion of the first conductive line, wherein the first protective cap and the first conductive line are formed of different conductive materials; forming a first dielectric layer over the substrate, the first conductive line, and the first protective cap, wherein the first dielectric layer has a first opening that partially exposes the first protective cap, the first dielectric layer includes sulfur, and the first dielectric layer continuously covers a first sidewall and a first top surface of the first conductive line and a second sidewall and a second top surface of the first protective cap; forming a magnetic core over the first dielectric layer, wherein the magnetic core extends across the first conductive line; forming a second dielectric layer over the first dielectric layer and the magnetic core, wherein the second dielectric layer has a second opening over and connected to the first opening; forming a via structure and a second conductive line over the first conductive line, wherein the via structure is in the first and second openings, and the second conductive line is over the via structure, the second dielectric layer, and the magnetic core; after forming the via structure and the second conductive line, forming a second protective cap over the second conductive line, wherein the second protective cap and the second conductive line are formed of different conductive materials; forming a third dielectric layer over the second dielectric layer, the second conductive line, and the second protective cap; and forming a third opening in the third dielectric layer, wherein the third opening partially exposes the second protective cap.

10. The method of claim 9, wherein the first conductive line, the first protective cap, the via structure, and the second conductive line together surround the magnetic core.

11. The method of claim 9, wherein the first and second dielectric layers separate the magnetic core from the first conductive line, the first protective cap, the via structure, and the second conductive line.

12. The method of claim 9, wherein the first protective cap separates the first conductive line and the via structure.

13. The method of claim 9, wherein the first protective cap and the via structure are formed of different conductive materials.

14. The method of claim 9, wherein the first dielectric layer covers all edges of the first protective cap.

15. A method of forming a semiconductor device structure, comprising: forming a first conductive line over a substrate, wherein the first conductive line has a first end portion and a main portion connected to the first end portion, and a first line width of the first end portion is greater than a second line width of the main portion; forming a first protective cap over the first end portion, wherein the first protective cap is formed of a first conductive material that is less reactive with sulfur and oxygen than a second conductive material of the first conductive line; forming a first dielectric layer over the substrate, the first conductive line, and the first protective cap, wherein the first dielectric layer has a first opening that partially exposes the first protective cap, and the first dielectric layer includes sulfur; forming a magnetic core over the first dielectric layer, wherein the magnetic core extends across the first conductive line; forming a second dielectric layer over the first dielectric layer and the magnetic core, wherein the second dielectric layer has a second opening over and connected to the first opening; forming a via structure in the first opening and the second opening and a second conductive line on the via structure, the second dielectric layer, and the magnetic core, the second conductive line having a second end portion and a third end portion, and the via structure being between the second end portion and the first protective cap; and forming a second protective cap on the third end portion, wherein the first protective cap and the second protective cap are formed of the same material.

16. The method of claim 15, wherein the first protective cap is formed of gold, silver, vanadium, chromium, tantalum, molybdenum, iron, palladium, indium, or gallium, and the first conductive line is formed of copper, aluminum, cobalt, nickel, or tungsten.

17. The method of claim 15, wherein the second dielectric layer includes sulfur.

18. The method of claim 17, wherein forming the second dielectric layer comprises: forming a layer of a dielectric material on the first dielectric layer and the magnetic core and in the first opening; and removing the layer of the dielectric material on and in the first opening to form the second opening.

19. The method of claim 15, wherein the first protective cap is thinner than the first conductive line.

20. The method of claim 15, further comprising: forming a third dielectric layer on the second dielectric layer, the second conductive line, and the second protective cap; and forming a third opening in the third dielectric layer, wherein the third opening partially exposes the second protective cap.

21. A semiconductor device structure, comprising: a first conductive line on a substrate, wherein the first conductive line has a first portion and a second portion connected to the first portion, and a line width of the second portion increases in a direction away from the first portion; a first protective cap on the first conductive line, wherein the first protective cap and the first conductive line are formed of different conductive materials, and the entire first protective cap is on the second portion, wherein the first protective cap exposes a ring-shaped area of a top surface of the second portion of the first conductive line; a first photosensitive dielectric layer on the substrate, the first conductive line, and the first protective cap; a via structure through the first photosensitive dielectric layer and connected to the first protective cap; a second conductive line on the via structure and the first photosensitive dielectric layer; a second protective cap on the second conductive line, wherein the second protective cap and the second conductive line are formed of different conductive materials; and a second photosensitive dielectric layer on the first photosensitive dielectric layer, the second conductive line, and the second protective cap, wherein the second photosensitive dielectric layer exposes a portion of the second protective cap.

22. The semiconductor device structure of claim 21, wherein the first conductive line comprises copper, aluminum, cobalt, nickel, or tungsten, and the first protective cap comprises titanium, gold, silver, vanadium, chromium, tantalum, molybdenum, iron, palladium, indium, or gallium.

23. The semiconductor device structure of claim 21, wherein the first photosensitive dielectric layer and the second photosensitive dielectric layer comprise sulfur. ​ 24. The semiconductor device structure of claim 21, wherein the second photo-sensitive dielectric layer covers a peripheral portion of a top surface of the second protective cap.

25. The semiconductor device structure of claim 21, wherein the second conductive line is electrically connected to the first conductive line through the via structure and the first protective cap.

26. The semiconductor device structure of claim 21, further comprising: a magnetic core over the first photo-sensitive dielectric layer, wherein the magnetic core extends across the first conductive line; and a third photo-sensitive dielectric layer over the first photo-sensitive dielectric layer and the magnetic core, wherein the via structure further passes through the third photo-sensitive dielectric layer, and the second conductive line and the second photo-sensitive dielectric layer are over the third photo-sensitive dielectric layer.

27. The semiconductor device structure of claim 26, wherein the second conductive line extends across the magnetic core.

28. The semiconductor device structure of claim 21, further comprising: a metallization structure on the portion of the second protective cap.

29. The semiconductor device structure of claim 28, further comprising: a conductive bump on the metallization structure.

30. The semiconductor device structure of claim 29, wherein the metallization structure and the conductive bump are partially on a top surface of the second photo-sensitive dielectric layer.

31. A semiconductor device structure, comprising: a first conductive line over a substrate, wherein the first conductive line has a first portion and a second portion connected to the first portion, and a line width of the second portion increases in a direction away from the first portion; a first protective cap over the first conductive line, wherein the first protective cap and the first conductive line are formed of different conductive materials, and the entire first protective cap is over the second portion, wherein the first protective cap exposes a ring-shaped area of a top surface of the second portion of the first conductive line; a first photo-sensitive dielectric layer over the substrate, the first conductive line, and the first protective cap; a via structure passing through the first photo-sensitive dielectric layer and connected to the first protective cap; a second conductive line over the via structure and the first photo-sensitive dielectric layer; and a second protective cap over the second conductive line, wherein the second protective cap and the second conductive line are formed of different conductive materials, and the first protective cap and the second protective cap are formed of the same material.

32. The semiconductor device structure of claim 31, further comprising: a second photo-sensitive dielectric layer over the first photo-sensitive dielectric layer, the second conductive line, and the second protective cap, wherein the second photo-sensitive dielectric layer exposes a portion of the second protective cap.

33. The semiconductor device structure of claim 32, further comprising: a conductive bump on the portion of the second protective cap, wherein the conductive bump is partially embedded in the second photo-sensitive dielectric layer.

34. The semiconductor device structure of claim 33, further comprising: a metallization structure between the conductive bump and the portion of the second protective cap, and between the conductive bump and the second photo-sensitive dielectric layer.

35. The semiconductor device structure of claim 32, wherein the second photo-sensitive dielectric layer includes sulfur.

36. A semiconductor device structure, comprising: ​ a first conductive line over a substrate, wherein the first conductive line has a first portion and a second portion connected to the first portion, and a line width of the second portion increases in a direction away from the first portion; a first protective cap over the first conductive line, and entirely over the second portion, wherein the first protective cap exposes a ring-shaped area of a top surface of the second portion of the first conductive line; a first photo-sensitive dielectric layer over the substrate, the first conductive line, and the first protective cap; a via structure through the first photo-sensitive dielectric layer, and connected to the first protective cap, wherein the first protective cap, the first conductive line, and the via structure are formed of different conductive materials; a second conductive line over the via structure and the first photo-sensitive dielectric layer; a second protective cap over the second conductive line, wherein the second protective cap and the second conductive line are formed of different conductive materials; and a second photo-sensitive dielectric layer over the first photo-sensitive dielectric layer, the second conductive line, and the second protective cap, wherein the second photo-sensitive dielectric layer directly contacts the second conductive line and the second protective cap, and the second photo-sensitive dielectric layer includes sulfur.

37. The semiconductor device structure of claim 36, wherein the second photo-sensitive dielectric layer exposes a central portion of the second protective cap, and covers a surrounding portion of the second protective cap.

38. The semiconductor device structure of claim 37, further comprising: a metallization structure conformally covering the central portion of the second protective cap and the second photo-sensitive dielectric layer.

39. The semiconductor device structure of claim 38, further comprising: a conductive bump over the metallization structure.

40. The semiconductor device structure of claim 36, wherein the first protective cap has a rectangular or hexagonal shape.

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