Integrated electronics for operation in variable temperature environments

Abstract

Embodiments of the present disclosure relate to integrated electronic devices suitable for operation in a variable temperature environment. An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region that receives a control voltage; a back gate that receives an adjustment voltage; a source / drain region that has a resistance portion; a first terminal that is coupled to a first voltage (e.g., a reference voltage) and is formed in the source / drain region and on a first side of the resistance portion; and a second terminal that generates a voltage representing the temperature of the integrated electronic device, the second terminal being formed in the source / drain region and on a second side of the resistance portion. An adjustment circuit generates the adjustment voltage to have a value that depends on the control voltage and the voltage generated by the second terminal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority from French patent application No. 1854829, filed on June 4, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to integrated circuits, particularly integrated circuits adapted for operation in variable temperature environments, and particularly to current management of such integrated circuits. Background Art

[0004] It is well known that the operation of integrated circuits can be affected by temperature changes. For example, the resistivity of silicon increases with temperature, which can cause the current value to drop during operation.

[0005] Furthermore, an increase in temperature may also increase the value of leakage current of components, typically transistors, which is particularly problematic in the case of devices having a large number of components.

[0006] Therefore, there is a need to obtain a device in which the effect of temperature on the operation and leakage current of the integrated circuit is reduced. Summary of the invention

[0007] According to one aspect, an integrated electronic device includes a silicon-on-insulator substrate and at least one MOS transistor formed in and on the substrate. The at least one MOS transistor includes a gate region configured to receive a control voltage; and a back gate configured to receive an adjustment voltage. The source region of the at least one MOS transistor includes a resistor portion. A first terminal configured to be linked to a reference voltage (e.g., ground) is located on a first side of the resistor portion, and a second terminal is formed on a second side of the resistor portion. The second terminal is configured to deliver a voltage whose value represents the temperature of the integrated electronic device.

[0008] The integrated electronic device comprises a regulating circuit configured to deliver a regulating voltage to the back gate, the value of the regulating voltage being dependent on the value of the control voltage and the value of the voltage delivered by the second terminal.

[0009] Therefore, the value of the operating current of at least one MOS transistor can be modulated depending on the temperature of the integrated electronic device, thereby advantageously making it possible to avoid excessive changes in the operating current of at least one MOS transistor or excessive increases in the leakage current of at least one MOS transistor.

[0010] The resistive portion may be covered by a line of gate material which is electrically isolated from the resistive portion by a dielectric material and which extends from the gate region perpendicular thereto while forming material continuity therewith. Thus, biasing of the gate and back gate can cause the resistance of the resistive portion to vary.

[0011] Thus, the resistance of the resistive portion may advantageously be controlled, in particular as a function of the temperature of the integrated electronic device, thereby advantageously allowing enhanced control of the operating current and the leakage current of the at least one MOS transistor.

[0012] The control voltage may have a first value (e.g., 1 volt) corresponding to an on-state of at least one MOS transistor and a second value (e.g., 0 volts) corresponding to an off-state of at least one MOS transistor. The adjustment circuit is configured to deliver the adjustment voltage to have a first state (e.g., a positive state) on the back gate when the control voltage has the first value, deliver the control voltage to have a second state (e.g., a negative state) on the back gate when the control voltage has the second value, and adjust the value of the adjustment voltage according to the temperature of the integrated electronic device.

[0013] The adjustment circuit may include a level shifter including an input coupled to a gate; and an output; and an additional transistor coupled between the output and the back gate of the level shifter. The gate of the additional transistor is coupled to the second terminal, and the output of the level shifter is configured to deliver a positive voltage if the voltage on the input is positive, and to deliver a negative voltage if the voltage on the input is zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other advantages and features will become apparent from a reading of the detailed description of entirely non-limiting embodiments and of the accompanying drawings, in which

[0015] Figure 1 is a top view of an electronic device according to the present disclosure;

[0016] Figure 2 yes Figure 1 Schematic diagram of the electronic device;

[0017] Figure 3 is a top view of another embodiment of an electronic device according to the present disclosure; and

[0018] Figure 4 yes Figure 3 Schematic diagram of the electronic device. DETAILED DESCRIPTION

[0019] Figure 1 and Figure 2 The integrated electronic device DIS is shown in FIG. Figure 2 This is a schematic diagram from an electrical point of view.

[0020] The electronic device DIS comprises a transistor TR, for example a MOS transistor formed on a silicon-on-insulator (SOI) type substrate, and an adjustment circuit MA, which is not shown in the figure for the sake of simplicity. Figure 1 Shown in.

[0021] The substrate is a semiconductor film which is positioned over a buried insulating layer (known to those skilled in the art by the term BOX ('buried oxide')), which itself is located over a carrier substrate (eg a semiconductor well).

[0022] The transistor TR includes a source semiconductor region S, a drain semiconductor region D, and a gate region G. The active region of the transistor TR is isolated from other components of the device by an isolation region TI (eg, a shallow trench isolation (STI) type isolation region).

[0023] Contacts (for example, contacts made of tungsten) are formed in respective regions of the transistor TR. In this case, the implanted regions of the contacts are silicided.

[0024] For example, in this case, the device DIS comprises several drain contacts CD, which are formed along the drain region D. In this case, the entire area of ​​the drain region is silicided, so that the resistance between two individual drain contacts is very low, close to zero.

[0025] The drain contacts CD are coupled to each other, for example, via metal tracks of an interconnect portion of the device.

[0026] The gate contacts CG are formed on either side of the gate region G and in this case, since the entire area of ​​the gate region is silicided, the resistivity between the contacts located on either side of the gate line is very low. This allows, among other things, uniform biasing of the gate region.

[0027] The gate contacts CG are also coupled to each other via metal tracks.

[0028] A well contact region RPC is formed within the isolation region TI and makes it possible to bias the well of the transistor TR, which then serves as a back gate of the transistor TR.

[0029] The well contact region RPC includes a plurality of well contacts CBG coupled to one another, and the entire area thereof is silicided.

[0030] The source region S includes two contacts on either side of the non-silicided resistance portion RS of the source region, the two contacts forming a first terminal B1 and a second terminal B2 and formed at two locations of the source region.

[0031] Therefore, the resistivity between the first terminal B1 and the second terminal B2 is larger, for example, in this case, of the order of 10 kΩ. The first terminal B1 and the second terminal B2 are not electrically coupled through the metal track of the interconnection part, as is the case with the drain contact CD, the gate contact CG and the well contact CBG.

[0032] like Figure 2 As shown, the transistor TR having the non-silicided portion RS may be functionally shown as two transistors TR1 and TR2 whose gates are coupled to each other, back gates BG are coupled to each other, drain regions are coupled to each other, and source regions are coupled to each other through the resistor RS.

[0033] In this case, the first terminal B1 is coupled to ground.

[0034] The transistor TR can be either in the off state, in which case the voltage VG on its gate G, or the control voltage, and the drain voltage VD are all equal to 0 volts, or in the on state, in which case the control voltage VG and the drain voltage VD are both equal to 1 volt.

[0035] When the transistor TR is in the on state, the first current I1 flows through the first transistor TR1 between the drain D and the first terminal B1 , that is, from the drain D to the ground.

[0036] In addition, the second current I2 flows through the second transistor TR2 between the drain D and the second terminal B2, and then flows from the second terminal B2 to the first terminal B1, that is, to the ground through the resistor RS.

[0037] It should be noted that in this case, for the sake of simplicity, the first current I1 and the second current I2 are used; in reality, the distribution of the current gradually changes along the substrate of the transistor TR.

[0038] Therefore, the voltage VS2 at the second terminal B2 depends on the value of the second current I2 and the value of the resistor RS.

[0039] Furthermore, since the resistor RS is a silicon part, its value depends inter alia on the temperature of the silicon and increases accordingly.

[0040] The voltage VS2 therefore depends on the temperature of the resistor RS and is therefore representative of the temperature of the device DIS.

[0041] When the transistor TR is in its off state, a leakage current can flow between the drain D and the source S of the transistor TR. This phenomenon can prove to be particularly disadvantageous when the device has a large number of transistors. In particular, the multiplied leakage current can lead to overheating of the device DIS through the Joule effect, in addition to generating additional consumption of the device DIS.

[0042] The value of leakage current within a transistor increases with temperature.

[0043] Therefore, by means of the leakage current flowing through the second transistor TR2 and the resistor RS, the temperature of the device DIS can be determined by reading the potential VS2 on the second terminal B2.

[0044] The adjustment circuit MA comprises an input terminal BE coupled to the gate contact CG of the transistor TR, an output terminal BS coupled to the well contact CBG, that is to say to the back gate of the transistor TR and capable of delivering the adjustment voltage VA, and a control terminal BCT coupled to the second terminal B2 and capable of receiving the voltage VS2.

[0045] The regulating circuit MA is configured to deliver a voltage having a first state (in this case a positive state) when the control voltage VG on the input terminal BE has a first value (in this case 1 Volt), that is, when the transistor TR is in the on-state. The regulating circuit MA is configured to deliver a voltage having a second state (in this case a negative state) when the control voltage VG on the input terminal BE has a second value (in this case 0 Volt), that is, when the transistor TR is in the off-state.

[0046] The adjustment circuit MA comprises, for example, a level shifter CN comprising an input, which forms an input terminal BE of the adjustment circuit MA, and an output terminal SS.

[0047] The level shifter CN is configured to transmit a high state (in this case a voltage of 1 volt) at its output terminal SS when it receives a high state (that is, a positive voltage value); and to transmit a low state (for example, a voltage of -1 volt) at its output terminal SS when it receives a zero state (that is, a voltage on the input terminal BE whose value is equal to 0 volts).

[0048] The third transistor TR3 (for example, a MOS transistor in this case) has a first terminal, which is coupled to the output terminal SS of the level shifter; a second terminal, which is coupled to the output terminal BS of the adjustment circuit MA, that is, coupled to the back gate of the transistor TR; and its gate, which is coupled to the control terminal BCT, that is, coupled to the second terminal B2.

[0049] Thus, when the transistor TR is in the conducting state, the input terminal BE receives a voltage of 1 volt and the shifter delivers a voltage of 1 volt at its output SS.

[0050] Furthermore, since the gate of the third transistor is coupled to the second terminal B2 , the resistance of the third transistor in the on-state is proportional to the voltage VS2 on the second terminal and therefore proportional to the temperature of the device DIS.

[0051] The regulating circuit is therefore configured in this case to deliver a positive voltage between 0 and 1 Volt at the output terminal BS, the value of which depends on the voltage VS2 and therefore on the temperature of the device DIS.

[0052] The higher the temperature, the closer the voltage delivered by the regulating circuit MA is to 1 Volt, and the lower the temperature, the closer the voltage delivered by the regulating circuit MA is to 0 Volt.

[0053] The regulating voltage VA delivered by the regulating circuit MA on the back gate BG of the transistor TR thus regulates the value of the current flowing in the transistors, in particular the value of the second current I2 flowing in the second transistor TR2 , and thus makes it possible to compensate for variations in the second current I2 .

[0054] In other words, the decrease in the value of the second current I2 due to the increase in temperature of the device DIS is compensated by biasing the back gate BG of the transistor with a positive voltage which tends to increase the value of the second current I2.

[0055] Thus, the normal (that is to say unaffected) operating temperature range of the device DIS is advantageously increased.

[0056] By way of indication, it has been observed that, according to this embodiment and for a temperature range from 173 to 473 degrees Kelvin, the variation in the current value is less than 5%, whereas in conventional integrated circuits it is between 10% and 15%.

[0057] Since transistors TR1 and TR2 are on the same active silicon, the first current I1 is also affected by the bias of the back gate.

[0058] When the transistor TR is in the off state, the level shifter CN delivers a negative voltage (in this case a voltage of -1 Volt) at its output terminal SS.

[0059] Thus, in operation similar to that described above, the higher the temperature of the device DIS, the more the regulation circuit will deliver a voltage closer to -1 volt on the back gate BG, and the lower the temperature, the more the regulation circuit will deliver a voltage closer to 0 volts.

[0060] Therefore, the increase in the value of the leakage current due to the increase in the temperature of the device DIS is compensated by biasing the back gate BG of the transistor with a negative voltage.

[0061] By way of indication, it has been observed that, according to this embodiment and for a temperature range ranging from 173 to 473 degrees Kelvin, the value of the leakage current can be reduced by 75% compared to an integrated circuit from the prior art.

[0062] Figure 3 and Figure 4 An alternative embodiment of a device DIS is illustrated, wherein Figure 4 This is a schematic diagram from an electrical point of view.

[0063] In this embodiment, the non-silicided portion RS is coated with a gate material extension EX extending from the gate region G perpendicular thereto into the source region S. The extension EX is electrically isolated from the non-silicided portion RS by a dielectric material such as a gate oxide.

[0064] Therefore, if Figure 4 As shown, this embodiment corresponds electrically to replacing the resistor RS with the fourth transistor TR4.

[0065] The fourth transistor TR4 is coupled between the first terminal B1 and the second terminal B2 , and has its gate electrically coupled to the gate G of the transistor TR, and its back gate BG coupled to the back gate of the transistor TR.

[0066] Therefore, when the transistor TR operates, the fourth transistor TR4 is in a turned-on state, and its back gate receives the adjustment voltage VA.

[0067] When the temperature of the device DIS increases, the resistivity in the on-state of the fourth transistor TR4 tends to increase on the one hand due to the temperature increase and on the other hand tends to decrease due to the bias of its back gate.

[0068] Therefore, the value of the current I2 is stable and has an even higher accuracy.

[0069] When the transistor TR is in the off state, the fourth transistor is also in the off state and acts like a resistor of very high value.

[0070] This is sufficient to significantly reduce the leakage current within the device DIS when the transistor TR is in the off-state, without interrupting the operation of the transistor TR in the on-state.

[0071] It should be noted that the position of the extension portion EX is not limited to Figure 3 Specifically, the extension EX may be formed closer to or farther from the first terminal B1 or closer to or farther from the second terminal B2, depending on whether it is desired to give priority to reducing the leakage current or to give priority to stabilizing the second current I2.

Claims

1. An integrated electronic device comprising: Silicon-on-insulator substrates, at least one MOS transistor formed in and on the silicon-on-insulator substrate; wherein the at least one MOS transistor comprises: a gate region configured to receive a control voltage; a back gate configured to receive an adjustment voltage; a source or drain region having a resistive portion; a first terminal configured to be coupled to a first voltage and formed in the source or drain region and on a first side of the resistive portion of the source or drain region; and a second terminal configured to generate a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source or drain region and on a second side of the resistive portion of the source or drain region; and The adjustment circuit is configured to generate the adjustment voltage to have a value depending on the control voltage and the voltage generated by the second terminal.

2. An integrated electronic device according to claim 1, wherein the resistance portion is covered by a gate material line, which is electrically isolated from the resistance portion by a dielectric material and extends from the gate region while forming material continuity with the gate region, wherein the resistance of the resistance portion varies depending on the bias of the gate region and the back gate.

3. The integrated electronic device of claim 2, wherein the gate material line extends vertically from the gate region.

4. The integrated electronic device of claim 1 , wherein the control voltage has a first value when the at least one MOS transistor is in an on state, and the control voltage has a second value when the at least one MOS transistor is in an off state; and wherein the adjustment circuit is configured to generate the adjustment voltage to have a first state when the control voltage has the first value, and to generate the adjustment voltage to have a second state when the control voltage has the second value, and wherein the adjustment circuit is further configured to adjust the adjustment voltage according to the voltage representing the temperature of the integrated electronic device.

5. An integrated electronic device according to claim 1, wherein the adjustment circuit includes a level shifter, the level shifter having an input and an output, the input being coupled to the gate region; and further comprising a transistor, the transistor being coupled between the output of the level shifter and the back gate of the at least one MOS transistor, the transistor having a gate, the gate being coupled to the second terminal; wherein the output of the level shifter is configured to generate a positive voltage if the voltage on the input of the level shifter is positive, and to generate a negative voltage if the voltage on the input of the level shifter is zero.

6. The integrated electronic device of claim 1, wherein the resistive portion has a non-silicided upper surface.

7. The integrated electronic device of claim 1, wherein the first voltage is a reference voltage.

8. The integrated electronic device of claim 1, wherein the source or drain region is a source region.

9. An electronic device comprising: Silicon-on-insulator substrate; A pair of MOS transistors is formed in and on the silicon-on-insulator substrate, wherein the pair of MOS transistors comprises: a common source region divided into a first source region and a second source region connected by a resistance portion of the common source region; A common drain region is formed to form a first connected drain region and a second connected drain region; A shared back gate region is formed to form a first connected back gate region and a second connected back gate region that receive an adjustment voltage; A common gate region forms a first connection gate region and a second connection gate region and receives a control voltage; a first terminal configured to be coupled to a reference voltage and formed in the second source region; and a second terminal configured to generate a voltage representative of a temperature of the electronic device, the second terminal being formed in the first source region; and The adjustment circuit is configured to generate the adjustment voltage to have a value depending on the control voltage and the voltage generated by the second terminal.

10. An electronic device according to claim 9, wherein the resistance portion is covered by a gate material line, which is electrically isolated from the resistance portion by a dielectric material and extends from the common gate region across the common source region while forming material continuity with the common gate region, wherein the resistance of the resistance portion varies depending on the bias of the common gate region and the common back gate region.

11. The electronic device of claim 10, wherein the gate material line extends vertically from the common gate region, spanning across and bisecting the common source region.

12. An electronic device comprising: a first transistor having a drain; A source coupled to a reference voltage; a gate coupled to a control voltage; and a back gate receiving an adjustment voltage; a second transistor having a drain coupled to the drain of the first transistor; a source coupled to the source of the first transistor through a resistor; a gate coupled to the control voltage; and a back gate receiving the adjustment voltage; a third transistor, the third transistor having a source electrode for generating the adjustment voltage; and a drain electrode; and a gate coupled to the source of the second transistor; as well as a level shifter having an input coupled to the gates of the first transistor and the second transistor; and an output coupled to the drain of the third transistor.

13. An electronic device according to claim 12, wherein the level shifter is configured to generate a positive voltage at the output of the level shifter if the voltage at the input of the level shifter is positive, and to generate a negative voltage at the output of the level shifter if the voltage at the input of the level shifter is zero. 14 . The electronic device of claim 12 , wherein the third transistor generates the adjustment voltage to have a first state when the first transistor is turned on, and the third transistor generates the adjustment voltage to have a second state when the first transistor is turned off. 15 . The electronic device according to claim 12 , wherein the third transistor generates the adjustment voltage according to a source voltage of the second transistor.

16. An electronic device comprising: a first transistor having a drain; A source coupled to a reference voltage; a gate coupled to a control voltage; and a back gate receiving an adjustment voltage; a second transistor having a drain coupled to the drain of the first transistor; source; a gate coupled to the control voltage; and a back gate receiving the adjustment voltage; a third transistor, the third transistor having a source electrode for generating the adjustment voltage; and a drain electrode; and a gate coupled to the source of the second transistor; a fourth transistor having a drain coupled to the source of the second transistor; a source coupled to a source of the first transistor; a gate coupled to the control voltage; and a back gate receiving the adjustment voltage; as well as a level shifter having an input coupled to the gates of the first transistor, the second transistor, and the third transistor; and an output coupled to the drain of the third transistor.

17. An electronic device according to claim 16, wherein the level shifter is configured to generate a positive voltage at the output of the level shifter if the voltage at the input of the level shifter is positive, and to generate a negative voltage at the output of the level shifter if the voltage at the input of the level shifter is zero. 18 . The electronic device of claim 16 , wherein the third transistor generates the adjustment voltage to have a first state when the first transistor is turned on, and the third transistor generates the adjustment voltage to have a second state when the first transistor is turned off.

19. The electronic device according to claim 16, wherein the third transistor generates the adjustment voltage according to a source voltage of the second transistor.

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