Semiconductor device with gate isolation layer and method for manufacturing the same

Abstract

A semiconductor device is provided. The semiconductor device includes a channel region protruding from a substrate. The semiconductor device includes a gate line on the channel region. In addition, the semiconductor device includes a gate isolation layer located between a first portion of the gate line and a second portion of the gate line. The gate isolation layer contacts the gate line and includes a gap in the gate isolation layer. A related method for manufacturing the semiconductor device is also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0067407 filed on June 12, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As the integration density of semiconductor devices increases, fin field effect transistors (FinFETs) with three-dimensional (3D) structures (which can replace two-dimensional (2D) transistors) have been developed to overcome the limitations of FETs in related art. In addition, in order to protect the gate insulation layer that is susceptible to subsequent annealing processes, a replacement metal gate (RMG) process that forms a dummy gate and then forms a gate has recently been used. A gate isolation layer configured to separate gate lines can be provided in a FinFET. As semiconductor devices are reduced in size to achieve high integration, the capacitance caused by the gate isolation layer may increase undesirably. Summary of the invention

[0005] Example embodiments of the inventive concepts are directed to providing a semiconductor device including a gate line formed using a replacement metal gate (RMG) process, in which a gate isolation layer includes an air gap to reduce capacitance.

[0006] In addition, example embodiments of the inventive concepts are directed to providing a semiconductor device in which a middle critical dimension (MCD) of a gate isolation layer is greater than a top critical dimension (TCD) thereof.

[0007] Furthermore, example embodiments of the inventive concepts are directed to providing a method of manufacturing a semiconductor device, wherein a gate isolation layer includes an air gap.

[0008] According to example embodiments, a semiconductor device may include a first channel region and a second channel region protruding from a substrate and extending in a first direction. The semiconductor device may include a first gate on the first channel region. The semiconductor device may include a second gate on the second channel region. The first gate and the second gate may extend in a second direction intersecting the first direction and may be spaced apart from each other in the second direction. The semiconductor device may include a first gate insulating layer between the first gate and the first channel region. The semiconductor device may include a second gate insulating layer between the second gate and the second channel region. In addition, the semiconductor device may include a gate isolation layer between the first gate and the second gate. The gate isolation layer may contact the first gate and the second gate and may include a gap in the gate isolation layer. A first width of the gate isolation layer in the second direction may be greater than a second width of the gate isolation layer in the second direction. A third width of the gate isolation layer in the second direction may be less than the first width of the gate isolation layer. In a third direction perpendicular to the first direction and the second direction, the first width may be between the second width and the third width.

[0009] According to example embodiments, a semiconductor device may include a substrate including a channel region protruding from the substrate. The semiconductor device may include a gate line on a first side surface and a second side surface of the channel region. The semiconductor device may include a gate spacer on a first side surface and a second side surface of the gate line. In addition, the semiconductor device may include a gate isolation layer in a gate cut region, the gate isolation layer separating a first portion of the gate line from a second portion of the gate line. The gate isolation layer may contact the gate line and may include a gap in the gate isolation layer. The first width of the gap may be greater than the second width of the gap. The third width of the gap may be narrower than the first width. The first width may be between the second width and the third width.

[0010] According to example embodiments, a semiconductor device may include a substrate including a channel region protruding from the substrate and extending in a first direction. The semiconductor device may include a first gate line and a second gate line extending on the channel region and in a second direction intersecting the first direction. The first gate line may be spaced apart from the second gate line in the first direction. The semiconductor device may include a gate spacer located on a first side surface and a second side surface of the first gate line. The semiconductor device may include a gate insulating layer located between the first gate line and the gate spacer. The semiconductor device may include a gate isolation layer in a gate cut region located between the first gate line and the second gate line in the first direction. In addition, the semiconductor device may include a gap in the gate isolation layer. The gate cut region may separate the first gate line, the separation gate insulating layer, and the separation gate spacer. The gate isolation layer may contact the first gate line. The first width of the gate isolation layer may be greater than the second width and the third width of the gate isolation layer, and is located between the second width and the third width of the gate isolation layer.

[0011] According to example embodiments, a method for manufacturing a semiconductor device may include forming a plurality of channel regions and a device isolation layer. The plurality of channel regions may protrude from a substrate, and the device isolation layer may be in a groove between the plurality of channel regions. The method may include forming a dummy gate structure on the plurality of channel regions and the device isolation layer. The method may include forming an interlayer insulating layer on a first side and a second side of the dummy gate structure, on the plurality of channel regions and the device isolation layer. The method may include removing the dummy gate structure to form a gate opening. The method may include forming a gate structure including a gate line in the gate opening. The method may include forming a gate cutout region that divides the gate line into a plurality of gates. In addition, the method may include forming a gate isolation layer in the gate cutout region. The gate isolation layer may include a gap in the gate isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view of main components of a semiconductor device according to some example embodiments.

[0013] Figure 2 It is along Figure 1 A sectional view taken along line II' of the plan view.

[0014] Figure 3 It is along Figure 1 A sectional view taken along line II-II' of the plan view.

[0015] Figure 4 It is along Figure 1 A sectional view taken along line III-III' of the plan view.

[0016] Figures 5 to 8 is a method according to some example embodiments corresponding to Figure 2 sectional view of .

[0017] Figures 9 to 28 are cross-sectional views and plan views according to sequential process operations for describing a method of fabricating a semiconductor device according to some example embodiments, wherein Figure 12 to Figure 14 Along the Fig.11 The cross-sectional views taken along the lines II-I', II-II' and III-III', Figures 16 to 18 is a cross-sectional view taken along line II', Fig. 20 and Fig.21 Along the Fig.19 The cross-sectional view taken along the lines I-I' and III-III', Fig.23 and Fig.24 Along the Fig. 22 A cross-sectional view taken along lines I-I' and III-III', and Fig.26 and Fig. 27 Along the Fig.25 Cross-sectional views taken along lines II' and III-III'.

[0018] Figure 29 to Figure 32 is a method according to some example embodiments corresponding to Figure 1 sectional view of . DETAILED DESCRIPTION

[0019] Figure 1 is a plan view of main components of a semiconductor device 100 according to some exemplary embodiments, and Figures 2 to 4 Along the Figure 1 Cross-sectional views taken along lines II', II-II' and III-III'.

[0020] refer to Figures 1 to 4 , the semiconductor device 100 of the present invention may include a substrate 102, a channel pattern 110 (e.g., a channel region) and a device isolation layer 120. In addition, the semiconductor device 100 may include a first gate insulating layer 130A, a second gate insulating layer 130B, an interlayer insulating layer 140, a first gate 150A, a second gate 150B, a first capping layer 160A and a second capping layer 160B on the channel pattern 110 and the device isolation layer 120. The semiconductor device 100 of the present invention may also include a gate isolation layer 170 and an air gap 180. The semiconductor device 100 according to an example embodiment of the present invention may include a fin field effect transistor (FinFET). The FinFET may be an NMOS transistor or a PMOS transistor.

[0021] Hereinafter, the first direction D1 will refer to a direction in which the channel pattern 110 extends. The second direction D2 will refer to a direction perpendicular to the first direction D1 and parallel to the gate line 150 (eg, see Fig.19 ). The third direction D3 will refer to a direction perpendicular to the first direction D1 and the second direction D2 and perpendicular to a main (eg, top) surface of the substrate 102 .

[0022] In some embodiments, the substrate 102 may include: a semiconductor including silicon (Si) or germanium (Ge), a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs) or gallium indium phosphide (GaInP), or a combination thereof. In some embodiments, the substrate 102 may be a silicon-on-insulator (SOI) substrate or an amorphous substrate.

[0023] The channel pattern 110 may be formed to extend in the first direction D1. In some embodiments, the channel pattern 110 may include the same material as the substrate 102 and may be formed to protrude from the substrate 102 in the third direction D3. For example, the channel pattern 110 may have a fin shape. In addition, the channel pattern 110 may be doped with n-type impurities or p-type impurities. Figure 2 As shown, four channel patterns 110 may be formed, but the inventive concept is not limited thereto.

[0024] The device isolation layer 120 may be formed on (e.g., covers) the top surface of the substrate 102 and the side surfaces of the channel pattern 110. In addition, the device isolation layer 120 may be located in (e.g., may fill) the trench between the channel patterns 110. The top end / surface of the device isolation layer 120 may be at a lower level than the top end / surface of the channel pattern 110, and the device isolation layer 120 may not cover the upper portion of the channel pattern 110. The device isolation layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0025] The first gate insulating layer 130A and the second gate insulating layer 130B may be formed to extend in the second direction D2. The first gate insulating layer 130A and the second gate insulating layer 130B may be on (e.g., may cover) a surface (e.g., an upper surface) of the channel pattern 110 and the device isolation layer 120. Although the first gate insulating layer 130A and the second gate insulating layer 130B are formed as straight lines, the first gate insulating layer 130A and the second gate insulating layer 130B may be spaced apart from each other using a gate isolation layer 170 interposed between the first gate insulating layer 130A and the second gate insulating layer 130B. The first gate insulating layer 130A and the second gate insulating layer 130B may be spaced apart by separating the gate insulating layer (reference numeral 170) to be described below. Fig.19 Hereinafter, the gate insulating layer 130 will refer to a first gate insulating layer 130A and a second gate insulating layer 130B formed as a straight line.

[0026] The first gate insulating layer 130A may be located on (e.g., may cover) a portion of the first gate 150A. In some embodiments, the first gate insulating layer 130A may not be on (e.g., may not cover) the inner side surface IA of the first gate 150A, and the first gate insulating layer 130A may be on (e.g., may cover) the first side surface W1A and the second side surface W2A of the first gate 150A. The second gate insulating layer 130B may be located on (e.g., may cover) a portion of the second gate 150B. In some embodiments, the second gate insulating layer 130B may not be on (e.g., may not cover) the inner side surface IB of the second gate 150B, and the second gate insulating layer 130B may be on (e.g., may cover) the first side surface W1B and the second side surface W2B of the second gate 150B.

[0027] Here, the inner side surface IA of the first gate 150A and the inner side surface IB of the second gate 150B may respectively refer to surfaces of the first gate 150A and the second gate 150B facing the gate isolation layer 170. The first side surfaces W1A and W1B and the second side surfaces W2A and W2B of the first gate 150A and the second gate 150B may refer to surfaces of the first gate 150A and the second gate 150B orthogonal to the first direction D1.

[0028] The first gate insulating layer 130A and the second gate insulating layer 130B may include silicon oxide, silicon nitride, a high-k dielectric material, or a combination thereof. The high-k dielectric material may include hafnium oxide (HfO 2 ), hafnium silicon oxynitride (HfSiON), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), barium titanate (BaTiO 3 ), Tantalum pentoxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), strontium titanate (STO), zirconium oxide, aluminum oxide or a combination thereof.

[0029] An interlayer insulating layer 140 may be formed on the device isolation layer 120. The interlayer insulating layer 140 may be located (eg, may fill) in a space between the channel patterns 110 and a space between the first gate 150A and the second gate 150B. The interlayer insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0030] The first gate 150A and the second gate 150B may be formed on the substrate 102 to extend in the second direction D2. The first gate 150A and the second gate 150B may be disposed across the channel pattern 110. For example, the first gate 150A and the second gate 150B may be on (eg, may cover) the top surface and both side surfaces of the channel pattern 110 on the device isolation layer 120.

[0031] The first gate 150A and the second gate 150B can be separated by a gate line 150 (refer to Fig.19 150 in. Although the first gate 150A and the second gate 150B are formed as a straight line, the first gate 150A and the second gate 150B may be arranged to be spaced apart from each other using a gate isolation layer 170 inserted between the first gate 150A and the second gate 150B. Hereinafter, the gate line 150 will be interpreted as including the first gate 150A and the second gate 150B, which are arranged as a straight line and may be referred to as the first part and the second part of the gate line 150 in this article. The first gate 150A and the second gate 150B may be formed using a replacement metal gate (RMG) process and a gate cutting process. The first gate insulating layer 130A may not be formed on the inner side surface IA of the first gate 150A, and the inner side surface IA of the first gate 150A may be in physical contact with the gate isolation layer 170. In addition, the second gate insulating layer 130B may not be formed on the inner side surface IB of the second gate 150B, and the inner side surface IB of the second gate 150B may be in physical contact with the gate isolation layer 170.

[0032] Each of the first gate 150A and the second gate 150B may include a metal. For example, each of the first gate 150A and the second gate 150B may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminide (TiAl), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), or a combination thereof.

[0033] The first gate spacer 152A and the second gate spacer 152B may extend in the second direction D2 and be formed on the first side surfaces W1A and W1B and the second side surfaces W2A and W2B of the first gate 150A and the second gate 150B. Figure 1As shown, the first gate insulating layer 130A may be disposed between the first gate spacer 152A and the first gate 150A. Similarly, the second gate insulating layer 130B may be disposed between the second gate spacer 152B and the second gate 150B. The first gate spacer 152A and the second gate spacer 152B may be spaced apart by a gate isolation layer 170 interposed between the first gate spacer 152A and the second gate spacer 152B.

[0034] The first gate spacer 152A and the second gate spacer 152B may be separated by a gate spacer (refer to Fig.19 The gate spacer 152 may be a first gate spacer 152A and a second gate spacer 152B arranged in a straight line. The first gate spacer 152A and the second gate spacer 152B may include silicon nitride, silicon carbonitride, silicon oxynitride or a combination thereof.

[0035] The first capping layer 160A and the second capping layer 160B may extend in the second direction D2 and be formed on the first gate 150A and the second gate 150B, respectively. Figure 3 As shown, the first capping layer 160A may be disposed between the first gate spacers 152A. Similarly, the second capping layer 160B may be disposed between the second gate spacers 152B. The top surface of the first capping layer 160A and the top surface of the second capping layer 160B may be at the same level as (i.e., may be coplanar with) the top surface of the first gate spacer 152A and the top surface of the second gate spacer 152B, respectively. The first capping layer 160A and the second capping layer 160B may be separated by the capping layer (refer to Fig. 20 The capping layer 160 may refer to a first capping layer 160A and a second capping layer 160B arranged in a straight line. The first capping layer 160A and the second capping layer 160B may include silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, or a combination thereof.

[0036] The gate isolation layer 170 may be disposed between the first gate 150A and the second gate 150B. The gate isolation layer 170 may be formed to pass through the capping layer 160 and extend in the third direction D3. The bottom end of the gate isolation layer 170 may be at the same level (e.g., may be in physical contact) with the top end of the device isolation layer 120. The gate isolation layer 170 may be in physical contact with the inner side surface IA of the first gate 150A and the inner side surface IB of the second gate 150B. The insulating material may not be disposed between the gate isolation layer 170 and the first gate 150A. Similarly, the insulating material may not be disposed between the gate isolation layer 170 and the second gate 150B.

[0037] The gate isolation layer 170 may have a first width, which may be a middle critical dimension (MCD) greater than a second width, which may be a top critical dimension (TCD) thereof. In addition, the gate isolation layer 170 may have a third width, which may be a bottom critical dimension (BCD) less than its MCD thereof. The BCD of the gate isolation layer 170 may be equal to or greater than its TCD thereof. Here, TCD may refer to a CD (critical dimension) of a point of the gate isolation layer 170 corresponding to the bottom end of the first capping layer 160A or the second capping layer 160B, and MCD may refer to a CD of a point of the gate isolation layer 170 between the TCD and the BCD of the gate isolation layer 170.

[0038] The gate isolation layer 170 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. Since the MCD of the gate isolation layer 170 is greater than the TCD of the gate isolation layer 170, the gate isolation layer 170 may have a larger volume than when the gate isolation layer 170 is etched to have a uniform CD. The gate isolation layer 170 may increase the spacing between the first gate 150A and the second gate 150B to reduce capacitance, so that the first gate 150A and the second gate 150B may be more effectively insulated from each other.

[0039] like Figure 1 As shown, the gate isolation layer 170 may be disposed in a gate cutout 175 (e.g., a gate cutout region). The gate cutout 175 may be formed in the gate line 150. The gate cutout 175 may be formed by etching the gate line 150 and the interlayer insulating layer 140 along the third direction D3. The gate cutout 175 may be formed not only in the gate line 150, but also in the gate insulating layer 130 and the gate spacer 152. The gate cutout 175 may be formed to have a greater width than the width of the first gate 150A and the second gate 150B in the first direction D1. Therefore, the gate cutout 175 may be fully filled with an insulating material, and the capacitance may be reduced, so that the first gate 150A may be more effectively insulated from the second gate 150B.

[0040] Due to the etching selectivity between the gate line 150 and the interlayer insulating layer 140, a portion of the gate cutout 175 that may overlap the gate line 150 may be formed to be larger than a portion of the gate cutout 175 that may overlap the interlayer insulating layer 140. Figure 1 As shown, a first CD GC1 of the gate cut 175 formed on the gate line 150 may be greater than a second CD GC2 of the gate cut 175 formed on the interlayer insulating layer 140 between the gate lines 150. In some embodiments, the gate cut 175 may have a scallop shape with a narrow portion when viewed from above.

[0041] The air gap 180 may be formed in the gate isolation layer 170. The air gap 180 may have a low dielectric constant and improve the insulation effect of the gate isolation layer 170. The air gap 180 may have a circular shape, an elliptical shape, or another shape. The top TA of the air gap 180 may be at a higher level than the top of the channel pattern 110. Although Figure 2 An example is shown in which the top end TA of the air gap 180 is at a lower level than the top end of the first gate 150A and the top end of the second gate 150B, but in some embodiments, the top end TA of the air gap 180 may be at a higher level than the top ends of the first gate 150A and the second gate 150B. The bottom end of the air gap 180 may be at a higher level than the top end of the device isolation layer 120. The air gap 180 may have a profile similar to that of the gate isolation layer 170. Figure 2 As shown, the air gap 180 may have an elliptical shape having a minor axis in the second direction D2.

[0042] like Figure 1 As shown, an air gap 180 may be formed at an intersection between the gate isolation layer 170 and the gate line 150. The air gap 180 may not be formed in a portion of the gate isolation layer 170 disposed between the interlayer insulating layers 140.

[0043] In addition, although air gaps have been discussed herein by way of example, any gap may be used according to embodiments of the present inventive concept. A gap may be defined, for example, as any void, cavity, or unobstructed space, and may be a gap filled with air (e.g., air gap 180), a gap filled with an inert gas or gas (e.g., an inert gas gap), a gap defining a vacuum (e.g., a vacuum gap), etc.

[0044] Figures 5 to 8 is a cross-sectional view according to some exemplary embodiments. Figure 2 Detailed description of the same components in .

[0045] refer to Figure 5 In the semiconductor device 200 according to some example embodiments, an upper portion of the device isolation layer 120 may be partially removed to form a recess. A portion of the gate isolation layer 270 may be formed in the recess. The bottom end of the gate isolation layer 270 may be at a lower level than the top end of the device isolation layer 120. The bottom end of the air gap 280 formed in the gate isolation layer 270 may be at the same level as the top end of the device isolation layer 120 or at a lower level than the top end of the device isolation layer 120.

[0046] Since the air gap 180 is formed by leaving air in the gate isolation layer 170 during the process of filling the gate cut 175 with the gate isolation layer 170, the air gap 180 may not be formed at the bottom end of the gate isolation layer 170. Figure 5 As shown, the bottom end of the gate isolation layer 270 may be formed at a lower level than the top end of the device isolation layer 120 , so that the bottom end of the air gap 280 may be at the same level as or lower than the top end of the device isolation layer 120 . Figure 5 The gate isolation layer 270 and the air gap 280 shown in FIG. 2 may more effectively insulate the first gate 150A and the second gate 150B from each other.

[0047] refer to Figure 6 In the semiconductor device 300 according to some example embodiments, the TCD of the gate isolation layer 370 may be smaller than its BCD, and the BCD of the gate isolation layer 370 may be larger than its MCD. For example, the CD of the gate isolation layer 370 may gradually increase from the top end of the gate isolation layer 370 toward the bottom end thereof (i.e., may gradually taper from the bottom end toward the top end).

[0048] The conventional gate cut is not formed to have a uniform CD, but is formed to have a gradually decreasing CD according to the etching depth. In this case, even if the gate isolation layer is formed, the bottom CD of the gate isolation layer may not be large enough. However, when the gate isolation layer is partially etched during the gate cutting process and then the process of depositing a passivation layer and etching the passivation layer again is repeatedly performed, the bottom CD of the gate isolation layer can be increased. For example, Figure 6 As shown, the CD of the gate isolation layer 370 may increase from the top end of the gate isolation layer 370 toward the bottom end thereof. The CD of the air gap 380 may also increase from the top end TA of the air gap 380 toward the bottom end BA thereof, so that the air gap 380 may have a triangular shape. According to some embodiments, the bottom end of the gate isolation layer 370 and the bottom end of the air gap 380 may be formed to be wide enough so that the first gate 150A and the second gate 150B may be more effectively insulated from each other.

[0049] refer to Figure 7 In the semiconductor device 400 according to some example embodiments, the TCD of the gate isolation layer 470 may be smaller than its MCD, and the MCD of the gate isolation layer 470 may be larger than its BCD. The gate isolation layer 470 may have a narrow portion whose CD is smaller than the CD of other portions. For example, the gate isolation layer 470 may have a scallop shape. As an example, the sidewall of the gate isolation layer 470 may include a plurality of protrusions (e.g., a top protrusion, a middle protrusion, and a bottom protrusion) protruding in the second direction D2.

[0050] The gate cutting process may further include a process of depositing a passivation layer to increase the MCD of the gate isolation layer 470. According to the above process, the gate isolation layer 470 may be formed to have an MCD greater than a TCD, so that the gate isolation layer 470 may have a Figure 7The scallop shape shown. Since the MCD of the gate isolation layer 470 is greater than its TCD or bottom CD, the first gate 150A and the second gate 150B can be more effectively insulated from each other. In addition, the air gap 480 can be in the gate isolation layer 470.

[0051] refer to Figure 8 In the semiconductor device 500 according to some example embodiments, an air gap 580 may be formed in the gate isolation layer 570. The top end of the air gap 580 may be at a higher level than the top end of the first gate 150A and the top end of the second gate 150B. In some embodiments, the top end of the air gap 580 may be at a higher level than the bottom end of the first capping layer 160A and the bottom end of the second capping layer 160B. In order to form the top end of the air gap 580 at a high level, the width BW between the bottom end of the first capping layer 160A and the bottom end of the second capping layer 160B may be greater than the width TW between the top ends of the first capping layer 160A and the second capping layer 160B.

[0052] When the thickness of the first capping layer 160A and the second capping layer 160B is large enough, the air gap 580 may not be exposed even if the upper portions of the first capping layer 160A and the second capping layer 160B are partially removed using a planarization process. Figure 8 As shown, the air gap 580 may be formed at a higher level than top ends of the first gate 150A and the second gate 150B, so that the first gate 150A and the second gate 150B may be more effectively insulated from each other.

[0053] Figures 9 to 28 1 is a cross-sectional view and a plan view showing sequential process operations for describing a method of manufacturing a semiconductor device 100 according to some example embodiments. Figures 9 to 28 Description Manufacturing Figures 1 to 4 An example method for a semiconductor device as shown in FIG.

[0054] refer to Fig. 9 , the substrate 102 may be partially etched to form a channel pattern 110. The channel pattern 110 may be formed to protrude from the substrate 102 in the third direction D3 and extend in the first direction D1. The width of the channel pattern 110 may gradually decrease upward. Fig. 9 As shown, the top end of the channel pattern 110 may have a rounded rectangular shape. The channel pattern 110 may be used for a p-type FinFET or an n-type FinFET.

[0055] The pad layer 112 and the mask layer 114 may be formed on the top of the channel pattern 110. In some embodiments, the pad layer 112 may include silicon oxide. The pad layer 112 may be formed by thermally oxidizing the silicon substrate 102 or using a chemical vapor deposition (CVD) process. The mask layer 114 may include silicon nitride and be formed using a CVD process.

[0056] refer to Fig.10 , a device isolation layer 120 may be formed on (eg, cover) a top surface of the substrate 102 and side surfaces of the channel pattern 110. The device isolation layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0057] In some embodiments, an etchback process may be used to partially remove the device isolation layer 120 to expose an upper portion of the channel pattern 110. First, the device isolation layer 120 may be formed to completely cover the substrate 102 and the channel pattern 110. After the device isolation layer 120 is formed, a planarization operation may be performed to remove an upper portion of the device isolation layer 120 as well as the pad layer 112 and the mask layer 114. Next, as shown in FIG. Fig.10 As shown, the device isolation layer 120 may be further removed / reduced to expose an upper portion of the channel pattern 110 .

[0058] Fig.12 It is along Fig.11 A cross-sectional view taken along line II'. Fig.13 It is along Fig.11 A cross-sectional view taken along line II-II'. Fig.14 It is along Fig.11 A cross-sectional view taken along line III-III'.

[0059] refer to Figures 11 to 14 , a dummy gate structure may be formed on the channel pattern 110 and the device isolation layer 120. The dummy gate structure may include a dummy gate insulating layer 132, a dummy gate line 154, and a dummy capping layer 162. The dummy gate insulating layer 132 may include silicon oxide and be formed using a CVD process or an atomic layer deposition (ALD) process. The dummy gate line 154 may include polysilicon (ploy-Si). The dummy capping layer 162 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0060] First, a dummy gate insulating layer 132 may be formed on the channel pattern 110 and the device isolation layer 120. Thereafter, a dummy gate line 154 and a dummy capping layer 162 may be formed on the dummy gate insulating layer 132. A gate spacer 152 may be formed on both sidewalls of the dummy gate line 154. The gate spacer 152 may include silicon nitride, silicon oxynitride, or a combination thereof.

[0061] In some embodiments, source and drain regions may be formed on both sides of the dummy gate line 154 along the channel pattern 110. The source and drain regions may be disposed at a higher level than the channel pattern 110.

[0062] First, the exposed portion of the channel pattern 110 not covered by the dummy gate line 154 can be removed to form a recess. Then, a source region and a drain region can be formed in the recess using an epitaxial growth process. In some embodiments, the source region and the drain region for a p-type FinFET can include silicon germanium. In addition, in some embodiments, the source region and the drain region for an n-type FinFET can include silicon carbide, silicon phosphide, etc.

[0063] Thereafter, an interlayer insulating layer 140 may be formed on (eg, covering) an upper portion of the channel pattern 110 and the device isolation layer 120 and a space between the dummy gate lines 154. The interlayer insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0064] Fig.16 It is along Fig.15 A cross-sectional view taken along line II'. Fig.17 It is along Fig.15 A cross-sectional view taken along line II-II'. Fig.18 It is along Fig.15 A cross-sectional view taken along line III-III'.

[0065] refer to Figures 15 to 18 , the dummy gate insulating layer 132, the dummy gate line 154, and the dummy capping layer 162 may be removed. The interlayer insulating layer 140 and the gate spacer 152 may be retained. The removal process may be performed using a dry etching process or a wet etching process, and a gate opening 155 may be formed between the gate spacers 152. The removal process may be performed using a dry etching process or a wet etching process.

[0066] Fig. 20 It is along Fig.19 A cross-sectional view taken along line II'. Fig.21 It is along Fig.19 A cross-sectional view taken along line III-III'.

[0067] refer to Figures 19 to 21 , a gate structure may be formed on the channel pattern 110 and the device isolation layer 120. The gate structure may include a gate insulating layer 130, a gate line 150, and a capping layer 160. The gate insulating layer 130 and the gate line 150 may be formed between the gate spacers 152 and may be located in (e.g., may fill) the gate opening 155. The gate insulating layer 130 and the gate line 150 may be formed using a CVD process, an ALD process, or a physical vapor deposition (PVD) process.

[0068] The gate insulating layer 130 may be on (e.g., may cover) the top surface of the channel pattern 110 and the top surface of the device isolation layer 120 and the side surface of the gate spacer 152. The gate insulating layer 130 may be located on (e.g., may cover) the first side surface W1 and the second side surface W2 of the gate line 150 to be formed below.

[0069] In some embodiments, an interface layer configured to suppress / prevent interface defects may be formed between the channel pattern 110 and the gate insulating layer 130. The interface layer may be formed by thermally oxidizing the channel pattern 110 or using a CVD process. The interface layer may include silicon oxide, silicon oxynitride, silicate, or a combination thereof.

[0070] After the gate line 150 is deposited on the gate insulating layer 130, a planarization process such as a chemical mechanical polishing (CMP) process may be used to partially remove the gate line 150. Due to the planarization process, the top end of the gate line 150 may be at the same level as the top end of the gate spacer 152, and the heights of the gate line 150 and the gate spacer 152 may be reduced.

[0071] In some embodiments, the lower portion of the gate line 150 may include a barrier layer and a work-function control layer. The barrier layer may include TiN, TaN, TiAlN, TaCN, TaC, or TaSiN. The work-function control layer may include titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium carbide (TiC), cobalt (Co), aluminum (Al), hafnium-titanium (HfTi), titanium silicide (TiSi), or a combination thereof.

[0072] After the planarization process, the upper portion of the gate line 150 may be removed by a predetermined thickness so that the height of the gate line 150 may be lower than the height of the gate spacer 152. A capping layer 160 may be formed in a space formed by removing a portion of the gate line 150. The capping layer 160 may be formed on the gate line 150 along the second direction D2 between the gate spacers 152. The capping layer 160 may be formed to have a planarized top surface.

[0073] Fig.23 It is along Fig. 22 A cross-sectional view taken along line II'. Fig.24 It is along Fig. 22 A cross-sectional view taken along line III-III'.

[0074] refer to Figure 22 to Figure 24 , the mask pattern 165 may be formed on Figures 19 to 21The mask opening 166 may be formed along the mask pattern 165 so that the capping layer 160 may be partially exposed through the mask opening 166. The mask pattern 165 may be formed along the first direction D1 so that the plurality of gate lines 150 may be etched during a gate cutting process to be described below. Fig.24 As shown, a mask opening 166 may be formed to fully expose the two gate lines 150 .

[0075] The mask pattern 165 may include a material having an etch selectivity with respect to the gate line 150. For example, the mask pattern 165 may include an oxide film, a nitride film, polysilicon (poly-Si), SOH, or a combination thereof.

[0076] Fig.26 It is along Fig.25 A cross-sectional view taken along line II'. Fig. 27 It is along Fig.25 A cross-sectional view taken along line III-III'.

[0077] refer to Figure 25 to Figure 27 , a gate cutting process (or a gate cutting forming process) may be performed along the mask opening 166. Due to the gate cutting process, the gate insulating layer 130, the interlayer insulating layer 140, the gate line 150, and the capping layer 160 may be partially removed to form a gate cut 175. Fig.26 An example is shown in which the device isolation layer 120 is not removed, but in some embodiments, an upper portion of the device isolation layer 120 may be partially removed.

[0078] The gate insulating layer 130 may be separated into a first gate insulating layer 130A and a second gate insulating layer 130B by the gate cutout 175. The gate line 150 may be separated into a first gate 150A and a second gate 150B by the gate cutout 175. The capping layer 160 may be separated into a first capping layer 160A and a second capping layer 160B by the gate cutout 175.

[0079] like Fig.25 As shown, when viewed from above, the gate cutout 175 may be formed in the gate line 150 and also in the gate insulating layer 130 and the gate spacer 152. Since the width of the mask pattern 165 in the second direction D2 is smaller than the width of the mask pattern 165 in the first direction D1, during the etching process, the width of the gate cutout 175 in the second direction D2 may be formed to be smaller than the width of the gate cutout 175 in the first direction D1.

[0080] A portion of the gate cutout 175 overlapping the gate line 150 may be formed to be larger than a portion of the gate cutout 175 overlapping the interlayer insulating layer 140. In some embodiments, a first CD GC1 of the gate cutout 175 formed on the gate line 150 may be larger than a second CD GC2 of the gate cutout 175 formed on the interlayer insulating layer 140 between the gate lines 150. In some embodiments, the gate cutout 175 may have a scallop shape including a narrow portion when viewed from above.

[0081] In some embodiments, the gate cutout 175 may be formed using a plasma etching process. Typically, during the gate cutting process, the gate cutout 175 may be formed to have a tapered shape so that the CD of the gate cutout 175 may decrease toward its bottom end. However, in some embodiments, a process of depositing a passivation layer may be performed during the gate cutting process. First, the gate line 150 may be partially etched to form a recess, and a passivation layer may be deposited in the recess. The passivation layer may include polysilicon. Thereafter, in the etching process, the sidewalls of the recess may not be removed by the passivation layer, but the bottom surface of the recess may be removed to expose the top surface of the gate line 150. The process of etching the gate line 150 may be repeated again to control the profile of the gate cutout 175. After the gate cutout 175 is formed, the passivation layer may be removed.

[0082] like Fig.26 As shown, the deposition process may be performed such that a middle portion of the gate cut 175 may have a CD greater than an upper portion thereof. In some embodiments, the gate cut 175 may have a scallop shape in a vertical cross-sectional view.

[0083] refer to Fig.28 , you can Figure 25 to Figure 27 An insulating layer 172 is formed on the resulting structure. The insulating layer 172 may be formed on the interlayer insulating layer 140 and the capping layer 160. The insulating layer 172 may be formed using a CVD process or an ALD process and may be located inside (eg, may fill) the gate cutout 175. Fig.28 As shown, in a vertical cross-sectional view, since the TCD of the gate cut 175 is smaller than the MCD thereof, an air gap 180 may be formed in the gate cut 175 during the deposition process. The first gate 150A and the second gate 150B may be effectively / sufficiently insulated from each other by the air gap 180.

[0084] refer to Fig.28 After forming the insulating layer 172, an etch-back process or a planarization process may be used to expose the interlayer insulating layer 140, the first capping layer 160A, and the second capping layer 160B. Thus, the gate isolation layer 170 may be formed in the gate cutout 175. Due to the etch-back process or the planarization process, the upper portion of the interlayer insulating layer 140 and the upper portion of the capping layer 160 may be partially removed.

[0085] Figure 29 to Figure 32 According to some example embodiments Figure 1 The plan view of the semiconductor device will be omitted. Figure 1 Detailed description of the same components in .

[0086] refer to Fig.29 , a gate cutout 675 may be formed in one gate line 150. The gate cutout 675 may be formed by partially etching the gate insulating layer 130 and the gate spacer 152. A gate isolation layer 670 may be formed in the gate cutout 675, and the gate isolation layer 670 may include an air gap 680. The gate cutout 675 may have an elliptical shape having a major axis in the first direction D1.

[0087] refer to Fig.30 , the three gate lines 150 may extend in the second direction D2 and be formed to be separated from each other. The gate cutout 775 may extend in the first direction D1 and be disposed above the three gate lines 150. The three gate lines 150 may be etched using one gate cutting process. The gate cutout 775 may have a scallop shape including a narrow shape. A gate isolation layer 770 may be formed in the gate cutout 775. An air gap 780 may be formed in the gate isolation layer 770, and the air gap 780 may be formed at the intersection between the gate line 150 and the gate isolation layer 770.

[0088] refer to Fig.31 , the gate cutout 875 may include a gate isolation layer 870, and the gate isolation layer 870 may include an air gap 880. The gate isolation layer 870 may further include an air gap 882. The air gap 882 may be formed in a portion of the gate cutout 875 overlapping the interlayer insulating layer 140. During the process of forming the gate cutout 875, not only the gate line 150 may be partially etched, but also the interlayer insulating layer 140 may be partially etched. The air gap 882 may be formed during the process of depositing the gate isolation layer 870 in the interlayer insulating layer 140.

[0089] refer to Fig.32 , the gate cutout 975 may include a gate isolation layer 970, which may include an air gap 980. The air gap 980 may be formed in the gate line 150 and the interlayer insulating layer 140. The air gap 980 may be formed during a process of depositing the gate isolation layer 970 in the partially etched gate line 150 and the interlayer insulating layer 140.

[0090] According to example embodiments, in a semiconductor device including a gate line formed using an RMG process, an air gap may be formed in a process of forming a gate isolation layer to electrically insulate the gate line after a gate cutting process, thereby further reducing capacitance.

[0091] According to example embodiments, the CD of the gate isolation layer may be controlled so that the CD of the top of the gate isolation layer is smaller than the CD of the middle of the gate isolation layer. Therefore, the volume of the gate isolation layer and the air gap may be increased to improve the insulation effect.

[0092] Although the exemplary embodiments of the present invention have been described with reference to the accompanying drawings, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention. Therefore, the above embodiments should be considered as merely illustrative and not for limiting purposes.

Claims

1. A semiconductor device, comprising: a first channel region and a second channel region, the first channel region and the second channel region protruding from the substrate and extending in a first direction; a first gate, located on the first channel region; a second gate located on the second channel region, wherein the first gate and the second gate extend in a second direction intersecting the first direction and are spaced apart from each other in the second direction; a first gate insulating layer, located between the first gate and the first channel region; a second gate insulating layer located between the second gate and the second channel region; and a gate isolation layer, which is located between the first gate and the second gate, wherein the gate isolation layer contacts the first gate and the second gate and includes a gap in the gate isolation layer, wherein a first width of the gate isolation layer in the second direction is greater than a second width of the gate isolation layer in the second direction, wherein a third width of the gate isolation layer in the second direction is smaller than the first width of the gate isolation layer, and wherein, in the vertical direction, the first width is between the second width and the third width, wherein the second width is at a level coplanar with an upper surface of the first gate, and Wherein, the width of the gate isolation layer decreases monotonically from the first width to the second width.

2. The semiconductor device according to claim 1, wherein The first gate insulating layer and the second gate insulating layer are spaced apart from each other by the gate isolation layer between the first gate insulating layer and the second gate insulating layer, and The gate isolation layer contacts the first gate and the second gate at each of the first width, the second width, and the third width.

3. The semiconductor device according to claim 1, wherein A top end of the gap is at a higher level than a top end of the first channel region.

4. The semiconductor device according to claim 1, in, The first gate insulating layer is on a first side surface and a second side surface of the first gate, and The second gate insulating layer is on the first side surface and the second side surface of the second gate.

5. The semiconductor device according to claim 1, further comprising: a device isolation layer, wherein the device isolation layer is in the trench between the first channel region and the second channel region, Wherein, the first gate insulating layer is between the first gate and the device isolation layer, Wherein, the second gate insulating layer is between the second gate and the device isolation layer, Wherein, the upper portion of the device isolation layer includes a concave portion, wherein a portion of the gate isolation layer is located in the recess, and Wherein, the bottom end of the gate isolation layer is at a lower level than the top end of the device isolation layer.

6. The semiconductor device according to claim 5, wherein: A bottom end of the gap is at a lower level than the top end of the device isolation layer.

7. The semiconductor device according to claim 1, in, The gap includes an air gap having an elliptical shape, and Wherein, a middle portion of the air gap is wider than an upper portion and a lower portion of the air gap in the second direction.

8. The semiconductor device according to claim 1, wherein When viewed from a vertical cross section, the sidewall of the gate isolation layer includes a plurality of protrusions.

9. The semiconductor device according to claim 1 , further comprising a first cover layer and a second cover layer on the first gate and the second gate, respectively, the first cover layer and the second cover layer being spaced apart from each other in the second direction by the gate isolation layer between the first cover layer and the second cover layer, in, A width between respective bottom ends of the first and second cover layers is greater than a width between respective top ends of the first and second cover layers, and a top end of the gap is at a higher level than the bottom ends of the first and second cover layers.

10. The semiconductor device according to claim 1, wherein The first width is at a level close to an upper surface of the first channel region.

11. A semiconductor device comprising: a substrate including a channel region protruding from the substrate; a gate line located on a first side surface and a second side surface of the channel region; A gate spacer, which is located on a first side surface and a second side surface of the gate line; as well as a gate isolation layer located in the gate cutout region, the gate isolation layer separating a first portion of the gate line from a second portion of the gate line, wherein the gate isolation layer contacts the gate line and includes a gap in the gate isolation layer, wherein the first width of the gap is greater than the second width of the gap, wherein the third width of the gap is narrower than the first width, and wherein the first width is between the second width and the third width, and Wherein, a first distance between the first portion and the second portion of the gate line is greater than a second distance between the first portion and the second portion of the gate line, the first distance is in the middle of the gate isolation layer, and the second distance is close to the top of the gate isolation layer. wherein the gate line comprises one gate line among a plurality of gate lines spaced apart from each other in a first direction intersecting a second direction, wherein the first portion of the gate line is spaced apart from the second portion of the gate line in the second direction, wherein the gate cutout region extends in the first direction to at least two gate lines among the plurality of gate lines, wherein the gate isolation layer extends in the gate cutout region in the first direction, and The gap is at the intersection between the gate isolation layer and the gate line, and Wherein, a width of a portion of the gate cutout region located between the at least two gate lines among the plurality of gate lines increases toward a middle of the portion of the gate cutout region.

12. The semiconductor device according to claim 11, wherein The gate cutout region separates the gate spacers.

13. The semiconductor device according to claim 11, wherein The gate cut region has an elliptical shape. 14 . The semiconductor device according to claim 11 , further comprising a gate insulating layer between the gate line and the gate spacer.

15. The semiconductor device according to claim 11, wherein A first width of the gate cut region in the gate line is greater than a second width of the gate cut region between the at least two gate lines among the plurality of gate lines.

16. The semiconductor device according to claim 11, wherein The top of the gap is at a higher level than the top of the channel region, and The gap extends over most of the height of the gate cutout region.

17. The semiconductor device according to claim 11, in, The gap includes an air gap having an elliptical shape, and The middle portion of the air gap is wider than the upper portion and the lower portion of the air gap.

18. The semiconductor device according to claim 11, wherein The first width is at a level close to an upper surface of the channel region.

19. A semiconductor device comprising: a substrate including a channel region protruding from the substrate and extending in a first direction; a first gate line and a second gate line, the first gate line and the second gate line extending on the channel region and in a second direction crossing the first direction, wherein the first gate line is spaced apart from the second gate line in the first direction; A gate spacer, which is located on a first side surface and a second side surface of the first gate line; A gate insulating layer, located between the first gate line and the gate spacer; a gate isolation layer located in a gate cutout region between the first gate line and the second gate line in the first direction; and a gap in the gate isolation layer, The gate cutout region separates the first gate line, separates the gate insulating layer, and separates the gate spacer. Wherein, the gate isolation layer is in contact with the first gate line, and The first width of the gate isolation layer is greater than the second width and the third width of the gate isolation layer, and the first width of the gate isolation layer is located between the second width and the third width of the gate isolation layer in the third vertical direction, and The first width is located in the middle between the level of the upper surface of the first gate line and the level of the lower surface of the first gate line in the third vertical direction.

20. The semiconductor device according to claim 19, wherein The gap includes an air gap having an elliptical shape having a minor axis in the second direction.

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