Page buffer and storage device including the same

Abstract

The present disclosure provides a page buffer and a memory device including the page buffer. The memory device includes: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches and a transmission transistor, the plurality of latches share a data transmission node and exchange data with each other through the data transmission node; the transmission transistor sets the connection between the data transmission node and another data transmission node of another page buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed on Korean Patent Application No. 10-2018-0069081 filed on June 15, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a page buffer and a memory device including the same. Background Art

[0004] As the demand for high-capacity memory devices with relatively small sizes increases, interest in and research on memory devices with vertically stacked memory cells has also increased. A memory device may include a page buffer for storing or outputting data. The page buffer may have multiple semiconductor elements. As the integration of memory devices increases, the area of ​​the area occupied by the page buffer tends to decrease, and thus the layout of the wires of the semiconductor elements connected to the page buffer becomes more and more complicated. Summary of the invention

[0005] Embodiments of the inventive concept provide a page buffer in which conductive lines connected to a semiconductor element of the page buffer can be efficiently arranged to increase the degree of freedom of design of circuits and layouts, and a memory device including the same.

[0006] An embodiment of the inventive concept provides a memory device, the memory device comprising: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines. Each of the plurality of page buffers comprises a plurality of latches and a transmission transistor. The plurality of latches share a data transmission node and exchange data with each other through the data transmission node. The transmission transistor sets a connection between the data transmission node and another data transmission node of another page buffer of the plurality of page buffers.

[0007] An embodiment of the present invention also provides a memory device, comprising: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; a page buffer circuit comprising a plurality of page buffers connected to the plurality of bit lines, each of the plurality of page buffers having a plurality of latches, the plurality of latches exchanging data with each other through a data transmission node in the page buffer; and control logic, the control logic controlling the connection between the data transmission nodes of at least some of the plurality of page buffers to identify the data stored in the plurality of page buffers, and controlling the data transmission nodes in the plurality of page buffers to be disconnected from each other to exchange data between the plurality of latches in each of the plurality of page buffers.

[0008] An embodiment of the present invention further provides a page buffer, which includes: a plurality of semiconductor elements, which are formed in a first region of a semiconductor substrate and are configured to provide a latch connected to at least one of a plurality of bit lines through a sensing node; a first latch signal line, which is arranged on a first level in the first region and connected to a first node of the latch; a second latch signal line, which is arranged on the first level and connected to a second node of the latch, wherein a voltage of the first node and a voltage of the second node are complementary; and a sensing line, which is arranged between the first latch signal line and the second latch signal line on the first level and is configured to provide the sensing node.

[0009] An embodiment of the present invention also provides a page buffer, which includes a first data transmission line; a transfer transistor, which is configured to set a connection between the first data transmission line and a second data transmission line of another page buffer; a plurality of latches, which are connected to the first data transmission line and are configured to exchange data with each other through the first data transmission line; and a control logic, which is configured to activate the transfer transistor to connect the first data transmission line and the second data transmission line during a data recognition mode, and deactivate the transfer transistor to disconnect the first data transmission line and the second data transmission line during the exchange of data between the plurality of latches. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A block diagram of a memory device according to an embodiment of the inventive concept is shown;

[0012] Figure 2 A diagram showing a connection relationship between a memory cell array and a page buffer in a memory device according to an embodiment of the inventive concept;

[0013] Figure 3A and Figure 3B A diagram showing different layers of a structure of a page buffer according to an embodiment of the inventive concept;

[0014] Figure 4 A diagram illustrating a structure of a plurality of page buffers in a page buffer circuit according to an embodiment of the inventive concept;

[0015] Figure 5 The embodiment according to the present invention is shown along Figure 4 A cross-sectional view of the structure of the page buffer taken along line II';

[0016] Figure 6 A block diagram of a page buffer according to an embodiment of the inventive concept is shown;

[0017] Figure 7 A circuit diagram of a page buffer according to an embodiment of the inventive concept is shown;

[0018] Figure 8 A circuit diagram showing a layout of a page buffer according to an embodiment of the inventive concept;

[0019] Fig. 9 A timing diagram illustrating the operation of a page buffer according to an embodiment of the inventive concept;

[0020] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 Various diagrams illustrating the operation of a page buffer according to an embodiment of the inventive concept;

[0021] Fig.16 A timing diagram illustrating the operation of a page buffer according to an embodiment of the inventive concept;

[0022] Fig.17 A timing diagram illustrating another operation of a page buffer according to an embodiment of the inventive concept; and

[0023] Fig.18 A block diagram of an electronic device including a memory device according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0025] As traditional in the field of the present invention, the embodiment can be described and illustrated according to the block that performs one or more functions described. These blocks (which may be referred to as units or modules, etc. in this article) are physically implemented by analog circuits and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software. For example, the circuit can be implemented in one or more semiconductor chips, or can be implemented on substrate supports such as printed circuit boards, etc. The circuit constituting the block can be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and related circuits), or by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block. Without departing from the scope of the present invention, each block of the embodiment can be physically divided into more than two interactive and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment can be physically combined into more complex blocks.

[0026] Figure 1 A block diagram of a memory device according to an embodiment of the inventive concept is shown.

[0027] Reference Figure 1 , the memory device 1 includes a memory cell array 10 and a memory controller 20. The memory cell array 10 may include a plurality of memory cells MC, and at least a portion of the plurality of memory cells or some of the memory cells may be connected to each other to provide a memory cell string. The memory cell array 10 may include a plurality of memory cell strings, and the plurality of memory cell strings may be divided into a plurality of blocks. The memory controller 20 includes a control logic (e.g., circuit) 21, an address decoder circuit 22, a page buffer circuit 23, and an input / output circuit 24. The memory device 1 may include additional circuits not shown.

[0028] The address decoder circuit 22 is connected to the memory cell MC through the word line WL, the string selection line SSL and the ground selection line GSL and other lines (not shown). The page buffer circuit 23 is connected to the memory cell MC through the bit line BL. In one embodiment, the address decoder circuit 22 can select the memory cell MC to which data is to be written or from which data is to be read, and can receive address information for selecting the memory cell MC.

[0029] The page buffer circuit 23 may write data to or read data from the memory cell MC, and may write or read data page by page. The page buffer circuit 23 may include a plurality of page buffers, and each of the plurality of page buffers may be connected to at least one bit line BL. Data written to the memory cell array 10 by the page buffer circuit 23 may be input through the input / output circuit 24, and data may be read from the memory cell array 10 by the page buffer circuit 23 and output through the input / output circuit 24. The operation of the address decoder circuit 22, the operation of the page buffer circuit 23, and the operation of the input / output circuit 24 may be controlled by the control logic 21. For example, the control logic 21 may provide various control signals to a plurality of transistors TR1 to TR25 in the page buffer 400, so that data within the latch of the page buffer 400 can be counted (e.g., identified) and / or data can be exchanged (e.g., transferred) between latches, such as subsequently being referenced. Figure 7 and Figures 10 to 15 Describe this.

[0030] Figure 2 A diagram illustrating a connection relationship between a memory cell array and a page buffer in a memory device according to an embodiment of the inventive concept.

[0031] Reference Figure 2 The memory device 2 has a plurality of memory cells MC included in a memory block 30 and a plurality of page buffers PB1 to PBn included in a page buffer circuit 40. Some of the plurality of memory cells MC may be connected to each other, and the connected memory cells provide a plurality of memory cell strings MCS. The plurality of memory cell strings MCS are disposed at respective intersections of a plurality of word lines WL1 to WLm and a plurality of bit lines BL1 to BLn.

[0032] Each of the plurality of memory cell strings MCS includes, in addition to the memory cell MC, a string selection transistor SST and a ground selection transistor GST. The string selection transistors SST in the plurality of memory cell strings MCS are respectively connected to a plurality of bit lines BL1 to BLn and are controlled by a string selection line SSL. The ground selection transistors GST in the plurality of memory cell strings MCS are respectively connected to a common source line CSL and can be controlled by a ground selection line GSL.

[0033] exist Figure 2In the embodiment of the inventive concept shown, the ground selection transistor GST has a different structure from the memory cell MC, and the string selection transistor SST has the same structure as the memory cell MC. However, in other embodiments, the structure of the ground selection transistor GST may be the same as the structure of the memory cell MC, and the structure of the string selection transistor SST may be different from the structure of the memory cell MC. When a plurality of memory cell strings MCS are formed in a three-dimensional structure, each of a plurality of bit lines BL1 to BLn may be connected to a plurality of memory cell strings MCS connected to different string selection lines SSL.

[0034] A plurality of memory cell strings MCS may be included in one memory block 30, and a memory cell array may include a plurality of memory blocks 30. When the memory cell strings MCS included in the memory block 30 are connected to n bit lines BL1 to BLn, the page buffer circuit 40 may include n page buffers PB1 to PBn corresponding to the bit lines BL1 to BLn. Figure 2 In a manner similar to the embodiment shown in , each of the page buffers PB1 to PBn can be connected to a corresponding one of the bit lines BL1 to BLn, and can temporarily store data to be stored or read through the bit lines BL1 to BLn. Each of the page buffers PB1 to PBn may include at least one latch circuit for temporarily storing data.

[0035] For example, in the architecture of the memory device 2, the page buffers PB1 to PBn connected to one memory block 30 may be arranged along a predetermined direction ( Figure 2 Each of the page buffers PB1 to PBn may include, in addition to a latch circuit, a connection circuit for connecting the bit lines BL1 to BLn to the latch circuit, a precharge circuit for precharging the sensing node to store or read data, etc. Each of the page buffers PB1 to PBn may include a plurality of semiconductor elements for implementing a circuit.

[0036] Figures 3A to 5 A diagram illustrating a structure of a page buffer according to an embodiment of the inventive concept.

[0037] Figure 3A and Figure 3B A diagram showing different layers of a structure of a page buffer according to an embodiment of the inventive concept. Figure 3A and Figure 3B , the page buffer PB may include multiple layers. In the illustrated embodiment of the inventive concept, although Figure 3A The layers shown only include semiconductor element 100. Figure 3BThe layer formed on the upper portion of the semiconductor element 100 shown includes wires 201 to 206, but the page buffer PB may also include other components and / or layers. In one example, wires may also be arranged on the upper portion of the wires 201 to 206 along the Z-axis direction, or a path connecting the wires 201 to 206 and the semiconductor element 100 may be arranged.

[0038] As described above, the page buffer PB may include a plurality of semiconductor elements 100 for providing or configuring a latch circuit, a connection circuit, a precharge circuit, etc. The plurality of semiconductor elements 100 may be disposed in the first region A1 of the semiconductor substrate to form the page buffer PB. As the integration of memory devices increases and the interval between memory cell strings connected to the page buffer PB decreases, the plurality of semiconductor elements 100 included in one page buffer PB may be arranged in a specific direction. Figure 3A and Figure 3B In the illustrated embodiment, a plurality of semiconductor elements 100 may be arranged in a first region A1 of a semiconductor substrate along a first direction (Y-axis direction) to provide a page buffer PB. The first direction is parallel to a top surface of the semiconductor substrate.

[0039] Each semiconductor element 100 may include a gate electrode 110 and an active region 120 intersecting the gate electrode 110 and providing a source / drain region. At least one of the gate electrode 110 and the active region 120 of each semiconductor element 100 may be connected to at least one of the conductive lines 201 to 206 disposed at an upper portion of the semiconductor element 100. Figure 3A and Figure 3B In the illustrated embodiment, the conductive lines 201 to 206 may be arranged on a first level located on an upper portion of the first area A1 along the Z-axis direction.

[0040] In one example, at least one of the gate electrode 110 and the active region 120 of each semiconductor element 100 may be connected to at least one of the conductive lines 201 to 206 formed on the first level. A plurality of semiconductor elements 100 may be connected to each other through the conductive lines 201 to 206 to provide a connection circuit, a precharge circuit, a latch circuit, etc. of the page buffer PB.

[0041] Each of the plurality of conductive lines 201 to 206 formed on the first level may be connected to at least one of the plurality of semiconductor elements 100. In one example, the conductive lines 201 to 206 may include a line for connecting the page buffer PB to an external cache latch, a line for providing a power supply voltage, a line for connecting the page buffer PB to a monitoring circuit, a line for transmitting a signal of a latch circuit included in the page buffer PB, a line for connecting to a sensing node of the page buffer PB, etc. Hereinafter, for ease of explanation, it is assumed that each of the conductive lines 201 to 206 may be matched with one of the lines illustrated above, but the inventive concept is not necessarily limited to the example based on this assumption. For example, in other embodiments, the number and arrangement order of the conductive lines 201 to 206 may be variously modified.

[0042] For example, the wires 201 to 206 may include a cache latch line for connecting the page buffer PB to an external cache latch and a power line for providing a power supply voltage. In one example, the power line may be divided into a plurality of regions to provide a plurality of power supply voltages with different amplitudes. The cache latch line may also be divided into a plurality of regions, and the plurality of regions of the cache latch line may be selectively connected to or disconnected from each other by at least one of the plurality of semiconductor elements 100.

[0043] Moreover, at least one of the plurality of conductors 201 to 206 may be used to transmit data between latch circuits included in the page buffer PB, or may be used as a wired OR line connected to a monitoring circuit that identifies data stored in the page buffer PB (or in other words, used in a wired OR configuration). The monitoring circuit may count the data stored in the page buffer PB through the wired OR line. In one embodiment, the wired OR line may be divided into a plurality of regions, and the plurality of regions may be selectively connected or disconnected through the transfer transistors PASS_TR of the plurality of semiconductor elements 100. At least one of the plurality of regions may be connected to a transfer transistor of another page buffer adjacent in the first direction (Y-axis direction).

[0044] For example, in a monitoring operation in which the monitoring circuit identifies data stored in the page buffer PB, the transmission transistor PASS_TR can be turned on, so that the plurality of regions included in the wired OR line can be connected to each other. In addition, the transmission transistor PASS_TR can be turned off, so that the plurality of regions included in the wired OR line can be used to transmit data between the latch circuits included in the page buffer PB.

[0045] At the same time, multiple wires 201 to 206 may include a latch signal line for transmitting a signal of a latch circuit and a sensing node line for providing a sensing node of a page buffer PB. In one embodiment, signals having complementary characteristics to each other may be transmitted through the latch signal line. The page buffer PB may store data in a storage unit or read data from a storage unit by using a method of precharging the sensing node and then developing the sensing node. Therefore, it is necessary to effectively shield the sensing node from external noise. In one embodiment, by arranging the sensing node line between the latch signal lines that transmit signals having complementary characteristics, the sensing node can be effectively protected from external noise.

[0046] Although the functions of the wires 201 to 206 have been described above for ease of explanation, various modifications may be made to the number and arrangement of the wires 201 to 206 according to the embodiment. The number of the wires 201 to 206 may be more or less than six. In addition, depending on the number of the wires 201 to 206, other functions may be added to the above functions, or a part of the above functions may be provided in wires at other levels.

[0047] Figure 4 FIG. 1 is a diagram showing a structure of a plurality of page buffers in a page buffer circuit according to an embodiment of the inventive concept. Figure 4 , the page buffer circuit PBC may include a plurality of page buffers PB. Figure 4 In the illustrated embodiment, it can be understood that the page buffers PB arranged in series along the first direction (Y-axis direction) and located at the same position in the second direction (X-axis direction) can be connected to the same memory block. The first direction and the second direction are orthogonal to each other.

[0048] exist Figure 4 In the illustrated embodiment, the plurality of wires 201 to 206 may be disposed on a first layer defined along the Z-axis direction on the upper portion of the plurality of semiconductor elements 100. As described above, each of the plurality of wires 201 to 206 may be connected to at least one of the plurality of semiconductor elements 100 to provide a latch circuit, a precharge circuit, a connection circuit, etc.

[0049] As mentioned above Figure 3A and Figure 3BAs described, the third wire 203 can be divided into a plurality of regions along the first direction (Y-axis direction). The plurality of regions included in the third wire 203 can be connected or disconnected to each other through the transfer transistor PASS_TR included in each page buffer PB. When the third wire 203 is connected to the monitoring circuit, the transfer transistor PASS_TR is turned on so that at least a portion of the plurality of regions can be connected to each other. In addition, when the third wire 203 is used as a data transmission node for each page buffer PB, the transfer transistor PASS_TR is turned off. In order to effectively place the third wire 203, the transfer transistor PASS_TR can be located at the lowest end of the page buffer PB in the first direction (Y-axis direction). That is, the transfer transistor PASS_TR can be set as the first device or component of the page buffer PB along the first direction (Y-axis direction).

[0050] The first conductive line 201 may extend in a first direction on a page buffer PB connected to one memory block. The first conductive line 201 may extend to a cache latch located at a lower portion of the page buffer PB in the first direction. The second conductive line 202 may be a line for providing a power supply voltage as described above, and may be divided into a plurality of regions to provide a first power supply voltage and a second power supply voltage having different amplitudes.

[0051] Figure 5 The embodiment according to the present invention is shown along Figure 4 1 is a cross-sectional view of the structure of the page buffer taken along line II'. Figure 5 2 shows a structure of a pass transistor PASS_TR capable of connecting or disconnecting a plurality of regions included in the third conductive line 203. Figure 5 In the illustrated embodiment, it is assumed that the pass transistor PASS_TR may be a FINFET including a fin type structure, but is not limited thereto but may be modified into various structures.

[0052] Reference Figure 5 , the pass transistor PASS_TR includes a gate electrode 110 and an active region 120 formed on a fin structure 102 of a semiconductor substrate 101. The fin structure 102 includes a first fin region 103 extending from the semiconductor substrate 101 and a second fin region 104 extending from the first fin region 103. The gate electrode 110 is formed to cross the second fin region 104 on the first fin region 103. The active region 120 may extend from the first fin region 103. For example, the active region 120 is formed by applying a selective epitaxial growth process to the first fin region 103. The active region 120 may include a first layer 121 and a second layer 122.

[0053] The gate electrode 110 may be formed in the spacer 140 and may include a gate insulating layer 111, a first gate metal layer 112, a second gate metal layer 113, a capping layer 114, and other layers. According to embodiments, various modifications may be made to the stacked structure of the gate electrode 110. In one example, at least one of the first gate metal layer 112 and the second gate metal layer 113 may include a plurality of layers.

[0054] The active region 120 is connected to the contact 130. The contact 130 may be formed by removing a portion of the interlayer insulating layer 160 formed to surround the gate electrode 110 through an etching process, and filling the space where the portion of the interlayer insulating layer 160 is removed with a conductive material. The contact 130 may have a first contact layer 131 and a second contact layer 132. The first contact layer 131 may be a shielding metal layer, and the second contact layer 132 may be a filling metal layer. The additional contact layer 150 may be disposed between the first contact layer 131 and the second layer 122 of the active region 120. Moreover, for example, the upper surface of the contact 130 may be coplanar with the upper surface of the gate electrode 110, and the upper insulating layer IML may be formed on the upper surface of the gate electrode 110 and the upper surface of the contact 130. The upper insulating layer IML may include a plurality of layers IML1 and IML2, and the region where the upper insulating layer IML is formed may be defined as a first plane L1 on the upper portion of the semiconductor substrate 101.

[0055] In one example, the conductive lines 201 to 206 and the vias 210 and 220 may be formed in an upper insulating layer IML. Figure 5 2 shows a third conductive line 203, which can be divided into a plurality of regions by the pass transistor PASS_TR. Each of the plurality of regions included in the third conductive line 203 can be connected to the corresponding active region 120 of the pass transistor PASS_TR through the first path 210 or the second path 220. Therefore, the plurality of regions included in the third conductive line 203 can be connected or disconnected to each other according to the on / off of the pass transistor PASS_TR.

[0056] Figure 6 A block diagram of a page buffer according to an embodiment of the inventive concept is shown.

[0057] Reference Figure 6 The memory device 300 includes a memory cell array 310 having a plurality of memory cell strings MCS and a page buffer circuit 320. The structure of each memory cell string in the plurality of memory cell strings MCS may be similar to that previously described for example. Figure 2The page buffer circuit 320 includes a plurality of page buffers 321. Each page buffer 321 includes a connection circuit 322, a precharge circuit 323, and a latch circuit 324. In one embodiment, the node to which the connection circuit 322, the precharge circuit 323, and the latch circuit 324 are connected may be defined as a sensing node SO.

[0058] Each page buffer 321 may include a plurality of semiconductor elements, and the plurality of semiconductor elements may be arranged in a straight line along a predetermined direction within an area allocated to each page buffer 321. The plurality of semiconductor elements may be connected to each other through a plurality of wires formed thereon to provide a connection circuit 322, a precharge circuit 323, and a latch circuit 324. Therefore, it is necessary to effectively design the layout of the wires to provide a limited number of wires for the connection circuit 322, the precharge circuit 323, and the latch circuit 324.

[0059] In one embodiment, one of the wires can be used to transmit data between the plurality of latches included in the latch circuit 324, and used as a connection line connected to the monitoring circuit using a wired OR mode (or a wired OR configuration). Therefore, by improving the utilization of a limited number of wires, the degree of freedom of design of each page buffer 321 can be relatively improved. In addition, when the sensing node SO is evolved, data transmission between the plurality of latches can be performed by separately configuring a wire for transmitting data between the plurality of latches and a wire connected to the sensing node SO.

[0060] Figure 7 A circuit diagram of a page buffer according to an embodiment of the inventive concept is shown.

[0061] Reference Figure 7 , the page buffer 400 according to the embodiment includes a plurality of transistors TR1 to TR25 and a plurality of latches LAT_S, LAT_L, and LAT_F. The plurality of transistors TR1 to TR25 may provide a connection circuit for connecting the sensing node SO and the data transmission node DT to the bit line BL, a precharge circuit for precharging the sensing node SO or the data transmission node DT, a circuit for controlling each of the plurality of latches LAT_S, LAT_L, and LAT_F, etc. For example, the plurality of latches LAT_S, LAT_L, and LAT_F may include a sensing latch LAT_S and a plurality of data latches LAT_L and LAT_F.

[0062] exist Figure 7In the illustrated embodiment, the page buffer 400 may include a data transmission node DT in addition to the sensing node SO. The data transmission node DT may be connected to the data transmission node DT of another page buffer or disconnected from the data transmission node DT of another page buffer through the transmission transistor TR24. For example, when the page buffer 400 is connected to a monitoring circuit for counting data stored in the latches LAT_S, LAT_L, and LAT_F of the page buffer 400, the transmission transistor TR24 may be turned on. When the transmission transistor TR24 is turned on, data exchange between the latches LAT_S, LAT_L, and LAT_F may not be performed, and the monitoring circuit may count the data stored in the latches LAT_S, LAT_L, and LAT_F in a wired OR mode using the data transmission node DT.

[0063] When the latches LAT_S, LAT_L, and LAT_F perform a data transmission operation through the data transmission node DT, the transmission transistor TR24 may be turned off. Therefore, when the latches LAT_S, LAT_L, and LAT_F exchange data with each other, the data transmission node DT of the page buffer 400 may be disconnected from the data transmission node DT of another adjacent page buffer. Therefore, the transmission transistor sets (in other words turns on or off) the connection between the data transmission node DT of the page buffer 400 and the data transmission node DT of another page buffer. The transmission transistor may be characterized as being activated during the data recognition mode and thus turned on to provide a connection between the data transmission node DT of the page buffer 400 and the data transmission node DT of another page buffer, and being deactivated and thus turned off during the data exchange between the latches LAT_S, LAT_L, and LAT_F.

[0064] At the same time, Figure 7 In the illustrated embodiment, each of the plurality of transistors TR1 to TR25 may be connected to at least one conductive wire. As previously described, the conductive wire may be a wire formed at the upper portion of the plurality of transistors TR1 to TR25. For example, one of the active regions of the second transistor TR2 and the active region of the seventh transistor TR7 may be connected to a conductive wire providing a second power supply voltage GND, and one of the active regions of the twelfth transistor TR12 and the active region of the thirteenth transistor TR13 may be connected to a conductive wire providing a first power supply voltage VDD. In addition, one of the active regions of the eleventh transistor TR11 may be connected to a conductive wire connecting the page buffer 400 to a cache latch.

[0065] Figure 8 A circuit diagram illustrating a layout of a page buffer according to an embodiment of the inventive concept.

[0066] Reference Figure 8, the page buffer circuit 500 according to the embodiment includes a plurality of page buffers PB1 to PBn. As described above, each of the plurality of page buffers PB1 to PBn may be connected to a corresponding bit line. Figure 7 As described, each of the plurality of page buffers PB1 to PBn may include a plurality of transistors TR1 to TR25 and a plurality of latches LAT_S, LAT_L, and LAT_F (not shown). The plurality of transistors TR1 to TR25 may be arranged in a straight line along one direction in each of the page buffers PB1 to PBn.

[0067] For example, refer to Figure 8 In the first page buffer PB1, the pass transistor TR24 can be set at the lowest end of the area allocated to the first page buffer PB1. That is, the pass transistor PASS_TR24 can be set as the first device or component of the first page buffer PB1 in the first direction (Y-axis direction). The fourteenth transistor TR14 and the seventeenth transistor TR17 can be connected to the pass transistor TR24. At least a portion of the plurality of transistors TR1 to TR25 included in the first page buffer PB1 or some of the transistors can be connected to the wire. Figure 8 In the illustrated embodiment, only a power supply line 501 for providing power supply voltages VDD and GND, a data transmission line 502 for providing a data transmission node DT, and a sense line 503 for providing a sense node SO are shown. Lines for transmitting latch signals, lines for connecting to cache latches, etc. may be additionally provided.

[0068] Reference Figure 8 , the data transmission lines 502 included in the page buffers PB1 to PBn adjacent to each other may be connected or disconnected to each other through the transfer transistors TR24 included in each of the plurality of page buffers PB1 to PBn. For example, when the monitoring circuit 510 monitors the data stored in at least one of the latches LAT_S, LAT_L, and LAT_F of the first page buffer PB1, the transfer transistors TR24 of all the page buffers PB1 to PBn may be turned on.

[0069] In contrast, when the monitoring circuit 510 monitors the data stored in at least one of the latches LAT_S, LAT_L, and LAT_F of the second page buffer PB2, the transmission transistor TR24 of the first page buffer PB1 may be turned off, and the transmission transistors TR24 of the remaining page buffers PB2 to PBn may be turned on. In addition, when the monitoring circuit 510 monitors the data stored in at least one of the latches LAT_S, LAT_L, and LAT_F of the nth page buffer PBn, all the transmission transistors TR24 of the page buffers PB1 to PBn-1 may be turned off. For example, in an embodiment, the monitoring circuit 510 may selectively turn on / off the transmission transistor TR24 included in each of the plurality of page buffers PB1 to PBn depending on the object to be monitored. Therefore, the power consumed in the monitoring operation may be effectively managed.

[0070] For example, when the monitoring circuit 510 monitors the data of the latches LAT_S, LAT_L, and LAT_F included in the nth page buffer PBn, the monitoring circuit 510 may precharge the data transmission line 502 connected to the data transmission node DT to a predetermined power supply voltage VDD. The monitoring circuit 510 may perform the monitoring operation by evolving the voltage of the data transmission line 502 precharged with the data of the latches LAT_S, LAT_L, and LAT_F included in the nth page buffer PBn.

[0071] In a conventional layout in which a wired OR connection for monitoring operation is provided, the monitoring circuit 510 and all page buffers PB1 to PBn are always connected, regardless of the object to be monitored, and the monitoring circuit 510 must always precharge the same length of the line. Therefore, in the conventional layout, the power to be consumed in the monitoring operation increases. In contrast, in an embodiment of the present invention, the length of the data transmission line 502 that the monitoring circuit 510 needs to precharge depends on the position of the object to be monitored, and the length can be adjusted by selectively turning on / off the transfer transistor TR24 included in each of the plurality of page buffers PB1 to PBn. Therefore, the power consumed during the monitoring operation can be effectively managed.

[0072] Fig. 9 A timing diagram illustrating an operation of a page buffer according to an embodiment of the inventive concept.

[0073] Refer to Figure 8 and Fig. 9, the on / off switching of the transfer transistor TR24 included in each page buffer PB1 to PBn can be controlled by the transfer control signal WOR_PASS. For example, the transfer control signal WOR_PASS(1) can control the on / off switching of the transfer transistor TR24 in the page buffer PB1, the transfer control signal WOR_PASS(2) can control the on / off switching of the transfer transistor TR24 in the page buffer PB2, and the transfer control signal WOR_PASS(n) can control the on / off switching of the transfer transistor TR24 in the page buffer PBn. Fig. 9 In the illustrated embodiment, during the first period T1 (e.g., monitoring period), the transmission transistors TR24 included in all the page buffers PB1 to PBn are turned on. Therefore, in the wired OR mode, the data transmission nodes DT of all the page buffers PB1 to PBn are connected to the monitoring circuit 510 through the data transmission line 502. Therefore, the monitoring circuit 510 can count the data of the page buffers PB1 to PBn.

[0074] During the second period T2 (e.g., sensing data / transmitting data period), the transmission transistors TR24 included in all the page buffers PB1 to PBn may be turned off. Therefore, the data transmission nodes DT included in the page buffers PB1 to PBn may be disconnected from each other, and data exchange between the latches LAT_S, LAT_L, and LAT_F in each page buffer PB1 to PBn may be performed. Next, during the third period T3 (e.g., monitoring period), the transmission transistors TR24 included in a part or some of the page buffers PB1 to PBn (e.g., page buffers PBn-1 and PBn) may be selectively turned on. Therefore, only the data transmission nodes DT of a part or some of the page buffers PB1 to PBn (e.g., page buffers PBn-1 and PBn) may be connected to the monitoring circuit 510 through the data transmission line 502.

[0075] As described above, in an embodiment of the inventive concept, the monitoring circuit 510 can selectively turn on / off the transmission transistors TR24 included in the page buffers PB1 to PBn according to the object (e.g., page buffer) where the data to be counted is located, so that the power consumed in the monitoring operation can be relatively reduced. When the monitoring circuit 510 determines the object where the data to be counted is located, the transmission transistor TR24 included in the object and the transmission transistor (or) TR24 provided between the object and the monitoring circuit 510 are turned on.

[0076] Fig.10 , Fig.11 , Fig.12 , Fig.13, Fig.14 and Fig.15 Various diagrams illustrating operations of the page buffer 400 according to an embodiment of the inventive concept.

[0077] Fig.10 The illustrated embodiment may correspond to a case where a monitoring circuit (eg, such as Figure 8 The monitoring circuit 510 in the embodiment of the present invention is used to perform a monitoring operation for counting data stored in at least one of the latches LAT_S, LAT_L and LAT_F. Fig.10 , according to (or in response to) the transmission control signal WOR_PASS, the transmission transistor TR24 is turned on, and the data transmission node DT of the page buffer 400 is connected to the data transmission node DT of another adjacent page buffer. The monitoring circuit can perform the monitoring operation by precharging the data transmission node DT to a predetermined power supply voltage VDD, and then evolving the voltage of the data transmission node DT using the data of the latch where the data to be counted is located.

[0078] As previously described, in an embodiment of the inventive concept, the transfer transistor TR24 included in the page buffer 400 may be turned off depending on an object to be monitored by the monitoring circuit (e.g., a data latch of the page buffer). Therefore, depending on the object to be monitored, the length of the line connecting the monitoring circuit and the data transmission node DT of the page buffer 400 to be monitored may be optimized, so the power consumption of the monitoring operation may be relatively reduced.

[0079] Figures 11 to 15 The illustrated embodiment is a diagram for explaining the operation of at least a portion (or some) of the latches LAT_S, LAT_L, and LAT_F exchanging data with each other in a state where the transmission transistor TR24 is turned off. In the following, for the sake of convenience, it is assumed that the data stored in the L latch LAT_L is moved to the S latch LAT_S. It should be understood that referring to Figures 11 to 15 The described embodiments may also be applied to other data transfer operations between the latches LAT_S, LAT_L, and LAT_F.

[0080] Reference Fig.11, the data transmission operation according to the embodiment may be performed in such a manner that the transfer transistor TR24 is turned off and the thirteenth transistor TR13 is turned on to precharge the data transmission node DT. For example, the thirteenth transistor TR13 may be a PMOS transistor and may be a first precharge element for precharging the data transmission node DT. When the thirteenth transistor TR13 is turned on, the data transmission node DT may be precharged to the first power supply voltage VDD. At the same time, the twelfth transistor TR12 may be turned on together with the thirteenth transistor TR13, so that the sensing node SO is precharged to the first power supply voltage VDD together with the data transmission node DT. The twelfth transistor TR12 may be a second precharge element for precharging the sensing node SO.

[0081] Next, refer to Fig.12 , the 23rd transistor TR23 connected to the L latch LAT_L is turned on. When the 23rd transistor TR23 is turned on, the voltage of the data transmission node DT may be evolved using a voltage corresponding to the data stored in the L latch LAT_L. For example, when a node connected to the 23rd transistor TR23 stores a relatively high logic value, the voltage of the data transmission node DT may decrease relatively slowly, or may not decrease substantially. On the contrary, when a node connected to the 23rd transistor TR23 stores a relatively low logic value, the voltage of the data transmission node DT may decrease relatively quickly.

[0082] When the voltage of the data transmission node DT is evolved, the on / off switching of the fifteenth transistor TR15 can be determined by the evolution result of the voltage of the data transmission node DT. For example, when the L latch LAT_L stores a relatively high logic value, the fifteenth transistor TR15 can be turned on. On the contrary, when the L latch LAT_L stores a relatively low logic value, the voltage of the data transmission node DT can be relatively reduced, and the fifteenth transistor TR15 can be turned off.

[0083] Next, refer to Fig.13 , the sixteenth transistor TR16 is turned on. For example, the sixteenth transistor TR16 can be turned on, and the twenty-third transistor TR23 can be turned on at the same time. Fig.12 As described above, when the L latch LAT_L stores a relatively high logic value, the fifteenth transistor TR15 may be turned on. When the sixteenth transistor TR16 is turned on, the voltage of the node SO may be reduced relatively quickly. On the contrary, when the L latch LAT_L stores a relatively low logic value, since the fifteenth transistor TR15 may be turned off, the voltage of the sense node SO hardly changes (e.g., changes very little, if at all) after the sixteenth transistor TR16 is turned on.

[0084] The determination result of the voltage of the sensing node SO may determine the on / off of the seventeenth transistor TR17. For example, when the L latch LAT_L stores a relatively high logic value, the voltage of the sensing node SO may decrease relatively quickly, and the seventeenth transistor TR17 may be turned off. On the contrary, when the L latch LAT_L stores a relatively low logic value, since the voltage of the sensing node SO is almost unchanged, the seventeenth transistor TR17 may be turned on.

[0085] Next, refer to Fig.14 , the fourteenth transistor TR14 is turned on. When the L latch LAT_L stores a relatively high logic value, since the seventeenth transistor TR17 is turned off, the voltage of the data transmission node DT may not change much before the fourteenth transistor TR14 is turned on. Therefore, the voltage of the data transmission node DT may have a value substantially equal to the precharged first power supply voltage VDD. Therefore, as Fig.15 As shown, when the eighteenth transistor TR18 (which may be a set transistor of the S latch LAT_S) is turned on, the S latch LAT_S may store a relatively high logic value. When the eighteenth transistor TR18 is turned on, a relatively high logic value may be stored in the S latch LAT_S, so that the voltage of the data transmission node DT may be relatively reduced.

[0086] Refer again Fig.14 , when the L latch LAT_L stores a relatively low logic value, the seventeenth transistor TR17 may be turned on before the fourteenth transistor TR14 is turned on, so that the data transmission node DT may be connected to the second power supply voltage GND. Therefore, the voltage of the data transmission node DT may be reduced to the second power supply voltage GND. Fig.15 As shown, when the eighteenth transistor TR18 (which may be a set transistor of the S latch LAT_S) is turned on, the F latch LAT_F may store a relatively low logic value.

[0087] Fig.16 A timing diagram illustrating an operation of a page buffer according to an embodiment of the inventive concept. Fig.17 A timing diagram illustrating another operation of a page buffer according to an embodiment of the inventive concept.

[0088] For example, Fig.16 and Fig.17 It can be a timing diagram for explaining the operation of transferring the data stored in the L latch LAT_L to the S latch LAT_S. Figures 11 to 15 The operation of the page buffer 400 is described.

[0089] Reference Fig.16 , the twelfth transistor TR12 and the thirteenth transistor TR13 are turned on at the first time point t1, and the sensing node SO and the data transmission node DT can be precharged respectively. For example, the sensing node SO and the data transmission node DT can be precharged to the first power supply voltage VDD. When the second time point t2 is reached, the twelfth transistor TR12 and the thirteenth transistor TR13 are turned off. When the third time point t3 is reached after a predetermined delay time from the second time point t2, the twenty-third transistor TR23 connected to the L latch LAT_L is turned on.

[0090] Reference Fig.16 The embodiment shown and further described below is an embodiment in which data "0" is stored in the node of the L latch LAT_L connected to the 23rd transistor TR23. Therefore, when the 23rd transistor TR23 is turned on, the voltage of the data transmission node DT can be relatively reduced. For example, the voltage of the data transmission node DT can be reduced to the second power supply voltage GND.

[0091] When the fourth time point t4 is reached, the sixteenth transistor TR16 is turned on, and the twenty-third transistor TR23 is turned on. The voltage of the data transmission node DT can be reduced to the second power supply voltage GND, so the fifteenth transistor TR15 is turned off, so that even after the sixteenth transistor TR16 is turned on, the sensing node SO can maintain the first power supply voltage VDD. When the fifth time point t5 is reached, the sixteenth transistor TR16 and the twenty-third transistor TR23 are turned off, and the fourteenth transistor TR14 is turned on.

[0092] Since the sensing node SO maintains the first power supply voltage VDD even after the fourth time point t4, the seventeenth transistor TR17 is continuously turned on. Therefore, when the fourteenth transistor TR14 is turned on at the fifth time point t5, the data transmission node DT can be connected to the second power supply voltage GND through the fourteenth transistor TR14 and the seventeenth transistor TR17. When the eighteenth transistor TR18 connected to the S latch LAT_S is turned on at the sixth time point t6, the data "0" is stored in the node of the S latch LAT_S connected to the eighteenth transistor TR18 through the data transmission node DT that is lowered to the second power supply voltage GND.

[0093] Next, refer to Fig.17 An embodiment illustrated and described below is an embodiment in which data "1" is stored in a node of the L latch LAT_L connected to the twenty-third transistor TR23. Fig.17, the sensing node SO and the data transmission node DT can be precharged by the twelfth transistor TR12 and the thirteenth transistor TR13 turned on between the first time point t1 and the second time point t2. Thereafter, when a predetermined delay time passes and the third time point t3 is reached, the twenty-third transistor TR23 is turned on. Fig.16 In contrast to the embodiment shown in , since data "1" is stored in the node of the L latch LAT_L connected to the twenty-third transistor TR23, the voltage of the data transmission node DT may not be substantially reduced. For example, even after the twenty-third transistor TR23 is turned on, the voltage of the data transmission node DT may be maintained at the first power supply voltage VDD, and the fifteenth transistor TR15 may be maintained in the on state.

[0094] When the sixteenth transistor TR16 is turned on at the fourth time point t4, the sensing node SO can be connected to the second power supply voltage GND through the fifteenth transistor TR15 and the sixteenth transistor TR16. Fig.17 As shown, after the fourth time point t4, the voltage of the sensing node SO is relatively reduced, and the seventeenth transistor TR17 is turned off. Therefore, even when the fourteenth transistor TR14 is turned on at the fifth time point t5, the data transmission node DT is not connected to the second power supply voltage GND, and the voltage of the data transmission node DT can be maintained at the first power supply voltage VDD.

[0095] When the eighteenth transistor TR18 connected to the S latch LAT_S is turned on at the sixth time point t6, data corresponding to the voltage of the data transmission node DT may be stored in the S latch LAT_S. Therefore, the data "1" stored in the L latch LAT_L may be stored in the S latch LAT_S. Since the data "1" is stored in the S latch LAT_S by maintaining the voltage of the data transmission node DT at the first power supply voltage VDD, the voltage of the data transmission node DT may be relatively reduced.

[0096] For example, in an embodiment of the inventive concept, the set transistor and the reset transistor of each of the latches LAT_S, LAT_L, and LAT_F may be connected to the data transmission node DT and the sensing node SO through the fourteenth transistor TR14 to the seventeenth transistor TR17. Therefore, compared with a conventional page buffer in which a transistor for connecting each of the latches LAT_S, LAT_L, and LAT_F to the sensing node SO is separately provided, the number of transistors TR1 to TR25 may be relatively reduced, and the page buffer may be effectively implemented in a limited area.

[0097] Moreover, in an embodiment of the present invention, the wire used only for the wired OR connection between the conventional page buffer and the monitoring circuit can be removed, and the wire used for the wired OR connection can also be used as a data transmission node between latches in the page buffer. Therefore, the design freedom of the layout of the page buffer in which the number and arrangement of the wires are limited can be improved, and at the same time, the power consumption of the memory device can be optimized by controlling the length of the wire used for the wired OR connection according to the object to be monitored. Moreover, by separating the sensing node and the data transmission node, the sensing node evolution and the data transmission operation can be performed simultaneously.

[0098] Fig.18 A block diagram of an electronic device including a memory device according to an embodiment of the inventive concept is shown.

[0099] according to Fig.18 The electronic device 1000 of the illustrated embodiment includes: a display 1010, an image sensor 1020, a memory 1030, a port 1040, and a processor 1050. The electronic device 1000 may include other components or devices. For example, the electronic device 1000 may also include a wired / wireless communication device and a power supply device, as well as other devices or components. Fig.18 Among the components shown, port 1040 may be a device that provides electronic device 1000 with, for example, a graphics card, a sound card, a memory card, a USB device, etc. Electronic device 1000 may be a comprehensive concept including, for example, a traditional desktop computer, a laptop computer, a smart phone, a tablet personal computer (PC), a smart wearable device, etc.

[0100] The processor 1050 may perform specific operations, commands, tasks, etc. The processor 1050 may be, for example, a central processing unit (CPU) or a microprocessor unit (MCU), and may communicate with other devices connected to the port 1040 in addition to communicating with the display 1010 , the image sensor 1020 , and the memory device 1030 .

[0101] The memory 1030 may be a storage medium for storing data required for the operation of the electronic device 1000 or, for example, multimedia data. The memory 1030 may be a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory. The memory 1030 may also include, for example, at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage device. The memory 1030 may include the storage device described above with reference to FIG. Figures 1 to 17 Any of the memory devices of the various embodiments described.

[0102] According to an embodiment of the present invention, the circuit and layout of the page buffer can be designed so that the line connected to the monitoring circuit in a conventional manner is used as a data transmission node, and the sensing line connected to the sensing node can be arranged between latch signal lines with complementary characteristics. Therefore, the design freedom of the circuit and layout according to the arrangement of the wires can be relatively improved, and the sensing node can be effectively protected from electromagnetic noise. In addition, by reading data from only a portion (some) of the page buffer during the monitoring operation, the power consumption of the memory device can be relatively reduced, and by evolving the sensing node when transmitting data between latches in the page buffer, the operating efficiency of the memory device can be relatively improved.

[0103] Various advantageous advantages and effects of the inventive concept are not limited to the above description and may be more easily understood in the course of describing specific embodiments of the inventive concept.

[0104] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; as well as a plurality of page buffers connected to the plurality of bit lines, Wherein, each of the plurality of page buffers comprises: a plurality of latches, the plurality of latches sharing a data transmission node and being configured to exchange data with each other through the data transmission node, and a pass transistor configured to set a connection between the data transmission node and another data transmission node of another page buffer of the plurality of page buffers, The storage device further includes a monitoring circuit, which is configured to selectively turn on or off the transmission transistors included in the multiple page buffers according to the page buffers where the objects to be monitored are located, and in response to the turning on of the transmission transistors in at least some of the multiple page buffers, is connected to the at least some of the page buffers in a wired OR configuration.

2. The memory device according to claim 1, wherein: Each of the plurality of page buffers further includes a connection circuit configured to connect a sensing node to at least one bit line of the plurality of bit lines and to exchange data with at least one latch of the plurality of latches through the sensing node.

3. The memory device according to claim 2, wherein: The data transmission node and the sensing node are different nodes.

4. The memory device according to claim 2, wherein: The plurality of latches include a sense latch connected to the sense node and a plurality of data latches configured to exchange data with the sense latch through the data transmission node.

5. The memory device according to claim 4, wherein: The sense latch and the plurality of data latches share at least one transistor connected between the data transmission node and the sense node.

6. The memory device according to claim 2, further comprising: a first pre-charging element, wherein the first pre-charging element is configured to pre-charge the data transmission node; as well as A second pre-charging element is configured to pre-charge the sensing node.

7. The memory device according to claim 1, wherein: At least one page buffer of the plurality of page buffers is connected to the monitoring circuit, The monitoring circuit is configured to count data of the plurality of latches through a transfer transistor included in the other page buffer.

8. The memory device according to claim 1, wherein: Each of the plurality of page buffers includes a plurality of conductive lines, and the data transmission node is one of the plurality of conductive lines.

9. The memory device according to claim 1, wherein: The plurality of page buffers are arranged along a first direction and a second direction orthogonal to the first direction, The data transmission nodes of some page buffers arranged at the same position in the second direction among the plurality of page buffers are connected or disconnected with each other through the transmission transistors of the some page buffers.

10. The memory device according to claim 9, wherein: The data transmission nodes of the some page buffers are connected to the monitoring circuit in response to the turning-on of the pass transistor, and the monitoring circuit is disposed at one side of the some page buffers along the first direction.

11. A storage device, comprising: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; a page buffer circuit, the page buffer circuit comprising a plurality of page buffers connected to the plurality of bit lines, each of the plurality of page buffers having a plurality of latches, the plurality of latches being configured to exchange data with each other through a data transmission node in the page buffer; as well as A control logic configured to selectively turn on or off a transfer transistor included in the multiple page buffers according to a page buffer in which an object to be monitored is located, to control the connection between the data transfer nodes of at least some of the multiple page buffers to identify data stored in the multiple page buffers, and to control the data transfer nodes in the multiple page buffers to be disconnected to exchange data between the multiple latches in at least one page buffer among the multiple page buffers.

12. The memory device according to claim 11, wherein: The control logic is configured to connect at least some of the data transmission nodes of the plurality of page buffers to each other to receive data in a wired OR configuration, and identify data stored in the plurality of page buffers based on the received data.

13. The memory device according to claim 11, wherein: Each of the plurality of page buffers includes a sense latch, a plurality of data latches, and a connection circuit connected between at least one bit line of the plurality of bit lines and a sense node, The sense latch and the plurality of data latches are connected to the connection circuit through the sense node.

14. The memory device according to claim 13, wherein: The control logic is configured to, in at least one page buffer among the multiple page buffers, precharge a data transmission node of the at least one page buffer to a first voltage, evolve the first voltage of the data transmission node into a second voltage corresponding to the data of the sensing latch, and store the data corresponding to the second voltage in at least one data latch among the multiple data latches through the data transmission node of the at least one page buffer among the multiple page buffers.

15. The memory device according to claim 13, wherein: The control logic is configured to control the sense latch and at least some of the plurality of data latches to exchange data between each other, while precharging the sense node to a predetermined voltage and evolving the predetermined voltage of the sense node to a voltage of at least one of the plurality of bit lines.

16. A page buffer, comprising: a plurality of semiconductor elements formed in a first region of a semiconductor substrate and configured to provide a latch connected to at least one bit line of a plurality of bit lines through a sensing node; a first latch signal line disposed on a first layer in the first region and connected to a first node of the latch; a second latch signal line disposed on the first level and connected to a second node of the latch, wherein a voltage of the first node and a voltage of the second node are complementary; as well as A sensing line is disposed between the first latch signal line and the second latch signal line on the first layer and is configured to provide the sensing node.

17. The page buffer according to claim 16, wherein: The first latch signal line, the second latch signal line, and the sensing line extend along a first direction parallel to a top surface of the semiconductor substrate.

18. The page buffer according to claim 17, wherein: The plurality of semiconductor elements in the first region are arranged along the first direction.

19. The page buffer according to claim 17, further comprising: A data transmission line is arranged adjacent to the first latch signal line on the first level and extends along the first direction.

20. The page buffer according to claim 19, wherein: The length of the data transmission line in the first direction is shorter than the length of the first region in the first direction.

21. The page buffer according to claim 19, wherein: The plurality of semiconductor elements include a transfer transistor having an active region connected to the data transmission line.

22. The page buffer according to claim 21, wherein: The data transmission line is electrically connected to other data transmission lines adjacent in a first direction, and is electrically connected to a monitoring circuit configured to identify data stored in the latch through the pass transistor.

23. The page buffer according to claim 21, wherein: The transfer transistor is disposed adjacent to a boundary of the first region in the first direction.

24. The page buffer according to claim 21, wherein: The plurality of semiconductor elements include: another transistor disposed adjacent to the transfer transistor and connected in series with the transfer transistor, An active region included in one of the additional transistors is connected to the data transmission line, and a gate electrode included in another of the additional transistors is connected to the sensing line.

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