Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including: forming first and second silicon nitride components on sidewall surfaces of a contact hole, the contact hole being disposed in a dielectric layer and above a source / drain (S / D) component. The method further includes forming a contact plug in the contact hole, the contact plug being electrically coupled to the source / drain component, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride components by selective etching to form first and second air gaps respectively. The present disclosure also provides a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same, and particularly to the formation of air gaps between metal lines. Background Art

[0002] The semiconductor industry has experienced rapid development. Technological advancements in semiconductor materials and designs have made semiconductor devices produced in each generation smaller than those produced previously and their circuits more complex. In the process of integrated circuit (IC) development, the functional density (i.e., the number of interconnected devices in each chip area) has generally increased, while the geometric size (i.e., the smallest component or circuit that can be created in the process) has generally decreased. This miniaturization process generally provides many benefits by increasing production efficiency and reducing related costs, but this miniaturization also increases the complexity of semiconductor device processing and manufacturing.

[0003] For example, as device geometry miniaturizes, the parasitic capacitance between interconnects (such as source / drain (S / D) contact plugs and nearby gates) increases. The increased parasitic capacitance degrades device performance. To reduce the parasitic capacitance, insulating materials with a relatively low dielectric constant (k), such as low-k dielectrics and air gaps, have been used between source / drain (S / D) components and nearby gates. However, these materials are fragile, unstable, difficult to deposit, or sensitive to processes such as etching, annealing, and polishing, and the formation of air gaps is difficult to control. For these and other reasons, it is desirable to improve the manufacturing technology of the dielectric between interconnects to reduce the parasitic capacitance while maintaining a high overall transistor density in an integrated circuit (IC). Summary of the Invention

[0004] According to an embodiment of the present invention, a method of manufacturing a semiconductor device is provided, including: forming first and second silicon nitride components on sidewall surfaces of a contact hole disposed in a dielectric layer and above a source / drain (S / D) component; forming a contact plug in the contact hole, the contact plug being electrically coupled to the source / drain component; removing a top portion of the contact plug to create a recess in the contact hole; forming a hard mask layer in the recess; and removing the first and second silicon nitride components by selective etching to respectively form first and second air gaps.

[0005] According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: providing a semiconductor device structure, the semiconductor device structure comprising: a substrate, first and second gate stacks located on the substrate, first and second silicon nitride components located between the first and second gate stacks, and a contact plug located between the first and second silicon nitride components and in contact with the first and second silicon nitride components; etching the first and second silicon nitride components to respectively form first and second air gaps, wherein the first and second air gaps expose the sidewalls of the contact plug to air within the first and second air gaps; and forming a sealing layer over the contact plug to cover the first and second air gaps.

[0006] According to another embodiment of the present invention, there is provided a semiconductor device, comprising: a substrate; a source / drain (S / D) component disposed on the substrate; a metal plug disposed over the source / drain component; a gate stack disposed adjacent to the metal plug; an air gap disposed between the metal plug and the gate stack, wherein the air gap at least partially exposes a sidewall of the metal plug to air within the air gap; and a covering layer covering the air gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present invention may be read in conjunction with the following drawings and detailed description for understanding. It should be emphasized that, in accordance with industrial standard practice, the various components (features) are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily enlarged or reduced.

[0008] Figure 1 is a flowchart showing a first method of manufacturing a semiconductor device according to various embodiments of the present invention.

[0009] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F shows Figure 1 a cross-sectional schematic view of a semiconductor device during various stages of the method shown.

[0010] Figure 3A 、 Figure 3B 、 Figure 3C FIG shows Figure 1 a cross-sectional schematic view of a semiconductor device during more stages of the method shown.

[0011] Figure 4 is a flowchart showing a second method of manufacturing a semiconductor device according to various embodiments of the present invention.

[0012] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、Figure 5E Display Figure 4 Cross-sectional schematic views of a semiconductor device during various stages of the method shown.

[0013] Figure 6 Is a partial plan view showing a semiconductor device according to various embodiments of the present invention.

[0014] Description of reference numerals:

[0015] 10, 40 Method

[0016] 12~30, 42~50 Operations

[0017] 100 Semiconductor device

[0018] 102 Substrate

[0019] 106a, 106b Source / drain (S / D) components

[0020] 110, 170 Interlayer dielectric (ILD) layers

[0021] 112 Gate spacer

[0022] 116a, 116b, 116c Gate stacks

[0023] 130a, 130b Contact holes

[0024] 132 Sidewall surface

[0025] 134 Bottom surface

[0026] 136a, 136b Contact plugs

[0027] 139 Barrier layer

[0028] 141 Metal fill layer

[0029] 142a, 142b, 142c, 142d Silicon nitride components

[0030] 150a, 150b, 150c, 150d Air gaps

[0031] 152 Sealing layer

[0032] 154 Metal nitride layer

[0033] 156 Etch stop layer

[0034] 160 Hard mask layer

[0035] A’, B-B’ Lines Detailed description

[0036] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. The following describes examples of specific elements and their arrangements to simplify the embodiments of the present invention. Of course, these are only examples and should not limit the scope of the embodiments of the present invention. For example, when it is described in the description that the first component is formed "on" or "above" the second component, it may include embodiments where the first component is in direct contact with the second component, and it may also include embodiments where other components are formed between the two without direct contact. Additionally, reference signs and / or labels may be reused in different embodiments of the present invention. These repetitions are for the purpose of simplification and clarity and are not used to define a specific relationship between the different embodiments and / or structures being discussed. Furthermore, for the purpose of simplification and clarity, each component may be arbitrarily drawn in different scales.

[0037] In addition, spatial-related terms used therein, such as "below", "beneath", "lower", "above", "higher", and their similar terms are used to facilitate the description of the relationship between one element or component shown in the drawings and another element or component. These spatial relationship terms are used to cover different orientations of the device in use or operation other than the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" other elements or components will be turned to be "above" other elements or components. Thus, the exemplary term "below" can cover both the "above" and "below" orientations. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial-related adjectives used therein can be similarly interpreted.

[0038] Embodiments of the present invention generally relate to semiconductor devices and methods of manufacturing the same, and more particularly to the formation of air gaps between metal wires such as contact plugs and adjacent gates. As the technology of fin field-effect transistors (FinFETs) continues to progress towards smaller technology nodes such as 16 nanometers, 10 nanometers, 7 nanometers, 5 nanometers, and below, reducing the fin pitch significantly limits the materials available between the gate stack and adjacent contact plugs connected to the source / drain (S / D) components. To minimize the parasitic capacitance between the gate stack and the contact plugs, air gaps can help because air has a lower dielectric constant (k = 1) than other dielectric materials. However, when the air gap is formed before the contact plug, the air gap tends to be close to the gate stack and away from the contact plug. In addition, subsequent formation of the contact plug is likely to damage the air gap. For example, when forming a contact plug, if the mask used to pattern the contact plug is not perfectly aligned with the underlying components, an overlay shift may occur. Due to the overlay shift, the position of the contact hole may be very close to the adjacent gate stack. In this case, etching the contact hole will expose the air gap that has been sealed, and the exposed air gap may be partially or completely filled by the contact plug. As a result, the air gap will lose its purpose of reducing the parasitic capacitance.

[0039] Embodiments of the present invention avoid these problems by forming the air gap after (not before or simultaneously with) the formation of the contact plug. For example, by first depositing a silicon nitride component in the contact hole, then forming the contact plug sandwiched between the silicon nitride components, and then selectively etching the silicon nitride components to form the air gap. The selective removal of the silicon nitride components is achieved by the etching selectivity of the silicon nitride component material compared to other surrounding materials. The post-plug formation of the air gap disclosed herein results in the air gap extending above the top surface of the adjacent gate stack. As a result, the parasitic capacitance between the gate stack and the contact plug can be effectively reduced. In addition, the disclosed air gap is in direct contact with the contact plug above the source / drain (S / D) components, thereby exposing the sidewalls of the contact plug to air. When the contact plug conducts current, this air exposure helps with heat dissipation.

[0040] Various manufacturing methods can be used to achieve the post-plug formation of the air gap disclosed herein. Figure 1 is a first method 10 of manufacturing a semiconductor device (or device structure) 100 according to aspects of embodiments of the present invention. Method 10 is merely an example, and method 10 is not intended to limit the embodiments of the present invention except as explicitly recited in the claims. Additional operations can be provided before, during, and after method 10, and some of the operations described can be replaced, deleted, or moved in other embodiments of method 10. In the following discussion, reference is made to Figures 2A - 2F and Figures 3A - 3C, Method 10 is described by partial schematic cross-sectional views of part or all of semiconductor device 100 at various manufacturing stages according to different embodiments of the present invention.

[0041] Semiconductor device 100 may be or include a fin field-effect transistor (FinFET) device (fin-based transistor), which may be included in a microprocessor, a memory cell, and / or other integrated circuit (IC) devices. Semiconductor device 100 may be an intermediate device manufactured during the process of an integrated circuit (IC) chip, a system on chip (SoC), or a part of the foregoing, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other suitable components, or a combination of the foregoing. For the purpose of clarity and easier understanding of the inventive concept of the present invention, Figures 2A - 2F . Additional components may be added to semiconductor device 100, and some of the components described below may be replaced, modified, or deleted in other embodiments of semiconductor device 100.

[0042] At operation 12, method 10 provides or is provided with an initial semiconductor device 100. As Figure 2A shown, the initial semiconductor device 100 includes elements such as a substrate 102, source or drain (S / D) components 106a and 106b, an inter-layer dielectric (ILD) layer 110, gate spacers 112, gate stacks 116a, 116b, and 116c, and contact holes 130a and 130b. Semiconductor device 100 may include other elements not shown in the accompanying drawings here. The elements of semiconductor device 100 will be further described below.

[0043] The substrate 102 is a semiconductor substrate (e.g., a silicon wafer) in this embodiment. Alternatively, the substrate 102 may include another elemental semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination of the foregoing. The substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the semiconductor device 100, the substrate 102 may include various doped regions (not shown). In some embodiments, the substrate 102 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant such as boron, indium, other p-type dopants, or a combination of the foregoing. In some embodiments, the substrate 102 includes an n-type doped region (e.g., an n-type well) doped with an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination of the foregoing. In some embodiments, the substrate 102 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Each doped region may be directly formed on and / or in the substrate 102, e.g., providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination of the foregoing. An ion implantation process, a diffusion process, and / or other suitable doping processes may be performed to form various doped regions in the substrate 102.

[0044] Source / drain (S / D) components 106a and 106b are disposed on substrate 102 and may include n-type doped silicon for n-type field effect transistors (NFETs), p-type doped silicon germanium for p-type field effect transistors (PFETs), or other suitable materials. The source / drain (S / D) components 106a and 106b may be formed by etching depressions in the active regions adjacent to the gate stacks 116a-116c and then epitaxially growing a semiconductor material in the depressions. The epitaxially grown semiconductor material may be doped in-situ or ex-situ with appropriate dopants. The source / drain (S / D) components 106a and 106b may have any suitable shape and may be fully or partially embedded in the active regions. For example, depending on the amount of epitaxial growth, the source / drain (S / D) components 106a and 106b may rise above, on, or below the top surface of the fin.

[0045] An interlayer dielectric (ILD) layer 110 is disposed on substrate 102. The interlayer dielectric (ILD) layer 110 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric (ILD) layer 110 may be formed by plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), or other suitable methods.

[0046] The gate stacks 116a to 116c may each include a bottom gate dielectric layer and a gate electrode layer disposed on the gate dielectric layer. The gate dielectric layer may include SiO2 or a high-k (high dielectric constant) dielectric material, such as hafnium silicate (HfSiO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or a combination of the foregoing. Chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable methods may be utilized to deposit the gate dielectric layer. The gate electrode layer of the gate stack 116a, 116b, or 116c may include polysilicon and / or one or more metal layers. For example, the gate electrode layer may include a work function metal layer, a conductive barrier layer, and a metal fill layer. Depending on the device type, the work function metal layer may be a p-type or an n-type work function layer. The p-type work function layer may include titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), another suitable metal, or a combination of the foregoing. The n-type work function layer may include titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), another suitable metal, or a combination of the foregoing. The metal fill layer may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials. The gate electrode layer may be deposited by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and / or other suitable processes. The gate stacks 116a, 116b, or 116c may further include an interface layer below the gate dielectric layer. The interface layer may include a dielectric material such as SiO2 or SiON, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0047] Each gate stack may be coupled to an adjacent gate spacer 112. In some embodiments, the gate spacer 112 is considered to be the sidewall of its adjacent gate stack. Each gate spacer 112 may be a single-layer or multi-layer structure. For example, the gate spacer 112 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination of the foregoing. The gate spacer 112 may be formed by deposition (e.g., CVD or PVD) and an etching process.

[0048] The gate stacks 116a - 116c can be formed by any suitable process, such as gate - first process and gate - last process. In an exemplary gate - first process, before forming the source / drain (S / D) components 106a and 106b, the respective material layers are deposited and patterned to be the gate stacks 116a - 116c. In an exemplary gate - last process (also known as gate replacement process), a temporary gate structure (sometimes called a "dummy" gate) is first formed. Then, after forming the transistor source / drain (S / D) components 106a and 106b, the temporary gate structure is removed and replaced by the gate stacks 116a - 116c. In Figure 2A the illustrated embodiment, the gate stack 116a, 116b, or 116c can be disposed over the channel region of the transistor to serve as a gate terminal. For example, although not shown in Figure 2A , metal plugs can be disposed on such a gate stack and electrically coupled to such a gate stack to apply an adjustable voltage to the gate stack. The voltage can control the channel region between the source / drain (S / D) components (such as 106a and 106b).

[0049] As Figure 2A shown, the contact hole 130a is located between the gate stacks 116a and 116b, and the contact hole 130b is located between the gate stacks 116b and 116c. The contact holes 130a and 130b expose the tops of the source / drain (S / D) components 106a and 106b respectively. Each contact hole includes a sidewall surface 132 and a bottom surface 134, where the bottom surface 134 is substantially the same as the top surface of the underlying source / drain (S / D) component.

[0050] At operation 14, the method 10 ( Figure 1 ) forms a silicon nitride component on the sidewall surface 132 of the contact hole. Still referring to Figure 2A, silicon nitride components 142a and 142b are formed in contact hole 130a, while silicon nitride components 142c and 142d are formed in contact hole 130b. The formation of the silicon nitride components involves multiple steps. In the first step, a silicon nitride layer is formed on semiconductor device 100 to cover, for example, at least contact holes 130a and 130b, but may also cover the topmost surface of semiconductor device 100. The silicon nitride layer can be formed by one or more methods such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and / or other suitable deposition or nitridation processes. For example, the silicon nitride layer can be a thin layer that has a generally compliant thickness across the top surface of semiconductor device 100. In addition to silicon nitride, the layer can also include other suitable materials such as doped carbon. In some embodiments, multiple deposition cycles can be performed to achieve the target thickness of the silicon nitride layer. In the second step, the silicon nitride layer is selectively etched (e.g., using mask-assisted dry etching) to remove portions located on the bottom surface 134 and the topmost surface of the interlayer dielectric (ILD) layer 110. As a result, silicon nitride components 142a - 142d remain on the sidewall surface 132. Since the top surfaces of the source / drain (S / D) components 106a and 106b need to be exposed, a selective etching process is performed to etch the portion of the silicon nitride layer located on the bottom surface 134. In addition, the selective etching process can also "thin" silicon nitride components 142a - 142d (remove a thickness portion) to create more lateral space for the subsequent deposition of contact plugs. In some embodiments, operation 14 is controlled to achieve the target dimensions (e.g., height and width) of silicon nitride components 142a - 142d. The dimensions of silicon nitride components 142a - 142d can effectively control the dimensions of the air gaps, which are formed by removing silicon nitride components 142a - 142d (described below).

[0051] It should be noted that since semiconductor device 100 is a three-dimensional structure (a cross-sectional view is shown here), silicon nitride components 142a and 142b can actually represent the same dummy component, but for clarity, they are separately labeled in the cross-sectional view. The same consideration applies to other labels, such as silicon nitride components 142c and 142d (as well as air gaps 150a - 150b and air gaps 150c and 150d, all of which will be further described below).

[0052] Next, method 10 fills one or more conductive materials into contact holes 130a and 130b to form first and second contact plugs, respectively. The contact plugs are labeled 136a and 136b in Figure 2F but their formation is through Figures 2C - 2FThe several steps shown in, because each contact plug includes a barrier layer 139 and a metal fill layer 141 located above and adjacent to the barrier layer 139, as Figure 2F shown.

[0053] Specifically, at operation 16, method 10 forms a barrier layer 139 over the semiconductor device 100 ( Figure 2B ). The barrier layer 139 covers at least the contact holes 130a and 130b, but may also cover the topmost surface of the semiconductor device 100, as Figure 2B shown. The barrier layer 139 includes a metal nitride layer such as TaN or TiN. The barrier layer 139 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or other suitable methods. In one embodiment, an atomic layer deposition (ALD) process is used to uniformly deposit the barrier layer 139 over the semiconductor device 100. The barrier layer 139 can help prevent the metal fill layer 141 to be formed from penetrating into the surrounding silicon or oxide regions. In some embodiments, the barrier layer 139 further includes a metal silicide layer located below the metal nitride layer. For example, method 10 first deposits a metal layer (using the same metal as the metal nitride layer, such as Ta or Ti), and then performs an annealing process at an elevated temperature. During annealing, the metal layer reacts with the semiconductor material (such as silicon) in the source / drain (S / D) components 106a and 106b to form a metal silicide layer thereon. The metal silicide layer can include tantalum silicide, titanium silicide, or other suitable silicidation or germanosilicidation. The metal silicide layer can cover the heavily doped regions of the source / drain (S / D) components 106a and 106b, and in some cases, the metal silicide layer is regarded as part of the source / drain (S / D) components 106a and 106b.

[0054] At operation 18, method 10 ( Figure 1 ) etches or "pulls back" the barrier layer 139 to partially expose the silicon nitride components 142a - 142d ( Figure 2C ). Specifically, method 10 selectively removes a portion of the barrier layer 139 disposed on the topmost surface of the interlayer dielectric (ILD) layer 110 and on the upper sidewall portions of the contact holes 130a and 130b. A dry etching or wet etching process can be utilized. Enough of the barrier layer 139 is removed such that the tops of the silicon nitride components 142a - 142d are exposed to the ambient environment.

[0055] At operation 20, method 10 ( Figure 1)Perform a surface cleaning and treatment process to clean and treat the surface of the barrier layer 139 and the exposed surfaces of the silicon nitride components 142a - 142d to remove chemicals and residues thereon.( Figure 2D )Any suitable method and / or material can be used for surface cleaning and treatment. In one embodiment, a solution containing hydrochloric acid (HCl) and an organic cleaner is used for deep cleaning. As Figure 2D shown, the cleaning and treatment process can also "thin" the higher portions of the barrier layer 139, resulting in a tapered thickness profile on the sidewall surface 132 of the barrier layer 139. The tapered thickness profile of the barrier layer 139 causes its thickness to gradually increase from top to bottom. For example, although the barrier layer 139 starts with a generally uniform thickness profile( Figure 2C ), after the cleaning and treatment process, the higher portions of the barrier layer 139 can be significantly thinner than its lower portions( Figure 2D ). In some embodiments, the thickness of the top surface of the barrier layer 139 is less than the bottom thickness of the barrier layer 139 (but still 50% or more of the bottom thickness (e.g., 60%, 70%)).

[0056] At operation 22, method 10( Figure 1 ) forms a metal fill layer 141 over the semiconductor device 100( Figure 2E ). The metal fill layer 141 can include cobalt (Co), tungsten (W), platinum (Pt), silver (Ag), nickel (Ni), copper (Cu), palladium (Pd), combinations of the foregoing, or other suitable materials. The metal fill layer 141 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or other suitable methods. In some embodiments, when depositing the metal fill layer 141, a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes is utilized. For example, a thin cobalt layer can be first deposited as a seed layer using a physical vapor deposition (PVD) process (at a slower deposition rate but with better quality), and then a thick cobalt layer can be deposited as a bulk layer using a chemical vapor deposition (CVD) process (at a faster deposition rate but possibly not having the same quality as the cobalt seed layer). When depositing the seed layer, its thickness is controlled so as not to block the deposition of the bulk layer in the curved profile region. As Figure 2E shown, the metal fill layer 141 is electrically coupled to the source / drain (S / D) components 106a and 106b through the barrier layer 139.

[0057] At operation 24, method 10( Figure 1)The metal fill layer 141 is planarized using a chemical mechanical planarization (CMP) process, which removes the top of the metal fill layer 141( Figure 2F ). Each of the contact plugs 136a and 136b includes a barrier layer 139 and a metal fill layer 141, as Figure 2F shown. Contact plugs are sometimes also referred to as vias, via plugs, metal contacts, or metal plugs. To facilitate the subsequent formation of air gaps, in some embodiments, the chemical mechanical planarization (CMP) process is long enough to ensure the exposure of the silicon nitride components 142a-142d.

[0058] After operation 24, air gaps can be formed using various methods. Figures 3A - 3C shows a first air gap formation method, and Figures 5A - 5E shows a second air gap formation method. The two methods are described in sequence below.

[0059] At operation 26, method 10( Figure 1 ) removes the silicon nitride components 142a-142d to form air gaps 150a-150d( Figure 3A ), respectively. Specifically, an air gap 150a is formed between the contact plug 136a and the adjacent gate stack 116a to reduce the first capacitance therebetween, an air gap 150b is formed between the contact plug 136a and the adjacent gate stack 116b to reduce the second capacitance therebetween, an air gap 150c is formed between the contact plug 136b and the adjacent gate stack 116b to reduce the third capacitance therebetween, and an air gap 150d is formed between the contact plug 136b and the adjacent gate stack 116c to reduce the fourth capacitance therebetween. The capacitance is reduced because air has a dielectric constant (k) of approximately 1, which is lower than other dielectric materials. In some embodiments (e.g., when there is no overlap shift), the air gaps 150a-150d have substantially the same size, and the first, second, third, and fourth capacitances are substantially equal. However, if there is an overlap shift, the air gaps 150a-150d may have different sizes, resulting in different corresponding capacitances. Unequal capacitances on both sides of the contact plug 136a may unevenly affect the associated circuit, but since both the first and second capacitances are reduced here, their overall impact on the circuit is also reduced.

[0060] It should be noted that in the method 10 disclosed herein, the air gaps 150a-150d are formed after the contact plugs 136a and 136b are formed. This is different from the conventional air gap formation method, which forms the air gap before forming its corresponding contact hole (and contact plug). This change in sequence is counterintuitive, for example, because the post-plug formation of the air gap brings unique etch selectivity considerations, and such etch selectivity cannot be achieved by the conventional method. However, as disclosed herein, the post-plug formation of the air gap brings various benefits, such as reducing the risk of short circuit between the gate stack and the adjacent source / drain (S / D) components in the presence of overlap shift. This in turn improves the reliability of the device and enables a higher breakdown voltage. In addition, since the volume of the air gap is precisely controlled by adjusting the height and / or width of the silicon nitride components 142a-142d, the parasitic capacitance between the gate stack and the contact plug can be effectively controlled. The optimized AC / DC gain can be achieved without potential air gap damage. Furthermore, different from the conventional method in which the top surface of the air gap is lower than the gate stack, the air gaps 150a-150d disclosed herein extend above the top surface of the gate stacks 116a-116c. The higher air gaps 150a-150d help to reduce the fringe capacitance that forms part of the parasitic capacitance. For example, the air gap 150a reduces the fringe capacitance between the higher part of the contact plug 136a and the higher part of the gate stack 116a. As a result, the overall parasitic capacitance between the adjacent gate stack and the contact plug is further reduced.

[0061] In one embodiment, the materials of the silicon nitride components 142a - 142d have high etch selectivity relative to the barrier layer 139, the interlayer dielectric (ILD) layer 110, and the metal fill layer 141, such that the silicon nitride components 142a - 142d can be completely removed with substantially no impact on the other surrounding layers. In one embodiment, the silicon nitride components 142a - 142d can be removed at a rate that is at least 10 times (or 20 times, or 50 times) faster than other materials in contact with the silicon nitride components 142a - 142d during the etching process. This etch selectivity depends on the material selection of the silicon nitride components 142a - 142d, the barrier layer 139, the interlayer dielectric (ILD) layer 110, and the metal fill layer 141. Thus, the material compositions of these layers are considered in a combined manner. In one embodiment, the silicon nitride components 142a - 142d include silicon nitride; the barrier layer 139 includes Ti and TiN; the interlayer dielectric (ILD) layer 110 includes low-k materials such as silicon oxide (SiO2), silicon carbonitride (SiCN), and / or silicon carbon oxide (SiCO); and the metal fill layer 141 includes cobalt (Co) and / or tungsten (W). The etch selectivity is based on different reactivities to the same etchant.

[0062] The selective etching process at operation 26 can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In one embodiment, dry etching is used with a fluorine-containing gas, which includes sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), selenium hexafluoride (SeF6), perfluoroethane (C2F6), perfluoropropane (C3F8), or another applicable gas, or a combination of the foregoing. Fluorine radicals can be diluted (e.g., between 1 - 5%) to aid in etch selectivity. In some embodiments, the flow rate of the fluorine-containing gas is in the range of about 10 sccm to about 500 sccm. Dry etching effectively reaches the silicon nitride at the bottom of the air gap, which improves the aspect ratio of the air gap. Additionally, wet etching can be used with diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH), or other suitable wet etchants.

[0063] At operation 28, method 10 ( Figure 1 ) seals the air gaps 150a - 150d by forming a capping layer or a sealing layer 152 ( Figure 3B ) that covers the air gaps 150a - 150d. When forming the sealing layer 152, the volume of the air gaps 150a - 150d is finalized. As Figure 3BAs shown, the sealing layer 152 interfaces with the air gaps 150a - 150d at a height above the top surface of the gate stacks 116a - 116c. The interface can be slightly below the top surface of the interlayer dielectric (ILD) layer 110 because during its formation, the sealing layer 152 slightly penetrates into the air gaps 150a - 150d (e.g., not more than 5 nanometers, such as 1 - 5 nanometers). In some embodiments, the air gaps 150a - 150d have a very small width (e.g., 1 - 5 nanometers) to reduce the risk of the sealing layer 152 deeply penetrating into the air gaps 150a - 150d.

[0064] The sealing layer 152 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and / or other suitable methods. In one embodiment, physical vapor deposition (PVD) is utilized because it can quickly deposit an initial layer that prevents other materials from entering the air gaps 150a - 150d. As a result, the air gaps 150a - 150d can become higher. In another embodiment, atomic layer deposition (ALD) with a carbon - containing precursor is used. In one embodiment, the thickness of the sealing layer 152 is between 2 - 7 nanometers. The sealing layer 152 can use any suitable material as long as it can completely enclose the air gaps 150a - 150d to prevent other materials from entering the air gaps 150a - 150d. In one embodiment, the sealing layer 152 uses silicon, silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbide (SiC), or a combination of the foregoing.

[0065] At operation 30, method 10 ( Figure 1 ) forms two additional layers - including a metal nitride layer 154 and an etch stop layer 156 - on top of the sealing layer 152 ( Figure 3C ). Both the sealing layer 152 and the etch stop layer 156 can serve as middle contact etch stop layers (MCESLs), and in this case, the metal nitride layer 154 is sandwiched between the two etch stop layers to create an interleaved layer structure. In one embodiment, the metal nitride layer 154 includes titanium nitride (TiN), and the etch stop layer 156 includes silicon nitride (SiN) or another suitable material. Compared with metals, the metal nitride layer 154 has a relatively high resistivity and can be used to form resistors in the semiconductor device 100. The etch stop layer 156 facilitates further processing of method 10 not described in detail here. For example, another contact plug can be formed on top of and electrically connected to the contact plugs 136a and 136b. Metal wires can be formed to interconnect the higher plugs and other circuit components.

[0066] As described above, Figures 3A - 3C (corresponding to operations 26, 28, and 30) shows a first air gap forming method. In contrast, Figures 5A - 5E shows a second air gap forming method, which corresponds to Figure 4 the method 40 shown in. Methods 10 and 40 are the same in many aspects, including operations 12 to 24, and for the sake of brevity, the same or similar aspects will not be described again. The following description focuses on the aspects in which method 40 is different from method 10.

[0067] Method 40 begins with the semiconductor device 100 that has undergone the above operation 24. Then, at operation 42, method 40 ( Figure 4 ) removes the upper portions of the contact plugs 136a and 136b to create two recesses in the contact holes 130a and 130b respectively ( Figure 5A ). Specifically, "back etching" is used to remove the remaining portion of the metal fill layer 141 as shown in Figure 2F to create the recesses. A small upper portion of the barrier layer 139 as shown in Figure 2F can also be removed. The recesses are formed by a selective etching process, which can utilize dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The etching conditions are tailored to maintain the target thickness of the contact plugs 136a and 136b in order to facilitate the subsequent operation 44. In one embodiment, the recesses are at least 3 nanometers above the top surface of the gate stacks 116a to 116c.

[0068] At operation 44, method 40 ( Figure 4 ) deposits a hard mask layer 160 on top of the top surface of the semiconductor device 100 ( Figure 5B ). The hard mask layer 160 can include any suitable material. In one embodiment, the hard mask layer 160 includes silicon, silicon carbonitride (SiCN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or a combination of the foregoing, or another isolation material. The hard mask layer 160 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or other suitable methods.

[0069] At operation 46, method 40 ( Figure 4 ) planarizes the hard mask layer 160 using a chemical mechanical polishing (CMP) process ( Figure 5C), which removes the top of the hard mask layer 160. To facilitate the subsequent formation of air gaps, in some embodiments, the chemical mechanical planarization (CMP) process is long enough to ensure the exposure of the silicon nitride components 142a - 142d. For example, the chemical mechanical planarization (CMP) process may also remove the top of the interlayer dielectric (ILD) layer 110 to expose the top surfaces of the silicon nitride components 142a - 142d. In one embodiment, 2 - 5 nanometers of the hard mask layer 160 are retained after chemical mechanical planarization (CMP). Operations 44 and 46 together form the hard mask layer 160, which fills the two recesses created by operation 42 in the contact holes 130a and 130b. The hard mask layer 160 exposes the top surfaces of the silicon nitride components 142a - 142d.

[0070] At operation 48, method 40 ( Figure 4 ) removes the silicon nitride components 142a - 142d to form air gaps 150a - 150d ( Figure 5D ), respectively. The characteristics of the above - mentioned air gaps 150a - 150d of method 10 also apply here. However, in method 40, if the top of the interlayer dielectric (ILD) layer 110 is removed during the chemical mechanical planarization (CMP) process of operation 46, the height of the air gaps 150a - 150d may be relatively small. In addition, compared to the barrier layer 139, the interlayer dielectric (ILD) layer 110, and the hard mask layer 160, the selective etching process at operation 48 has a high etching selectivity for the silicon nitride components 142a - 142d, such that the silicon nitride components 142a - 142d can be completely removed with substantially no impact on other surrounding layers. Such etching selectivity now additionally depends on the material selection of the hard mask layer 160.

[0071] At operation 50, method 40 ( Figure 4 ) seals the air gaps 150a - 150d ( Figure 5E ) by depositing a second interlayer dielectric (ILD) layer 170 that covers the air gaps 150a - 150d. The interlayer dielectric (ILD) layer 170 is also a sealing layer or a covering layer. When forming the interlayer dielectric (ILD) layer 170, the volume of the air gaps 150a - 150d is finalized. As Figure 5E shown, the interlayer dielectric (ILD) layer 170 interfaces with the air gaps 150a - 150d at a height above the top surfaces of the gate stacks 116a - 116c. The interface may be slightly below the top surface of the interlayer dielectric (ILD) layer 110 because during its formation, the interlayer dielectric (ILD) layer 170 slightly penetrates into the air gaps 150a - 150d (e.g., 1 - 5 nanometers). But the interface is still above the bottom surface of the hard mask layer 160 (which corresponds to the top surfaces of the contact plugs 136a and 136b, as Figure 5Eas shown). In some embodiments, the air gaps 150a-150d have a very small width (e.g., 1-5 nanometers or even smaller, such as 0.5 nanometers) to reduce the risk of the interlayer dielectric (ILD) layer 170 penetrating deeply into the air gaps 150a-150d.

[0072] The interlayer dielectric (ILD) layer 170 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and / or other suitable methods. In one embodiment, physical vapor deposition (PVD) is used because it can quickly deposit an initial layer that prevents other materials from entering the air gaps 150a-150d. As a result, the air gaps 150a-150d can become higher. In another embodiment, atomic layer deposition (ALD) with a carbon-containing precursor is used. The interlayer dielectric (ILD) layer 170 can use any suitable material as long as it can completely enclose the air gaps 150a-150d to prevent other materials from entering the air gaps 150a-150d. In one embodiment, the interlayer dielectric (ILD) layer 170 includes silicon oxide (SiO2).

[0073] Note that although methods 10 and 40 result in different structures on the semiconductor device 100, those structures can be similar or identical in many respects. For example, a partial plan view of a portion of the semiconductor device 100 at a height below the gate stacks 116a-116c will be the same. Figure 6 Shown by Figure 3C center line A-A' and Figure 5E a partial plan view of the semiconductor device 100 at the height marked by center line B-B'. Figure 6 Shown Figure 3C and Figure 5E the same local views. It is worth noting that the air gap 150b disposed between the contact plug 136a and the gate stack 116b is close to and aligned with the contact plug 136a. In fact, the air gap 150b directly exposes the sidewall of the contact plug 136a to the air within the air gap 150b. When the contact plug 136a conducts current, this air exposure helps with heat dissipation because air has a higher thermal conductivity than other materials next to the contact plug 136a. Note that the air within the air gap 150b can be atmospheric air or other suitable gas (e.g., an inert gas) filled into the air gap 150b to facilitate heat conduction. On the other hand, the air gap 150b is relatively far from the gate stack 116b because the air gap 150b is separated from the gate stack 116b by the interlayer dielectric (ILD) layer 110 (and by the spacer 112 when the spacer 112 is not considered part of the gate stack 116b).

[0074] In methods 10 and 40, each component can be formed with suitable dimensions (e.g., thickness, height, depth, or width). For example, in one embodiment, as Figure 6 shown, the width of the contact plug 136a is between 20 and 50 nanometers; the width of the barrier layer 139 on either side of the contact plug 136a is between 1 and 2 nanometers; the width of each of the air gaps 150a and 150b is between 1 and 5 nanometers.

[0075] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. Specifically, changing the time of air gap formation results in changes in the structure and position of various elements. For example, the air gap formation technique disclosed herein enables an air gap to extend above the top surface of an adjacent gate stack. Thus, the parasitic capacitance between the gate stack and the contact plug can be effectively reduced. In addition, the air gap is aligned with the contact plug rather than with the gate stack. The air gap directly exposes the sidewalls of the contact plug to air, which helps with heat dissipation when the contact plug conducts current. Embodiments of the disclosed method can be easily integrated into existing manufacturing processes and technologies, such as middle end of line (MEoL) and back end of line (BEoL) processes.

[0076] In an exemplary aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming first and second silicon nitride components on a sidewall surface of a contact hole, wherein the contact hole is disposed in a dielectric layer and above a source / drain (S / D) component. The method further includes forming a contact plug in the contact hole, the contact plug being electrically coupled to the source / drain (S / D) component; removing a top portion of the contact plug to create a recess in the contact hole; forming a hard mask layer in the recess; and removing the first and second silicon nitride components by selective etching to respectively form first and second air gaps. In an embodiment, the first air gap is formed between the contact plug and the dielectric layer to reduce a first capacitance between the contact plug and a first adjacent gate stack. The second air gap is formed between the contact plug and the dielectric layer to reduce a second capacitance between the contact plug and a second adjacent gate stack. In an embodiment, the formation of the first and second air gaps exposes the contact plug directly to the first and second air gaps. In an embodiment, the dielectric layer is a first interlayer dielectric (ILD) layer, and the method further includes forming a second interlayer dielectric layer on the contact plug, wherein the second interlayer dielectric layer covers the first and second air gaps. In an embodiment, the second interlayer dielectric layer interfaces the first and second air gaps at a height above a top surface of the first and second adjacent gate stacks. In an embodiment, the first and second air gaps are separated from the first and second adjacent gate stacks by at least the first interlayer dielectric layer, wherein the first interlayer dielectric layer includes a low-k material. In an embodiment, forming the hard mask layer in the recess includes: depositing the hard mask layer, and removing a top portion of the hard mask layer using a chemical mechanical planarization (CMP) process. The chemical mechanical planarization process (CMP) exposes top surfaces of the first and second silicon nitride components to facilitate removal of the first and second silicon nitride components. In an embodiment, after the chemical mechanical planarization (CMP) process, a remaining thickness of the hard mask layer in the recess is 2 to 5 nanometers, and the recess is located at least 3 nanometers above an adjacent gate stack of the contact plug. In an embodiment, the contact plug includes a barrier layer and a metal fill layer. Here, forming the contact plug includes: forming the barrier layer between the first and second silicon nitride components; depositing the metal fill layer to cover the barrier layer and the dielectric layer; and removing a top portion of the metal fill layer using a chemical mechanical planarization (CMP) process. In an embodiment, the first and second silicon nitride components have an etching selectivity such that the first and second silicon nitride components can be removed at a rate that is at least 10 times faster than other materials in contact with the first and second silicon nitride components.

[0077] In another aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including providing a semiconductor device structure, the semiconductor device structure including: a substrate; first and second gate stacks located on the substrate; first and second silicon nitride components located between the first and second gate stacks; and a contact plug located between the first and second silicon nitride components and in contact with the first and second silicon nitride components. The method further includes etching the first and second silicon nitride components to respectively form first and second air gaps, wherein the first and second air gaps expose the sidewalls of the contact plug to air within the first and second air gaps. The method further includes forming a sealing layer over the contact plug to cover the first and second air gaps. In one embodiment, the sealing layer interfaces the first and second air gaps at a height above the top surface of the first and second gate stacks. In one embodiment, the sealing layer is formed using a physical vapor deposition (PVD) process such that the sealing layer interfaces the first and second air gaps at a height not exceeding 5 nanometers below the top surface of the contact plug. In one embodiment, the widths of the first and second air gaps are both between 1 and 5 nanometers. The first and second air gaps are separated from the first and second gate stacks by at least one interlayer dielectric (ILD) layer, wherein the interlayer dielectric layer (ILD) includes a low-k material.

[0078] In yet another aspect, an embodiment of the present invention provides a semiconductor device, including: a substrate; a source / drain (S / D) component disposed on the substrate; a metal plug disposed on the source / drain (S / D) component; a gate stack disposed adjacent to the metal plug; an air gap disposed between the metal plug and the gate stack; and a capping layer covering the air gap. The air gap at least partially exposes a sidewall of the metal plug to air within the air gap. In one embodiment, an interface between the capping layer and the air gap is higher than the top surface of the gate stack. In one embodiment, the metal plug includes a barrier layer having a tapered thickness profile. In one embodiment, the metal plug further includes a metal fill layer disposed above and adjacent to the barrier layer, wherein the barrier layer includes titanium nitride (TiN), and wherein the metal fill layer includes tungsten (W) or cobalt (Co). In one embodiment, the semiconductor device further includes an interlayer dielectric (ILD) layer in direct contact with the air gap, wherein the interlayer dielectric layer includes silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), or a combination of the foregoing. In one embodiment, the semiconductor device further includes a hard mask layer disposed between the metal plug and the capping layer and below the capping layer, wherein a bottom surface of the hard mask layer is higher than the top surface of the gate stack.

[0079] The foregoing text outlines the components of many embodiments so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, comprising: Forming a first silicon nitride component and a second silicon nitride component on a sidewall surface of a contact hole, the contact hole being disposed in a dielectric layer and above a source / drain component; Forming a contact plug in the contact hole, the contact plug being electrically coupled to the source / drain component; Removing a top portion of the contact plug to create a recess in the contact hole; Forming a hard mask layer in the recess; And Removing the first silicon nitride component and the second silicon nitride component by selective etching to respectively form a first air gap and a second air gap.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the first air gap is formed between the contact plug and the dielectric layer to reduce a first capacitance between the contact plug and a first adjacent gate stack, and the second air gap is formed between the contact plug and the dielectric layer to reduce a second capacitance between the contact plug and a second adjacent gate stack.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the first air gap and the second air gap are formed such that the contact plug is directly exposed to the first air gap and the second air gap.

4. The method of manufacturing a semiconductor device according to claim 2, wherein the dielectric layer is a first interlayer dielectric layer, and the method of manufacturing the semiconductor device further comprises forming a second interlayer dielectric layer on the contact plug, wherein the second interlayer dielectric layer covers the first air gap and the second air gap.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the second interlayer dielectric layer joins the first air gap and the second air gap at a height above a top surface of the first adjacent gate stack and the second adjacent gate stack.

6. The method of manufacturing a semiconductor device according to claim 5, wherein the first air gap and the second air gap are at least separated from the first adjacent gate stack and the second adjacent gate stack by the first interlayer dielectric layer, wherein the first interlayer dielectric layer comprises a low dielectric constant material.

7. The method of manufacturing a semiconductor device according to claim 1, wherein forming the hard mask layer in the recess comprises: Depositing the hard mask layer; And Removing a top portion of the hard mask layer using a chemical mechanical planarization process, wherein the chemical mechanical planarization process exposes top surfaces of the first silicon nitride component and the second silicon nitride component to facilitate removal of the first silicon nitride component and the second silicon nitride component.

8. The method of manufacturing a semiconductor device according to claim 7, wherein after the chemical mechanical planarization process, a remaining thickness of the hard mask layer in the recess is 2 to 5 nanometers, and the recess is located at least 3 nanometers above an adjacent gate stack of the contact plug.

9. The method of manufacturing a semiconductor device according to claim 1, wherein the contact plug comprises a barrier layer and a metal filling layer, wherein forming the contact plug comprises: Forming the barrier layer between the first silicon nitride component and the second silicon nitride component; Depositing the metal filling layer to cover the barrier layer and the dielectric layer; And Removing a top portion of the metal filling layer using a chemical mechanical planarization process.

10. The manufacturing method of a semiconductor device as claimed in claim 1, wherein the first silicon nitride component and the second silicon nitride component have an etching selectivity such that the first silicon nitride component and the second silicon nitride component can be removed at a rate that is at least 10 times faster than other materials in contact with the first silicon nitride component and the second silicon nitride component.

11. A manufacturing method of a semiconductor device, comprising: providing a semiconductor device structure, the semiconductor device structure comprising: a substrate; a first gate stack and a second gate stack, located on the substrate; a first silicon nitride component and a second silicon nitride component, located on a sidewall surface of a contact hole, the contact hole being provided in a dielectric layer between the first gate stack and the second gate stack and surrounded by the dielectric layer; a barrier layer, formed of a material different from silicon nitride, and the barrier layer being located on a lower portion of the first silicon nitride component and the second silicon nitride component; and a metal fill layer, including a top and a bottom, wherein the top directly contacts the first silicon nitride component and the second silicon nitride component, and the bottom directly contacts the barrier layer; etching the first silicon nitride component and the second silicon nitride component without substantially etching the barrier layer to respectively form a first air gap and a second air gap, wherein the first air gap and the second air gap expose sidewalls of the metal fill layer to air within the first air gap and the second air gap; and forming a sealing layer over the metal fill layer to cover the first air gap and the second air gap.

12. The manufacturing method of a semiconductor device as claimed in claim 11, wherein the sealing layer joins the first air gap and the second air gap at a height above a top surface of the first gate stack and the second gate stack.

13. The manufacturing method of a semiconductor device as claimed in claim 12, wherein the sealing layer is formed by a physical vapor deposition process such that the sealing layer joins the first air gap and the second air gap at a height not exceeding 5 nanometers below a top surface of the metal fill layer.

14. The manufacturing method of a semiconductor device as claimed in claim 11, wherein widths of the first air gap and the second air gap are both between 1 and 5 nanometers, wherein the first air gap and the second air gap are separated from the first gate stack and the second gate stack by at least one interlayer dielectric layer, and the interlayer dielectric layer includes a low dielectric constant material.

15. The manufacturing method of a semiconductor device as claimed in claim 11, wherein the metal fill layer is separated from the first gate stack by the first air gap.

16. A manufacturing method of a semiconductor device, comprising: forming a first silicon nitride component and a second silicon nitride component on a sidewall surface of a contact hole, the contact hole being provided in a dielectric layer and above a source / drain component; forming a contact plug in the contact hole, the contact plug being electrically coupled to the source / drain component, the contact plug comprising: a barrier layer; and A metal filling layer is located above the barrier layer such that a top of the metal filling layer directly contacts the first silicon nitride component and the second silicon nitride component, and a bottom of the metal filling layer is separated from the first silicon nitride component and the second silicon nitride component by the barrier layer; and The first silicon nitride component and the second silicon nitride component are removed by selective etching to respectively form a first air gap and a second air gap.

17. The method of manufacturing a semiconductor device according to claim 16, wherein forming the contact plug includes: Depositing the barrier layer above the contact hole; Etching the barrier layer to expose a top of a sidewall of the first silicon nitride component and the second silicon nitride component; And After etching the barrier layer, depositing the metal filling layer above the contact hole.

18. The method of manufacturing a semiconductor device according to claim 17, further comprising: Cleaning the etched barrier layer to form a tapered thickness profile of the barrier layer, Wherein the tapered thickness profile includes a first thickness of an upper portion of the barrier layer and a second thickness of a bottom portion of the barrier layer, Wherein the second thickness is greater than the first thickness.

19. The method of manufacturing a semiconductor device according to claim 17, wherein forming the barrier layer includes: Depositing a metal layer in contact with the source / drain component, the first silicon nitride component, and the second silicon nitride component; And Annealing the metal layer to form a metal silicide in contact with the source / drain component, and the barrier layer in contact with the first silicon nitride component and the second silicon nitride component.

20. The method of manufacturing a semiconductor device according to claim 19, wherein the metal layer includes titanium or tantalum, and the barrier layer includes titanium nitride or tantalum nitride.

21. A semiconductor device, comprising: A substrate; A source / drain component disposed on the substrate; A metal plug disposed above the source / drain component, the metal plug including a metal filling layer and a barrier layer disposed along a bottom surface and a sidewall of the metal filling layer; A gate stack disposed in an interlayer dielectric layer and adjacent to the metal plug; A gap disposed between the metal plug and the interlayer dielectric layer, wherein the gap at least partially exposes a sidewall of the metal plug; And A capping layer covering the gap, wherein a portion of the capping layer extends below a top surface of the interlayer dielectric layer.

22. The semiconductor device according to claim 21, wherein an interface between the capping layer and the gap is higher than a top surface of the gate stack.

23. The semiconductor device according to claim 21, wherein the barrier layer includes a tapered thickness profile.

24. The semiconductor device according to claim 23, Wherein the barrier layer includes titanium nitride, and the metal filling layer includes tungsten or cobalt.

25. The semiconductor device according to claim 21, wherein the interlayer dielectric layer is exposed in the gap, and the interlayer dielectric layer includes silicon oxide, silicon carbonitride, silicon oxycarbide, or a combination of the foregoing.

26. The semiconductor device according to claim 25, wherein the composition of the interlayer dielectric layer is the same as that of the capping layer.

27. The semiconductor device as described in claim 21 further includes a hard mask layer disposed between the metal plug and the capping layer and below the capping layer, wherein a bottom surface of the hard mask layer is higher than a top surface of the gate stack.

28. The semiconductor device as described in claim 27, wherein the hard mask layer includes silicon carbonitride, hafnium oxide, aluminum oxide, or zirconium oxide.

29. The semiconductor device as described in claim 27, wherein the capping layer is in direct contact with a sidewall of the hard mask layer.

30. A semiconductor device includes: a substrate; a contact plug disposed on the substrate, the contact plug including a metal filling layer and a barrier layer disposed along a bottom surface and a sidewall of the metal filling layer; a gate stack disposed in an interlayer dielectric layer and adjacent to the contact plug; a gap disposed between the interlayer dielectric layer and the contact plug; and a sealing layer covering the gap, wherein a part of the sealing layer extends to be lower than a top surface of the interlayer dielectric layer.

31. The semiconductor device as described in claim 30, wherein the interlayer dielectric layer is separated from the contact plug by the gap and a part of the sealing layer.

32. The semiconductor device as described in claim 30, wherein an interface between the sealing layer and the gap is higher than a top surface of the gate stack.

33. The semiconductor device as described in claim 30, wherein the metal filling layer includes cobalt, tungsten, platinum, silver, nickel, copper, palladium; and the barrier layer includes tantalum nitride, titanium nitride, tantalum silicide, or titanium silicide.

34. The semiconductor device as described in claim 30 further includes a hard mask layer disposed between the contact plug and the sealing layer, wherein a bottom surface of the hard mask layer is higher than a top surface of the gate stack.

35. The semiconductor device as described in claim 34, wherein the hard mask layer includes silicon carbonitride, hafnium oxide, aluminum oxide, or zirconium oxide.

36. The semiconductor device as described in claim 34, wherein a part of the sealing layer is disposed between the interlayer dielectric layer and the hard mask layer.

37. A semiconductor device includes: a substrate; a source / drain component disposed on the substrate; a metal plug disposed on the source / drain component, wherein the metal plug includes a metal filling layer and a barrier layer disposed along a bottom surface and a sidewall of the metal filling layer; a gate stack disposed in an interlayer dielectric layer and adjacent to the metal plug; a gap disposed between the barrier layer and the interlayer dielectric layer, wherein the gap at least partially exposes a sidewall of the metal plug within the gap; a capping layer covering the gap, wherein a part of the capping layer extends to be lower than a top surface of the interlayer dielectric layer; and a hard mask layer disposed between the metal plug and the capping layer.

38. The semiconductor device as described in claim 37, wherein the hard mask layer includes silicon carbonitride, hafnium oxide, aluminum oxide, or zirconium oxide.

39. The semiconductor device as described in claim 37, wherein the barrier layer includes a tapered thickness profile.

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