Semiconductor device having a stress active region and method of forming the same

Abstract

A method of manufacturing a semiconductor device includes: providing a substrate comprising a semiconductor material having a first lattice constant; then patterning the substrate to form a first semiconductor pattern extending along a first direction. A second semiconductor pattern is also formed on the first semiconductor pattern. The second semiconductor pattern extends along the first direction and has a second lattice constant greater than the first lattice constant. The second semiconductor pattern is further patterned to define sidewalls of the second semiconductor pattern extending along a second direction intersecting the first direction. A gate extending along the first direction is formed on the second semiconductor pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0071254, filed with the Korean Patent Office on June 21, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor devices and methods of forming the same, and more specifically, to semiconductor devices having stress channel regions therein and methods of forming the same. Background Technology

[0004] As the feature size of MOS transistors decreases, the gate length and the length of the channel formed beneath the gate can also be reduced. Furthermore, as the channel length of the transistor decreases, charge scattering in the channel typically increases and charge mobility typically decreases. This decrease in charge mobility may be an obstacle to further improving the saturation current of the transistor.

[0005] Therefore, various research efforts are underway to improve charge mobility in transistors with reduced channel lengths. Summary of the Invention

[0006] The present invention provides a method for manufacturing a semiconductor device that can produce a semiconductor device with improved operating performance and reduced size.

[0007] Various aspects of the present invention provide a semiconductor device with improved operational performance and reduced size.

[0008] The inventive concept is not limited to those mentioned above, and those skilled in the art will clearly understand from the following description all other aspects not mentioned.

[0009] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate comprising a semiconductor material having a first lattice constant; patterning the substrate to form a first semiconductor pattern extending along a first direction; forming a second semiconductor pattern on the first semiconductor pattern, the second semiconductor pattern extending along the first direction and having a second lattice constant greater than the first lattice constant; patterning the second semiconductor pattern to form sidewalls of the second semiconductor pattern extending along a second direction, the second direction intersecting the first direction; and forming a gate extending along the first direction on the second semiconductor pattern.

[0010] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate in which a first semiconductor film, a buried insulating film, and a second semiconductor film are sequentially stacked; forming a first trench extending in a first direction in the second semiconductor film; performing an epitaxial growth process using the second semiconductor film as a seed to form a semiconductor pattern extending in the first direction; forming a second trench defining sidewalls of the semiconductor pattern extending in a second direction, the second direction intersecting the first direction; and forming an element isolation film filling the first trench and the second trench.

[0011] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising providing a substrate comprising a semiconductor material having a first lattice constant; forming a semiconductor pattern on the substrate, the semiconductor pattern comprising a first sidewall and a second sidewall intersecting the first sidewall, and the semiconductor pattern having a second lattice constant greater than the first lattice constant; forming an element isolation film on the substrate surrounding the first sidewall and the second sidewall; and forming a gate intersecting the second sidewall of the semiconductor pattern and the element isolation film, wherein a first angle formed between the lower surface of the semiconductor pattern and the first sidewall is greater than a second angle formed between the lower surface of the semiconductor pattern and the second sidewall.

[0012] According to various aspects of the present invention, a semiconductor device is provided, comprising: a substrate including a semiconductor material having a first lattice constant; a semiconductor pattern located on the substrate, the semiconductor pattern including a first sidewall and a second sidewall intersecting the first sidewall, and the semiconductor pattern having a second lattice constant greater than the first lattice constant; an element isolation film surrounding the first sidewall and the second sidewall on the substrate; and a gate intersecting the second sidewall of the semiconductor pattern and the element isolation film; wherein a first angle formed between a lower surface of the semiconductor pattern and the first sidewall is greater than a second angle formed between the lower surface of the semiconductor pattern and the second sidewall. Attached Figure Description

[0013] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0014] Figures 1 to 16 These are diagrams illustrating intermediate steps of a semiconductor device and a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0015] Figures 17 to 24 These are diagrams illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0016] Figures 25 to 37These are diagrams illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0017] Figures 38 to 44 These are diagrams illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0018] In the following text, reference will be made to Figures 1 to 44 Semiconductor devices and methods for manufacturing semiconductor devices according to some embodiments of the present invention are described.

[0019] Figures 1 to 16 These are illustrations illustrating intermediate steps in a semiconductor device and a method of manufacturing a semiconductor device according to some embodiments of the present invention. For reference. Figure 2 It is along Figure 1 A cross-sectional view taken from the A-A' line. Figures 4 to 6 It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 7 yes Figure 6 A magnified view of R1. Figure 9 It is along Figure 8 A cross-sectional view taken from the B-B' line. Figure 10 yes Figure 9 A magnified view of R2. Figure 12 It is along Figure 11 A cross-sectional view taken from line A-A'. Figure 13 It is along Figure 11 A cross-sectional view taken from the B-B' line. Figure 15 and Figure 16 It is along Figure 14 A cross-sectional view taken from line A-A'.

[0020] Now refer to Figure 1 and Figure 2 A substrate 100 is provided, which may include, but is not limited to, a base substrate and an epitaxial layer grown on the base substrate. The substrate 100 may also consist only of the base substrate without the epitaxial layer. The substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate, etc., and may even be an SOI (semiconductor-on-insulator) substrate. In the following description, for illustrative purposes, the substrate 100 will be described as comprising silicon (Si). Furthermore, the substrate 100 will be considered as a semiconductor material having a first lattice constant.

[0021] Reference Figure 3 and Figure 4A first semiconductor pattern 100P extending along a first direction Y is formed in a substrate 100. As shown, a first trench T1 extending along the first direction Y can be formed in the substrate 100 to define the first semiconductor pattern 100P. For example, the formation of the first trench T1 can be performed by photolithography. For example, a first mask M1 extending along the first direction Y can be formed on the substrate 100. Subsequently, the first mask M1 can be used as an etching mask to pattern the substrate 100. Thus, a first semiconductor pattern 100P including a first sidewall 100Pa extending along the first direction Y can be formed. After the first semiconductor pattern 100P is formed, the first mask M1 can be removed. As shown, the first trench T1 may have a tapered shape, but this is only a feature in the process of forming the first trench T1, and the present disclosure is not limited thereto.

[0022] The first trench T1 can be formed to a predetermined depth. For example, the first trench T1 can be formed to a first depth D1 based on the upper surface of the substrate 100 (or the upper surface of the first semiconductor pattern 100P).

[0023] Reference Figure 5 A first insulating pattern 112 is formed in the first trench T1. For example, an insulating film filling the first trench T1 can be formed on the first semiconductor pattern 100P. Subsequently, a planarization process can be performed until the upper surface of the first semiconductor pattern 100P is exposed. For example, the formation of the first insulating pattern 112 can be performed by a shallow trench isolation (STI) process, but this disclosure is not limited thereto. As a result, a first insulating pattern 112 can be formed around the first sidewall 100Pa of the first semiconductor pattern 100P. Furthermore, the first insulating pattern 112 can expose the upper surface of the first semiconductor pattern 100P. The first insulating pattern 112 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0024] Reference Figure 6 and Figure 7 A second semiconductor pattern 120 is formed on the first semiconductor pattern 100P. The second semiconductor pattern 120 can be formed to extend along the first direction Y on the first semiconductor pattern 100P. Therefore, as Figure 7 As shown, a second semiconductor pattern 120 can be formed, including a second sidewall 120a extending along the first direction Y.

[0025] The second semiconductor pattern 120 may have a second lattice constant that is different from the first lattice constant associated with the first semiconductor pattern 100P. Therefore, compressive or tensile stress can be applied to the second semiconductor pattern 120. In some embodiments, the second semiconductor pattern 120 may have a second lattice constant greater than the first lattice constant. For example, the first semiconductor pattern 100P may include silicon (Si), and the second semiconductor pattern 120 may include silicon germanium (SiGe). As a result, the first semiconductor pattern 100P can apply compressive stress to the second semiconductor pattern 120. The compressive stress may include a first compressive stress applied to the second semiconductor pattern 120 along a first direction Y and a second compressive stress applied to the second semiconductor pattern 120 along a second direction X.

[0026] In some embodiments, the formation of the second semiconductor pattern 120 may include crystal growth of the second semiconductor pattern 120 on the first semiconductor pattern 100P. For example, an epitaxial growth process using the upper surface of the first semiconductor pattern 100P as a seed may be performed. Since the upper surface of the first semiconductor pattern 100P is exposed by the first insulating pattern 112, the second semiconductor pattern 120 may be formed on the upper surface of the first semiconductor pattern 100P.

[0027] In some embodiments, the second sidewall 120a of the second semiconductor pattern 120 may include a facet. For example, as... Figure 7 As shown, the second sidewall 120a of the second semiconductor pattern 120 may include a lower sidewall 120a1 that contacts the upper surface of the first semiconductor pattern 100P and an upper sidewall 120a1 on the lower sidewall 120a1.

[0028] In some embodiments, the first angle θ1 formed between the lower surface and the lower sidewall 120a1 of the second semiconductor pattern 120 can be greater than the second angle θ2 formed between the lower surface and the upper sidewall 120a1 of the second semiconductor pattern 120. For example, as shown in the figure, the first angle θ1 can be an obtuse angle, and the second angle θ2 can be an acute angle. Here, the first angle θ1 and the second angle θ2 refer to the angles formed in the second semiconductor pattern 120.

[0029] Reference Figures 8 to 10A third sidewall 120b extending along a second direction X intersecting the first direction Y is formed in the second semiconductor pattern 120. For example, a second trench T2 extending along the second direction X can be formed in the second semiconductor pattern 120. The formation of the second trench T2 can be performed, for example, by an etching process defined by photolithography. For example, a second mask M2 extending along the second direction X can be formed on the second semiconductor pattern 120. Subsequently, the second mask M2 can be used as an etching mask to pattern the second semiconductor pattern 120. Thus, a second semiconductor pattern 120 including the third sidewall 120b extending along the second direction X can be formed. After the third sidewall 120b of the second semiconductor pattern 120 is formed, the second mask M2 can be removed.

[0030] The second direction X is shown as orthogonal to the first direction Y, but this disclosure is not limited thereto. For example, the second direction X can be another direction that is not parallel to the first direction Y. The second groove T2 is shown as having a tapered shape, but this is merely a feature in the process of forming the second groove T2, and this disclosure is not limited thereto.

[0031] like Figure 10 As shown, the third sidewall 120b of the second semiconductor pattern 120 can form a third angle θ3 with the lower surface of the second semiconductor pattern 120. Here, the third angle θ3 refers to the angle formed in the second semiconductor pattern 120. In some embodiments, the third angle θ3 formed between the lower surface of the second semiconductor pattern 120 and the third sidewall 120b can be the same as the first angle θ1 formed between the lower surface of the second semiconductor pattern 120 and the lower sidewall 120a1. Figure 7 The angles θ1 and θ3 are different. For example, the first angle θ1 can be an obtuse angle, while the third angle θ3 can be an acute angle (or a right angle).

[0032] In some embodiments, since the second trench T2 is formed in the second semiconductor pattern 120, the first compressive stress applied to the second semiconductor pattern 120 along the first direction Y can be relieved. However, since the second trench T2 is formed to extend along the second direction X, the second compressive stress applied to the second semiconductor pattern 120 along the second direction X can be maintained. In some embodiments, the first compressive stress applied to the second semiconductor pattern 120 along the first direction Y may be less than the second compressive stress applied to the second semiconductor pattern 120 along the second direction X.

[0033] In some embodiments, the formation of the second trench T2 may further include patterning the first semiconductor pattern 100P. For example, the lower surface of the second trench T2 may be formed below the lower surface of the second semiconductor pattern 120. Therefore, the first semiconductor pattern 100P, including a fourth sidewall 100Pb extending along the second direction X, may be formed. Furthermore, the sidewalls of the second trench T2 may be defined by the third sidewall 120b of the second semiconductor pattern 120 and the fourth sidewall 100Pb of the first semiconductor pattern 100P. Moreover, in some embodiments, the formation of the second trench T2 may further include patterning the first insulating pattern 112.

[0034] The second trench T2 can be formed at a predetermined depth. For example, the second trench T2 can be formed at a second depth D2 based on the upper surface of the substrate 100 (or the upper surface of the first semiconductor pattern 100P). The second depth D2 is shown as being the same as the first depth ( Figure 4 The second depth D2 may be the same as the first depth D1, but this disclosure is not limited thereto. For example, the second depth D2 may be deeper than the first depth D1.

[0035] Reference Figures 11 to 13 A second insulating pattern 114 is formed in the second trench T2. For example, an insulating film for filling the second trench T2 can be formed on the first semiconductor pattern 100P and the second semiconductor pattern 120. Subsequently, a planarization process can be performed until the upper surface of the second semiconductor pattern 120 is exposed. The formation of the second insulating pattern 114 can be performed, for example, by an STI process, but this disclosure is not limited thereto.

[0036] As a result, Figure 12 As shown, a second insulating pattern 114 can be formed around the second sidewall 120a of the second semiconductor pattern 120. Furthermore, as... Figure 13 As shown, a second insulating pattern 114 can be formed around the fourth sidewall 100Pb of the first semiconductor pattern 100P and the third sidewall 120b of the second semiconductor pattern 120. Furthermore, the second insulating pattern 114 can expose the upper surface of the second semiconductor pattern 120.

[0037] The first insulating pattern 112 and the second insulating pattern 114 can form a device isolation film 110. That is, the device isolation film 110 can be formed on the substrate to surround the first sidewall 100Pa of the first semiconductor pattern 100P, the second sidewall 120a of the second semiconductor pattern 120, the fourth sidewall 100Pb of the first semiconductor pattern 100P, and the third sidewall 120b of the second semiconductor pattern 120.

[0038] The second insulating pattern 114 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The second insulating pattern 114 may include, but is not limited to, a material substantially the same as the first insulating pattern 112. For example, the second insulating pattern 114 may include an insulating material different from the first insulating pattern 112.

[0039] Reference Figure 14 and Figure 15 A gate dielectric film 132, a gate 134, a gate spacer 136, and a source / drain region 122 are formed on / in the second semiconductor pattern 120. Figure 14 For ease of explanation, only gate 134 is shown in this illustration. In the following description, gate 134 is described as being formed by a first gate processing, but this disclosure is not limited thereto. For example, gate 134 can be formed by a post-gate processing or a replacement processing. For example, a dielectric film and a conductive film can be sequentially formed on the second semiconductor pattern 120 and the element isolation film 110. Next, the dielectric film and the conductive film can be patterned. As a result, gate dielectric film 132 and gate 134 can be formed on the second semiconductor pattern 120. In some embodiments, gate dielectric film 132 and gate 134 can be formed to extend along a first direction Y, such as... Figure 14 As shown.

[0040] The gate dielectric film 132 may include an electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material with a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, but is not limited to, at least one of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0041] Gate 134 may be, but is not limited to, materials such as polysilicon or metal. Gate 134 is shown as a single film, but this disclosure is not limited thereto. For example, gate 134 may be formed by stacking multiple conductive materials. For example, gate 134 may include a work function adjustment film for adjusting the work function, and a filling conductive film for filling the space formed by the work function adjustment film. The work function adjustment film may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al. Gate 134 may be formed by, for example, a replacement process, but this disclosure is not limited thereto.

[0042] Gate spacers 136 can be formed on the sidewalls of gate 134. For example, spacer films can be formed on gate dielectric film 132 and gate 134. Next, the spacer film can be patterned to form gate spacers 136 on the sidewalls of gate 134. Since gate 134 can extend along a first direction Y, gate spacer 136 can also extend along the first direction Y. Gate spacer 136 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0043] Source / drain regions 122 can be formed in a second semiconductor pattern 120 on the sidewall of gate 134. The formation of source / drain regions 122 can be performed, for example, by ion implantation. For example, gate 134 and / or gate spacer 136 can be used as a mask to dope impurities into the second semiconductor pattern 120.

[0044] However, this disclosure is not limited thereto, and the formation of the source / drain region 122 can be performed by an epitaxial growth process. For example, the source / drain region 122 can also be formed by an epitaxial growth process after a portion of the second semiconductor pattern 120 has been removed. In some embodiments, the source / drain region 122 may include p-type impurities. For example, the gate 134 and / or the gate spacer 136 can be used as a mask to dope p-type impurities into the second semiconductor pattern 120.

[0045] Reference Figure 16 An interlayer insulating film 140, a first contact 152, and a second contact 154 are formed. The interlayer insulating film 140 may be formed to cover the second semiconductor pattern 120, the element isolation film 110, the gate 134, and the gate spacer 136. The interlayer insulating film 140 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material with a dielectric constant lower than that of silicon oxide. Low dielectric constant materials may include, but are not limited to, at least one of the following: FOX (flowable oxide), TOSZ (Torene Silazene), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorinated silicate glass), CDO (carbon-doped silica), degel, aerogel, amorphous fluorinated carbon, OSG (organosilicon glass), parylene, BCB (bis-benzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0046] As shown, a vertical first contact 152 can be formed to connect to the gate 134, and a vertical second contact 154 can be formed to connect to the source / drain region 122. For example, contact holes exposing the gate 134 and the source / drain region 122 can be formed in the interlayer insulating film 140. Next, conductive material can be filled into the contact holes. Therefore, a first contact 152 that penetrates the interlayer insulating film 140 and connects to the gate 134 can be formed. Furthermore, a second contact 154 that penetrates the interlayer insulating film 140 and connects to the source / drain region 122 can be formed.

[0047] The charge mobility of each semiconductor device can be improved by controlling the stress applied to each corresponding channel. For example, in a P-type MOS transistor, the charge (hole) mobility can be improved by applying compressive stress in the length direction of the channel (e.g., the second direction X). However, in a P-type MOS transistor, compressive stress applied in the width direction of the channel (e.g., the first direction Y) leads to a decrease in charge mobility.

[0048] However, methods for manufacturing semiconductor devices according to some embodiments can provide improved charge mobility for the semiconductor device by alleviating compressive stress applied in the width direction of the channel (e.g., a first direction Y). For example, as referenced above... Figures 8 to 10 The first compressive stress applied to the second semiconductor pattern 120 in the first direction Y can be alleviated by patterning the second semiconductor pattern 120 in the second direction X. However, since the second semiconductor pattern 120 is not patterned separately in the first direction Y, the second compressive stress applied to the second semiconductor pattern 120 in the second direction X can be maintained. Therefore, a semiconductor device with improved charge mobility and improved operating performance can be provided.

[0049] Furthermore, the second semiconductor pattern 120 can be formed to extend along the first direction Y without being patterned separately in the first direction Y. (Refer to the above) Figure 6 and Figure 7 As shown, by forming a second semiconductor pattern 120 on a first semiconductor pattern 100P extending along a first direction Y, a second semiconductor pattern 120 extending along a second direction Y can be formed. Therefore, a semiconductor device that can reduce size without sacrificing charge mobility can be provided.

[0050] Therefore, as mentioned above... Figures 1 to 16 The field-effect transistor according to an embodiment of the present invention may include a lattice-strained second semiconductor pattern 120 defining a semiconductor heterojunction (e.g., a SiGe-Si junction) having the following first semiconductor pattern 100P. The lattice-strained second semiconductor pattern 120 has: a first pair of photolithographically defined and etched sidewalls 120b extending along a first direction, such as... Figure 13 As shown; and a second pair of sidewalls 120a, which extend along a second direction and have sidewall profiles 120au, 120al, said sidewall profiles 120au, 120al are formed by Figure 6 and Figure 7 The epitaxial lateral overgrowth (ELO) during the manufacturing steps shown is used to define the process. Figure 16 Also shown is a P-channel field-effect transistor having a channel, source and drain regions 122 within a second semiconductor pattern 120 with lattice strain, and an insulated gate (132, 134 and 136) on the second semiconductor pattern 120.

[0051] Figures 17 to 24 These are diagrams illustrating intermediate steps in a method of manufacturing a semiconductor device according to some embodiments of the present invention. For reference only. Figure 17 It is used for explanation Figure 2 Diagrams illustrating the subsequent steps. Furthermore, Figure 17 and 18 It is along Figure 3 The cross-sectional view taken by line A-A' in the diagram. Figure 20 It is along Figure 19 A cross-sectional view taken from line A-A'. Figure 21 It is along Figure 19 A cross-sectional view taken from the B-B' line. Figure 23 It is along Figure 22 A cross-sectional view taken from line A-A'. Figure 24 It is along Figure 22 The cross-sectional view taken by the B-B' line. For ease of explanation, a brief description will be provided (refer to...). Figures 1 to 16 The provided description is repetitive.

[0052] Reference Figure 3 and Figure 17 A first semiconductor pattern 100P extending along a first direction Y is formed in a substrate 100. For example, a third trench T3 extending along the first direction Y can be formed in the substrate 100. Therefore, a first semiconductor pattern 100P including a first sidewall 100Pa extending along the first direction Y can be formed. The third trench T3 can be formed at a predetermined depth. For example, the third trench T3 can be formed at a third depth D3 based on the upper surface of the substrate 100 (or the upper surface of the first semiconductor pattern 100P).

[0053] Reference Figure 18 A first insulating pattern 112 is formed in the third trench T3, and a second semiconductor pattern 120 is formed on the first semiconductor pattern 100P. Since the formation of the first insulating pattern 112 and the first semiconductor pattern 100P is similar to that of the reference... Figures 5 to 7 The formation process is described, therefore a detailed description will not be provided below.

[0054] Reference Figures 19 to 21 This forms a third sidewall 120b extending along the second direction X of the second semiconductor pattern 120. For example, as... Figure 21 As shown, a fourth trench T4 extending along the second direction X can be formed in the second semiconductor pattern 120. Therefore, a second semiconductor pattern 120 including a third sidewall 120b extending along the second direction X can be formed. Furthermore, the first compressive stress applied to the second semiconductor pattern 120 in the first direction Y can be relieved.

[0055] In some embodiments, a portion of the fourth trench T4 may extend along the first direction Y. For example, as... Figure 19 and Figure 20 As shown, a portion of the fourth trench T4 extending along the first direction Y can be formed in the second semiconductor pattern 120.

[0056] For example, such as Figure 19 As shown, a third mask M3 with a rectangular shape can be formed on the second semiconductor pattern 120. Subsequently, the third mask M3 is used as an etching mask to pattern the second semiconductor pattern 120. Therefore, a fourth trench T4, partially extending along the first direction Y and partially extending along the second direction X, can be formed. After the third sidewall 120b of the second semiconductor pattern 120 is formed, the third mask M3 can be removed.

[0057] In some embodiments, the third mask M3 may be formed to cover at least a portion of the second sidewall 120a of the second semiconductor pattern 120. As a result, at least a portion of the second sidewall 120a of the second semiconductor pattern 120 may not be patterned. Moreover, the second compressive stress applied to the second semiconductor pattern 120 along the second direction X can be maintained.

[0058] In some embodiments, the fourth trench T4 may be formed to be deeper than the third trench T3. For example, the fourth trench T4 may be based on the upper surface of the substrate 100 (or the upper surface of the first semiconductor pattern 100P) to a depth greater than the third trench T3. Figure 17 A fourth depth D4 is formed, deeper than D3. Therefore, in some embodiments, the first sidewall 100Pa of the first semiconductor pattern 100P may have a stepped shape.

[0059] Reference Figures 22 to 24 A second insulating pattern 114 is formed in the fourth trench T4. For example, an insulating film for filling the fourth trench T4 can be formed on the first semiconductor pattern 100P and the second semiconductor pattern 120. Subsequently, a planarization process can be performed until the upper surface of the second semiconductor pattern 120 is exposed.

[0060] Therefore, as Figure 23 and Figure 24 As shown, a second insulating pattern 114 can be formed around the sidewalls of the first semiconductor pattern 100P and the sidewalls of the second semiconductor pattern 120. Furthermore, the second insulating pattern 114 can expose the upper surface of the second semiconductor pattern 120.

[0061] The first insulating pattern 112 and the second insulating pattern 114 can form the element isolation film 110. In other words, the element isolation film 110 can be formed on the substrate 100, surrounding the sidewalls of the first semiconductor pattern 100P and the sidewalls of the second semiconductor pattern 120.

[0062] Subsequently, execution Figures 14 to 16 Each step of the process. Therefore, it is possible to provide semiconductor devices with improved operating performance and smaller size.

[0063] Figures 25 to 37 These are diagrams illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention. For reference. Figures 26 to 29 It is along Figure 25 The cross-sectional view taken by line A-A' in the diagram. Figure 31 It is along Figure 30 A cross-sectional view taken from line A-A'. Figure 32 It is along Figure 30 A cross-sectional view taken from the B-B' line. Figure 34 It is along Figure 33 A cross-sectional view taken from line A-A'. Figure 35 It is along Figure 33 A cross-sectional view taken from the B-B' line. Figure 37 It is along Figure 36 A cross-sectional view taken along line A-A'. For ease of explanation, references will be briefly described or omitted. Figures 1 to 24 The provided description is repetitive.

[0064] Reference Figure 25 and Figure 26 A substrate 100 is provided, comprising a base film 101, a well 103, a first semiconductor film 105, a buried insulating film 107, and a second semiconductor film 109. The well 103 may be formed on the base film 101. In some embodiments, the well 103 may be doped with an impurity of a first conductivity type. For example, the well 103 may be doped with a P-type impurity.

[0065] A first semiconductor film 105 may be formed on the well 103. In some embodiments, the first semiconductor film 105 may be doped with an impurity of a second conductivity type different from the first conductivity type. For example, the first semiconductor film 105 may be doped with an N-type impurity.

[0066] A buried insulating film 107 may be formed on the first semiconductor film 105. The buried insulating film 107 may include, but is not limited to, at least one of, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. A second semiconductor film 109 may be formed on the buried insulating film 107. In some embodiments, the second semiconductor film 109 may be doped with an impurity of a second conductivity type. For example, the second semiconductor film 109 may be doped with an N-type impurity. In some embodiments, the second semiconductor film 109 may have a third lattice constant. Hereinafter, by way of example, the second semiconductor film 109 will be described as containing silicon (Si).

[0067] In some embodiments, the first semiconductor film 105 can be used as the main region of the substrate 100. Furthermore, the first semiconductor film 105 can be completely separated from the second semiconductor film 109 by burying the insulating film 107. That is, the first semiconductor film 105 and the second semiconductor film 109 do not need to be in direct contact with each other.

[0068] In some embodiments, substrate 100 may have an FD-SOI (fully depleted silicon-on-insulator) structure. For example, the channel of the transistor formed in the second semiconductor film 109 may be completely depleted. Therefore, the method of manufacturing a semiconductor device according to some embodiments can provide a semiconductor device that effectively prevents short-channel effects.

[0069] Reference Figure 27 A third semiconductor pattern 109P extending along the first direction Y is formed on the buried insulating film 107. For example, a third trench T3 extending along the first direction Y can be formed by patterning the second semiconductor film 109. Therefore, a third semiconductor pattern 109P including a fifth sidewall 109Pa extending along the first direction Y can be formed. The third trench T3 can be formed at a predetermined depth. For example, with the upper surface of the third semiconductor pattern 109P as a reference, the third trench T3 can be formed at a third depth D3. In some embodiments, the third trench T3 can be etched until the upper surface of the buried insulating film 107 is exposed. That is, the upper surface of the buried insulating film 107 can be exposed by the third trench T3.

[0070] Reference Figure 28 A first insulating pattern 112 is formed in the third trench T3. Since the formation of the first insulating pattern 112 is similar to that of the reference... Figure 5 The formation process is described, and therefore its detailed description will not be provided below. Thus, a first insulating pattern 112 can be formed around the fifth sidewall 109Pa of the third semiconductor pattern 109P.

[0071] Reference Figure 29A second semiconductor pattern 120 is formed on the third semiconductor pattern 109P. The second semiconductor pattern 120 can be formed to extend along a first direction Y on the third semiconductor pattern 109P. Therefore, a second semiconductor pattern 120 including a second sidewall 120a extending along the first direction Y can be formed. The second semiconductor pattern 120 can have a second lattice constant different from the third lattice constant. Therefore, compressive or tensile stress can be applied to the second semiconductor pattern 120.

[0072] In some embodiments, the second semiconductor pattern 120 may have a second lattice constant greater than the third lattice constant. For example, the third semiconductor pattern 109P may include silicon (Si), and the second semiconductor pattern 120 may include silicon germanium (SiGe). As a result, compressive stress can be applied to the second semiconductor pattern 120.

[0073] In some embodiments, the formation of the second semiconductor pattern 120 may include crystal growth of the second semiconductor pattern 120 on the third semiconductor pattern 109P. For example, an epitaxial growth process using the third semiconductor pattern 109P as a seed may be performed. Since the upper surface of the third semiconductor pattern 109P is exposed by the first insulating pattern 112, the second semiconductor pattern 120 may be formed on the upper surface of the third semiconductor pattern 109P.

[0074] Reference Figures 30 to 32 This forms the third sidewall 120b of the second semiconductor pattern 120 extending along the second direction X. For example, as... Figure 32 As shown, a fourth trench T4 extending along the second direction X can be formed in the second semiconductor pattern 120. Therefore, a second semiconductor pattern 120 including a third sidewall 120b extending along the second direction X can be formed. Furthermore, the first compressive stress applied to the second semiconductor pattern 120 in the first direction Y can be relieved.

[0075] In some embodiments, a portion of the fourth trench T4 may extend along the first direction Y. For example, as... Figure 30 and Figure 31 As shown, the portion of the fourth trench T4 extending along the first direction Y can be formed in the second semiconductor pattern 120. For example, the third mask M3 can be used as an etching mask to pattern the second semiconductor pattern 120.

[0076] In some embodiments, the third mask M3 may be formed to cover at least a portion of the second sidewall 120a of the second semiconductor pattern 120, such that at least a portion of the second sidewall 120a of the second semiconductor pattern 120 may not be patterned. Nevertheless, the second compressive stress applied to the second semiconductor pattern 120 along the second direction X may be maintained.

[0077] In some embodiments, the fourth trench T4 may be formed to be deeper than the third trench T3. For example, the fourth trench T4 may be based on the upper surface of the third semiconductor pattern 109P at a depth greater than the third trench T3. Figure 27 It is formed from a deeper fourth depth, D4, which is D3.

[0078] In some embodiments, the formation of the fourth trench T4 may further include patterning a portion of the well 103. For example, the lower surface of the fourth trench T4 may be formed below the lower surface of the first semiconductor film 105. Therefore, a third semiconductor pattern 109P including a sixth sidewall 109Pb extending along the second direction X may be formed. Furthermore, the sidewalls of the fourth trench T4 may be defined by the sixth sidewall 109Pb of the third semiconductor pattern 109P, the sidewalls of the buried insulating film 107, the sidewalls of the first semiconductor film 105, and the sidewalls of the well 103.

[0079] Reference Figures 33 to 35 A second insulating pattern 114 is formed in the fourth trench T4. For example, an insulating film for filling the fourth trench T4 can be formed on the third semiconductor pattern 109P and the second semiconductor pattern 120. Subsequently, a planarization process can be performed until the upper surface of the second semiconductor pattern 120 is exposed. Thus, as Figure 34 and Figure 35 As shown, a second insulating pattern 114 can be formed around the sidewalls of the third semiconductor pattern 109P and the sidewalls of the second semiconductor pattern 120. Furthermore, the second insulating pattern 114 can expose the upper surface of the second semiconductor pattern 120, such as... Figures 34 to 44 As shown. First insulating pattern 112 ( Figure 34 As shown), the second insulating pattern 114 can form an element isolation film 110. That is, an element isolation film 110 can be formed around the sidewalls of the third semiconductor pattern 109P and the sidewalls of the second semiconductor pattern 120.

[0080] Reference Figure 36 and Figure 37 A gate dielectric film 132, a gate 134, a gate spacer 136, a source / drain region 122, an interlayer insulating film 140, a first contact 152, and a second contact 154 are formed on the second semiconductor pattern 120. The formation of the gate dielectric film 132, gate 134, gate spacer 136, source / drain region 122, interlayer insulating film 140, first contact 152, and second contact 154 is described with reference to the reference description. Figures 14 to 16 The process described is similar, so a detailed description will not be provided.

[0081] Figures 38 to 44 These are diagrams illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention. For reference. Figure 38 It is used for explanation Figure 27 The following are the diagrams of each processing step. Figure 40 It is along Figure 39 A cross-sectional view taken from line A-A'. Figure 41 It is along Figure 39 A cross-sectional view taken from the B-B' line. Figure 43 It is along Figure 42 A cross-sectional view taken from line A-A'. Figure 44 It is along Figure 42 The cross-sectional view taken along line B-B'. For ease of explanation, references will be briefly described or omitted. Figures 1 to 37 A repeated description section was provided.

[0082] Reference Figure 38 A second semiconductor pattern 120 is formed on the third semiconductor pattern 109P. The second semiconductor pattern 120 can be formed to extend along a first direction Y on the third semiconductor pattern 109P. Therefore, a second semiconductor pattern 120 including a second sidewall 120a extending along the first direction Y can be formed.

[0083] In some embodiments, the formation of the second semiconductor pattern 120 may include crystal growth of the second semiconductor pattern 120 on the third semiconductor pattern 109P. For example, an epitaxial growth process using the third semiconductor pattern 109P as a seed may be performed. In some embodiments, the upper surface and sidewalls of the third semiconductor pattern 109P may be exposed. Therefore, the second semiconductor pattern 120 may be formed on the upper surface and sidewalls of the third semiconductor pattern 109P.

[0084] In some embodiments, the second sidewall 120a of the second semiconductor pattern 120 may include a facet. For example, as... Figure 38 As shown, the second sidewall 120a of the second semiconductor pattern 120 may include a lower sidewall 120a1 in contact with the upper surface of the buried insulating film 107, and an upper sidewall 120a1 on the lower sidewall 120a1.

[0085] Reference Figures 38 to 41 This forms the third sidewall 120b of the second semiconductor pattern 120 extending along the second direction X. For example, as... Figure 41 As shown, a fourth trench T4 extending along the second direction X can be formed in the second semiconductor pattern 120. Therefore, a second semiconductor pattern 120 including a third sidewall 120b extending along the second direction X can be formed. Furthermore, the first compressive stress applied to the second semiconductor pattern 120 in the first direction Y can be relieved.

[0086] In some embodiments, a portion of the fourth trench T4 may extend along the first direction Y. For example, as... Figure 39 and Figure 40As shown, a portion of the fourth trench T4 extending along the first direction Y can be formed in the second semiconductor pattern 120. For example, the third mask M3 can be used as an etching mask to pattern the second semiconductor pattern 120.

[0087] In some embodiments, the third mask M3 may be formed to cover at least a portion of the second sidewall 120a of the second semiconductor pattern 120. As a result, at least a portion 120 of the second sidewall 120a of the second semiconductor pattern may not be patterned. Moreover, the second compressive stress applied to the second semiconductor pattern 120 along the second direction X may be maintained.

[0088] Reference Figures 42 to 44 An element isolation film 110 is formed in the fourth trench T4.

[0089] For example, an insulating film for filling the fourth trench T4 can be formed on the third semiconductor pattern 109P and the second semiconductor pattern 120. Subsequently, a planarization process can be performed until the upper surface of the second semiconductor pattern 120 is exposed. As a result, as... Figure 43 and Figure 44 As shown, a device isolation film 110 can be formed around the sidewalls of the third semiconductor pattern 109P and the sidewalls of the second semiconductor pattern 120. Furthermore, the device isolation film 110 can expose the upper surface of the second semiconductor pattern 120. Subsequently, the following can be performed: Figure 36 and Figure 37 This processing allows for the provision of semiconductor devices with improved operational performance and reduced size.

[0090] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed herein are for general and descriptive purposes only and not for limiting purposes.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a substrate including a semiconductor material having a first lattice constant; patterning the substrate to form a first semiconductor pattern extending in a first direction; forming a second semiconductor pattern on the first semiconductor pattern, the second semiconductor pattern extending in the first direction and having a second lattice constant larger than the first lattice constant; patterning the second semiconductor pattern using a second mask extending in a second direction as an etching mask to form a sidewall of the second semiconductor pattern extending in the second direction, the second direction crossing the first direction; forming a gate electrode extending in the first direction on the second semiconductor pattern; and forming source / drain regions in the second semiconductor pattern on both sides of a sidewall of the gate electrode extending in the first direction, such that the gate electrode is located between the source / drain regions in the second direction, after forming the gate electrode. The first semiconductor pattern includes silicon, and the second semiconductor pattern includes silicon germanium.

2. The method of claim 1, wherein, Forming the second semiconductor pattern includes performing an epitaxial growth process using the first semiconductor pattern as a seed.

3. The method of claim 1, wherein, The substrate includes a first semiconductor film, a buried insulating film, and a second semiconductor film sequentially laminated such that the buried insulating film is on the first semiconductor film, and the second semiconductor film is on the buried insulating film.

4. The method of claim 1, wherein, Forming the first semiconductor pattern includes patterning the second semiconductor film.

5. The method of claim 4, wherein, 6. The method according to claim 1, further comprising: forming an element isolation film around the first semiconductor pattern and the second semiconductor pattern, before forming the gate electrode. Forming the first semiconductor pattern includes forming a first trench extending in the first direction in the substrate; and wherein forming a sidewall of the second semiconductor pattern includes forming a second trench extending in the second direction in the substrate.

7. The method of claim 1, wherein, The first trench is formed at a first depth; and wherein the second trench is formed at a second depth deeper than the first depth.

8. The method of claim 7, wherein, Forming the first semiconductor pattern includes patterning the substrate using a first mask extending in the first direction as an etching mask.

9. The method of claim 1, wherein, Forming the source / drain regions includes doping an impurity into the second semiconductor pattern.

10. The method of claim 1, wherein, The source / drain regions include a P-type impurity.

11. The method of claim 1, wherein, 12. A method of manufacturing a semiconductor device, comprising: providing a substrate in which a first semiconductor film, a buried insulating film, and a second semiconductor film are sequentially laminated; forming a first trench extending in a first direction in the second semiconductor film; performing an epitaxial growth process using the second semiconductor film as a seed to form a semiconductor pattern extending in the first direction; patterning the semiconductor pattern using a second mask extending in a second direction as an etching mask to form a second trench, the second trench defining a sidewall of the semiconductor pattern extending in the second direction, the second direction crossing the first direction; forming an element isolation film filling the first trench and the second trench; forming a gate electrode extending in the first direction on the semiconductor pattern; and forming source / drain regions in the semiconductor pattern on both sides of a sidewall of the gate electrode extending in the first direction, such that the gate electrode is located between the source / drain regions in the second direction, after forming the gate electrode. and forming source / drain regions in the semiconductor pattern on both sides of the sidewall of the gate extending in the first direction, so that the gate is located between the source / drain regions in the second direction, after the gate is formed.

13. The method of claim 12, wherein, The first lattice constant of the second semiconductor film and the second lattice constant of the semiconductor pattern are different from each other.

14. The method of claim 12, wherein, The forming of the first trench includes etching the first trench for a sufficient duration to expose an upper surface of the buried insulating film.

15. The method of claim 12, wherein, The second trench is formed deeper than the first trench.

16. The method of claim 12, wherein, At least a portion of the second trench extends in the first direction.

17. The method of claim 12, wherein, The performing of the epitaxial growth process occurs after the forming of the first trench and before the forming of the second trench.

18. The method of claim 12, wherein, The forming of the element isolation film includes: before the forming of the semiconductor pattern, forming a first insulating pattern filling the first trench, and forming a second insulating pattern filling the second trench.

19. A method of manufacturing a semiconductor device, comprising: providing a substrate including therein a semiconductor material having a first lattice constant; forming a semiconductor pattern having a second lattice constant on the semiconductor material, the second lattice constant being greater than the first lattice constant, the semiconductor pattern having a first sidewall and a second sidewall intersecting the first sidewall; forming an element isolation film on the substrate surrounding the first sidewall and the second sidewall; and forming a gate intersecting the second sidewall of the semiconductor pattern and the element isolation film; wherein a first angle formed between a lower surface of the semiconductor pattern and the first sidewall is greater than a second angle formed between the lower surface of the semiconductor pattern and the second sidewall.

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