Method for producing a semiconductor device

Abstract

The present invention discloses a method for producing a semiconductor device, the method comprising: partially removing a support layer (130) arranged between a first semiconductor layer (120) and a second semiconductor layer (140) using an etching process, thereby forming at least one undercut portion between the first semiconductor layer (120) and the second semiconductor layer (140); at least partially filling the at least one undercut portion with a first material (150) having a higher thermal conductivity than the support layer (130); and forming a sensor device (20) in or on the second semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to methods for producing semiconductor devices, in particular semiconductor devices including sensor devices. Background Art

[0002] Semiconductor devices such as insulated gate power transistor devices, such as power MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors), are widely used as electronic switches in various types of electronic applications. In many applications, the reliability of such semiconductor devices is a critical aspect. For example, according to international functional safety standards, semiconductor devices used in automotive applications must comply with requirements regarding the specified ASIL (Automotive Safety Integrity Level) classification.

[0003] In some applications, destructive junction temperatures may be generated inside semiconductor devices during high SOA (safe operating area) switching, ringing, or short circuit events. In addition, the packaging volume of semiconductor devices is constantly decreasing. Therefore, temperature monitoring has become essential to prevent semiconductor devices from overheating. It is often critical that the sensor provides accurate temperature measurement and has a fast response time.

[0004] It is desirable to provide a temperature sensor and a method for producing a temperature sensor having a fast reaction time while providing reliable measurement results. Summary of the invention

[0005] One example relates to a method. The method includes: partially removing a support layer disposed between a first semiconductor layer and a second semiconductor layer using an etching process, thereby forming at least one undercut portion between the first semiconductor layer and the second semiconductor layer; at least partially filling the at least one undercut portion with a first material having a higher thermal conductivity than the support layer; and forming a sensor device in or on the second semiconductor layer.

[0006] Another example relates to a semiconductor device. The semiconductor device includes a support layer arranged between a first semiconductor layer and a second semiconductor layer, wherein the support layer has a first thermal conductivity. The semiconductor device also includes at least one first region formed of a first material, wherein the at least one first region is formed between the first semiconductor layer and the second semiconductor layer and adjacent to the support layer, and wherein the first material has a second thermal conductivity higher than the first thermal conductivity. The semiconductor device also includes a sensor device formed in or on the second semiconductor layer.

[0007] Another example relates to a semiconductor device comprising a semiconductor body including a first semiconductor layer, and a transistor device including at least one gate electrode and a plurality of transistor cells, each of the transistor cells comprising a source region, a body region and a compensation region formed in the first semiconductor layer. The body region extends from a first surface of the first semiconductor layer into the first semiconductor layer and is dielectrically insulated from the at least one gate electrode by a gate dielectric. The compensation region is adjacent to the body region and extends from the body region into the first semiconductor layer. The transistor device is arranged in a first section of the semiconductor body, the first section forming an active region. The semiconductor device also includes a second semiconductor layer arranged on the active region and / or the inactive region of the semiconductor body and a sensor device formed in or on the second semiconductor layer.

[0008] The following examples will be explained with reference to the accompanying drawings. The accompanying drawings serve to illustrate certain principles and thus only show aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Equivalent circuit diagrams of transistor devices and sensor devices are shown.

[0010] Figure 2 A cross-sectional view of a semiconductor device is schematically shown.

[0011] Figure 3 A cross-sectional view of another semiconductor device is schematically shown.

[0012] Figure 4 A top view of a semiconductor body is schematically shown.

[0013] Figure 5 The diagram is schematically shown in more detail. Figure 4 Cross-sectional view of a section of a semiconductor body.

[0014] Figure 6 A cross-sectional view of a semiconductor body including a semiconductor device according to an example is schematically shown.

[0015] Figure 7 Schematically shows Figure 6 A cross-sectional view of a section of a semiconductor device.

[0016] Figure 8 A cross-sectional view of a semiconductor device according to an example is schematically shown.

[0017] Fig. 9 Schematically shows Figure 8 Top view of a section of a semiconductor device.

[0018] Fig.10 A cross-sectional view of a semiconductor device according to another example is shown.

[0019] Figure 11, including Figures 11A-11G , schematically illustrating a method for producing a semiconductor device according to an example.

[0020] Fig.12 Schematically shows Fig.10 A top view of a section of a semiconductor device.

[0021] Fig.13 A cross-sectional view of a semiconductor body including a semiconductor device according to another example is schematically shown.

[0022] Fig.14 A cross-sectional view of a semiconductor body including a semiconductor device according to another example is schematically shown.

[0023] Fig.15 Schematically shows a method according to another example Figure 8 Top view of a section of a semiconductor device.

[0024] Figure 16, including Fig.16A and Fig. 16B , schematically showing Fig.15 Cross-sectional views of different sections of a semiconductor device.

[0025] Figure 17, including Fig.17A and Fig. 17B , schematically showing the method for generating Fig.15 A method for a first section of a semiconductor device.

[0026] Figure 18, including Figures 18A-18C , schematically showing the method for generating Fig.15 A method for a second section of a semiconductor device.

[0027] Figure 19, including Fig.19A and Fig.19B , schematically illustrates a cross-sectional view of a semiconductor device including a sensor device according to an example. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings constitute part of the specification and show examples of how the invention may be used and implemented for illustrative purposes. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically indicated.

[0029] Figure 1Schematically shows an equivalent circuit diagram of a transistor device 10. The transistor device 10 includes a drain node D and a source node S together with a load path formed between the drain node D and the source node S. The transistor device 10 also includes a gate node G. The sensor device 20 is coupled to the source node S and the sensing node P of the transistor device 10. 感测 Between. Figure 1 In the example of FIG. 1 , the sensor device 20 includes a source node S and a sensing node P coupled in series between the transistor device 10. 感测 A plurality of diodes 201, 202, ... 20 n . The sensor device 20 is configured to detect the temperature of the transistor device 10. For example, the sensor device 20 can be coupled to a detection unit (not shown). If the temperature of the transistor device 10 increases during the switching operation of the transistor device 10 and crosses a certain threshold, such a detection unit can generate a signal, for example, which causes the transistor device 10 to perform a switching operation at a lower switching frequency or to become a cut-off state. In this way, the temperature of the transistor device 10 can be reduced. For example, once the temperature of the transistor device 10 falls below the threshold, the transistor device can resume its normal switching operation.

[0030] Reference now Figure 2 , schematically shows a cross-sectional view of an exemplary semiconductor device. The semiconductor device includes a first semiconductor layer 120 and a second semiconductor layer 140. The support layer 130 is arranged between the first semiconductor layer 120 and the second semiconductor layer 140. The support layer 130 may have a first thermal conductivity λ1. At least one region of the first material 150 is formed between the first semiconductor layer 120 and the second semiconductor layer 140. At least one region of the first material 150 is formed adjacent to the support layer 130 and has a second thermal conductivity λ2, which is higher than the first thermal conductivity λ1 of the support layer 130. According to one example, λ2=90*λ1. The sensor device 20 is formed in the second semiconductor layer 140. Since the thermal conductivity λ2 of the first material 150 is higher than the thermal conductivity λ1 of the support layer 130, the heat generated in the first semiconductor layer 120 is transferred from the first semiconductor layer 120 to the second semiconductor layer 140 mainly via the first material 150. That is, the second semiconductor layer 140 is heated by the first semiconductor layer 120 mainly via the first material 150. Depending on the thickness of the first material 150 (the distance between the first semiconductor layer 120 and the second semiconductor layer 140) and the thermal conductivity λ2 of the first material, the temperature of the second semiconductor layer 140 may be substantially the same as the temperature of the first semiconductor layer 120. Therefore, the temperature detected by the temperature sensor 20 in or on the second semiconductor layer 140 is indicative of the temperature in the first semiconductor layer 120. Figure 1 The example shown, Figure 2The illustrated sensor device 20 may include a diode.

[0031] although Figure 2 The sensor device 20 in the example of FIG. 1 is shown as being in the second semiconductor layer 140, but it is also possible to arrange the sensor device 20 on the second semiconductor layer 140. For example, one or more layers (e.g., metal layers) can be arranged on the second semiconductor layer 140 to form the sensor device 20, wherein the second semiconductor layer 140 is arranged between the sensor device 20 and the first material 150.

[0032] Reference now Figure 3 , schematically shows a cross-sectional view of another exemplary semiconductor device. The general structure of the semiconductor device is similar to that of the above Figure 2 That is, the support layer 130 and at least one first region of the first material 150 are arranged between the first semiconductor layer 120 and the second semiconductor layer 140. However, Figure 3 The semiconductor device shown in also includes a first insulating layer 122 arranged between the first semiconductor layer 120 and the first material 150. The semiconductor device may further include a second insulating layer 142. In one section, for example, in a first section of the lower surface (the surface facing the support layer 130) of the second semiconductor layer 140, the second semiconductor layer 140 is directly adjacent to the support layer 130 without an insulating layer arranged between the support layer 130 and the second semiconductor layer 140. Other sections of the second semiconductor layer 140 (for example, the second section of the lower surface) and the side surface and the top surface of the semiconductor layer 140 are not adjacent to the support layer 130. Such a section of the second semiconductor layer 140 that is not adjacent to the support layer 130 may be at least partially covered by the second insulating layer 142. For example, the second insulating layer 142 may be arranged on the side surface and the top surface of the second semiconductor layer 140. Alternatively or in addition, the second insulating layer 142 may be arranged between the first material 150 and the second semiconductor layer 140, for example, on the second section of the lower surface of the second semiconductor layer 140.

[0033] The first insulating layer 122 may be configured to electrically isolate the first material 150 from the first semiconductor layer 120. The second insulating layer 142 may be configured to electrically isolate the first material 150 from the second semiconductor layer 140. A method for forming a semiconductor device having the first insulating layer 122 and the second insulating layer 142 will be described below in conjunction with FIG.

[0034] Reference now Figure 4 , schematically shows a top view of a semiconductor body 100. The semiconductor body 100 may include a transistor device (not shown). Figure 4). The gate pad 310 and the source pad 320 are arranged on the top surface of the semiconductor body 100. The gate pad 310 and the source pad 320 allow for connection with the gate electrode ( Figure 4 not shown) and the source electrode ( Figure 4 In addition, the sensor pad 330 is arranged on the top surface of the semiconductor body 100. Figure 4 In the example shown, the sensor pad 330 is arranged in the central area of ​​the semiconductor body 100 and is surrounded by the source pad 320 in the horizontal directions x, z. The gate pad 310 is arranged in one corner of the semiconductor body 100. However, such an arrangement is only an example. The gate pad 310 may have any other suitable shape and may be arranged at any other suitable position on the semiconductor body 100. For example, the gate pad 310 may be arranged in the central area of ​​the semiconductor body 100 and may be surrounded by the source pad 320 in the horizontal directions x, z. In general, the gate pad 310 may be completely or only partially surrounded by the source pad 320. For example, the sensor pad 330 may no longer be arranged in the central area of ​​the semiconductor body 100, but may be arranged closer to one of the edges of the semiconductor body 100. The sensor pad 330 may be completely or only partially surrounded by the source pad 320. For example, the sensor pad 320 may have a rectangular or square shape. However, other shapes are also possible. For example, the sensor pad 330 may have a width w1 and a length l1 between 30 μm and 1 mm or between 300 μm and 400 μm in the horizontal direction x, z. The surface area of ​​the sensor pad 330 may be large enough, for example, to enable a bonding connection with a bonding wire. In the vertical direction y of the semiconductor body 100, for example, the sensor pad 330 may have a thickness d1 of 0.5 μm to 1 μm or 1 μm to 5 μm (for example, see FIG. 1 ). Figure 6 ).

[0035] For example, source pad 320 and sensor pad 330 may include a conductive material, such as a metal. For example, source pad 320 and sensor pad 330 may include at least one of Al, Cu, W, Ti, Ni, Sn, Au, Ag, Pt, Pd, and alloys of one or more of these metals. The thickness of sensor pad 330 may be in the range of, for example, 0.5 μm to 1 μm or 1 μm to 5 μm (for example, refer to Figure 6 ).

[0036] Contact Figure 2 and Figure 3 The described semiconductor device may be included in the semiconductor body 100 or may be formed on a surface of the semiconductor body 100 . Figure 5The diagram is schematically shown in more detail. Figure 4 A region A of the semiconductor body 100 is shown. Figure 5 The region A shown includes a portion of the source pad 320 and the sensor pad 330. The semiconductor device may be electrically connected to the source pad 320 and the sensor pad 330. In addition, for example, the semiconductor device may be configured to be partially below the source pad 320 and partially below the sensor pad 330, which will be described below. Figures 6 to 9 Describe this.

[0037] Reference now Figure 6 , schematically showing the Figure 5 1 is a cross-sectional view of the semiconductor body 100 in the cross-sectional plane BB shown in FIG. A transistor device is formed in the semiconductor body 100. The semiconductor body 100 may include conventional semiconductor materials, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs). Figure 6 1 shows a section of a semiconductor device, which forms an active region within a semiconductor body 100. The semiconductor device comprises in its active region at least one operating transistor cell having a gate electrode 33, which is dielectrically insulated from a body region 32 by a gate dielectric 34. The body region 32 is a doped semiconductor region in the active region of the semiconductor body 100. Figure 6 In the example shown, the gate electrode 33 is arranged over the first surface 101 of the semiconductor body 100 .

[0038] Figure 6The transistor device shown further comprises a drift region 35. The drift region 35 adjoins the body region 32 of at least one transistor cell and forms a pn junction with the body region 32. The drift region 35 is arranged between the body region 32 and the drain region 36 of the at least one transistor cell. The drain region 36 may adjoin the drift region 35 (as shown). According to another example (not shown), a field stop region having the same doping type as the drift region 35 but being more highly doped than the drift region 35 is arranged between the drift region 35 and the drain region 36. Furthermore, the transistor device comprises at least one compensation region 38 having a doping type complementary to the doping type of the drift region 35. According to an example, the at least one compensation region 38 adjoins the body region 32 of the at least one transistor cell. According to an example, the transistor device comprises a plurality of transistor cells, and each transistor cell comprises a compensation region 38 adjoining the body region 32 of the respective transistor cell. In a vertical direction y of the semiconductor body 100, which is a direction perpendicular to the first surface 101, the at least one compensation region 38 extends towards the drain region 36. According to one example (not shown), the compensation region 38 is spaced apart from the drain region 36 such that there is a section or buffer zone of the drift region 35 between the compensation region 38 and the drain region 36. For example, such a buffer zone may have the same doping type as the drift region 35, but be more highly doped than the drift region 35. According to another example, the compensation region is adjacent to the drain region 36 (see Figure 6 ).

[0039] Still reference Figure 6 , the transistor device further includes a source electrode 41. The source electrode 41 is electrically connected to the source region 31 and the body region 32 of at least one transistor unit through a first contact plug 421. For example, the first contact plug 421 may include at least one of tungsten, aluminum, copper, and a Ti / TiN barrier liner. The source electrode 41 forms a source node S or is electrically connected to the source node S of the transistor device. The transistor device further includes a drain node D electrically connected to the drain region 36. The drain electrode electrically connected to the drain region 36 may form the drain node D. However, in Figure 6 Such a drain electrode is not explicitly shown in FIG.

[0040] The transistor device can be an n-type transistor device or a p-type transistor device. The device type is defined by the doping type of the source region 31. In an n-type transistor device, the source region 31 is an n-type region, the body region 32 is a p-type region, the drift region 35 having a doping type complementary to the doping type of the body region 32 is an n-type region, and at least one compensation region 38 is a p-type region. In a p-type transistor device, the source region 31 is a p-type region, the body region 32 is an n-type region, the drift region 35 is a p-type region, and at least one compensation region 38 is an n-type region. The transistor device can be implemented as a MOSFET or an IGBT. In a MOSFET, the drain region 36 has the same doping type as the drift region 35, and in an IGBT, the drain region 36 (which can also be referred to as a collector region) has a doping type complementary to the doping type of the drift region 35. For example, the doping concentration of the drain region 36 is selected from 1E18cm -3 and 1E19cm -3 Between, 1E18cm -3 and 1E20cm -3 Between or 1E18cm -3 and 1E21cm -3 The doping concentration of the drift region 35 and the compensation region 38 is selected from 1E15cm -3 and 5E16cm -3 and the doping concentration of the main region 32 is selected from 5E16cm -3 and 5E17cm -3 The transistor cell shown in the drawings is a planar transistor cell. However, implementing the transistor cell as a planar transistor cell is only an example. According to another example (not shown), the transistor cell is implemented as a trench transistor cell. That is, at least one gate electrode 33 is arranged in a trench extending from the surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0041] In the transistor device explained above, a plurality of transistor cells are connected in parallel. That is, the source regions 31 of these transistor cells are connected to the source node S, the common drain region 36 is connected to the drain node D, and at least one gate electrode 33 is connected to the gate node ( Figure 6 not shown).

[0042] Figure 6 The source electrode 41 in the example is not a continuous layer, as already mentioned above. Figure 4 and Figure 5As described. The sensor electrode 43 is arranged adjacent to the source electrode 41 in the horizontal direction x of the semiconductor body 100. The sensor electrode 43 forms a sensor node ASP or is electrically connected to the sensor node ASP. However, the source electrode 41 and the sensor electrode 43 are not directly connected to each other, but are spaced apart by means of a gap formed between the source electrode 41 and the sensor electrode 43. For example, if the source electrode 41 and the sensor electrode 43 have a considerable thickness d1 (for example, between 2 μm and 10 μm), the gap may have a width w2 between 10 μm and 20 μm. For example, if the source electrode 41 and the sensor electrode 43 have a considerable thickness d1 (for example, between 0.5 μm and 5 μm), the gap may have a width w2 between 1 μm and 10 μm. However, these are just examples. Any other width is also possible. The first contact plug 421 arranged directly below the source electrode 41 extends from the source region 31 through the third insulating layer 51 formed on the top surface 101 of the semiconductor body 100 to the source electrode 41 to electrically couple the source region 31 arranged below the source electrode 41 to the source electrode 41. In the drawings, the third insulating layer 51 is shown as a single continuous layer extending from the surface 101 of the semiconductor body 100 to the source electrode 41. However, this is only an example. A gate oxide layer having a thickness of (for example) 5nm to 200nm or 40nm to 120nm is often arranged on the surface 101 of the semiconductor body 100. The third insulating layer 51 may include the gate oxide layer and an additional layer formed on top of the gate oxide layer. For example, the additional layer may include undoped TEOS (tetraethylorthosilicate) having a thickness of about 50nm to 200nm and doped BPSG (borosilicate glass) having a thickness of about 200nm to 2μm or 1100nm to 1300nm. Thus, the third insulating layer 51 may include several sub-layers, which are however not explicitly shown in the drawings. The second contact plug 422 is arranged below the gap between the source electrode 41 and the sensor electrode 43. The second contact plug 422 may contact the transistor cell arranged below the gap between the source electrode 41 and the sensor electrode 43, but may not extend completely through the third insulating layer 51. The fourth insulating layer 45 may be arranged above the second contact plug 422 in the vertical direction y of the semiconductor body 100, so that the second contact plug 422 is not exposed and does not establish any undesired electrical connection. The same applies to the third contact plug 423, which is configured to contact the transistor cell arranged below the sensor electrode 43. The third contact plug 423 arranged below the sensor electrode 43 may only partially extend from the corresponding source region 31 through the third insulating layer 51.The third contact plug 423 disposed under the sensor electrode 43 may be electrically insulated from the sensor electrode 43 by a fourth insulating layer 45 disposed between the third contact plug 423 and the sensor electrode 43. The conductive material of the first, second, third and fourth contact plugs 421, 422, 423, 44 is made of. Figure 6 The shaded area in represents.

[0043] The semiconductor device is arranged on the top surface 101 of the semiconductor body 100. The semiconductor device may be arranged at least partially below the sensor electrode 43, such as Figure 6 shown. Figure 6 The semiconductor device shown basically corresponds to the Figure 3 The second semiconductor layer 140 is electrically connected to the sensor electrode 43 through the fourth contact plug 44. For example, the fourth contact plug 44 may include tungsten. Figure 3 In the example shown, the support layer 130 is arranged directly adjacent to the first semiconductor layer 120. Figure 6 In FIG. 1 , the first semiconductor layer 120 is formed in the semiconductor body 100 and substantially corresponds to the drift region 35. However, in Figure 6 In the example of , the implant zone 124 is formed between the support layer 130 and the first semiconductor layer 120 or the drift region 35, respectively. The implant zone 124 can extend along the entire width w3 of the semiconductor device in the horizontal direction x of the semiconductor body 100. The implant zone 124 can further extend beyond the width w3 of the semiconductor device. The implant zone 124 can have a doping type complementary to the doping type of the first semiconductor layer 120. For example, if the transistor device is an n-type transistor device, the implant zone 124 can be a p-type region. The implant zone 124 can have a doping type selected from 5E12cm -3 and 1E14cm -3 For example, implant zone 124 may include boron.

[0044] The semiconductor device may be implemented in the active region of the transistor device. However, in the region directly below the semiconductor device, no transistor unit may be implemented or only part of a transistor unit may be implemented. For example, the semiconductor device may be arranged between two operating transistor units of the transistor device, that is, the semiconductor device may extend only above one transistor unit, such as Figure 6is schematically shown (only one compensation region 38 is arranged under the semiconductor device). The distance s1 between two successive contact plugs 421, 422, 423, 44 can be between 3 μm and 10 μm, for example, 5.5 μm. Thus, the width w3 of the semiconductor device in the first horizontal direction x of the semiconductor body 100 can be less than 20 μm or less than 6 μm, for example, less than 11 μm (w3 < 2*s1). However, this is only an example. According to another example, the semiconductor device can extend over more than one transistor unit. That is, more than one compensation region 38 is arranged under the semiconductor device (not specifically shown). In this example, the following formula will hold: w3 < n*s1, where n > 2. According to another example, the semiconductor device extends in the second horizontal direction z instead of the first horizontal direction x, which will be described hereinafter in connection with Figure 7 This is described. For example, the width w3 of the semiconductor device in the first horizontal direction x or the second horizontal direction z of the semiconductor body 100 can be between 10 μm and 200 μm.

[0045] Now referring to Figure 7 , a partial cross-sectional view of the semiconductor device in the second horizontal direction z of the semiconductor body 100 in the cross-sectional plane C-C shown schematically is shown. However, in the example shown in Figure 5 , for simplicity, any part of the arrangement of the semiconductor device and the transistor device below the first surface 101 of the semiconductor body 100 is not shown. As shown in Figure 7 , the semiconductor device can include at least one pn junction. At least one pn junction can form a series connection of at least one diode 201, 202... 20 Figure 7 , which is implied by the circuit symbol representing the diode in n (see also Figure 7 ). The pn junction can be formed by successive first junction regions 143 and second junction regions 144 (which have complementary doping types). For example, the first junction region 143 can be an n-type region, and the second junction region 144 can be a p-type region. In other words, a diode chain or string can be formed in the second horizontal direction z between the fourth contact plug 44 and the fifth contact plug 424, and the diode chain or string has successive pn junctions at the region boundaries of the first junction region 143 and the second junction region 144. According to an exemplary embodiment, the doping concentrations of the first junction region 143 and the second junction region 144 are adapted to form a series connection of at least two diodes 201, 202... 20 n , and each of the successive diodes 201, 202... 20 n includes one of the first junction regions 143 and an adjacent second junction region 144.

[0046] ​​The semiconductor device may optionally further include a third region 145, which has the same doping type as the first junction region 143, but is more highly doped than the first junction region 143. For example, the third region 145 may be arranged between two consecutive pn junctions. That is, arranged between the first junction region 143 of the first pn junction and the second junction region 144 of the consecutive pn junction. The third region 145 may further form a terminal region contacted by the fourth contact plug 44 and the fifth contact plug 424. For example, the fourth contact plug 44 may contact the diodes 201, 202, ... 20 n The cathode of one of the diodes 201, 202, ... 20 n A length s2 of the semiconductor device in the second horizontal direction z between the fourth contact plug 44 and the fifth contact plug 424 may be between 10 μm and 30 μm, between 10 μm and 50 μm, or even up to 500 μm or up to 1500 μm, for example, 1000 μm.

[0047] In a device without any third region 145, the first junction region 143 of the first pn junction and the second junction region 144 of the successive pn junction form at least one additional anti-series pn junction. Such an additional anti-series pn junction is generally undesirable. Similar effects may occur in a device including a third region 145. Since the third region 145 has the same doping type as the first junction region 143, and the doping type is different from the doping type of the second junction region 144, the third region and the adjacent second junction region 144 form at least one additional anti-series pn junction that is undesirable. Still referring to Figure 7, the semiconductor device may optionally further include one or more shunt elements 70. The number of shunt elements 70 may depend on the number of additional anti-series pn junctions formed in the semiconductor device between the first region (or third region 145) of the first pn junction and the second junction region 144 of the successive pn junction. Each of the at least one shunt element 70 partially extends into the semiconductor device (extends into the second semiconductor layer 140) and contacts different additional anti-series pn junctions in at least one additional anti-series pn junction. The shunt element 70 is configured to electrically shunt the additional anti-series pn junction. Each shunt element 70 is in electrical contact with one of the second junction regions 144 and the adjacent first or third region 143, 145. The first end 72 of the shunt element 70 extends into and is in direct contact with the third insulating layer 51. The second end 73 of the shunt element 70 extends into one of the second junction regions 144 and is inserted between the corresponding second junction region 144 and the adjacent first or third region 143, 145 in the second horizontal direction z of the semiconductor body 100. The shunt element 70 may be a buried structure, for example, a buried plug. That is, the shunt element 70 may not extend all the way from the second junction region 144 through the third insulating layer 51 to the sensor electrode 43. The shunt element 70 may only partially extend through the third insulating layer 51 and may be covered by the fourth insulating layer 45. That is, the fourth insulating layer 45 is arranged between the shunt element 70 and the sensor electrode 43 to prevent electrical connection between the shunt element 70 and the sensor electrode 43.

[0048] For example, at least one shunt element 70 may include highly doped polysilicon or metal. According to one example, at least one shunt element 70 includes tungsten. Alternatively, at least one shunt element 70 may include highly doped polysilicon, AlCu, or a barrier liner, wherein the barrier liner may include, for example, at least one of Ti and Ti / N. According to another example, for example, the shunt element 70 includes a tungsten layer having a thickness of at least 1*1019cm -3 However, other suitable materials are also possible.

[0049] According to another example, and if Figure 7 As further shown, the additional shunt layer 71 may be arranged adjacent to the shunt element 70 and abutting the second end 73 of the shunt element 70. Thus, the additional shunt layer 71 may be arranged between the second end 73 of the shunt element 70 and the corresponding second junction region 144 in the vertical direction y of the semiconductor body 100. For example, the additional shunt layer 71 may include a metal silicide, such as TiSi2. According to an example, the additional shunt layer 71 is electrically coupled to a highly doped layer 74, which has the same doping concentration as the corresponding second junction region 144, but may be more highly doped than the second junction region 144.

[0050] Each of the at least one shunt device including the shunt element 70, the additional shunt layer 71 and the highly doped layer 74 is configured to shunt one of the at least one additional pn junction. Therefore, if the corresponding shunt element 70 and the additional shunt layer 71 are provided, the additional pn junctions between the two adjacent second junction regions 144 and the first or third regions 143, 145 will be effectively electrically shunted or blocked.

[0051] Contact as above Figure 6 and Figure 7 As described above, one or more pn junctions may be arranged successively in the semiconductor device along the second horizontal direction z of the semiconductor body 100. However, this is only an example. According to another example, one or more pn junctions may be formed in the semiconductor device, in particular in the second semiconductor layer 140, in the first horizontal direction x of the semiconductor body 100, wherein the first horizontal direction x is perpendicular to the second horizontal direction z. Figure 8 and Fig. 9 An exemplary description of this is given in . Figure 8 Schematically shows Figure 5 1. A cross-sectional view of the semiconductor device in the cross-sectional plane BB is shown. Fig. 9 Schematically shows Figure 5 4. A top view of a region D shown in FIG. 4 is a top view of a region D shown in FIG. 4. In this example, the semiconductor device has a width w3 that is greater than a width w2 of a gap between the source electrode 41 and the sensor electrode 43. The second semiconductor layer 140 may be electrically coupled to the source electrode 41 through the fifth contact plug 424, and electrically coupled to the sensor electrode 43 through the fourth contact plug 44. The fifth contact plug 424 may contact the second semiconductor layer 140 in a section arranged to be adjacent to the first material 150 on the first side, and the fourth contact plug 44 may contact the second semiconductor layer 140 in a section arranged to be adjacent to the first material 150 on the second side of the second semiconductor layer 140.

[0052] One or more pn junctions may be formed into the second semiconductor layer 140, wherein each pn junction is formed between a first junction region 143 and an adjacent second junction region 144. As already described above, at least one pn junction may form at least one diode 201, 202, . . . 20 n The series connection, Fig. 9 This is hinted at by the circuit symbols in FIG. As already described further above, in a chain of two or more consecutive pn junctions, an additional pn junction may be formed between a first junction region 143 of a first pn junction and a second junction region 144 of an adjacent pn junction. Figure 7 As described above, such additional pn junctions can be shunted or blocked by the shunt element 70. Figure 8In the embodiment, only the shunt element 70 is schematically indicated. Such a shunt element 70 and the corresponding additional shunt layer ( Figure 8 The arrangement and function of the components not explicitly shown) can be related to the above Figure 7 The arrangement and function described are similar.

[0053] exist Figure 8 and Fig. 9 In the example shown, the first and second junction regions 143, 144 are elongated regions. That is, the length s2 of the first and second junction regions 143, 144 in the second horizontal direction z is significantly greater than the width of the first and second junction regions 143, 144 in the first horizontal direction x. For example, the second junction region 144 can form a contact region contacted by the fifth contact plug 424, and another second junction region 144 can form another contact region contacted by the fourth contact plug 44. The two contact regions are arranged adjacent to the undercut portion filled with the first material 150 between the second semiconductor layer 140 and the first semiconductor layer 120. The undercut portion can have a maximum depth w4 in the first horizontal direction x. The maximum depth w4 can be (for example) up to 5.5μm.

[0054] As mentioned above, Figures 6 to 9 As described, the semiconductor device can be arranged above or close to the active cell field of the transistor device arranged in the semiconductor body 100. Since the thermal conductivity λ2 of the first material 150 is higher than the thermal conductivity λ1 of the support layer 130, the heat generated in the transistor device is mainly transferred to the second semiconductor layer 140 via the first material 150. For example, at room temperature, the thermal conductivity λ2 of the first material 150 (e.g., polysilicon) can be 90 times the thermal conductivity λ1 of the support layer 130 (e.g., silicon dioxide). That is, the second semiconductor layer 140 is mainly heated by the first semiconductor layer 120 via the first material 150. Therefore, the temperature in at least a portion of the second semiconductor layer 140 can be similar to the temperature of the transistor device. Therefore, the sensor device formed in or on the second semiconductor layer 140 can detect a temperature representing the temperature in the transistor device. For example, the current flowing through at least one pn junction or at least one diode 20 can be detected. n current or at least one diode 20 n If a constant forward current is forced through at least one diode 20 n , then the obtained at least one diode 20 n The forward voltage Vf generally depends on the pn junction or diode 20 nTherefore, the detected forward voltage Vf indicates the temperature of the second semiconductor layer 140 and also indicates the temperature of the transistor device. If the semiconductor device including the sensor device is not arranged on the active cell field of the transistor device but is arranged in a region adjacent to the active cell field, the temperature of the second semiconductor layer 140 may be lower than the temperature of the transistor device because the temperature may not be directly transferred to the second semiconductor layer 140. This may extend the response time of the sensor device.

[0055] according to Fig.10 In another example schematically shown, the sensor device may be at least partially arranged in a sensor region 1401, which is a region of the second semiconductor layer 140 arranged adjacent to the first material 150. As already described above, heat from the transistor device, or more generally from the first semiconductor layer 120, is mainly transferred to the second semiconductor layer 140 via the first material 150. The thermal resistance R of the first material 150 is th Can be quite low. A short response time of the sensor device is crucial for many applications in order to avoid thermal loading of the transistor device. th The support layer 130 of the first semiconductor layer 120 and the second semiconductor layer 140 provides good thermal isolation. The heat capacity C of the second semiconductor layer 140 th For some applications, it may be desirable to reduce the heat capacity C of the second semiconductor layer 140. th According to one example, the semiconductor device may therefore include a region formed of a second material 162 having a thermal conductivity lower than the thermal conductivity of the second semiconductor layer 140. The region of the second material 162 is configured to thermally decouple the first region 1402 of the second semiconductor layer 140 from the sensor region 1401. In the case where the thermal conductivity of the second material 162 is rather low, heat from the sensor region 1401 is transferred to the first region 1402 of the second semiconductor layer 140 only to a very limited extent. This may significantly reduce the heat capacity C of the sensor region 1401. th .like Fig.10As exemplarily illustrated in , the second material 162 may extend through the second semiconductor layer 140 in the vertical direction y. In this way, the sensor region 1401 may be at least partially separated from the remaining first region 1402 and thereby thermally decoupled therefrom. Such thermal decoupling may make the response time of the sensor device faster and the accuracy of the temperature measurement higher. The sensor device may be at least partially arranged in the sensor region 1401. However, some parts of the sensor device may also be arranged in the remaining first region 1402. That is, the sensor device may extend from the sensor region 1401 into the remaining first region 1402. For example, the terminal area contacted by the fourth and fifth contact plugs 44, 424 may be arranged at least in the first region 1402.

[0056] Referring now to FIG. 11 , an exemplary method for producing a semiconductor device is schematically illustrated. Fig.11A As schematically shown in FIG. 1 , the support layer 130 is arranged between the first semiconductor layer 120 and the second semiconductor layer 140. For example, the second semiconductor layer 140 may be a structured layer. That is, the second semiconductor layer 140 is only arranged on some parts of the support layer 130, while other parts of the support layer 130 are not covered by the second semiconductor layer 140. The first semiconductor layer 120 may include conventional semiconductor materials, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs), etc. For example, the first semiconductor layer 120 may have a thickness of at least 5 μm. For example, the support layer 130 may include at least one of oxide, nitride, oxynitride, high-k material, imide, insulating resin or glass. The support layer 130 may include a field dielectric (e.g., field oxide) or a gate dielectric (e.g., gate oxide). The support layer 130 may include a field oxide formed by, for example, a local oxidation of silicon (LOCOS) process, a deposited oxide or a shallow trench isolation (STI). For example, the thickness of the support layer 130, that is, the distance between the first semiconductor layer 120 and the second semiconductor layer 140, can be at least 500nm or at least 800nm. For example, the second semiconductor layer 140 can be a polysilicon layer. For example, the second semiconductor layer 140 can have a thickness of at least 200nm or at least 300nm.

[0057] like Fig. 11B As schematically shown in FIG. 1 , the support layer 130 is partially removed. For example, the support layer may be partially removed using an etching process. During the etching process, the second semiconductor layer 140 may function as a protective layer. That is, the support layer 130 is etched only in those areas that are not covered by the second semiconductor layer 140. However, during the etching process, an undercut may be formed between the first semiconductor layer 120 and the second semiconductor layer 140. Fig. 11BSchematically shows a structure including an undercut portion between the first semiconductor layer 120 and the second semiconductor layer 140 obtained after the etching process.

[0058] Reference now Fig. 11C , insulating layers 122, 142 may be deposited onto exposed surfaces of the first semiconductor layer 120, the support layer 130, and the second semiconductor layer 140. For example, the insulating layers 122, 142 may include at least one of oxide, nitride, oxynitride, high-k material, imide, insulating resin, or glass. The insulating layer may include a field dielectric (e.g., field oxide) or a gate dielectric (e.g., gate oxide). Fig. 11C , the insulating layer is designated as the first insulating layer 122 in those portions covering the first semiconductor layer 120, and is designated as the second insulating layer 142 in those portions covering the second semiconductor layer 140. In those portions thereof covering the support layer 130, the insulating layer is shown as a dotted line. The insulating layer may include the same material as the support layer 130. Thus, in those portions thereof covering the support layer 130 (e.g. Fig. 11C ), which can be regarded as part of the support layer 130. For example, the insulating layer may include a thermally grown oxide. For example, the thickness of such an insulating layer including a thermally grown oxide in those portions thereof covering the support layer 130 may be in the range of several nanometers. However, in those portions thereof covering the first semiconductor layer 120 and the second semiconductor layer 140, the thickness of the thermally grown oxide may be greater than several nanometers. According to another example, the insulating layer may be deposited using a CVD (chemical vapor deposition) process. In this case, the thickness of the insulating layer in those regions where it covers the support layer 130 may be substantially the same as the thickness in those regions where it covers the first semiconductor layer 120 and the second semiconductor layer 140.

[0059] In a subsequent step, the undercut portion may be filled with the first material 150. Thus, a layer of the first material 150 may be formed on the first semiconductor layer 120 and the second semiconductor layer 140, wherein the first insulating layer 122 and the second insulating layer 142 are arranged between the first material 150 and the first semiconductor layer 120 and the second semiconductor layer 140, respectively. During the process of depositing the first material 150, the undercut portion between the first semiconductor layer 120 and the second semiconductor layer 140 may be at least partially filled with the first material 150. Fig.11DIn the example shown, the undercut is completely filled with the first material 150. However, this is only an example. It is possible that the first material 150 does not reach such an area on the far side of the back side of the undercut arranged below the second semiconductor layer 140. Therefore, the undercut may not always be completely filled with the first material 150, and a small cavity may remain between the second semiconductor layer 140 and the support layer 130. After depositing the first material 150, the first material 150 in such an area that is not arranged within at least one undercut may be removed, such as Fig.11E As shown schematically, for example, the first material 150 may be removed using an anisotropic etching process.

[0060] Reference now Fig.11F , a mask layer 180 may be formed. The mask layer 180 may cover the exposed surfaces of the first insulating layer 122 and the first material 150. In addition, the mask layer 180 may partially cover the exposed surface of the second insulating layer 142. However, there may be openings in the mask layer 180. In the etching process described below, at least one trench 160 may be formed in those areas not covered by the mask layer 180. The at least one trench 160 may extend through the second insulating layer 142 and the second semiconductor layer 140 in the vertical direction y. The at least one trench 160 may separate at least one sensor region 1401 of the second semiconductor layer 140 from the remaining first region 1402, as described above in connection with Fig.10 Afterwards, at least one trench 160 may be filled with a second material 162, such as Fig.11G . The second material 162 may have a thermal conductivity lower than that of the second semiconductor layer 140. For example, the second material 162 may include an oxide, a thermal oxide, or an inter-level oxide (TEOS or BPSG). However, the use of another mask layer 180 is only an example. It is also possible to form at least one trench 160 without using an additional mask. For example, at least one trench 160 may be formed in the same step of etching the second semiconductor layer 140. Initially, the second semiconductor layer 140 may be a continuous layer that will be partially removed during the patterning step. That is, the second semiconductor layer 140 may have a final size (width w3, length s2) that is larger than the final size after the patterning step (for example, see Fig. 9 ). After performing this patterning step (during which at least one trench may also be formed), the at least one trench 160 may be filled with a photoresist, which is used for a field oxide mask in a subsequent field oxide etching process (etching of the support layer 130). Once the field oxide is etched and the photoresist is removed, the at least one trench 160 is oxidized during a subsequent gate oxidation and later filled with an inter-level oxide (TEOS and / or BPSG) forming a second material 162.

[0061] like Fig.12 As schematically shown in FIG. 1 , the second material 162 may be arranged to thermally decouple the sensor region 1401 from the first region 1402, wherein the first region 1402 may function as a connection region. That is, the first region 1402 may be a region where the fifth contact plug 424 and the fourth contact plug 44 are arranged to contact the second semiconductor layer 140. Fig.12 Schematically shows a top view of a semiconductor body including an exemplary semiconductor device. The top view shows the region of the second semiconductor layer 140. The support layer 130 arranged below the second semiconductor layer 140 along the vertical direction y is Fig.12 The fourth contact plug 44 and the fifth contact plug 424 are indicated with dotted lines in FIG. 1404 because they are covered by the second semiconductor layer 140. A connection region 1402 in which the fourth contact plug 44 and the fifth contact plug 424 contact the second semiconductor layer 140 is also indicated with dotted lines. Fig.12 The example in FIG. 1 shows a double-line connection, that is, a fourth contact plug 44 and a fifth contact plug 424 are used to electrically connect the second semiconductor layer 140 to the first metallization 41 and the second metallization 43, respectively (the first metallization 41 and the second metallization 43 are connected at Fig.12 1402 and 1403. The second material 162 partially surrounds the connection region 1402 in the horizontal directions x, z of the semiconductor body 100. However, the connection may still allow current to flow between the connection region 1402 and the at least one sensor region 1401. Fig.12 The shape of the second material 162 shown is only an example. Any other shape is possible to thermally decouple the connection region 1402 from the at least one sensor region 1401. For example, the second material 162 may be arranged in a meandering connection line (not shown).

[0062] As already contacted above Figures 6 to 9 As described, the semiconductor device and the sensor pad 330 may be arranged in an active region of a transistor device arranged within the semiconductor body 100. However, this is only an example. Fig.13In another example schematically shown, the semiconductor device may be alternatively arranged in an inactive region of a transistor device arranged within the semiconductor body 100. The inactive region of the transistor device may be a region that does not include all active components required to form a functioning (working) transistor unit (e.g., the active components are gate oxide, source region 31, body region 32, gate electrode 33, or drain region 36). In addition, the inactive region may include a field oxide instead of a gate oxide. In the active region, the gate oxide may form the first insulating layer 122 as described above. For example, the inactive region may be a region (edge ​​region) adjacent to a horizontal edge of the semiconductor body 100. However, the sensor pad 330 or the second metallization 43 may be arranged at least partially in the active region of the transistor device, respectively. That is, the active components of the transistor device (e.g., gate oxide, source region 31, body region 32, gate electrode 33, compensation region 38) may be arranged below the second metallization 43. However, the second metallization 43 may extend to the inactive region of the transistor device so as to electrically contact the semiconductor device and the sensor device. In Fig.13 In FIG. 2 , the semiconductor devices are indicated only by diodes 201 and 202. Fig.13 As shown in FIG. 4 , a portion of the second metallization 43 can be used as a bonding area (see also Fig.14 That is, a bonding wire can be bonded to this section of the second metallization 43 in order to electrically contact the second metallization. Fig.13 In FIG, this section of the second metallization is indicated as having a width w5. Any contact plug arranged below the second metallization 43 may be electrically insulated from the second metallization 43 by the fourth insulating layer 45 so as to prevent an electrical short circuit between the second metallization 43 and the first metallization 41. Fig.13 This applies to the third contact plug 423 , for example.

[0063] Reference now Fig.14 In an alternative example, the semiconductor device may be arranged in a high voltage edge termination zone of the semiconductor body 100. The high voltage edge termination zone is arranged in an inactive region of the transistor device. The second metallization 43 may be arranged in the active region of the transistor device, but may extend into the inactive region of the transistor device in order to electrically contact the semiconductor device. The semiconductor device, when arranged in the inactive region of the transistor device, may be arranged in a portion of the inactive region that is arranged to be directly adjacent to the active region of the transistor device. For example, Fig.14As shown, the undercut filled with the first material 150 can be arranged adjacent to the body region 32 of one of the transistor cells. In this way, the thermal coupling between the active region of the transistor device that generates heat and the semiconductor device is still sufficient to allow a fast reaction time and accurate measurement. That is, the temperature detected by the sensor device arranged in the semiconductor device is substantially equal to the temperature of the transistor device. The other parts of the semiconductor device can be thermally decoupled by the second material 162, as described above in connection with Fig.10 and Fig.12 described.

[0064] The second metallization 43 forming the active sensor pad ASP is generally formed by bonding wires ( Fig.14 Such a bonding wire may be bonded to the second metallization 43 in a designated bonding area BA. For example, the bonding area BA may be formed by such a portion of the second metallization 43 that is arranged on the active area of ​​the transistor device, such as Fig.14 However, it is also possible to provide a bonding area BA (not shown) on such a portion of the second metallization 43 that is arranged on an inactive area of ​​the transistor device.

[0065] As mentioned above Figure 7 and Fig. 9 As stated and Fig.15 As further shown in , the semiconductor device can be an elongated structure. That is, the length s2 of the semiconductor device in the second horizontal direction z is larger than the width w3 of the semiconductor device in the first horizontal direction x. As described above, the length s2 of the semiconductor device in the second horizontal direction z can be between 50μm and 1500μm, can be between 100μm and 1500μm, or can be between 500μm and 1500μm, for example, can be 1000μm. The undercut is generally formed on opposite sides along the entire length s2 of the semiconductor device. After the undercut is formed and before the undercut is filled with the first material 150, the second semiconductor layer 140 includes a freestanding structure in those areas adjacent to the undercut (see Fig. 11B and Fig. 11C ). The semiconductor device in this intermediate state has a structure similar to a table. However, the thickness of the second semiconductor layer 140 is quite small, as described above. Fig.11AAs described. For example, the second semiconductor layer 140 may have a thickness d2 of 200nm, 300nm, 500nm or up to 1μm. For example, the extended region of the second semiconductor layer 140 arranged adjacent to the undercut portion may have a length w4 of about 4.5μm. In other words, the maximum depth w4 of the undercut portion in the first horizontal direction x may be about 4.5μm. However, other depths w4 are also possible. The different thicknesses d2 of the second semiconductor layer 140 (for example) from about 200nm to about 1μm and the maximum depth w4 of the undercut portion of about 4.5μm bring about a finite aspect ratio of about 4 to 22 (w4 / d2=4.5μm / 200...1000nm) (see, for example, Figure 16). For different thicknesses of the second semiconductor layer 140 and different maximum depths w4 of the undercut portion, other aspect ratios are also possible. For many applications, such a finite aspect ratio is tolerable. However, in this intermediate state with the undercut formed between the first semiconductor layer 120 and the second semiconductor layer 140, the semiconductor device may be mechanically unstable. For example, the mechanical stability of the structure may be adversely affected by a wet etching process or may be adversely affected during a drying process. Due to capillary forces between adjacent structures, for example, an extended area of ​​the second semiconductor layer 140 may stick to the support layer 130 or the first semiconductor layer 120. There is also a high risk of cracks forming in the second semiconductor layer 140, especially in those areas that are arranged adjacent to the undercut. Therefore, there is a risk of increased defect counts and yield losses may also be high.

[0066] In order to improve the mechanical stability of the semiconductor device, the semiconductor device may include at least one support structure 132. The at least one support structure 132 may be formed by a portion of the support layer 130. For example, the support layer 130 may include a segment extending from under the second semiconductor layer 140 along a first horizontal direction, and the extended segment forms the at least one support structure 132. Fig.15 Schematically shows a semiconductor device with a support structure 132. The semiconductor device may include one support structure 132 arranged along the length s2 of the support structure. However, in other embodiments, two or more support structures 132 may be arranged along the length s2 of the semiconductor device. The number of support structures 132 may depend on the length s2 of the semiconductor device. Therefore, the support layer 130 may have a first minimum width w7 (w7 = (w3-2*w4), see Fig. 9 and Fig.16A ), and may have a second width w5 (w5=w3+2*w6, see Fig. 16B). For example, the second width w5 may be 22 μm or more. For example, the extended portion of the support layer 130 may have a width w6 of about 4.5 μm. For example, the at least one support structure 132 may have a width s3 of about 9 μm.

[0067] Fig.16A Schematically shows Fig.15 The cross-sectional view of the semiconductor device in the cross-sectional plane EE is shown in a region where the undercut is formed between the first semiconductor layer 120 and the second semiconductor layer 140 . Fig.16A Basically corresponds to the above connection Figure 3 The structure has been fully described. Fig. 16B Schematically shows Fig.15 1 , a cross-sectional view of the semiconductor device in the cross-sectional plane E'-E' shown, which is in the region where the support structure 132 is formed. The support layer 130 in this region protrudes from under the second semiconductor layer 140. That is, no undercut is formed in this section of the semiconductor device. Therefore, in the region of the support structure 132, the thermal conductivity between the first semiconductor layer 120 and the second semiconductor layer 140 is low. Therefore, according to one example, a sensor device may not be formed in a section of the second semiconductor layer 140 that is arranged adjacent to one of the at least one support structure 132.

[0068] No additional etching process is required to form at least one support structure 132. At least one support structure 132 may be formed during the same etching process used to form the undercut. Exemplary illustrations of this are given by FIGS. 17 and 18. Fig.18A , the mask layer 190 may be partially disposed on the second semiconductor layer 140 and on a portion of the support layer 130. However, it is optional to dispose the mask layer 190 on a portion of the second semiconductor layer 140. The second semiconductor layer 140 itself may function as a mask layer during the etching process. Therefore, it will be sufficient to dispose the mask layer 190 only on a portion of the support layer 130 adjacent to the second semiconductor layer 140. Fig.18A Schematically shows Fig.15 A cross-sectional view of the semiconductor device in the cross-sectional plane E'-E' is shown. Fig.17A Shows Fig.15 A cross-sectional view of the semiconductor device in the cross-sectional plane EE is shown. Fig.17A Corresponding to what has been described above Fig.11A , and shows a semiconductor device before an etching process is performed in those areas where undercuts are to be formed. During the etching process described below, undercuts are formed in those areas of the semiconductor structure that are not covered by the mask layer 190 (see Fig. 17B ). However, if Fig.18BAs schematically shown, in those sections where the mask layer 190 is arranged on the support layer 130, no undercut is formed between the first semiconductor layer 120 and the second semiconductor layer 140. During the etching process, an undercut will be formed between the first semiconductor layer 120 and the mask layer 190, as shown in FIG. Fig.18B However, when the mask layer 190 is removed after the etching process is completed, the undercut portion between the first semiconductor layer 120 and the mask layer 190 is naturally removed, and the protruding region of the support layer 130 remains to form the support structure 132, as shown in FIG. Fig.18C shown.

[0069] Reference now Fig.19A , schematically shows an exemplary semiconductor device. The semiconductor device includes a semiconductor body 100 and a transistor device. The semiconductor body 100 includes a first semiconductor layer 120. The transistor device includes a plurality of transistor cells. For example, the transistor device may include a so-called super junction device. Fig.19A The transistor device shown corresponds essentially to the one already mentioned above. Figure 6 and Figure 8 The transistor device. In the example shown in FIG. 19 , the transistor device is arranged in a first section of the semiconductor body 100 or the first semiconductor layer 120, respectively, wherein the first section forms an active area of ​​the semiconductor body 100 or the first semiconductor layer 120. In the active area, the semiconductor device includes at least one working transistor unit having a gate electrode 33, and the gate electrode 33 is dielectrically insulated from the body region 32 by a gate dielectric 34. The body region 32 is a doped semiconductor region in the active area of ​​the semiconductor body 100. Fig.19A In the example shown, the gate electrode 33 is arranged over the first surface 101 of the semiconductor body 100 .

[0070] Fig.19AThe transistor device shown further comprises a drift region 35. The drift region 35 is adjacent to the body region 32 of at least one transistor cell and forms a pn junction with the body region 32. The drift region 35 is arranged between the body region 32 and the drain region 36 of the at least one transistor cell. The drain region 36 may be adjacent to the drift region 35 (as shown). According to another example (not shown), a field stop region having the same doping type as the drift region 35 but being more highly doped than the drift region 35 is arranged between the drift region 35 and the drain region 36. Furthermore, the transistor device comprises at least one compensation region 38, the doping type of the compensation region 38 being complementary to the doping type of the drift region 35. According to an example, the at least one compensation region 38 is adjacent to the body region 32 of the at least one transistor cell. According to an example, the transistor device comprises a plurality of transistor cells, and each transistor cell comprises a compensation region 38 adjacent to the body region 32 of the respective transistor cell. In the vertical direction y of the semiconductor body 100 / first semiconductor layer 120 (which is a direction perpendicular to the first surface 101), at least one compensation region 38 extends towards the drain region 36. According to one example (not shown), the compensation region 38 is spaced apart from the drain region 36 such that there is a section or buffer zone of the drift region 35 between the compensation region 38 and the drain region 36. For example, such a buffer zone may have the same doping type as the drift region 35, but be more highly doped than the drift region 35. According to another example, the compensation region adjoins the drain region 36 (see FIG. 2 ). Fig.19A ).

[0071] The semiconductor device further comprises a sensor structure, wherein the sensor structure is formed in or on the second semiconductor layer 140. The second semiconductor layer 140 is arranged above the first semiconductor layer 120 or the drift region 35 in the vertical direction y of the semiconductor body 100, respectively, and is dielectrically insulated from the first semiconductor layer 120 / drift region 35 by the gate dielectric 34. Figure 6 The explained implantation zone 124 may be formed between the gate dielectric 34 and the first semiconductor layer 120 or the drift region 35, respectively, under the second semiconductor layer 140. The second semiconductor layer 140 may be electrically coupled to the source electrode 41 through the fifth contact plug 424, and electrically coupled to the sensor electrode 43 through the fourth contact plug 44. The second semiconductor layer 140 having the sensor structure is at least partially arranged in the active region of the semiconductor body 100.

[0072] The second semiconductor layer 140 having the sensor device arranged therein or thereon can be arranged completely in the active area of ​​the semiconductor body 100, as shown in FIG. 19. However, this is only an example. Alternatively, the second semiconductor layer 140 can be arranged completely on the inactive area of ​​the semiconductor body 100. According to another example, the second semiconductor layer 140 can be arranged partially on the active area and partially on the inactive area. The inactive area of ​​the semiconductor body 100 can be an area that does not include all active components (for example, the active components are gate oxide, source region 31, body region 32, gate electrode 33 or drain region 36) required to form a functioning (working) transistor unit. In addition, the inactive area can include a field oxide instead of a gate oxide. For example, the inactive area can be an area (edge ​​area) adjacent to the horizontal edge of the semiconductor body 100.

[0073] Reference now Fig.19B , the sensor device may include at least one pn junction. Fig.19B Only a very rough indication is given for at least one pn junction. Each pn junction may be formed between a first junction region 143 and an adjacent second junction region 144 (the first and second junction regions are located at Fig.19B As already described above, at least one pn junction can form a series connection of at least one diode. As already described further above, in a chain of two or more consecutive pn junctions, additional pn junctions may be formed between a first junction region of a first pn junction and a second junction region of an adjacent pn junction. Figure 7 and Figure 8 As has been described, such additional pn junctions can be shunted or blocked by the shunt element 70. Fig.19B In the embodiment, only the shunt element 70 is schematically indicated. Such a shunt element 70 and the corresponding additional shunt layer ( Fig.19B The arrangement and function of the components not explicitly shown) can be related to the above Figure 7 and Figure 8 The arrangement and function described are similar.

Claims

1. A method for producing a semiconductor device, comprising: Partially removing a support layer (130) disposed between a first semiconductor layer (120) and a second semiconductor layer (140) using an etching process, thereby forming at least one undercut portion between the first semiconductor layer (120) and the second semiconductor layer (140); Filling the at least one undercut with a first material (150) having a higher thermal conductivity (λ2) than the support layer (130) such that the at least one undercut is completely filled with the first material, or such that the at least one undercut is completely filled with the first material except for a cavity where the second semiconductor layer intersects the support layer; as well as A sensor device (20) is formed in or on the second semiconductor layer (140).

2. The method according to claim 1, wherein: At least partially filling the at least one undercut comprises: forming a layer of the first material (150) on an exposed surface of the first semiconductor layer (120) and on an exposed surface of the support layer (130); and The first material (150) is removed in such areas not arranged within the at least one undercut.

3. The method according to claim 1 or 2, further comprising: A trench (160) is formed in the second semiconductor layer (140), wherein the trench extends from a top surface of the second semiconductor layer (140) to an opposite bottom surface of the second semiconductor layer (140).

4. The method according to claim 3, further comprising: The trench (160) is filled with a second material (162) having a thermal conductivity lower than the thermal conductivity of the second semiconductor layer (140).

5. The method according to claim 1 or 2, wherein: Forming a sensor device (20) in the second semiconductor layer (140) includes: At least one pn junction is formed in the second semiconductor layer (140).

6. The method according to claim 1 or 2, wherein: The second semiconductor layer (140) functions as a protective layer during the etching process for partially removing the support layer (130).

7. The method according to claim 6, further comprising: Before partially removing the support layer (130), a mask layer (190) is formed adjacent to at least one section of the support layer (130), wherein the mask layer (190) is configured to prevent an undercut from being formed between the first semiconductor layer (120) and the second semiconductor layer (140) in the at least one section.

8. The method according to claim 7, further comprising: When the etching process for partially removing the support layer (130) is completed, the mask layer (190) is removed.

9. A semiconductor device comprising: A support layer (130) arranged between the first semiconductor layer (120) and the second semiconductor layer (140), wherein the support layer (130) has a first thermal conductivity (λ1); at least one first region formed between the first semiconductor layer (120) and the second semiconductor layer (140) and adjacent to the support layer (130), wherein the at least one first region is completely filled with a first material (150), or the at least one first region is completely filled with the first material (150) except for a hole where the second semiconductor layer and the support layer intersect, and wherein the first material (150) has a second thermal conductivity (λ2) higher than the first thermal conductivity (λ1); and A sensor device (20) is formed in or on the second semiconductor layer (140).

10. The semiconductor device according to claim 9, wherein: The sensor device (20) comprises at least one pn junction.

11. The semiconductor device according to claim 9 or 10, wherein: The support layer (130) includes a section extending from below the second semiconductor layer (140).

12. The semiconductor device according to claim 9 or 10, further comprising: a first insulating layer (122) disposed between the first semiconductor layer (120) and the first material (150); as well as A second insulating layer (142) is disposed between the second semiconductor layer (140) and the first material (150).

13. The semiconductor device according to claim 12, wherein: The second insulating layer (142) is further arranged on a surface of the second semiconductor layer (140) not covered by the supporting layer (130).

14. The semiconductor device according to claim 9 or 10, further comprising a transistor device, the transistor device comprising at least one gate electrode (33) and a plurality of transistor units, each transistor unit comprising a source region (31) and a body region (32) formed in the first semiconductor layer (120), wherein The body region (32) extends from a first surface (101) of the first semiconductor layer (120) into the first semiconductor layer (120) and is dielectrically insulated from the at least one gate electrode (33) by a gate dielectric (34).

15. The semiconductor device according to claim 14, wherein: The source region (31) and the body region (32) of each transistor cell are electrically connected to a first metallization (41) forming a source node (S) of the transistor device; and The second semiconductor layer (140) is electrically connected to the first metallization (41).

16. The semiconductor device according to claim 15, wherein: The second semiconductor layer (140) is further electrically connected to a second metallization (43) forming an active sensor pad (ASP).

17. The semiconductor device according to claim 16, further comprising a third insulating layer (51) arranged on the first surface (101) of the first semiconductor layer (120), wherein: The third insulating layer (51) is further arranged between the second metallization (43) and the first semiconductor layer (120).

18. The semiconductor device according to claim 17, wherein: At least one of the plurality of transistor cells is arranged in a section of the first semiconductor layer (120) arranged below the second metallization (43).

19. The semiconductor device according to any one of claims 16 to 18, wherein: The sensor device (20) includes at least one diode (20) in the second semiconductor layer (140) n ).

20. The semiconductor device according to claim 19, wherein The first metallization (41) is electrically connected to the at least one diode (20 n ) is a cathode of one of the following: The second metallization (43) forming a sensor pad (ASP) is electrically connected to the at least one diode (20 n ) is one of the anodes.

21. The semiconductor device according to claim 14, wherein The sensor device is at least partially arranged in an active region of the transistor device, or at least partially arranged in an inactive region of the transistor device.

22. The semiconductor device according to claim 9 or 10, wherein: The second semiconductor layer (140) has a first width (w3) in a first horizontal direction (x) of the semiconductor body (100) and a first length (s2) in a second horizontal direction (z) of the semiconductor body (100), the first horizontal direction (x) being perpendicular to the second horizontal direction (z); The first width (w3) is between 10 μm and 200 μm; and The first length (s2) is between 10 μm and 1500 μm.

23. The semiconductor device according to claim 9 or 10, wherein: The second semiconductor layer (140) comprises a sensor region (1401) and a remaining region (1402), wherein the sensor device (20) is at least partially formed in the sensor region (1401), and wherein the semiconductor device further comprises a layer of a second material (162) configured to provide thermal insulation between the sensor region (1401) and the remaining region (1402).

24. The semiconductor device according to claim 10, wherein: Each of the at least one pn junction includes a first junction region (143) having a first doping type and a second junction region (144) having a second doping type complementary to the first doping type; or Each of the at least one pn junction includes a first junction region (143) having a first doping type, a second junction region (144) having a second doping type complementary to the first doping type, and at least one third region (145) having the same doping type as the first junction region (143) but more highly doped than the first junction region (143), wherein each of the at least one third region (145) is arranged between the first junction region (143) of the first pn junction and the second junction region (144) of the successive pn junction.

25. The semiconductor device according to claim 24, wherein: The first junction region (143) of the first pn junction and the second junction region (144) of the successive pn junction form at least one additional anti-series pn junction; The semiconductor device further comprises at least one shunt element (70); Each of the at least one shunt element (70) is in electrical contact with the first junction region (143) of a first pn junction and an adjacent second junction region (144) of a successive pn junction; and Each of the at least one shunt element (70) is configured to electrically shunt one of the additional anti-series pn junctions.

26. The semiconductor device according to claim 24, wherein: The third region (145) and the second junction region (144) adjacent to the pn junction form at least one additional anti-series pn junction; The semiconductor device further comprises at least one shunt element (70); Each of the at least one shunt element (70) is in electrical contact with the third region (145) of the first pn junction and the second junction region (144) of the successive pn junction; and Each of the at least one shunt element (70) is configured to electrically shunt one of the additional anti-series pn junctions.

27. The semiconductor device according to claim 25 or 26, wherein: The at least one shunt element (70) includes tungsten, highly doped polysilicon, AlCu, or a barrier liner.

28. The semiconductor device according to claim 25 or 26, wherein: A fourth insulating layer (45) is arranged between the at least one shunt element (70) and the second metallization (43) in order to dielectrically insulate the at least one shunt element (70) from the second metallization (43).

29. A semiconductor device comprising: A semiconductor body (100) comprising a first semiconductor layer (120); as well as A transistor device comprising at least one gate electrode (33) and a plurality of transistor cells, each of the transistor cells comprising a source region (31), a body region (32) and a compensation region (38) formed in the first semiconductor layer (120), wherein The body region (32) extends from the first surface (101) of the first semiconductor layer (120) into the first semiconductor layer (120) and is dielectrically insulated from the at least one gate electrode (33) by a gate dielectric (34); The compensation region (38) is adjacent to the main region (32) and extends from the main region (32) into the first semiconductor layer (120); The transistor device is arranged in a first section of the semiconductor body (100), the first section forming an active area; and The semiconductor device further comprises a second semiconductor layer (140) arranged on an active region and / or an inactive region of the semiconductor body (100), a sensor device (20) formed in or on the second semiconductor layer (140), a support layer (130) arranged between the first semiconductor layer (120) and the second semiconductor layer (140), and at least one first region formed between the first semiconductor layer (120) and the second semiconductor layer (140) and adjacent to the support layer (130), wherein the at least one first region is completely filled with a first material (150), or the at least one first region is completely filled with the first material (150) except for a hole at the intersection of the second semiconductor layer and the support layer, and wherein the first material (150) has a higher thermal conductivity (λ2) than the support layer.

30. The semiconductor device according to claim 29, wherein The second semiconductor layer (140) is dielectrically insulated from the first semiconductor layer (120) by the gate dielectric (34).

31. The semiconductor device according to claim 29 or 30, wherein: The sensor device (20) includes at least one pn junction within the second semiconductor layer (140).

32. The semiconductor device according to claim 31, wherein Each of the at least one pn junction includes a first junction region (143) having a first doping type and a second junction region (144) having a second doping type complementary to the first doping type; or Each of the at least one pn junction includes a first junction region (143) having a first doping type, a second junction region (144) having a second doping type complementary to the first doping type, and at least one third region (145) having the same doping type as the first junction region (143) but more highly doped than the first junction region (143), wherein each of the at least one third region (145) is arranged between the first junction region (143) of the first pn junction and the second junction region (144) of the successive pn junction.

33. The semiconductor device according to claim 32, wherein: The first junction region (143) of the first pn junction and the second junction region (144) of the successive pn junction form at least one additional anti-series pn junction; The semiconductor device further comprises at least one shunt element (70); Each of the at least one shunt element (70) is in electrical contact with the first junction region (143) of a first pn junction and an adjacent second junction region (144) of a successive pn junction; and Each of the at least one shunt element (70) is configured to electrically shunt one of the additional anti-series pn junctions.

34. The semiconductor device according to claim 32, wherein: The third region (145) and the second junction region (144) of the adjacent pn junction form at least one additional anti-series pn junction; The semiconductor device further comprises at least one shunt element (70); Each of the at least one shunt element (70) is in electrical contact with the third region (145) of the first pn junction and the second junction region (144) of the successive pn junction; and Each of the at least one shunt element (70) is configured to electrically shunt one of the additional anti-series pn junctions.

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