Semiconductor device having a recess in an encapsulating material and associated manufacturing method

Abstract

Embodiments of the present disclosure relate to a semiconductor device having a recess in an encapsulation material and a manufacturing method therefor. The method includes providing at least one semiconductor component, wherein each of the at least one semiconductor components includes: a semiconductor chip, wherein the semiconductor chip includes a first main surface and a second main surface opposite to the first main surface, and a sacrificial material disposed on the opposite second main surface of the semiconductor chip. The method further includes encapsulating the at least one semiconductor component with an encapsulation material. The method further includes removing the sacrificial material, wherein a recess in the encapsulation material is formed on each of the at least one semiconductor chips. The method further includes disposing at least one lid on the at least one recess, wherein a closed cavity is formed on each of the at least one semiconductor chips through the at least one recess and the at least one lid.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor technology. In particular, this disclosure relates to semiconductor devices having recesses in an encapsulation material and methods of manufacturing such semiconductor devices. Background Art

[0002] In many applications, semiconductor chips included in semiconductor devices must be protected from external influences. For this purpose, for example, the semiconductor chips are embedded in an encapsulation material. Using the encapsulation material can cause undesired power losses during operation of the semiconductor device. For example, coupling may occur between the encapsulation material and electromagnetic waves emitted from the semiconductor device, which may result in signal loss. Semiconductor device manufacturers are seeking to provide improved semiconductor devices and methods of manufacturing such semiconductor devices. In particular, it may be desirable to provide semiconductor devices having low performance losses and methods of manufacturing the same. Summary of the Invention

[0003] One aspect of the present disclosure relates to a method, comprising: providing at least one semiconductor component, wherein each of the at least one semiconductor component includes: a semiconductor chip, wherein the semiconductor chip includes a first major surface and a second major surface opposite the first major surface, and a sacrificial material disposed above the opposite second major surface of the semiconductor chip; encapsulating the at least one semiconductor component with an encapsulation material; removing the sacrificial material, wherein a recess in the encapsulation material is formed above each of the at least one semiconductor chip; and disposing at least one lid above the at least one recess, wherein a closed cavity is formed above each of the at least one semiconductor chip through the at least one recess and the at least one lid.

[0004] Another aspect of the present disclosure relates to a device, comprising: a semiconductor chip, which includes a first major surface and a second major surface opposite the first major surface; an encapsulation material, wherein the semiconductor chip is encapsulated by the encapsulation material; a recess disposed in the encapsulation material, wherein the recess is disposed above the opposite major surface of the semiconductor chip, and wherein in an orthogonal projection onto the opposite major surface, a base surface of the recess at least partially extends beyond a base surface of the semiconductor chip.

[0005] Another aspect of the present disclosure relates to a device, comprising: a semiconductor chip, which includes a first major surface and a second major surface opposite the first major surface; an encapsulation material, wherein the semiconductor chip is at least partially encapsulated by the encapsulation material; and a recess disposed in the encapsulation material, wherein the recess is disposed above the opposite major surface of the semiconductor chip, and wherein in a projection perpendicular to the first major surface of the semiconductor chip, a base surface of the recess is disposed above a region of the semiconductor chip and / or the encapsulation material in which high-frequency signals are processed or transmitted.

[0006] Another aspect of the present disclosure relates to an apparatus, comprising: a semiconductor chip including a first major surface and a second major surface opposite to the first major surface; an encapsulating material, wherein the semiconductor chip is encapsulated by the encapsulating material; and a material disposed above opposite major surfaces of the semiconductor chip, wherein in a projection perpendicular to the first major surface of the semiconductor chip, the material does not overlap at least one high-frequency region of the semiconductor chip and / or the encapsulating material, and high-frequency signals are processed or transmitted in the high-frequency region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The semiconductor device and the associated manufacturing method according to the present disclosure will be explained in more detail below with reference to the drawings. The elements shown in the drawings are not necessarily drawn to scale. The same reference numerals may represent the same components.

[0008] FIG. 1 includes Figures 1A to 1D , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 100 according to the present disclosure.

[0009] FIG. 2 includes Figure 2A and 2B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 200 according to the present disclosure.

[0010] FIG. 3 includes Figures 3A to 3O , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 300 according to the present disclosure.

[0011] FIG. 4 includes Figures 4A to 4H , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 400 according to the present disclosure.

[0012] FIG. 5 includes Figures 5A to 5I , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 500 according to the present disclosure.

[0013] Figure 6 Schematically shows a cross-sectional side view of a semiconductor device 600 according to the present disclosure.

[0014] Figure 7 Schematically shows a cross-sectional side view of a semiconductor device 700 according to the present disclosure.

[0015] Figure 8 Shows a flowchart of a method for manufacturing a semiconductor device according to the present disclosure.

[0016] FIG. 9 includes Figure 9A and 9B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 900 according to the present disclosure.

[0017] Figure 10 includes Figure 10A and 10B and schematically shows a cross-sectional side view and a top view of a semiconductor device 1000 according to the present disclosure.

[0018] Figure 11 includes Figure 11A and 11B and schematically shows a cross-sectional side view and a top view of a semiconductor device 1100 according to the present disclosure.

[0019] Figure 12 includes Figure 12A and 12B and schematically shows a cross-sectional side view and a top view of a semiconductor device 1200 according to the present disclosure.

[0020] Figure 13 Shows a chart in which the isolation quality between a transmission channel and an adjacent reception channel for different semiconductor devices is shown.

[0021] Figure 14 includes Figure 14A and 14B and schematically shows a cross-sectional side view and a top view of a semiconductor device 1400 according to the present disclosure.

[0022] Figure 15 includes Figure 15A and 15B and schematically shows a cross-sectional side view and a top view of a semiconductor device 1500 according to the present disclosure.

[0023] Figure 16 Schematically shows a top view of a semiconductor device 1600 according to the present disclosure.

[0024] Figure 17 Schematically shows a top view of a semiconductor device 1700 according to the present disclosure.

[0025] Figure 18 Schematically shows a top view of a semiconductor device 1800 according to the present disclosure.

[0026] Figure 19 Schematically shows a top view of a semiconductor device 1900 according to the present disclosure.

[0027] Figure 20 Schematically shows a top view of a semiconductor device 2000 according to the present disclosure.

[0028] Figure 21 includes Figure 21A and 21B and schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 2100 according to the present disclosure.

[0029] Figure 22 A top view of a semiconductor device 2200 according to the present disclosure is schematically shown.

[0030] Figure 23 A top view of a semiconductor device 2300 according to the present disclosure is schematically shown.

[0031] Figure 24 A top view of a semiconductor device 2400 according to the present disclosure is schematically shown. Detailed Description

[0032] In the following detailed description, reference is made to the accompanying drawings, which show by way of illustration specific aspects and embodiments in which the present disclosure may be practiced. In this regard, directional terms such as "top", "bottom", "front", "rear", etc. may be used with reference to the orientation of the described drawings. Since the components of the described embodiments may be positioned in different orientations, the directional terms are used for illustrative purposes and are not limiting in any way. Other aspects may be utilized and structural or logical changes may be made without departing from the concept of the present disclosure. That is, the following detailed description should not be construed as limiting.

[0033] FIG. 1 includes Figures 1A to 1D , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 100 according to the present disclosure. The method is described in a general manner to qualitatively describe aspects of the present disclosure. The method may have other aspects, which are not shown in FIG. 1 for simplicity. For example, the method may be extended to any aspect described in combination with other devices and methods according to the present disclosure.

[0034] In Figure 1A , at least one semiconductor component 2 is provided. In the example of Figure 1A , only a single semiconductor component 2 is shown for simplicity. In other examples, the number of semiconductor components 2 may be different and may be arbitrarily selected. Each of the at least one semiconductor components 2 has a semiconductor chip 4, wherein the semiconductor chip 4 includes a first main surface 6 and a second main surface 8 opposite to the first main surface 6. In addition, each of the at least one semiconductor components 2 has a sacrificial material 10 disposed above the opposite second main surface 8 of the semiconductor chip 4.

[0035] Generally, the semiconductor chip 4 may include integrated circuits, passive electronic components, active electronic components, etc. The integrated circuits may be formed as integrated logic circuits, analog integrated circuits, mixed-signal integrated circuits, power integrated circuits, etc. The semiconductor chip 4 may be manufactured from elemental semiconductor materials (e.g., Si (silicon), etc.) or compound semiconductor materials (e.g., GaN (gallium nitride), SiC (silicon carbide), SiGe (silicon germanium), GaAs (gallium arsenide), etc.).

[0036] In an example, the semiconductor chip 4 may be a high-frequency chip, such as a radar sensor chip. Thus, the semiconductor chip 4 may operate in the high-frequency or microwave frequency range, which typically can reach from about 10 GHz to about 300 GHz. Exemplarily, the semiconductor chip 4 thus includes one or more integrated high-frequency or microwave circuits, which can operate in a frequency range greater than 10 GHz. Such microwave circuits may include, for example, microwave transmitters, microwave receivers, microwave transceivers, microwave sensors, or microwave detectors. The devices described here can be used for radar applications. Radar microwave devices can be used, for example, in automotive or industrial applications for distance determination / distance measurement systems. Exemplarily, an automatic vehicle speed regulation system or a vehicle collision avoidance system can operate in the microwave frequency range, for example, at about 24 GHz, 77 GHz, or 79 GHz.

[0037] In another example, the semiconductor chip 4 may be a sensor chip including a detection structure. In particular, it may relate to a sensor chip that requires a cavity or recess for its operation. The sensor chip may especially include MEMS (mikroelektromechanisches System, microelectromechanical system), which may be integrated in the semiconductor chip 4. The MEMS may include one or more micro-mechanical structures, such as bridges, membranes, cantilevers, tongue structures, etc. The MEMS may be designed to detect physical variables, such as pressure, temperature, humidity, etc. Examples of sensors are pressure sensors, tire pressure sensors, gas sensors, humidity sensors, etc.

[0038] The semiconductor chip 4 can have one or more electronic structures, which can be arranged on or near the main upper surface of the semiconductor chip 4. Such a main surface may hereinafter be referred to as an active main surface. In an example, the electronic structure can be an electrical contact (or contact electrode or contact pad). In another example, the electronic structure can be an electronic component capable of generating electromagnetic radiation. For example, the antenna of a radar chip can transmit or receive electromagnetic waves in the above frequency range. Opposite to the active main surface of the semiconductor chip 4, the main surface without electronic structures can be referred to as an inaktive main surface. Thus, the inaktive main surface can be constituted only by the semiconductor material of the semiconductor chip 4 or, for example, a passivation layer arranged above it. Generally, the active main surface of a semiconductor chip is referred to as the front side of the semiconductor chip, and the inaktive main surface of the semiconductor chip is referred to as the back side. In the example of FIG. 1, the first main surface 6 can in particular be the active main surface of the semiconductor chip 4.

[0039] The sacrificial material 10 can be designed to be removed in a subsequent process (see Figure 1C ). In particular, the sacrificial material 10 can be any suitable etchable material. The sacrificial material 10 can include a semiconductor material that is the same as or different from the semiconductor material of the semiconductor chip 4. For example, the sacrificial material 10 can exist in the form of a silicon layer or a silicon wafer. In this case, etching of the sacrificial material 10 can be performed using a wet chemical agent, such as a caustic soda solution (KOH etching). In this case, for example, silicon oxide (SiO2) can be used as an etch stop layer (not shown). The sacrificial material 10 can include a glass material. For example, the sacrificial material 10 can exist in the form of a glass layer or a glass wafer. In this case, etching of the sacrificial material 10 can be performed using hydrofluoric acid (HF etching). Here, silicon nitride (SiN) can be used as an etch stop layer, for example. In another example, the sacrificial material 10 can include (in particular, etchable) plastic. In yet another example, the sacrificial material 10 can include (in particular, etchable) metal. As can be seen in Figure 1A , the sacrificial material 10 can extend over the base surface of the semiconductor chip 4 with a base surface, and the region extending laterally of the semiconductor chip 4 and below the sacrificial material 10 remains free of material.

[0040] In Figure 1B , at least one semiconductor component 2 is encapsulated using an encapsulation material 12. In Figure 1BIn an example, when encapsulating the semiconductor component 2, at least the sidewalls of the semiconductor component 2 or the sidewalls of the semiconductor chip 4 and the sidewalls of the sacrificial material 10 are covered by the encapsulating material 12. In an embodiment, all the sidewalls of the semiconductor chip 4 or all the sidewalls of the sacrificial material 10 may be covered by the encapsulating material 12. Here, the encapsulating material 12 can particularly contact the semiconductor component 2. In other words, the semiconductor component 2 can be embedded in the encapsulating material 12, and thus the encapsulating material can also be referred to as the embedding material. As can be seen in Figure 1B After the semiconductor component 2 is embedded, the main surface of the sacrificial material 10 can be exposed, that is, not covered by the material. In another example, additionally, the upper main surface of the sacrificial material 10 can be covered by and in contact with the encapsulating material 12. In this case, in a subsequent process (not shown), the encapsulating material 12 is partially removed to expose the upper main surface of the sacrificial material 10. For example, the encapsulating material 12 can be removed by grinding and / or chemical mechanical polishing (CMP) in this case. Additionally, in Figure 1B As can be seen, the encapsulating material 12 extends in a region on the side of the semiconductor chip 4 and under the sacrificial material 10, and this region is exposed before encapsulation as described in reference Figure 1A Therefore, the encapsulating material 12 connects the region of the main surface of the sacrificial material 10 to the side surface of the semiconductor chip 4.

[0041] Generally, the encapsulating material 12 can be any material used as an encapsulating material in the manufacture of semiconductor packages (or semiconductor housings or semiconductor chips with housings). In an example, the encapsulating material 12 can be a molding material, and the semiconductor component 2 can be embedded in the molding material, where at least the sides of the semiconductor component 2 can be covered by the molding material. The molding material or molding compound can be designed for applications in the scope of molding processes, such as: Compression Molding, Injection Molding, Powder Molding, Liquid Molding, etc. For example, the molding material can include at least one of the following materials: epoxy resin, filled epoxy resin, glass-filled epoxide, imide, thermoplastic, thermosetting polymer, polymer blend.

[0042] In another example, the encapsulation material 12 can be a glass material. The glass material can include, for example, one or more of the following substances: silicate glass, photosensitive glass, float glass, soda-lime glass, borosilicate glass, alkali-free glass, low-Tg glass, etc. The glass material can be heated above its glass transition temperature and thus transformed into a viscous state. Then, this or these semiconductor components 2 can be embedded in the liquid glass material, and afterwards the glass material can be cooled again below its glass transition temperature.

[0043] In Figure 1C , the sacrificial material 10 is removed, and in which above each of at least one semiconductor chip 4, recesses 14 are formed in the encapsulation material 12. In particular, the sacrificial material 10 can be removed by an etching process, as already combined Figure 1B described. The sacrificial material 10 can be removed in such a way that the material below the sacrificial material 10 is exposed. For example, an optional etch stop layer (not shown) or the opposite main surface 8 of the semiconductor chip 4 located below the sacrificial material 10 can be exposed. As can be seen in Figure 1C , the exposed surface can be partly constituted by the surface of the semiconductor chip 4 and partly by the surface of the encapsulation material 12. The geometry of the resulting recesses 14 can particularly depend on and correspond to the geometry of the sacrificial material 10. A possible shape of the recesses 14 is discussed in connection with FIG. 4. Since the active main surface 6 (as Figure 1C shown) is arranged on a side away from the sacrificial material, the etching process for removing the sacrificial material does not affect the active structure of the semiconductor chip 4.

[0044] In Figure 1D , at least one lid 16 is arranged above at least one recess 14, and in which a closed cavity is formed by at least one recess 14 and at least one lid 16, and at least one lid is located above each of at least one semiconductor chip 4. Depending on the function of the semiconductor device 100 to be manufactured, the lid 16 can be made of one of the following materials: molding material, metal, glass, semiconductor material, in particular silicon. The lid 16 can be connected to the encapsulation material 12. For example, the lid 16 can be glued to the encapsulation material 12.

[0045] In one example, the cavity 18 can be formed only by the recesses 14 and the lid 16. In another example, the cavity 18 can be formed by the recesses 14, the lid 16 and other components. In this case, the other components can particularly be arranged between the recesses 14 and the lid 16. In one example, the cavity 18 can be tightly sealed. In another example, the cavity 18 can include an opening (not shown). For example, in the case of a sensor chip, such an opening can provide a connection between the sensor chip and the environment outside the cavity 18 required for the function of the sensor chip.

[0046] In one example, the cavity 18 may contain air. In another example, the cavity 18 may contain a vacuum, especially in the case of a sensor chip with MEMS. In another example, the cavity 18 may contain a protective gas, a filling gas or a functional gas. In yet another example, the cavity 18 may be partially or completely filled with a liquid or solid material. The material filling the cavity 18 may in particular have good filling properties and / or a dielectric constant that is less than the dielectric constant of the semiconductor material of the semiconductor chip 4 and / or less than the dielectric constant of the encapsulation material 12.

[0047] Figure 2 includes Figure 2A and 2B , which schematically shows a cross-sectional side view and a top view of the semiconductor device 200 according to the present disclosure. The semiconductor device 200 is described in a general manner in order to qualitatively describe aspects of the present disclosure. The semiconductor device 200 may have other aspects which, for the sake of simplicity, are not shown in Figure 2. For example, the semiconductor device 200 may be extended to any aspect described in combination with other devices and methods according to the present disclosure.

[0048] The semiconductor device 200 includes a semiconductor chip 4 having a first main surface 6 and a second main surface 8 opposite the first main surface 6. The semiconductor device 200 further includes an encapsulation material 12, wherein the semiconductor chip 4 is encapsulated by the encapsulation material 12. The semiconductor device 200 further includes a recess 14 arranged in the encapsulation material 12, wherein the recess 14 is arranged above the opposite main surface 8 of the semiconductor chip 4. In the orthogonal projection onto the opposite main surface 8, the base surface of the recess 14 at least partially protrudes beyond the base surface of the semiconductor chip 4. The orthogonal projection may in particular be along Figure 2A the z-axis shown in.

[0049] In the example of Figure 2, the base surfaces of the semiconductor chip 4 and the recess 14 are shown rectangularly. In other examples, the base surfaces may also have other geometries. In particular, the base surface of the recess 14 does not necessarily have to be rectangular, but may have any other shape, such as circular, elliptical, triangular, etc. In the example of Figure 2, the base surface of the semiconductor chip 4 is completely contained within the base surface of the recess 14 (see Figure 2B ). That is, in the orthogonal projection, the base surface of the recess 14 protrudes beyond the base surface of the semiconductor chip 4 along its entire contour. In additional examples, the base surface of the recess 14 may also only partially protrude beyond the base surface of the semiconductor chip 4. In the case where the recess 14 has a rectangular base surface, the base surface of the semiconductor chip 4 may protrude beyond one side, two sides, three sides or four sides of the base surface of the semiconductor chip 4.

[0050] The semiconductor device 200 may also include a lid (not shown), wherein a closed cavity is formed by the recess 14 and the lid, for example as shown in Figure 1D . In the orthogonal projection onto the opposite main surface 8 of the semiconductor chip 4, the base surface of the cavity accordingly projects at least partially beyond the base surface of the semiconductor chip 4.

[0051] The material located in the cavity 18 (see Figure 1D ) or the recess 14 (see Figure 1C and 2A ), such as air, may have a lower dielectric constant than the encapsulation material 12 according to the present disclosure. Thereby, coupling between the encapsulation material 12 and the electromagnetic radiation can be prevented, and the electromagnetic radiation can be generated by the electronic structure of the semiconductor chip 4. For example, the semiconductor chip 4 may be a radar sensor chip, which has, for example, radio frequency leads to an antenna or the antenna itself on the active main surface. Since the coupling between the encapsulation material 12 and the electromagnetic radiation is reduced, the quality loss of the signals transmitted and received by the antenna can be offset. For example, if the base surface of the semiconductor chip 4 is completely contained in the base surface of the recess 14, the redistribution structure extending above the semiconductor chip 4 can also result in high-frequency electromagnetic signals with low coupling.

[0052] In addition to the reduced performance loss, the semiconductor device according to the present disclosure has a sufficiently large thickness or mechanical stability to withstand various mechanical forces and environment-determined forces. Such forces may occur, for example, during the encapsulation process, during other processing / handling processes (unit processing) of the semiconductor device, during the surface mounting of the semiconductor device, during the operation of the semiconductor device, and so on.

[0053] FIG. 3 includes Figures 3A to 3O , which schematically shows a cross-sectional side view and a top view of a semiconductor device 300 according to the present disclosure. The semiconductor device 300 is described in a general manner in order to qualitatively describe aspects of the present disclosure. The method of FIG. 3 can be considered a more detailed implementation of the method of FIG. 1. That is, the method shown in FIG. 1 can be extended to any aspect of the method of FIG. 3.

[0054] In Figure 3A , a plurality of semiconductor chips 4 may be arranged spaced apart from each other on a carrier 20. In the example of Figure 3A , three semiconductor chips 4 are shown. In other examples, the number of semiconductor chips 4 can be arbitrarily and differently selected. The semiconductor chips 4 each have a first main surface 6 and an opposite second main surface 8. In Figure 3AIn the example, the first main surface 6 can be on the active main surface of the semiconductor chip 4, on or in which the electronic structure 22 can be arranged. The semiconductor chip 4 can be placed on the carrier 20, for example, by means of a pick-and-place process. In order to fix the semiconductor chip 4 on the carrier 20, a double-sided adhesive film 24 can optionally be arranged between the semiconductor chip 4 and the carrier 20.

[0055] In Figure 3B it is possible to deposit an etch stop layer 26 on the semiconductor chip 4. In Figure 3B the example, the etch stop layer 26 covers the side surface and the opposite second main surface 8 of the semiconductor chip 4. In a further example, the etch stop layer 26 can be deposited at least partially on the carrier 20 and the adhesive film 24, respectively. The material of the etch stop layer 26 can depend in particular on the etching process subsequently selected for removing the sacrificial material. If the sacrificial material is silicon, the etching of the sacrificial material can be carried out using a caustic soda solution (KOH etching). In this case, the etch stop layer 26 can be composed of, for example, silicon oxide (SiO2) and can be deposited, for example, by plasma oxidation. The silicon oxide can be a thermal oxide, which can be deposited by thermal oxidation of silicon. In this regard, it should be noted that the deposition of the thermal oxide is possible and feasible if the oxidation is carried out before the semiconductor chip 4 is bonded to the carrier 20. The temperature of the thermal oxide can be higher than 700 °C, which can be a problem in the case of the carrier 20 with an adhesive connection. As an alternative to the above plasma oxidation, the etch stop layer 26 can also be deposited in the form of a CVD oxide. If the sacrificial material is a glass material, the etching of the sacrificial material can be carried out using hydrofluoric acid (HF etching). In this case, the etch stop layer 26 can be made of, for example, silicon nitride (SiN).

[0056] In Figure 3C it is provided with a sacrificial material 10 coated with a layer 28. The sacrificial material 10 can be, for example, one of the following materials: semiconductor material, especially silicon, glass material, plastic, metal. The layer 28 can be composed of the same material as the etch stop layer 26. In Figure 3C it is possible to invert the carrier 20 with the semiconductor chip 4 arranged thereon and connect it to the coated sacrificial material 10. In one example, both the etch stop layer 26 and the layer 28 can be composed of oxides and the connection can be formed by oxide-oxide bonding. In a further example, the connection between the sacrificial material 10 and the semiconductor chip 4 can be achieved by anodic bonding (for example, glass-silicon connection) or direct bonding (for example, silicon-silicon connection).

[0057] In Figure 3D

[0057] , the carrier 30 and the adhesive film 24 can be removed, and the sacrificial material 10 together with the semiconductor chips 4 arranged thereon can be disposed on the carrier 30. The sacrificial material 10 together with the semiconductor chips 4 arranged thereon can be separated into a plurality of semiconductor components 2. For this purpose, the sacrificial material 10 is removed or detached in the regions between the respective semiconductor chips 4. In this regard, for example, a plasma cutting process, a mechanical ultrasonic cutting process, and / or a laser cutting process can be applied. Each separated semiconductor component 2 has a semiconductor chip 4 with a part of the sacrificial material 10 as well as parts of the layers 26 and 28.

[0058] In Figure 3E

[0058] , a plurality of semiconductor components 2 can be arranged above the carrier 32. In the example of Figure 3E Figure 3E , three semiconductor components 2 are shown. In a further example, the number of semiconductor components 2 can be arbitrarily selected differently. The semiconductor components 2 can be arranged on the carrier 32 such that the main active surface 6 of the semiconductor chip 4 faces the carrier 32. The semiconductor components 2 can be placed on the carrier 20, for example, by means of a pick-and-place process. In order to fix the semiconductor components 2 to the carrier 32, a double-sided adhesive film 34 can optionally be arranged between the semiconductor components 2 and the carrier 32.

[0059] In Figure 3F

[0059] , the semiconductor components 2 can be encapsulated by an encapsulation material 12. In the example of Figure 3F Figure 3F , the semiconductor components 2 can be embedded, for example, in a molding material, wherein the sides and the upper main surface of the semiconductor components 2 can be covered by the molding material.

[0060] In Figure 3G

[0060] , the carrier 32 and the adhesive film 34 can be removed. After the removal, the active main surface 6 of the semiconductor chip 4 and the main surface 36 of the encapsulation material 12 can be particularly located in a common plane. Then, one or more redistribution layers 38 can be formed above the active main surface 6 of the semiconductor chip 4 and the main surface 36 of the encapsulation material 12. In the example of Figure 3G Figure 3G , a separate redistribution layer 38 is formed above each of the semiconductor components 2. In a further example, the redistribution layer 38 or its components can also extend above a plurality of semiconductor components 2.

[0061] The redistribution layer 38 may include one or more conductive paths 40 in the form of metal layers or metal tracks that can extend substantially parallel to the active main surface 6 of the semiconductor chip 4. The conductor paths 40 can fulfill a redistribution or reallocation function in order to electrically couple electrical contacts 44 provided on the redistribution layer 38 to the electronic structure 22 (such as electrical contacts) of the semiconductor chip 4. In other words, the conductor paths 40 are designed for using the electronic structure 22 and the contacts of the semiconductor chip 4 at other positions of the semiconductor device to be manufactured. Between the plurality of conductor paths 40, a plurality of dielectric layers 42 may be arranged in order to electrically insulate the conductor paths 40 from each other. In addition, metal layers arranged in different planes are electrically connected to each other by a plurality of metallization vias (or conductive vias Vias).

[0062] In Figure 3H , the encapsulation material 12 is at least partially removed above the opposite main surfaces 8 of the semiconductor chip 4 embedded in the encapsulation material 12. Here, the layer 28 and part of the sacrificial material 10 may additionally be removed. In this regard, for example, a grinding process and / or chemical mechanical polishing (CMP) may be applied. By removing the encapsulation material 12, the sacrificial material 10 can be at least partially exposed. In Figure 3H example, after removing the encapsulation material 12, the upper main surface of the sacrificial material 10 and the upper main surface of the encapsulation material 12 may be in a common plane.

[0063] In Figure 3I , the sacrificial material 10 may be at least partially removed, and recesses 14 may be formed in the encapsulation material 12 above the opposite main surfaces 8 of the semiconductor chip 4. For example, the sacrificial material 10 may be removed by an etching process that may be stopped by the etch stop layer 26. Here, the etch stop layer 26 may be at least partially exposed. In Figure 3I example, the sacrificial material 10 may be completely removed. In another example, a remaining portion of the sacrificial material 10 may remain above the main surface 8 of the semiconductor chip 4.

[0064] In Figure 3J , the etch stop layer 26 is at least partially removed above the opposite main surfaces 8 of the semiconductor chip 4, wherein the opposite main surfaces 8 of the semiconductor chip 4 are at least partially exposed. In Figure 3J example, the etch stop layer 26 may be completely removed above the opposite main surfaces 8 of the semiconductor chip 4. In another example, the remaining portion of the etch stop layer 26 may remain above the opposite main surfaces 8 of the semiconductor chip 4. In particular, a portion of the etch stop layer 26 may remain at the sidewalls of the semiconductor chip 4.

[0065] In Figure 3KIn this case, a connection material 46, such as an adhesive, can be deposited on the partial encapsulation material 12. For the deposition, for example, printing or dispensing processes can be used. In Figure 3K In the example of

[0066] In Figure 3L at least one lid 16 can be arranged above the recess. In Figure 3L In the example of Figure 3L a single lid 16 can be arranged above the recess 14. In a further example, a plurality of lids 16 can be arranged, where each lid 16 can cover any number of recesses 14. By means of the corresponding recesses 14 and lids 16, a closed cavity 18 can be formed above each of the semiconductor chips 4. The cavity 18 can be arranged here above the opposite main surfaces 8 of the respective semiconductor chips 4. In the orthogonal projection onto the opposite main surfaces 8, the base surface of the recess 14 or the cavity 18 at least partially projects beyond the base surface of the semiconductor chip 4, as already discussed in connection with FIG. 2. In Figure 3L the example of Figure 2B the base surfaces of the semiconductor chip 4 and the cavity 18 can be formed as shown in

[0067] In Figure 3L the example of

[0068] In Figure 3M the lid 16 can be fixed to the encapsulation material 12 via the connection material 46. In a further example, the lid 16 and the encapsulation material 12 can be interconnected in other suitable ways. The lid 16 can be made of one of the following materials depending on the function of the semiconductor device to be manufactured: molding material, metal, glass, semiconductor material, in particular silicon.

[0068] In Figure 3M external electrical contact elements 48 can be arranged on the electrical contacts 44 of the redistribution layer 38. The contact elements 48 can be, for example, solder balls or solder deposits (Lotdepots). Thus, the respective semiconductor chips 4 can be externally electrically contacted via the contact elements 48, the electrical contacts 44 and the redistribution layer 38 from the outside of the encapsulation material 12.

[0069] In Figure 3N the arrangement of Figure 3M can be arranged on a carrier 50. The semiconductor assembly 2 embedded in the encapsulation material 12 can be separated into a plurality of semiconductor packages 52. In this case, for example, plasma cutting processes, mechanical ultrasonic cutting processes and / or laser cutting processes can be used.

[0070] In Figure 3OIn [description], the fabricated semiconductor device 300 is shown in the form of a semiconductor package 52. The semiconductor package 52 can in particular be a fan-out wafer-level package, in which the external electrical contact elements 48 are fanned out compared to the electronic structure 22 of the semiconductor chip 4 due to the use of the redistribution layer 38.

[0071] FIG. 4 includes Figures 4A to 4H , which schematically shows a cross-sectional side view and a top view of a semiconductor device 400 according to the present disclosure. The method of FIG. 4 can be considered a more detailed implementation of the method of FIG. 1. That is, the method described in FIG. 1 can be extended to any aspect of the method of FIG. 4.

[0072] In Figure 4A , a plurality of semiconductor chips 4 can be arranged on a carrier 20, where the semiconductor chips 4 with the first active main surface 6 can face the carrier 20. In Figure 4A example, the semiconductor chips 4 can be placed individually on the carrier 20. In another example, a semiconductor wafer including a plurality of semiconductor chips 4 can be arranged on the carrier 20 and subsequently separated into a plurality of semiconductor chips 4. In addition, the semiconductor chips 4 or the semiconductor wafer on the carrier 20 can be thinned, which is achieved by removing material from the second main surface 8 of the semiconductor chip 4. In connection with the mentioned method, for example, the DBG (Dicing-Before-Grinding) technique can be applied.

[0073] In Figure 4B , the carrier 20 can be removed, and the semiconductor chips 4 can be arranged on a sacrificial material 10. In Figure 4B example, the active main surface 6 of the semiconductor chip 4 can face away from the sacrificial material 10 here. An optional adhesive layer 54 and an etch stop layer 26 can be arranged between the semiconductor chip 4 and the sacrificial material 10. The sacrificial material 10 together with the semiconductor chips 4 arranged thereon can be arranged on another carrier 56 and separated by an appropriate cutting process (not shown).

[0074] In Figure 4C , the separated semiconductor assemblies 2 can be arranged on a carrier 32, where the active main surface 6 of the semiconductor chip 4 can face the carrier 32. The carrier 32 can in particular be a metal carrier. In a further process, the semiconductor assemblies 2 can be encapsulated by an encapsulation material 12.

[0075] In Figure 4D , the carrier 32 can be removed, and one or more redistribution layers 38 are made above the active main surface 6 of the semiconductor chip 4. Figure 4D The process of can at least partially correspond to Figure 3G the process of .

[0076] AttachedFigures 4E to 4H The process shown can be at least partially similar to Figures 3H to 3O the process. For simplicity, the description of FIG. 3 is referred to herein. In Figure 4G the process, the lid 16 can additionally be thinned by a grinding process.

[0077] FIG. 5 includes Figures 5A to 5I , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 500 according to the present disclosure. The method of FIG. 5 can be considered a more detailed implementation of the method of FIG. 1. That is, any aspect of the method described in FIG. 1 can be extended to the method of FIG. 5.

[0078] Figures 5A to 5I The process shown can be at least partially similar to Figures 3A to 3O the process. For simplicity, the description of FIG. 3 is referred to herein. Similar to Figure 3O the semiconductor device 300, Figure 5I the semiconductor device 500 can have a cavity 18 above the opposing main surfaces 8 of the semiconductor chip 4. Contrary to Figure 3O , for Figure 5I the semiconductor device 500, in the orthogonal projection onto the opposing main surfaces 8 of the semiconductor chip 4, the base surface of the recess 14 or the cavity 18 does not substantially protrude beyond the base surface of the semiconductor chip 4. Specifically, in Figure 5I the example, the base surfaces of the cavity 18 and the semiconductor chip 4 can be substantially congruent. A slight deviation between the base surfaces can be caused by an optional remaining portion of the etch stop layer 26 remaining at the sidewalls of the semiconductor chip 4, if such a remaining portion should still be present in the manufactured semiconductor device 500.

[0079] Figure 6 Schematically shows a cross-sectional side view of a semiconductor device 600 according to the present disclosure. For example, the semiconductor device 600 can be manufactured in accordance with one of the above methods according to the present disclosure.

[0080] The semiconductor device 600 may include a semiconductor chip 4 having a first major surface 6 and a second major surface 8 opposite to the first major surface 6. The semiconductor chip 4 may be encapsulated by an encapsulation material 12. A cavity 18 may be formed on the opposite major surfaces 8 of the semiconductor chip 4 by the encapsulation material 12 and a lid 16. Here, the lid 16 may be fixed to the encapsulation material 12 by an optional connecting material 46. The electronic structure 22 (such as an electrical contact or an antenna of the semiconductor chip 4) of the semiconductor chip 4 may be electrically connected to an external electrical contact element 48 via a redistribution layer 38. A remaining portion of the etch stop layer 26 may be present on the side surfaces and a part of the opposite major surface 8 of the semiconductor chip 4. In an orthogonal projection onto the opposite major surface 8, the base surface of the cavity 18 may be entirely within the base surface of the semiconductor chip 4. That is, in the orthogonal projection, the base surface of the cavity 18 does not extend beyond the base surface of the semiconductor chip 4 here.

[0081] Figure 7 A cross-sectional side view of a semiconductor device 700 according to the present disclosure is schematically shown. For example, the semiconductor device 700 may be manufactured in accordance with one of the above-described methods according to the present disclosure.

[0082] The semiconductor device 700 may be, for example, similar to Figure 3O the semiconductor device 300 and have corresponding components. In addition, the semiconductor device 700 may have one or more recesses 58 that are formed in the semiconductor material of the semiconductor chip 4 in the opposite major surfaces 8 of the semiconductor chip 4. For example, in the manufacturing method of FIG. 3, the recesses 58 may be formed before or during the process of Figure 3A , that is, before the etch stop layer 26 is deposited on the semiconductor chip 4. The recesses 58 may be formed, for example, in the semiconductor material by using a suitable etching method in the case of applying an etch mask. The recesses 58 may have any base surface and the same or different depths. Similar to the cavity 18, the recesses 58 can prevent coupling between the semiconductor material of the semiconductor chip 4 and electromagnetic radiation that can be generated or received by the electronic structure of the semiconductor chip 4.

[0083] Figure 8 A flowchart showing a method for manufacturing a semiconductor device according to the present disclosure is shown. Figure 8 The method of may be similar to the method of FIG. 1 and is to be read in conjunction with Figures 1A to 1D reading.

[0084] At 70, provide at least one semiconductor component (see Figure 1A)。Each of the at least one semiconductor component includes a semiconductor chip, where the semiconductor chip includes a first major surface and a second major surface opposite to the first major surface. Each of the at least one semiconductor component further includes a sacrificial material disposed above the opposite second major surface of the semiconductor chip. At 72, the at least one semiconductor component is encapsulated with an encapsulating material (see Figure 1B ). At 74, the sacrificial material is removed, where a recess is formed in the encapsulating material above each of the at least one semiconductor chip (see Figure 1C ). At 76, at least one lid is disposed above the at least one recess, where a closed cavity is formed above each of the at least one semiconductor chip through the at least one recess and the at least one lid (see Figure 1D ).

[0085] Figure 9 includes Figure 9A and 9B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 900 according to the present disclosure. The semiconductor device 900 can be at least partially similar to the semiconductor devices previously described according to the present disclosure.

[0086] The semiconductor device 900 can have a semiconductor chip 4, which has a first major surface 6 and a second major surface 8 opposite to the first major surface 6. The semiconductor chip 4 can be at least partially encapsulated with an encapsulating material 12. A recess 14 can be disposed in the encapsulating material 12, where the recess 14 is disposed above the opposite major surface 8 of the semiconductor chip 4. The recess 14 can in particular form a closed cavity, for example with air in the cavity. The recess 14 is shown as a shaded area in the Figure 9B top view.

[0087] The semiconductor device 900 can have electrical contact elements 48, which can be disposed on the lower major surface of the semiconductor chip 4 and / or the encapsulating material 12. In the Figure 9A cross-sectional side view, only a few electrical contact elements 48 are described qualitatively, while the Figure 9B top view shows a more detailed arrangement of the electrical contact elements 48 in the form of small empty circles. The electrical contact elements 48 can have one or more transmitting (TX) high-frequency interfaces 48A, which can be designed to provide high-frequency transmission signals generated by the semiconductor chip 4. In addition, the electrical contact elements 48 can include one or more receiving (RX) high-frequency interfaces 48B, which can be designed to receive high-frequency reception signals and transmit them to the semiconductor chip 4.

[0088] In the example of Figure 9, three TX high-frequency interfaces 48A and four RX high-frequency interfaces 48B are shown. In other examples, the number of these interfaces can be arbitrarily different from this. From Figure 9BAs can be seen in the top view, the TX high-frequency interface 48A and the RX high-frequency interface 48B can be arranged above the lower main surface of the encapsulation material 12. In another example, the interfaces 48A and 48B can also be at least partially arranged above the lower main surface of the semiconductor chip 4. The electrical contact element 48 can have an additional interface 48C, for example, a signal interface for analog and digital signals, a ground connection, etc.

[0089] The device 900 can have a thermal contact element 60, which can be designed to conduct heat away from the semiconductor device 900, for example, in the direction of a circuit board on which the semiconductor device 900 can be arranged. The thermal contact element 60 can be, for example, a so-called "thermo ball". In Figure 9B it, the thermal contact element 60 is represented by small dotted circles.

[0090] As discussed in connection with the foregoing examples, the semiconductor chip 4 can be a radio frequency chip. That is, the semiconductor chip 4 can have one or more regions in which high-frequency signals are processed or transmitted. Such a region of the semiconductor chip 4 can have, for example, at least one of a high-frequency interface, high-frequency conductors, or an oscillator circuit. In a similar manner, the encapsulation material 12 can have one or more regions in which high-frequency signals are processed or transmitted. For example, such a region of the encapsulation material 12 can have at least one of a high-frequency interface or high-frequency conductors. In a projection perpendicular to the first main surface 6 of the semiconductor chip 4 (with reference to the Z-axis), the base surface of the recess 14 can be arranged above one or more of the aforementioned regions of the semiconductor chip 4 and / or the encapsulation material 12 in which high-frequency signals are processed or transmitted.

[0091] In the example of FIG. 9, the base surface of the recess 14 can at least partially extend beyond the base surface of the semiconductor chip 4 in the projection. From Figure 9B the top view, it can be seen that the base surface of the semiconductor chip 4 can particularly be completely within the base surface of the recess 14. The recess 14 can be arranged above the TX high-frequency interface 48A and the RX high-frequency interface 48B. The material located in the recess 14, such as air, can have a smaller dielectric constant than the material of the encapsulation material 12 and / or the semiconductor chip 4. Thereby, coupling between these materials and the electromagnetic radiation that can be generated by the electronic structure of the semiconductor chip 4 can be prevented. In particular, the material in the recess 14 can be arranged between the TX high-frequency interface 48A and the RX high-frequency interface 48B. Thereby, coupling between the (especially side-by-side arranged) TX and RX channels can be prevented or at least reduced. The isolation achieved between the side-by-side arranged TX and RX channels of different semiconductor devices is in Figure 13Shown and discussed in. The TX or RX channel may include a TX or RX high-frequency interface 48A and a high-frequency wire electrically connected thereto, the high-frequency wire extending, for example, on the lower main surface of the encapsulation material 12.

[0092] FIG. 10 includes Figure 10A and 10B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 1000 according to the present disclosure. For example, the semiconductor device 1000 may be similar to the semiconductor device 900 of FIG. 9 and have corresponding components.

[0093] Comparing with FIG. 9, the semiconductor device 1000 of FIG. 10 has a recess 14 with a smaller area (refer to Figure 9B and Figure 10B ). It can be seen from Figure 10B that the base surface of the recess 14 can be completely arranged inside the base surface of the semiconductor chip 4. For example, the recess 14 may be arranged above the oscillator circuit of the semiconductor chip 4, and the oscillator circuit may be specifically designed to provide high-frequency signals. Compared with the semiconductor device 900 of FIG. 9, due to the smaller recess 14, the semiconductor device 1000 may have reduced isolation but improved mechanical stability.

[0094] FIG. 11 includes Figure 11A and 11B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 1100 according to the present disclosure. For example, the semiconductor device 1100 may be similar to the semiconductor device 900 of FIG. 9 and have corresponding components.

[0095] Same as FIG. 9, the recess 14 may be arranged above the RX high-frequency interface 48B, while the TX high-frequency interface 48A remains uncovered by the recess 14. By this arrangement of the recess 14, the TX and RX channels arranged side by side can be separated from each other. In Figure 11B 's top view, the recess 14 may be formed in a U shape, so that a larger area above the semiconductor chip 4 is not covered by the recess 14 compared with FIG. 9. The semiconductor device 1100 can thus be provided with isolation between the TX and RX channels arranged side by side on the one hand and have good mechanical stability on the other hand.

[0096] FIG. 12 includes Figure 12A and 12B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 1200 according to the present disclosure. For example, the semiconductor device 1200 may be similar to the semiconductor device 900 of FIG. 9 and have corresponding components.

[0097] The recess 14 in FIG. 12 can be regarded as a combination of the recesses 14 in FIGS. 10 and 11. That is, with this arrangement of the recess 14, the TX and RX channels arranged side by side can be separated from each other, and also a part of the recess 14 can be arranged, for example, above the oscillator circuit in the inner region of the semiconductor chip 4.

[0098] Figure 13 There is shown a graph in which the isolation quality between a transmitting channel and an adjacent receiving channel, or between a TX high-frequency interface and an adjacent RX high-frequency interface, for different semiconductor devices is shown. For example, adjacent TX and RX channels are shown in FIGS. 9 to 11. In Figure 13 , the isolation between the channels is represented by bars, where the height of the bar corresponds to the unit of the isolation measure [-dB]. This means that the higher the bar, the better the isolation between the channels.

[0099] Bar “A” represents a semiconductor device that includes a semiconductor chip with a thickness of about 450 microns and a backside protection (BSP) with a thickness of about 25 microns. The height of bar “A” indicates a reference value for the isolation between the channels. The reference value is represented by a horizontal dashed line. Bar “B” represents a semiconductor device that includes a semiconductor chip with a thickness of about 100 microns and a mold cap with a thickness of about 375 microns. Bar “C” represents a semiconductor device that includes a semiconductor chip with a thickness of about 200 microns and a mold cap with a thickness of about 275 microns. Bar “D” represents a semiconductor device that includes a semiconductor chip with a thickness of about 100 microns and small recesses or small cavities in the encapsulation material (see, for example, FIG. 10). Bar “E” represents a semiconductor device that includes a semiconductor chip with a thickness of about 100 microns and large recesses or large cavities in the encapsulation material (see, for example, FIG. 9).

[0100] From Figure 13 the graph, it can be seen that the heights of bars “D” and “E” are above the reference value of bar “A”. The semiconductor devices belonging to bars “D” and “E” thus provide the best isolation between the TX and RX channels arranged side by side.

[0101] FIG. 14 includes Figure 14A and 14B , which schematically shows a cross-sectional side view and a top view of a semiconductor device 1400 according to the present disclosure. Figure 14A The cross-sectional side view of Figure 14B is based on the cross-section along section “A” and the viewing direction along the y-axis. Section “A” is indicated by a dashed line in the Figure 14B top view of

[0102] The semiconductor device 1400 may be one or more openings 64 formed in the encapsulation material 12. In the example of FIG. 14, one or more openings 64 may be formed in one or more sidewalls of the encapsulation material 12. Alternatively or additionally thereto, one or more of the openings 64 may be formed in the upper main surface of the encapsulation material 12. In the example of FIG. 14, the semiconductor device 1400 has an opening 64 at each TX and RX channel or at each TX and RX high-frequency interface. In another example, the openings may be located only at some channels. In yet another example, additional openings may be formed in addition to the openings shown.

[0103] Furthermore, the opening 64 may be designed to provide air exchange with the recess 14. More specifically, air exchange is performed between the recess 14 and the atmosphere surrounding the semiconductor device 1400 through the opening. By the air exchange with the recess 14, an excessive humidity value of the air located in the recess 14 can be prevented. In contrast, the air enclosed in the (hermetically) sealed recess 14 condenses when the humidity is too high, which can lead to an increase in damage to the components of the semiconductor device 1400.

[0104] In Figure 14B a top view, the opening 64 may be arranged in a region for transmitting high-frequency signals. Specifically, the opening 64 may be arranged above at least one of the high-frequency wires and / or high-frequency interfaces. Since the dielectric constant of the air located in the opening 64 is low, coupling of the high-frequency signals to be transmitted into the encapsulation material 12 and crosstalk between adjacent channels can be prevented or at least reduced.

[0105] In addition to the above, the semiconductor device 1400 may have a support structure 62 for mechanical stabilization of the semiconductor device 1400. For example, the support structure 62 may be formed by a part of the encapsulation material 12.

[0106] FIG. 15 includes Figure 15A and 15B which schematically shows a cross-sectional side view and a top view of a semiconductor device 1500 according to the present disclosure. The semiconductor device 1500 may be at least partially similar to the previously described semiconductor device according to the present disclosure.

[0107] The semiconductor device 1500 may have a semiconductor chip 4 having a first major surface 6 and a second major surface 8 opposite to the first major surface 6. The semiconductor chip 4 may be at least partially encapsulated by an encapsulation material 12. In the example of FIG. 15, the encapsulation material 12 may cover the side surfaces of the semiconductor chip 4. In another example, the encapsulation material 12 may additionally be at least partially disposed on the top side of the semiconductor chip 4. The semiconductor device 1500 may further have a material 66 disposed above the opposite major surfaces 8 of the semiconductor chip 4. In a projection perpendicular to the first major surface 6 of the semiconductor chip 4, at least one high-frequency region of the material 66 and the semiconductor chip 4 and / or the encapsulation material 12 do not overlap, in which high-frequency signals are processed or transmitted. In other words, the material 66 is particularly disposed above the region of the semiconductor chip 4 and / or the encapsulation material 12 in which high-frequency signal transmission and / or processing do not occur.

[0108] The thickness of the semiconductor device 1500 may be increased by the material 66 formed in the corresponding regions. Thus, improved mechanical stability of the semiconductor device 1500 can be achieved. Furthermore, coupling between particularly side-by-side high-frequency regions of the semiconductor chip 4 and / or the encapsulation material 12 can be prevented or at least reduced by appropriately selecting the regions without the material 66. In a projection onto the major surface of the semiconductor chip 4, the region without the material 66 is disposed between two high-frequency regions of the semiconductor chip 4 and / or the encapsulation material 12. For example, such a region may be disposed between two high-frequency channels and is designed to reduce crosstalk between the channels.

[0109] The material 66 may include or be made of at least one of the following materials: molding material, glass material, ceramic material, semiconductor material, metal, or metal alloy. The material 66 made of metal or a metal alloy may be particularly designed to provide heat dissipation of the semiconductor device 1500 through its top surface. The material 66 and the encapsulation material 12 may be made of the same material or different materials.

[0110] The semiconductor device 1500 may particularly not have a cavity in which air with too high humidity may be trapped. Thus, condensation and the increasing damage that may be caused thereby to the components of the semiconductor device 1500 can be avoided.

[0111] Figures 16 to 20 A schematic top view according to the present disclosure is shown. The semiconductor devices 1600 to 2000 may be at least partially similar to the semiconductor device 1500 of FIG. 15 and have the same components. Figures 16 to 20 Exemplarily and qualitatively, it shows how the material 66 is arranged.

[0112] In Figure 16In a top view, the material 66 may substantially have a cross shape, where the corners of the semiconductor device 1600 may remain uncovered by the material 66. Regions without the material 66 may be respectively arranged between adjacent high-frequency wires or high-frequency channels (see the arrangement of the TX and RX channels in FIG. 14 for this), and are designed to reduce crosstalk between them.

[0113] In Figure 17 's top view, the material 66 may substantially have a diamond shape, where the corners of the semiconductor device 1700 may remain uncovered by the material 66. Similar to Figure 16 , regions without the material 66 may be respectively arranged between adjacent high-frequency wires or high-frequency channels (see the arrangement of the TX and RX channels in FIG. 14 for this).

[0114] In Figure 18 's top view, the material 66 may be substantially X-shaped, where the corners of the semiconductor device 1800 may remain uncovered by the material 66. Similar to Figure 16 , regions without the material 66 may be respectively arranged between adjacent high-frequency wires or high-frequency channels (see the arrangement of the TX and RX channels in FIG. 14 for this).

[0115] In Figure 19 's top view, the material 66 may have a rectangular frame structure along the edge of the semiconductor device 1900. In the middle region, the semiconductor device 1900 may have a support structure 62, as discussed in connection with FIG. 14. In particular, the mechanical stability of the semiconductor device 1900 may be provided by the support structure 62 and the material 66.

[0116] In Figure 20 's top view, regions without the material 66 may be arranged above the high-frequency wires or high-frequency channels of the semiconductor device 2000 (see the arrangement of the TX and RX channels in FIG. 14 for this). The semiconductor device 2000 may additionally have a support structure 62.

[0117] FIG. 21 includes Figure 21A and 21B , which schematically shows a cross-sectional side view of a method for manufacturing a semiconductor device 2100 according to the present disclosure.

[0118] In Figure 21A , an intermediate product that may have been manufactured through the foregoing method steps is provided. For simplicity, these method steps are not shown in FIG. 21. The intermediate product may have a semiconductor chip 4, which may be at least partially encapsulated by an encapsulation material 12. A chip interface (not shown) disposed on the bottom side of the semiconductor chip 4 may be electrically coupled to an electrical contact element 48 of the intermediate product via a redistribution layer (not shown).

[0119] In Figure 21B there is formed one or more recesses 14 on the top surface of the encapsulation material 12. In Figure 21B example, the encapsulation material 12 can be removed by applying a laser, thereby forming the recess 14. Alternatively or additionally thereto, the recess 14 can be formed by an etching process. The recess 14 can have any depth. In particular, the recess 14 can extend from the top side of the encapsulation material 12 to the top side of the semiconductor chip 4. As already discussed in the previous example, the recess 14 can be arranged such that the coupling between the electromagnetic radiation of the encapsulation material 12 and the semiconductor chip 4 is prevented. In addition, the coupling between, in particular, the TX and RX channels arranged side by side can be prevented or at least reduced.

[0120] Figures 22 to 24 A top view of semiconductor devices 2200 to 2400 according to the present disclosure is shown. An exemplary arrangement of the recess 14 is shown in the top view, as it can be manufactured, for example, by the method of FIG. 21.

[0121] Figure 22 The top view of

[0122] Figure 23 shows the semiconductor device 2200, which can be particularly similar to the semiconductor device 2100 of FIG. 21. The recess 14 can have a rectangular frame structure along the edge of the semiconductor chip 4. Here, the recess 14 can in particular be arranged above these high-frequency interfaces and / or high-frequency conductors arranged in this edge region. Figure 20 The semiconductor device 2300 of

[0123] In Figure 24 the top view can be particularly similar to the semiconductor device 2000 of

[0124] Example

[0125] The recess 14 can in particular be arranged above the high-frequency conductors or high-frequency channels of the semiconductor device 2300 (see the arrangement of the TX and RX channels in FIG. 14 for this).

[0126] Example 1 is a method, comprising: providing at least one semiconductor component, wherein each semiconductor component of the at least one semiconductor component comprises: a semiconductor chip having a first major surface and a second major surface opposite to the first major surface on the semiconductor chip, and a sacrificial material disposed above the opposite second major surface of the semiconductor chip; encapsulating the at least one semiconductor component with an encapsulation material; removing the sacrificial material, wherein a recess is formed in the encapsulation material above each semiconductor chip of the at least one semiconductor chip; and disposing at least one lid above the at least one recess, wherein a closed cavity is formed above each semiconductor chip of the at least one semiconductor chip through the at least one recess and the at least one lid.

[0127] Example 2 is the method according to Example 1, wherein the cavity is disposed above the opposite major surfaces of the respective semiconductor chips, and wherein in an orthogonal projection onto the opposite major surfaces, the base plane of the sacrificial material and the base plane of the recess at least partially extend beyond the base plane of the semiconductor chip.

[0128] Example 3 is the method according to Example 1 or 2, wherein providing at least one semiconductor component comprises disposing an etch stop layer between the at least one semiconductor chip and the sacrificial material, and wherein removing the sacrificial material comprises etching the sacrificial material, wherein the etch stop layer is exposed.

[0129] Example 4 is the method according to Example 3, further comprising: after removing the sacrificial material, removing the etch stop layer, wherein the opposite major surfaces of the at least one semiconductor chip are exposed.

[0130] Example 5 is the method according to any one of the foregoing examples, further comprising: before removing the sacrificial material, removing the encapsulation material above the opposite major surfaces of the at least one semiconductor chip embedded in the encapsulation material, wherein the sacrificial material is exposed.

[0131] Example 6 is the method according to any one of the foregoing examples, wherein, after encapsulating the at least one semiconductor component, the major surface of the encapsulation material and the first major surface of the at least one semiconductor chip are in a common plane.

[0132] Example 7 is the method according to Example 6, further comprising: forming a redistribution layer above the first major surface of the at least one semiconductor chip and the major surface of the encapsulation material.

[0133] Example 8 is the method according to any one of the foregoing examples, further comprising: after disposing at least one lid above the at least one recess, separating the at least one semiconductor component encapsulated with the encapsulation material into at least one semiconductor package, wherein each semiconductor package of the at least one semiconductor package comprises one of the cavities.

[0134] Example 9 is a method according to any of the foregoing examples, wherein the first major surface of the semiconductor chip is the active major surface of the semiconductor chip.

[0135] Example 10 is a method according to any of the foregoing examples, wherein the sacrificial material comprises a semiconductor material or a glass material.

[0136] Example 11 is a method according to any of the foregoing examples, further comprising: forming at least one recess in the semiconductor material of at least one semiconductor chip in at least one of the opposed major surfaces of the at least one semiconductor chip before providing at least one semiconductor component.

[0137] Example 12 is a method according to any of the foregoing examples, wherein providing at least one semiconductor component comprises: arranging at least one semiconductor chip on a first carrier, wherein the first major surface of at least one semiconductor chip face faces the first carrier; arranging an etch stop layer on the opposed major surfaces of the at least one semiconductor chip; arranging a sacrificial material above the etch stop layer; separating the at least one semiconductor chip, the etch stop layer, and the sacrificial material into at least one semiconductor component; and arranging the at least one semiconductor component above a second carrier, wherein the first major surface of the at least one semiconductor chip faces the second carrier.

[0138] Example 13 is a method according to Examples 1 to 11, wherein providing at least one semiconductor component comprises: arranging at least one semiconductor chip above a sacrificial material, wherein the opposed major surfaces of the at least one semiconductor chip face the sacrificial material, wherein an etch stop layer is arranged between the at least one semiconductor chip and the sacrificial material; and separating the sacrificial material together with the at least one semiconductor chip arranged thereon into at least one semiconductor component; and arranging the at least one semiconductor component on a second carrier, wherein the first major surface of the at least one semiconductor chip faces the second carrier.

[0139] Example 14 is a device comprising: a semiconductor chip comprising a first major surface and a second major surface opposed to the first major surface; an encapsulating material, wherein the semiconductor chip is encapsulated by the encapsulating material; and a recess arranged in the encapsulating material, wherein the recess is arranged above the opposed major surfaces of the semiconductor chip, wherein in an orthogonal projection onto the opposed major surfaces, a base surface of the recess at least partially extends beyond a base surface of the semiconductor chip.

[0140] Example 15 is a device according to Example 14, further comprising: a cover arranged above the recess, wherein a closed cavity is formed above the opposed major surfaces of the semiconductor chip through the recess and the cover.

[0141] Example 16 is a device according to Example 14 or 15, wherein the first major surface of the semiconductor chip is the active major surface of the semiconductor chip.

[0142] Example 17 is a device according to any one of Examples 14 to 16, wherein the semiconductor chip includes an integrated high-frequency circuit designed to operate at a frequency greater than 10 GHz.

[0143] Example 18 is a device according to any one of Examples 14 to 17, wherein the lid is made of a molded material and connected to the encapsulating material.

[0144] Example 19 is a device according to any one of Examples 14 to 18, wherein the opposite main surfaces of the semiconductor chip are not covered by the encapsulating material.

[0145] Example 20 is a device according to any one of Examples 14 to 19, further comprising: an etch stop layer disposed between the end side of the semiconductor chip and the encapsulating material.

[0146] Example 21 is a device according to any one of Examples 14 to 20, further comprising: recesses formed in the semiconductor material of the semiconductor chip in the opposite main surfaces of the semiconductor chip.

[0147] Example 22 is a method comprising: providing at least one semiconductor component, wherein each semiconductor element of the at least one semiconductor element includes: a semiconductor chip including a first main surface and a second main surface opposite the first main surface, and a sacrificial material disposed above the opposite second main surfaces of the semiconductor chip; encapsulating the at least one semiconductor component with an encapsulating material; and removing the sacrificial material, wherein recesses are formed in the encapsulating material above each semiconductor chip of the at least one semiconductor chip, wherein the recesses are disposed above the opposite second main surfaces of the respective semiconductor chips, and in an orthogonal projection onto the opposite main surfaces, the base plane of the recesses at least partially protrudes beyond the base plane of the semiconductor chip.

[0148] Example 23 is a device comprising: a semiconductor chip including a first main surface and a second main surface opposite the first main surface; an encapsulating material, wherein the semiconductor chip is encapsulated by the encapsulating material; recesses disposed in the encapsulating material, wherein the recesses are disposed above the opposite main surfaces of the semiconductor chip; a lid disposed above the recesses, wherein a closed cavity is formed on the opposite main surfaces of the semiconductor chip through the recesses and the lid.

[0149] Example 24 is a device comprising: a semiconductor chip including a first major surface and a second major surface opposite the first major surface; an encapsulation material, wherein the semiconductor chip is at least partially encapsulated by the encapsulation material; and a recess disposed in the encapsulation material, wherein the recess is disposed above the opposite major surfaces of the semiconductor chip, and wherein in a projection perpendicular to the first major surface of the semiconductor chip, a base surface of the recess is disposed above a region of the semiconductor chip and / or the encapsulation material in which high-frequency signals are processed or transmitted.

[0150] Example 25 is the device according to Example 24, wherein in the projection, the base surface of the recess extends beyond the base surface of the semiconductor chip.

[0151] Example 26 is the device according to Example 24, wherein in the projection, the base surface of the recess is entirely disposed within the base surface of the semiconductor chip.

[0152] Example 27 is the device according to any one of Examples 24 to 26, wherein in the projection, the base surface of the recess is disposed above at least one of the following components: a high-frequency interface, a high-frequency conductor, or an oscillation circuit.

[0153] Example 28 is the device according to any one of Examples 24 to 27, further comprising: at least one opening formed in the encapsulation material, the opening being designed to provide air exchange with the recess.

[0154] Example 29 is the device according to Example 28, wherein the opening is formed in a sidewall of the encapsulation material that is not parallel to the first major surface of the semiconductor chip.

[0155] Example 30 is the device according to Example 28 or 29, wherein in the projection, the opening is disposed above at least one of the high-frequency conductor or the high-frequency interface.

[0156] Example 31 is a device comprising: a semiconductor chip including a first major surface and a second major surface opposite the first major surface; an encapsulation material, wherein the semiconductor chip is encapsulated by the encapsulation material; and a material disposed above the opposite major surfaces of the semiconductor chip material, wherein in a projection perpendicular to the first major surface of the semiconductor chip, the material does not overlap with at least one high-frequency region of the semiconductor chip and / or the encapsulation material in which high-frequency signals are processed or transmitted.

[0157] Example 32 is the device according to Example 31, wherein in the projection, a region without the material is disposed between two high-frequency regions of the semiconductor chip and / or the encapsulation material.

[0158] Example 33 is the device according to Example 32, wherein the exposed region is designed to reduce crosstalk between two high-frequency conductors.

[0159] Example 34 is a device according to any one of Examples 31 to 33, wherein the material comprises at least one of the following materials: a molding material, a glass material, a ceramic material, a semiconductor material, a metal, or a metal alloy.

[0160] As used herein, the terms "connected", "coupled", "electrically connected", and / or "electrically coupled" do not necessarily mean that the components must be directly connected or coupled. There may be intermediate components between the components that are "connected", "coupled", "electrically connected", or "electrically coupled".

[0161] In addition, the term "above" as used, for example, with reference to an entity surface that is formed "above" or located "above" a face of an object may be used in this specification in the sense that the entity surface is "directly" disposed (e.g., formed, deposited, etc.) "on" the indicated face, e.g., in direct contact therewith. The term "above" as used, for example, with reference to an entity surface that is formed or disposed "above" a face may be used herein in the sense that the entity surface is "directly" disposed (e.g., formed, deposited, etc.) "on" the indicated face, where there is one or more additional layers between the indicated surface and the entity layer.

[0162] Whenever the terms "have", "comprise", "include", "with", or variants thereof are used in a particular specification or claim, these terms should be similar to the term "comprising". That is, in the sense of this specification, the terms "have", "comprise", "include", "with", "comprising", etc. are open-ended terms that indicate the presence of the element or feature, without excluding other elements or features. Unless the context clearly indicates a different understanding, the article "a" or "the" should be understood to include both plural and singular meanings.

[0163] In addition, the term "exemplary" as used herein is used in the sense that the term is used as an example, instance, or illustration. An aspect or design described as "exemplary" herein is not necessarily to be understood as having an advantage over other aspects or designs. Instead, the use of the term "exemplary" is intended to represent a concept in a concrete manner. For the purposes of this application, the term "or" does not mean an exclusive "or" but an inclusive "or". That is, unless otherwise stated or the context does not permit another interpretation, "X uses A or B" means any natural inclusive arrangement. That is, if X uses A, X uses B, or X uses both A and B, then in each of the above cases, "X uses A or B" is satisfied. Additionally, the article "a" used in this application and the appended claims may be broadly interpreted as "one or more" unless explicitly stated or clearly indicated from the context to mean only a single number. Further, at least one of A and B generally means A or B, or both A and B.

[0164] Devices and methods for manufacturing the devices are described in this specification. The remarks made in connection with the described devices can also be applied to the corresponding methods and vice versa. For example, when describing a particular component of a device, the corresponding method for manufacturing the device may include a process for providing the component in a suitable manner even if such an operation is not explicitly described or shown in the figures. Further, unless otherwise explicitly stated, the features of the various exemplary aspects described herein can be combined with each other.

[0165] Although the present disclosure has been shown and described with reference to one or more embodiments, those skilled in the art are capable of making equivalent substitutions and modifications, which are at least partially based on the reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and variations and is limited only by the concepts of the appended claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe these components are intended to correspond to each such component that performs the function of the component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure when such structure performs the functions of the exemplary embodiments shown herein. Further, even if a particular feature of the present disclosure has been disclosed with reference to only one of the respective embodiments, such feature can be combined with one or more other features of other embodiments and is thus desirable and advantageous, for example, for a given or particular application.

Claims

1. A method of manufacturing a semiconductor, comprising: Provide a semiconductor component, wherein each semiconductor component in the semiconductor component includes: a semiconductor chip, wherein the semiconductor chip includes a first main surface and a second main surface opposite to the first main surface, and a sacrificial material disposed above the second main surface of the semiconductor chip; encapsulating the semiconductor component with an encapsulating material layer; wherein all sidewalls of the semiconductor chip are covered by and in contact with the encapsulating material layer, removing the sacrificial material, wherein, above the semiconductor chip, a recess is formed in the encapsulating material based on removing the sacrificial material wherein based on removing the sacrificial material, the entire second main surface is exposed to a gas; and wherein, in an orthogonal projection onto the second main surface, a base surface of the recess at least partially protrudes beyond a base surface of the semiconductor chip; and arranging a cover above the recess, wherein a cavity is formed above the semiconductor chip through the recess and the cover.

2. The method according to claim 1, wherein, The cavity is disposed above the second main surface of the semiconductor chip and a surface of the encapsulating material layer.

3. The method according to claim 1, wherein, Providing the semiconductor component includes: arranging an etch stop layer between the semiconductor chip and the sacrificial material, and wherein removing the sacrificial material includes: etching the sacrificial material, wherein the etch stop layer is exposed.

4. The method according to claim 3, further comprising: After removing the sacrificial material, removing the etch stop layer, wherein the first main surface and the second main surface of the semiconductor chip are exposed.

5. The method according to claim 1, further comprising: Before removing the sacrificial material, removing a part of the encapsulating material layer above the first main surface and the second main surface of the semiconductor chip embedded in the encapsulating material layer, wherein the sacrificial material is exposed.

6. The method according to claim 1, wherein, After encapsulating the semiconductor component, a main surface of the encapsulating material layer and the first main surface of the semiconductor chip are in a common plane.

7. The method according to claim 6, further comprising: Forming a redistribution layer above the first main surface of the semiconductor chip and the main surface of the encapsulating material layer.

8. The method according to claim 1, further comprising: After arranging the cover above the recess, separating the semiconductor component encapsulated with the encapsulating material layer into semiconductor packages, wherein the semiconductor packages include the cavity.

9. The method according to claim 1, wherein, The first main surface of the semiconductor chip is the active main surface of the semiconductor chip.

10. The method according to claim 1, wherein, The sacrificial material includes a semiconductor material or a glass material.

11. A semiconductor device, comprising: a semiconductor chip, including a first main surface and a second main surface opposite to the first main surface; an encapsulating material layer, wherein all sidewalls of the semiconductor chip are encapsulated by and in contact with the encapsulating material layer; and a recess disposed in the encapsulating material layer, wherein the recess in the encapsulating material layer is disposed above the second main surface of the semiconductor chip, wherein the entire second main surface is exposed to a gas, and wherein in an orthogonal projection onto the second main surface, a base surface of the recess in the encapsulating material layer at least partially protrudes beyond a base surface of the semiconductor chip.

12. The semiconductor device according to claim 11, further comprising: a cover disposed above the recess in the encapsulating material layer, A closed cavity is formed above the second main surface of the semiconductor chip by the recess and the lid in the encapsulation material layer.

13. The semiconductor device according to claim 11, wherein The semiconductor chip includes an integrated high-frequency circuit designed to operate at a frequency greater than 10 GHz.

14. The semiconductor device according to claim 11, wherein The second main surface of the semiconductor chip is not covered by the encapsulation material layer.

15. The semiconductor device according to claim 11, further comprising: A recess formed in the semiconductor material on the second main surface of the semiconductor chip.

16. The semiconductor device according to claim 11, further comprising: A lid disposed above the recess in the encapsulation material layer. Wherein, a cavity is formed above the second main surface of the semiconductor chip by the recess and the lid in the encapsulation material layer. Wherein the cavity includes an opening.

17. A semiconductor device, comprising: A semiconductor chip, including a first main surface and a second main surface opposite to the first main surface. An electrical contact element. An encapsulation material layer. Wherein all sidewalls of the semiconductor chip are encapsulated by and in contact with the encapsulation material layer. And A recess disposed in the encapsulation material layer. Wherein the recess in the encapsulation material layer is disposed above the second main surface of the semiconductor chip, and the electrical contact element is disposed on the first main surface of the semiconductor chip. Wherein the entire second main surface is exposed to gas, and Wherein in a projection perpendicular to the first main surface of the semiconductor chip, the base surface of the recess in the encapsulation material layer is disposed above the region of the semiconductor chip and / or the region of the encapsulation material layer, and high-frequency signals are processed or transmitted in the region.

18. The semiconductor device according to claim 17, wherein In the projection, the base surface of the recess in the encapsulation material layer extends beyond the base surface of the semiconductor chip.

19. The semiconductor device according to claim 17, further comprising: The material in the recess in the encapsulation material layer. Wherein the material in the recess in the encapsulation material layer has a dielectric constant at least lower than: the encapsulation material layer, or the semiconductor chip.

20. The semiconductor device according to claim 17, wherein In the projection, the base surface of the recess in the encapsulation material layer is disposed above at least one of the following components: a high-frequency interface serving as the electrical contact element, a high-frequency wire electrically connected to the high-frequency interface, or an oscillation circuit.

21. The semiconductor device according to claim 17, further comprising: An opening formed in the encapsulation material layer, and the opening is designed to provide an exchange of gas with the recess in the encapsulation material layer.

22. The semiconductor device according to claim 21, wherein In the projection, the opening is disposed above at least one of a high-frequency interface serving as the electrical contact element or a high-frequency wire electrically connected to the high-frequency interface.

23. A semiconductor device, comprising: A semiconductor chip, including a first main surface and a second main surface opposite to the first main surface. An encapsulation material layer. An etch stop material disposed between the sidewalls of the semiconductor chip and the encapsulation material layer. Wherein all sidewalls of the semiconductor chip are covered by and in contact with the etch stop material; and A recess disposed in the encapsulation material layer above the second main surface of the semiconductor chip. Wherein the entire second main surface is exposed to gas, and Wherein in a projection perpendicular to the first main surface of the semiconductor chip, the base surface of the recess in the encapsulation material layer at least partially extends beyond the base surface of the semiconductor chip.

24. The semiconductor device according to claim 23, further comprising: A lid disposed above the recess in the encapsulation material layer, wherein a cavity is formed above the second main surface of the semiconductor chip by the recess and the lid in the encapsulation material layer, wherein the cavity includes an opening.

25. The semiconductor device according to claim 23, further comprising: A lid disposed above the recess in the encapsulation material layer, wherein a closed cavity is formed above the second main surface of the semiconductor chip by the recess and the lid in the encapsulation material layer.

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