Heat dissipation structure and method for manufacturing heat dissipation structure

Abstract

The present disclosure describes a heat dissipation structure that can be formed in a functional area or a non-functional area of ​​a three-dimensional system integration chip structure. In some embodiments, the heat dissipation structure maintains the average operating temperature of the memory die or chip to less than about 90°C. For example, the heat dissipation structure includes a stack of two or more chip layers, wherein a chip layer of the stack of two or more chip layers includes a center portion and an edge portion, the center portion includes one or more chips, and the edge portion surrounds the center portion. The edge portion includes a thermal interface material ring and a thermally conductive structure. The thermal interface material ring includes a first material having a first thermal conductivity. The thermally conductive structure includes a second material having a second thermal conductivity higher than the first thermal conductivity. The structure also includes a thermal interface material layer disposed above the top chip layer of the stack, and a heat sink above the thermal interface material layer.

Description

Technical Field

[0001] The present disclosure relates to a heat dissipation structure and a method for manufacturing the heat dissipation structure. Background Art

[0002] Three-dimensional system integration wafer structures with increased wafer density may exhibit high heat density and poor heat dissipation performance compared to their two-dimensional counterparts. Increased heat density in three-dimensional system integration wafer structures may lead to electromigration and reliability issues. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a heat dissipation structure is provided, comprising: a stack of two or more wafer layers, a thermal interface material layer, and a heat sink. A wafer layer of the stack of two or more wafer layers comprises: a central portion and an edge portion, wherein the central portion comprises one or more wafers, and the edge portion surrounds the central portion and comprises a thermal interface material ring and a thermally conductive structure. The thermal interface material ring comprises a first material having a first thermal conductivity. The thermally conductive structure comprises a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the wafer layer and physically contacts the thermal interface material ring. The thermal interface material layer is disposed on the top wafer layer of the stack. The heat sink is located above the thermal interface material layer.

[0004] According to one embodiment of the present disclosure, a method for manufacturing a heat dissipation structure includes attaching one or more chips to a first region of a substrate, wherein the substrate with the one or more chips forms a first chip layer; depositing a thermal interface material on a second region of the substrate, wherein the thermal interface material forms a closed loop around the one or more chips; forming one or more heat-conducting structures on the thermal interface material; and depositing a dielectric layer on the substrate, such that the one or more chips and the one or more heat-conducting structures are embedded in the dielectric layer.

[0005] According to one embodiment of the present disclosure, a heat dissipation structure is provided, comprising a bottom wafer layer and a stack of multiple dies. The stack of multiple dies is disposed on the bottom wafer layer, wherein the stack includes multiple interconnect layers and a molding region. The multiple interconnect layers are configured to provide multiple interconnects for the multiple dies, wherein the multiple interconnect layers include multiple first vertical heat conductive structures. The molding region surrounds each die in the stack, wherein the molding region includes multiple second vertical heat conductive structures and a thermal interface material.

[0006] According to one embodiment of the present disclosure, a heat dissipation structure is provided, comprising a plurality of wafer layers and a thermal interface material layer disposed on the plurality of wafer layers. A wafer layer of the plurality of wafer layers comprises one or more wafers and an edge portion surrounding the one or more wafers. The edge portion comprises a thermal interface material ring and a thermally conductive structure. The thermal interface material ring comprises a first material having a first thermal conductivity and surrounds the one or more wafers. The thermally conductive structure comprises a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the wafer layer and physically contacts the thermal interface material ring.

[0007] According to one embodiment of the present disclosure, a heat dissipation structure is provided, comprising a stack of two or more wafer layers, a thermal interface material layer, and a heat sink. A wafer layer in the stack of two or more wafer layers comprises one or more wafers and a non-functional area, including a thermal interface material ring and a thermally conductive structure. The thermal interface material ring comprises a first material having a first thermal conductivity. The thermally conductive structure comprises a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the wafer layers and physically contacts the thermal interface material ring. The thermal interface material layer is located on the topmost wafer layer in the stack of two or more wafer layers. The heat sink is above the thermal interface material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with conventional practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a partial isometric view of a three-dimensional system integration wafer structure with a thermal interface ring according to some embodiments;

[0010] Figure 2A is a cross-sectional view of a three-dimensional system integration wafer structure having a thermal interface ring in a phantom region according to some embodiments;

[0011] Figure 2B is a cross-sectional view of a three-dimensional system integration wafer structure having a thermal interface ring and vertical heat conducting structures in a phantom region according to some embodiments;

[0012] Figure 3 is a thermal map of a three-dimensional system integration wafer structure having a thermal interface ring in a virtual region according to some embodiments;

[0013] Figure 4 is a thermal map of a three-dimensional system integration wafer structure without a thermal interface ring in a virtual region according to some embodiments;

[0014] Figure 5isometric partial views of a three-dimensional system integration wafer structure with vertical thermal structures arranged in two exemplary layouts according to some embodiments;

[0015] Figure 6 is a top view of a wafer layer having thermally conductive structures disposed between electrically conductive structures according to some embodiments;

[0016] Figure 7 is a cross-sectional view of a virtual thermally conductive structure having a liner including metal particles according to some embodiments;

[0017] Figure 8 is a cross-sectional view of a three-dimensional system integration wafer structure having vertical heat conducting structures in a molding region according to some embodiments;

[0018] Figure 9 is a flow chart of a method for fabricating a three-dimensional system integration wafer structure having a thermal interface ring and a thermally conductive structure, according to some embodiments.

[0019]

Explanation of symbols

[0020] 100 3D system integrated chip structure

[0021] 100A chip layer

[0022] 100B wafer layer

[0023] 100C wafer layer

[0024] 100D chip layer

[0025] 110 chips

[0026] 120 vertical conductive structure

[0027] 130 Thermal Interface Material Ring

[0028] 140 Top blanket thermal interface material layer

[0029] 200A 3D system integrated chip structure

[0030] 200B 3D system integrated chip structure

[0031] 210 memory chip stacking

[0032] 220 Virtual Area

[0033] 230 Vertical Conductive Structure

[0034] 240 vertical conduction structure

[0035] 250 bonding pad structure

[0036] 260 bottom floor

[0037] 260A logic chip

[0038] 270 Arrow

[0039] 280 Radiator

[0040] 290 Ball Grid Array (BGA) Connector

[0041] 295A complementary thermal conductive structure

[0042] 295B complementary structure

[0043] 300A hot zone

[0044] 300B hot zone

[0045] 310A hot zone

[0046] 310B Hot Zone

[0047] 400 hot zones

[0048] 410 Hot Zone

[0049] 420 Hot Zone

[0050] 500 vertical thermal structures

[0051] 500p spacing

[0052] 500p' pitch

[0053] 510 chip layer

[0054] 520 heat dissipation layer

[0055] 530 lateral offset

[0056] 540A heat dissipation path

[0057] 540B heat dissipation path

[0058] 600 chip area

[0059] 610 Through Silicon Via

[0060] 700 Virtual Vertical Structure

[0061] 710 wafer layer

[0062] 720 middle layer

[0063] 730 metal core

[0064] 740 gasket material

[0065] 800 3D system integrated chip structure

[0066] 810 Molding Area

[0067] 820 memory stack

[0068] 830 memory chips

[0069] 840 hybrid joint structure

[0070] 850 System on Chip (SoC)

[0071] 860 Interface Layer

[0072] 870 Electrical Connection

[0073] 880 vertical structure

[0074] 890 Arrow

[0075] 900 Method

[0076] 910 Operation

[0077] 920 Operation

[0078] 930 Operation

[0079] 940 Operation DETAILED DESCRIPTION

[0080] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are intended to be limiting. For example, forming a first feature above a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0081] Additionally, spatially relative terms such as "below," "below," "lower," "above," "upper," etc., may be used herein to simplify the description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device / element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0082] As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter of a component or process operation that is set during the design phase of a product or process, as well as a range of values ​​above and / or below the desired value. This range of values ​​may be subject to minor variations due to manufacturing processes or tolerances.

[0083] As used herein, the term "vertical" means nominally perpendicular to the substrate surface.

[0084] As used herein, the term "substantially" indicates that the value of a given quantity may vary based on a particular technology node associated with the subject semiconductor device. In some embodiments, the term "substantially" may indicate that the value of a given quantity varies within, for example, ±5% of a target (or intended) value based on the particular technology node.

[0085] As used herein, the term "approximately" indicates that the value of a given quantity may vary based on a particular technology node associated with the subject semiconductor device. In some embodiments, based on the particular technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 5-30% of the value (e.g., ±5%, ±10%, ±20%, or ±30% of the value).

[0086] A three-dimensional system on integrated chip (3DSoIC) structure is a non-monolithic vertical structure that includes two to eight two-dimensional (2D) flip chips stacked on top of each other. A 2D flip chip can be a compilation of chips with different functions, such as logic chips, memory chips, radio frequency (RF) chips, etc. By way of example and not limitation, the logic chip can include a central processing unit (CPU), and the memory chip can include a static access memory (SRAM) array, a dynamic random access memory (DRAM) array, a magnetic random access memory (MRAM) array, or other memory arrays. In a 3D system on integrated chip structure, each 2D chip can be interconnected via microbumps, bonding pads, through silicon vias (TSVs), or other interconnect structures, which can be shorter than the interconnects used in a 2D system on integrated chip structure. As a result, a 3D system on integrated chip structure can be faster, denser, and have additional functionality than its 2D counterpart. Furthermore, compared to a 2D system integration chip structure, a 3D system integration chip structure may have a smaller footprint.

[0087] On the other hand, because 3D system-integrated chip structures have increased chip density and reduced footprint (which translates into limited heat dissipation area), they also have a higher heat density per unit area than 2D system-integrated chip structures and are more susceptible to heat dissipation issues. The increased heat density in 3D system-integrated chip structures can lead to electromigration and reliability issues. For example, electromigration can increase the resistance of interconnects and through-silicon vias, degrading chip performance and shortening the lifespan of the 3D system-integrated chip structure. Reliability issues can arise due to the materials included in the 3D system-integrated chip structure, including materials with different coefficients of thermal expansion (CTE). Materials with different CTEs can cause thermomechanical stress between integrated circuit (IC) chips. In addition, different types of IC chips can have different heat tolerances. For example, memory chips (e.g., SRAM arrays) can have lower heat tolerances (e.g., equal to or below approximately 90°C) compared to logic chips, which can have higher heat tolerances (e.g., equal to or above approximately 120°C). For these reasons, heat dissipation issues in 3D system-integrated chip structures should be addressed.

[0088] To address the above shortcomings, the embodiments described herein relate to heat dissipation structures that can be formed in functional or non-functional areas of a 3D system integrated chip structure. In some embodiments, the heat dissipation structure may include a thermal interface material (TIM) ring, a vertical conductive structure disposed in a dummy area (e.g., a non-functional area) or a molded area of ​​the 3D system integrated chip structure, a vertical conductive structure disposed within an active chip area and around a high heat output area (hot spot), or a combination thereof. In some embodiments, existing vertical structures in a 3D system integrated chip structure can be reused as additional heat dissipation paths. The embodiments described herein can be applied to a range of 3D system integrated chip structures, including but not limited to 3D system integrated chip structures having dummy areas and molded areas.

[0089] According to some embodiments, Figure 1 is a partial isometric view of a 3D system integration wafer structure 100. The 3D system integration wafer structure 100 includes four wafer layers (e.g., 100A, 100B, 100C, and 100D); however, the number of wafer layers is not limiting, and fewer or additional wafer layers (e.g., 2, 6, or 8) may be used. For illustrative purposes, Figure 1Includes selected portions of the 3D system integration chip structure and may include other portions (not shown). For example, it may include microbumps, molded areas / dummy areas, adhesive layers, heat sinks, interconnects, ball grid array (BGA) connectors, silicon interposers, and other components or structural elements. Each chip layer may include one or more chips 110, which are electrically connected to the chips in the adjacent chip layer through vertical conductive structures 120. In some embodiments, the vertical conductive structures 120 may include through-silicon vias or other types of vertical conductive structures. By way of example and not limitation, the bottom chip layer 100A may include one or more microprocessors or CPUs, while the chip layers 100B to 100D may include one or more memory chips (e.g., SRAM chips, DRAM chips, MRAM chips, other types of memory chips, or combinations thereof). In some embodiments, the bottom chip layer 100A generates more heat than the chip layers 100B, 100C, and 100D. By way of example and not limitation, the temperature of the bottom wafer layer 100A during operation may be greater than about 100° C. (eg, about 105° C., about 110° C., about 115° C., or about 130° C.).

[0090] In terms of heat dissipation, the 3D system integration wafer structure 100 includes a thermal interface material ring 130 on the periphery of each wafer layer and a top blanket thermal interface material layer 140 over the entire top wafer layer 100D. By way of example and not limitation, the thermal interface material ring 130 and thermal interface material layer 140 may comprise materials such as silver, aluminum nitride, silicon carbide, or combinations thereof. In further embodiments, the thermal interface material ring 130 and thermal interface material layer 140 may comprise a thermal grease having a thermal conductivity between approximately 1.5 W / (m·K) and approximately 15 W / (m·K). By way of example and not limitation, the thickness of the thermal interface material layer 140 may range from approximately 0.1 mm to approximately 0.5 mm, and the thickness of the thermal interface material ring 130 may range from approximately 0.3 mm to approximately 0.8 mm. In some embodiments, each thermal interface material ring 130 forms a continuous layer around one or more wafers 110 in the non-functional region of each wafer layer. For example, the periphery of the wafer layers 100A-100D may not include active / functional components. Alternatively, the periphery of the wafer layers 100A-100D may be occupied by layers that provide structural support for the 3D system integration wafer structure 100. According to some embodiments, the periphery of the wafer layers 100A-100D may be used to carry the thermal interface material ring 130. A heat sink ( Figure 1 According to some embodiments, the thermal interface material ring 130 and the blanket thermal interface material layer 140 form a heat dissipation path to transfer the heat generated by the bottom wafer layer 100A to the heat sink above the blanket thermal interface material layer 140. Figure 1 As shown and described above, a thermal interface material ring 130 is located at the periphery of each wafer layer and forms a continuous layer that includes non-functional areas of the 3D system integration wafer structure.

[0091] Figure 2A is a cross-sectional view of a 3D system integration wafer structure 200A. According to some embodiments, the 3D system integration wafer structure 200A is similar to the 3D system integration wafer structure 100. However, the 3D system integration wafer structure 200A is more sophisticated and, therefore, includes additional electrical components or structural elements. For example, the 3D system integration wafer structure 200A includes a memory wafer stack 210, a dummy region 220 surrounding the memory wafer stack 210, vertical conductive structures 230 and 240, a bonding pad structure 250, a bottom layer 260, and a heat sink 280. The bottom layer 260 has a logic wafer 260A below the memory wafer stack 210 and the dummy region 220. The heat sink 280 is above the top thermal interface material layer 140. The dummy region 220 is a non-electrically functional structure with poor electrical conductivity (e.g., less than approximately 1.3 W / (m K)). By way of example, and not limitation, dummy regions 220 (e.g., non-functional regions) can provide structural support for the 3D system integration wafer structure 200A and include a combination of electrically insulating materials and metal conductive structures or metal-containing conductive structures. By way of example, and not limitation, dummy regions 220 can include a molding compound (e.g., an epoxy-based material) to electrically isolate the various components of the memory wafer and provide structural support for the 3D system integration wafer structure 200A. In an alternative embodiment, dummy regions 220 can include an oxide-based dielectric material (e.g., silicon oxide) and metal conductive structures or metal-containing conductive structures. The wafers in the 3D system integration wafer structure 200A can be electrically coupled to adjacent top and bottom wafers via conductive structures 230 (e.g., bond pads), vertical conductive structures 240 (e.g., through-silicon vias), and bond pad structures 250. The above structures are examples only, and alternative or additional structures or methods may be used to electrically couple the wafers in the 3D system integration wafer structure 200A. In some embodiments, the conductive structures 230, vertical conductive structures 240, and bond pad structures 250 may be used for signal propagation and / or power distribution between the memory chip 210 and the logic chip 260A. In some embodiments, the logic chip 260A may include one or more CPU chips, which may generate more heat than the memory chip 210.

[0092] In some embodiments, the purpose of the 3D system integrated chip structure 200A is to form a heat dissipation path to guide a portion of the heat generated by the logic chip 260A to the heat sink 280 through the dummy area 220, so that the average operating temperature of the memory chip 210 can be lower than about 90°C. To facilitate the formation of the heat dissipation path, a thermal interface material ring 130 is disposed in the dummy area 220 and inserted between adjacent memory chips 210. In addition, a top blanket thermal interface material layer 140 is inserted between the surface of the top memory chip 210 and the back surface of the heat sink 280. In some embodiments, placing the thermal interface material ring 130 can improve the thermal conductivity of the dummy area 220 and reduce the average operating temperature of the memory chip 210 by guiding most of the heat generated in the logic chip 260A through the dummy area 220. By way of example and not limitation, the thermal interface material ring 130 can reduce the average operating temperature of the memory chip 210 from about 100°C to about 90°C, which is a reduction of about 10%. A thermal map can reveal the heat distribution achieved by the thermal interface material ring 130. For example, Figure 3 is when the 3D system integration wafer structure 200A is viewed from the top (e.g., from Figure 2A The heat sink 280 is viewed downwards, which corresponds to the thermal image of the 3D system integrated chip structure 200A. Figure 3 , thermal zones 300A and 300B correspond to the areas above the memory chip 210 and the dummy area 220, respectively. Thus, thermal zone 310A corresponds to the area between the memory chip 210 and the dummy area 220, and thermal zone 310B corresponds to the edge of the 3D system integration chip structure 200A outside the periphery of the logic chip 260A. In some embodiments, the temperature of thermal zones 300A and 300B is about 90°C, while the temperature of thermal zones 310A and 310B is lower than about 90°C (e.g., about 85°C, about 80°C, or about 70°C). By way of example and not limitation, Figure 2A The arrows 270 in FIG. 2 illustrate the heat dissipation path in the 3D system integrated chip structure 200A. Figure 2A As shown, part of the heat generated in the logic chip 260A is guided through the thermal interface material ring 230 in the dummy area 220, thereby reducing the heat dissipated directly through the memory chip 210. Therefore, the heat can escape to the memory chip 210 through the ball grid array (BGA) connector 290. Figure 2A A printed circuit board (PCB) or another substrate not shown.

[0093] In contrast, Figure 4 is another thermal map corresponding to a 3D system integration chip structure that does not include the thermal interface material ring 230 in the virtual area 220. Therefore, the thermal distribution of this 3D system integration chip structure is different from Figure 3. For example, thermal zone 400 corresponds to the area above the memory die 210, thermal zone 410 corresponds to the area between the memory die 210 and above the dummy area 220, and thermal zone 420 corresponds to the corner of the 3D system integration wafer structure. In this example, the temperature corresponding to thermal zone 400 (e.g., above the memory die 210) is approximately 100°C, while the temperatures corresponding to thermal zones 410 and 420 are each below approximately 100°C. This means that the average operating temperature of the memory die can be higher without the thermal interface material ring 130, and the dummy area 220 shares less heat load with the memory die 210.

[0094] According to some embodiments, Figure 2B is a cross-sectional view of a 3D system integrated chip structure 200B. The 3D system integrated chip structure 200B may be Figure 2A . By way of example and not limitation, the 3D system integration wafer structure 200B may have a dummy region 220 that may extend beneath the memory die stack 210 and surround the bottom layer 260. Furthermore, the 3D system integration wafer structure 200B may include complementary thermally conductive structures 295A and 295B within the dummy region 220. According to some embodiments, in addition to the thermal interface material ring 130, the thermally conductive structures 295 may also increase the heat dissipation rate of the 3D system integration wafer structure 200B. By way of example and not limitation, the thermally conductive structures 295A may form a network of structures extending laterally within the dummy region 220, while the thermally conductive structures 295B may extend vertically through the dummy region 220. In some embodiments, the thermally conductive structures 295A and 295B may comprise copper, aluminum, a metal alloy, or a material having a thermal conductivity greater than approximately 200 W / (m·K). The thermally conductive structures 295A and 295B may be in physical contact with the thermal interface material ring 130 and may be configured to enhance heat dissipation through the dummy area 220. Additionally, the layout of the thermally conductive structures 295A and 295B is not limited to Figure 2B Therefore, additional arrangements are within the spirit and scope of the present disclosure. Figure 2B Arrows 270 in FIG. 1 represent heat dissipation paths between the logic chip 260A and the heat sink 280 in the 3D system integrated chip structure 200B.

[0095] In addition to the above, vertical thermal structures can be used within each wafer layer to provide additional heat dissipation paths in the 3D system integration wafer structure. By way of example and not limitation, the vertical thermal structures can include through-silicon vias (TSVs), which can be formed at predetermined locations across the various wafer layers to improve heat dissipation between the layers in the vertical direction (e.g., the z-direction). According to some embodiments, these vertical structures are collectively referred to as "vertical thermal structures" or "thermal TSVs."

[0096] According to some embodiments, Figure 5 3D system integration wafer structures with vertical thermal structures 500 according to two exemplary layouts, A and B, are isometric partial views. In the example of Layout A, the vertical thermal structures 500 can be vertically aligned (e.g., stacked) between wafer layer 510 and heat dissipation layer 520. Thus, the thermal paths 540A in Layout A can be limited to the vertical direction (e.g., the z-direction). In Layout B, the vertical thermal structures 500 can be formed with lateral offsets 530 within each wafer layer 510, such that the thermal paths 540B can be vertical (e.g., in the z-direction) and lateral (e.g., in the x- and y-directions). By way of example and not limitation, the lateral offsets 530 can be configured to have different orientations from one wafer layer to another. Thus, the length and direction of each heat dissipation path 540A and 540B can vary for each layout (e.g., Layout A and Layout B). Thus, each layout can be used for different purposes. For example, Layout A can be used to create vertical heat dissipation paths, while Layout B can be used to provide a combination of lateral and vertical heat dissipation paths from one layer to the next. Thus, a 3D system integration wafer structure may include Layout A, Layout B, or a combination thereof to improve heat transfer between one location on the wafer and another.

[0097] respectively Figure 2A and Figure 2B In the example of 3D system integration chip structures 200A and 200B, vertical thermal conductive structures can be provided in the bottom chip layer 260 and arranged according to layouts A and B to form vertical and lateral / vertical heat dissipation paths between the logic chip 260A and the heat sink 280. In addition, both layouts A and B can be used to provide targeted heat dissipation to local heat sources or "hot spots" within the chip layer. For example, the vertical thermal structure 500 can be arranged above the local hot spot according to layout A, layout B, or a combination thereof to improve the heat transfer rate near the hot spot. In some embodiments, the local hot spot can appear on any chip layer, not limited to the chip layer with the logic chip. Therefore, the vertical thermal structure can be formed at any chip level 510 on an "as needed" basis to transfer heat away from the local hot spot.

[0098] In some embodiments, reference Figure 5Depending on the design and heat dissipation requirements of the 3D system integration wafer structure, the spacing between the vertical thermal structures 500 within the same wafer layer 510 may be in the range of about 1 μm to about 100 μm (e.g., from 1 μm to 20 μm, from 5 μm to 25 μm, from 15 μm to 30 μm, from 25 μm to 60 μm, from 50 μm to 80 μm, from 70 μm to 100 μm, etc.). In addition, the diameter of the vertical thermal structures 500 may be in the range of about 0.5 μm to about 2 μm. According to some embodiments, as the spacing of the vertical thermal structures 500 within the wafer layer 510 decreases, the heat dissipation rate increases. In other words, the heat dissipation rate is inversely proportional to the spacing between the vertical thermal structures within the wafer layer. In addition, the heat dissipation rate increases when the ratio of the total area occupied by the vertical thermal structures to the total area occupied by the wafer increases. However, the number of vertical thermal structures cannot be increased indefinitely because the wafer density within the wafer layer may be compromised. Therefore, it is desirable to balance the density of vertical thermal structures with the chip density to achieve optimal heat dissipation performance within a 3D system integration chip structure.

[0099] Figure 6 yes Figure 5 FIG2 is a top view of an exemplary wafer layer 510 in FIG2 , illustrating an exemplary distribution of vertical thermal structures 500 among other through-silicon vias 610 within a wafer region 600. In some embodiments, the through-silicon vias 610 may be electrical connections to a CPU die or a memory die (such as an SRAM, DRAM, MRAM, and / or other memory die). In some embodiments, as described above, the spacing 500p (e.g., within a wafer region 600) and the spacing 500p′ (e.g., between adjacent wafer regions 600) may be adjusted based on the desired thermal characteristics of the 3D system integration wafer structure and / or the presence of hot spots in the wafer region 600. Figure 6 The distribution of vertical thermal structures 500 shown in FIG. 5 is not limiting, and layouts having fewer or additional vertical structures 500 are within the spirit and scope of the present disclosure.

[0100] According to some embodiments, modifying existing structural elements within a 3D system integration wafer structure can improve heat dissipation within the 3D system integration wafer structure. By way of example and not limitation, "dummy" vertical structures—non-functional structural elements used to improve the process window for certain operations (e.g., etching, chemical mechanical polishing, patterning)—can be modified to also function as heat dissipation elements. More specifically, incorporating metal particles into the backing material of the dummy vertical structures can "transform" structural elements such as the dummy vertical structures into heat dissipation elements.

[0101] According to some embodiments, Figure 7 is a cross-sectional view of a virtual vertical structure 700 disposed between wafer layers 710. Figure 7In the example of FIG, wafer layers 710 are separated by an intermediate layer 720. In some embodiments, intermediate layer 720 comprises a dielectric material such as silicon oxide or hafnium oxide. By way of example, and not limitation, dummy vertical structure 700 may include a metal core 730 and a liner material 740 surrounding metal core 730. By way of example, and not limitation, liner material 740 may include silicon oxide, organosilicate glass, or the like. By way of example, and not limitation, metal core 730 may include a material having a thermal conductivity greater than approximately 200 W / (mK) (e.g., copper, aluminum, etc.). In some embodiments, liner material 740 (which may be a dielectric layer (e.g., silicon oxide) serving as an adhesion layer for metal core 730) may be implanted with metal particles or metal-containing particles that may improve the thermal conductivity of dummy vertical structure 700. By way of example, and not limitation, the metal particles or metal-containing particles may include tungsten, tungsten silicide, titanium nitride, titanium, copper, or a combination thereof. According to some embodiments, metal particles may be incorporated into the liner material 740 during its formation and may have a diameter of about 50 μm. The thickness of the liner material 740 may be in a range from about 100 nm to about 800 nm.

[0102] In some embodiments, the virtual vertical structures may be collectively referred to as "virtual TSVs," and like vertical thermal structures or thermal TSVs, they are interposed between wafer layers of a 3D system integration wafer structure and have substantially equal sizes (e.g., diameters of about 0.5 μm to about 2 μm). However, the difference between virtual TSVs and vertical thermal structures is that the positions of virtual TSVs do not change based on the presence of hot spots in the 3D system integration wafer structure, in contrast to the positions of vertical thermal structures. In other words, the virtual TSVs remain in their original positions, which are determined by process requirements rather than the locations of hot spots. On the other hand, virtual TSVs and vertical thermal structures may share the same liner material and metal core material. For example, both virtual TSVs and vertical thermal structures may have: a liner material comprising silicon oxide, organosilicate glass, or the like; and a core comprising a material having a thermal conductivity greater than about 200 W / (m·K) (e.g., copper, aluminum, or the like).

[0103] Some types of 3D system integration wafer structures do not include dummy regions, but instead have molded regions. According to some embodiments, for these types of 3D system integration wafer structures with molded regions, vertical structures and thermal interface material ring structures can be formed in the molded regions to assist in the heat dissipation process. By way of example, and not limitation, the molded regions of the 3D system integration wafer structure can include a molding compound (e.g., an epoxy-based material) that encapsulates the wafer or die within the entire die layer and provides structural support for the 3D system integration wafer structure. This means that the molded region can extend across the area of ​​each wafer layer (e.g., the entire area of ​​each wafer layer) and is therefore not limited to the periphery or edges of the die layer (as in dummy regions in other types of 3D system integration wafer structures). Furthermore, the molding compound can be an electrical insulator (e.g., a dielectric material) with poor thermal conductivity. Therefore, when hot spots exist in the 3D system integration wafer structure or the 3D system integration wafer structure includes multiple die layers (e.g., between approximately two and approximately eight die layers), the 3D system integration wafer structure with molded regions may suffer from poor heat dissipation.

[0104] By way of example and not limitation, Figure 8 is a cross-sectional view of a 3D system integrated wafer structure 800. According to some embodiments, the 3D system integrated wafer structure 800 has a molding region 810 (e.g., a region having a molding compound). By way of example and not limitation, the 3D system integrated wafer structure 800 further includes a memory stack 820 having a plurality of memory dies 830 embedded in the molding region 810. The plurality of memory dies 830 are stacked on top of each other, such as Figure 8 The memory die 830 in the memory stack 820 may include, for example, an SRAM chip, a DRAM chip, an MRAM chip, other types of memory chips, a logic chip, or a combination thereof. Figure 8 The number of memory dies in the stack 820 shown is not limiting, and additional or fewer memory dies are within the spirit and scope of the present disclosure. In addition, the 3D system integration wafer structure 800 may include additional circuits and electrical components that are not shown for simplicity. Figure 8 . The 3D system integrated chip structure 800 may also include a system chip (SoC) 850, which may include a chip or a chip stack (e.g., a CPU, a heating element, a power distribution circuit, etc.) that may generate excess heat that needs to be dissipated from the memory stack 820 toward the heat sink 280. The interface layer 860 is disposed below each memory die 830 and is electrically coupled to each memory die 830 via a hybrid bonding structure 840. The interface layer 860 may be connected via a network of vertical connections (for simplicity in FIG. Figure 8The interface layer 860 (not shown) provides electrical connections 870 within a single memory die and between adjacent memory dies 830. In some embodiments, the interface layer 860 is a redistribution layer (RDL) or a back-end of the line (BEOL) metallization network (e.g., an interconnect layer).

[0105] In some embodiments, the excess heat generated by the system chip 850 needs to be dissipated from the memory stack 820 toward the heat sink 280 so that the temperature of the memory stack 820 is below about 90° C. To this end, the 3D system integrated chip structure 800 (similar to Figure 2A and Figure 2B The 3D system integration wafer structure 200 shown in FIG. 1 can include a thermal interface material ring 130 on each molding region 810 . The 3D system integration wafer structure 800 also includes a top thermal interface material layer 140 positioned below the heat sink 280 . In some embodiments, the thermal interface material ring 130 is disposed at the periphery of the molding region 810 to enhance heat dissipation from the system die 850 around the memory stack 820 . According to some embodiments, the dummy vertical structures 700 and vertical structures 880 (which can be disposed in the interface layer 860 and molding region 810 , respectively) are coupled with the thermal interface material ring 130 to provide an upward heat dissipation path from the system die 850 toward the heat sink 280 . According to some embodiments, each vertical structure 880 in the molding region 810 has a diameter approximately twice that of the dummy vertical structure 700 and can provide electrical connections between adjacent dies in the memory stack 820 . Furthermore, the vertical structures 880 can include a thermally conductive material having a thermal conductivity greater than approximately 200 W / (m·K). By way of example and not limitation, vertical structures 880 may comprise a metal, such as copper or aluminum.

[0106] In addition to the above-mentioned heat conduction structure in the mold area 810 of the 3D system integrated chip structure, the system chip 850 may also include Figure 5 The vertical thermal structure of the layout combination (in Figure 8 800) to dissipate heat generated by the system die 850 toward the periphery of the 3D system integration die structure 800 and along the heat dissipation path formed by the dummy vertical structures 700, the vertical structures 880, and the thermal interface material ring 130. According to some embodiments, arrow 890 illustrates the heat dissipation path from the system die 850 toward the heat sink 280. Therefore, the vertical thermal structures in the system die 850, the thermal interface material ring 130, the dummy vertical structures 700, and the vertical structures 880 in the molding area 810 can combine to direct the heat generated by the system die 850 to the vicinity of the memory stack 820 to limit the temperature of the memory stack 820 to below approximately 90°C.

[0107] According to some embodiments, Figure 9 It is used to manufacture 3D system integrated chip structures (such as Figure 1 、 Figure 2A 、 Figure 2B and Figure 8 The exemplary method 900 for manufacturing a 3D system integrated wafer structure as shown in FIG. The manufacturing method 900 is exemplary and not limiting. Therefore, in the method 900, additional or alternative operations may be performed instead of Figure 9 In addition, Figure 9 The order in which the operations of method 900 are shown is not intended to be limiting.

[0108] The method 900 begins at operation 910 and forms a thermal interface material ring in a virtual area of ​​a wafer layer. The wafer layer may include one or more wafers attached to a substrate, such as Figure 1 As shown for any one of the wafer layers 100A-100D. Figure 1 , for simplicity, the substrate on which the chip 110 is attached is not shown. In some embodiments, the substrate comprises a polyimide (PI) or polybenzoxazole (PBO) material, and one or more redistribution layers. As described above, the virtual area of ​​the chip layer can be located, for example, at the periphery of the chip layer. In some embodiments, the periphery of the chip layer is reserved for components that provide structural support for the structure formed when two or more chip layers are stacked vertically. At this stage of the manufacturing process, the periphery of the chip layer is not occupied. According to some embodiments, a thermal interface material ring can be formed at the periphery of the chip layer to form a ring of chips surrounding the chip layer. In some embodiments, the thermal interface material ring can be formed before the chip is attached to the substrate. For example, the thermal interface material ring can be deposited and patterned before the chip is attached. Alternatively, the thermal interface material ring can be provided (for example, with a nozzle) on the substrate after the chip is attached to the substrate.

[0109] Method 900 continues to operation 920, depositing a dielectric material to encapsulate the thermal interface material ring and the components of the wafer layer (e.g., the wafer). In some embodiments, the dielectric material can be an oxide-based dielectric, such as silicon oxide, which is deposited using plasma enhanced chemical vapor deposition or other suitable methods. The dielectric material can then be planarized using chemical mechanical polishing (CMP). In an alternative embodiment, the dielectric material is a molding compound, such as an epoxy-based material, which is dispensed (e.g., coated) and allowed to cool and harden naturally. Once the molding compound hardens, the molding compound can be partially ground and polished. As a result of the above process, the wafer and the thermal interface material ring are encapsulated in the dielectric material. In some embodiments, the dielectric layer extends over the entire surface of the wafer layer. In other embodiments, the dielectric material provides structural support when two or more wafer layers are stacked together. By way of example and not limitation, the dielectric material of operation 920 can be similar to Figure 2A and Figure 2B The materials in the virtual area 220 and Figure 8 The material in the molded area 810 in.

[0110] refer to Figure 9 , method 900 continues to operation 930, forming a thermally conductive structure in the dielectric material. In some embodiments, the thermally conductive structure can be formed by forming an opening in the dielectric material using photolithography and etching operations, and then depositing a thermally conductive material in the opening to form the thermally conductive structure. The thermally conductive structure can be arranged to form a heat dissipation path at the periphery of the wafer layer by making physical contact with the thermal interface material ring, such as (i) as shown in FIG. Figure 2B The segments of complementary thermally conductive structures 295A and complementary structures 295B are shown; and (ii) Figure 8 Vertical structures 880 are shown. In some embodiments, if the dielectric material is a mold compound, the thermally conductive structures are formed before the mold compound is applied to the wafer layer. For example, the thermally conductive structures can be formed in a sacrificial photoresist layer that is removed before the mold compound is applied. Thus, the thermally conductive structures are present when the mold compound is dispensed onto the wafer layer. In this case, depending on the type of dielectric material, operation 930 can be performed before operation 920.

[0111] refer to Figure 9 , method 900 continues to operation 940, wherein two or more wafer layers are stacked together to form a 3D system integration wafer structure. In some embodiments, a bonding structure (such as Figure 2A and Figure 2B The bonding pad structure 250 shown in FIG. Figure 8 hybrid bonding structure 840 shown in FIG) and an interface layer such as Figure 8 In an alternative embodiment, an interface layer (such as an interface layer 860) is formed before the wafer is attached to the substrate to form the wafer layer. Figure 8 The interface layer 860 shown in FIG. 8 or a bonding structure may be present on this substrate. In some embodiments, the wafer layers are then aligned via an alignment process using alignment marks as a guide so that their respective mechanical and electrical connection points are properly aligned when the wafer layers are stacked. Subsequently, the aligned wafer layers are bonded together to form a stack. In some embodiments, the wafer layer stack is cut at the end of the bonding process.

[0112] The present disclosure relates to heat dissipation structures that can be formed in functional areas or non-functional areas of a 3D system integrated chip structure. In some embodiments, the heat dissipation structure maintains the average operating temperature of the memory die or chip to below about 90°C. By way of example and not limitation, the heat dissipation structure may include a thermal interface material (TIM) ring and a vertical conductive structure disposed in a dummy area or molded area of ​​the 3D system integrated chip structure, a vertical conductive structure disposed within the chip area and around a heat output area (hot spot), or a combination thereof. In some embodiments, the existing vertical structure in the 3D system integrated chip structure can be structurally modified to serve as an additional heat dissipation path. The embodiments described herein can be applied to a series of 3D system integrated chip structures, including but not limited to 3D system integrated chip structures having a dummy area and a molded area.

[0113] In some embodiments, a heat dissipation structure includes a stack of one or more wafer layers, wherein each wafer layer includes a central portion having one or more wafers and an edge portion surrounding the central portion, the edge portion having a ring of thermal interface material. The structure also includes a thermal interface material layer disposed above the top wafer layer of the stack, and a heat sink above the thermal interface material layer.

[0114] In some embodiments, the heat dissipation structure further includes a virtual region located at an edge portion of each wafer layer, wherein the virtual region includes a dielectric material, the dielectric material is disposed on and in physical contact with the thermal interface material ring; a second heat-conducting structure extends laterally through the dielectric material of the virtual region; and a first heat-conducting structure extends vertically through the dielectric material of the virtual region, wherein the first heat-conducting structure, the second heat-conducting structure, and the thermal interface material ring are configured to direct heat generated in the stack toward the heat sink via the edge portion of each wafer layer.

[0115] In some embodiments, the first heat-conducting structure and the second heat-conducting structure include materials with a thermal conductivity greater than about 200 W / m·K.

[0116] In some embodiments, the thermal interface material ring forms a continuous layer around one or more wafers in each wafer layer.

[0117] In some embodiments, the continuous layer has a thickness between about 0.3 mm and about 0.8 mm.

[0118] In some embodiments, the one or more chips include memory chips.

[0119] In some embodiments, a method includes attaching one or more dies to a first region of a substrate, wherein the substrate with the one or more dies forms a first die layer. The method also includes depositing a thermal interface material on a second region of the substrate, wherein the thermal interface material forms a closed loop around the one or more dies; forming one or more thermally conductive structures on the thermal interface material; and depositing a dielectric layer on the substrate, such that the one or more dies and the thermally conductive structures are embedded in the dielectric layer.

[0120] In some embodiments, the above method also includes: forming a second chip layer; and vertically stacking the first and second chip layers to form a stack, so that one or more thermally conductive structures of the first chip layer are aligned with corresponding one or more thermally conductive structures of the second chip layer, and wherein the thermal interface material of the first chip layer is aligned with the corresponding thermal interface material of the second chip layer.

[0121] In some embodiments, the above method also includes: forming a thermal interface material layer on the dielectric layer of the second chip layer, wherein the thermal interface material layer covers the entire surface of the dielectric layer; and arranging a heat sink on the thermal interface material layer, so that the heat generated by the first and second chip layers is guided to the heat sink via the thermal interface materials of the first and second chip layers and the heat conductive structures of the first and second chip layers.

[0122] In some embodiments, forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures with a thermal conductivity greater than about 200 W / (m·K).

[0123] In some embodiments, depositing the thermal interface material includes depositing a thermal interface material to a thickness between about 0.3 mm and about 0.8 mm.

[0124] In some embodiments, forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures to have a diameter between about 0.5 μm and about 2 μm.

[0125] In some embodiments, a structure includes a bottom wafer layer and a die stack on the bottom wafer layer. The stack includes an interconnect layer configured to provide interconnects for the die, wherein the interconnect layer includes a first vertical thermally conductive structure. The stack also includes a molded region surrounding each die in the stack, wherein the molded region includes a second vertical thermally conductive structure and a thermal interface material.

[0126] In some embodiments, a diameter of the second vertical heat conducting structure is greater than a diameter of the first vertical heat conducting structure.

[0127] In some embodiments, the thermal interface material is interposed between a top surface of the second vertical thermally conductive structure and a bottom surface of the first vertical thermally conductive structure.

[0128] In some embodiments, the thermal interface material forms a continuous layer around the periphery of each die in the stack.

[0129] In some embodiments, the first and second vertical thermally conductive structures comprise a material having a thermal conductivity greater than about 200 W / (m·K).

[0130] In some embodiments, the structure further comprises: another thermal interface material above the stack of the plurality of dies, wherein the other thermal interface material covers the entire surface of the stack; and a heat sink above the other thermal interface material layer.

[0131] In some embodiments, the above structure further includes: a plurality of conductive structures disposed in the bottom wafer layer; and a plurality of third vertical heat-conducting structures disposed in the bottom wafer layer and distributed between the conductive structures, wherein the third vertical heat-conducting structures are configured to guide the heat generated by the bottom wafer layer to the heat sink via the first vertical heat-conducting structure, the thermal interface material, the second vertical heat-conducting structure and other thermal interface materials.

[0132] In some embodiments, the first vertical heat conductive structure, the second vertical heat conductive structure, the third vertical heat conductive structure, and the thermal interface material are configured to transfer heat away from the die stack.

[0133] It should be understood that the detailed description section, rather than the abstract section of the present disclosure, is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more but not all possible embodiments of the present disclosure contemplated by the inventors and is therefore not intended to limit the appended claims in any way.

[0134] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A heat dissipation structure, characterized in that: include: A stack of multiple wafer layers, wherein a wafer layer of the stack of multiple wafer layers comprises: a central portion comprising one or more wafers; and a rim portion surrounding the central portion and comprising: a thermal interface material ring comprising a first material having a first thermal conductivity; and a first thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the first thermally conductive structure extends vertically through the wafer layer and physically contacts the thermal interface material ring, and wherein the edge portion of the wafer layer further comprises: a dummy region located at the edge portion of the wafer layer, wherein the dummy region comprises a dielectric material disposed on and in physical contact with the thermal interface material ring, wherein the dielectric material has a third thermal conductivity lower than the first thermal conductivity; and a second heat-conducting structure extending laterally through the dielectric material of the dummy area; a thermal interface material layer disposed on a top wafer layer of the stack; and A heat sink is located above the thermal interface material layer, wherein the first thermally conductive structure, the second thermally conductive structure, and the thermal interface material ring are configured to direct heat generated in the stack toward the heat sink through the edge portion of the wafer layer.

2. The heat dissipation structure according to claim 1, characterized in that: The first heat-conducting structure and the second heat-conducting structure include a material with a thermal conductivity greater than 200 W / m·K.

3. The heat dissipation structure according to claim 1, characterized in that: The thermal interface material ring forms a continuous layer around the one or more wafers in the wafer layer.

4. The heat dissipation structure according to claim 3, characterized in that: The continuous layer has a thickness between 0.3 mm and 0.8 mm.

5. The heat dissipation structure according to claim 1, characterized in that: The one or more chips include memory chips.

6. A method for manufacturing a heat dissipation structure, characterized in that: include: attaching one or more chips to a first region of a substrate, wherein the substrate with the one or more chips forms a first chip layer; depositing a thermal interface material on a second area of ​​the substrate, wherein the thermal interface material forms a closed loop around the one or more chips; forming one or more thermally conductive structures on the thermal interface material; depositing a dielectric layer on the substrate such that the one or more chips and the one or more thermally conductive structures are embedded in the dielectric layer; forming a second wafer layer; as well as The first wafer layer and the second wafer layer are vertically stacked to form a stack, wherein the one or more thermally conductive structures of the first wafer layer are aligned with the corresponding one or more thermally conductive structures of the second wafer layer, and wherein the thermal interface material of the first wafer layer is aligned with a corresponding thermal interface material of the second wafer layer.

7. The method according to claim 6, characterized in that Further including: forming a thermal interface material layer on a dielectric layer of the second wafer layer, wherein the thermal interface material layer covers an entire surface of the dielectric layer; as well as A heat sink is arranged on the thermal interface material layer so that the heat generated by the first wafer layer and the second wafer layer is guided to the heat sink via the thermal interface material of the first wafer layer and the second wafer layer and the heat conductive structure of the first wafer layer and the second wafer layer.

8. The method according to claim 6, characterized in that Forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures with a thermal conductivity greater than 200 W / (m·K).

9. The method according to claim 6, characterized in that Depositing the thermal interface material includes depositing a thermal interface material having a thickness between 0.3 mm and 0.8 mm.

10. The method according to claim 6, characterized in that Forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures to have a diameter between 0.5 μm and 2 μm.

11. A heat dissipation structure, characterized in that: include: a bottom wafer layer; as well as a stack of a plurality of dies on the bottom wafer layer, wherein the stack comprises: a plurality of interconnect layers configured to provide a plurality of interconnects for the plurality of dies, wherein the plurality of interconnect layers comprises a plurality of first vertical thermally conductive structures; as well as A molding region surrounds each die in the stack, wherein the molding region includes a plurality of second vertical heat conductive structures and a thermal interface material, wherein the thermal interface material is interposed between a top surface of the plurality of second vertical heat conductive structures and a bottom surface of the plurality of first vertical heat conductive structures.

12. The heat dissipation structure according to claim 11, characterized in that: A diameter of the second vertical heat-conducting structure is greater than a diameter of the plurality of first vertical heat-conducting structures.

13. The heat dissipation structure according to claim 11, characterized in that: The thermal interface material forms a continuous layer around a periphery of each die in the stack.

14. The heat dissipation structure according to claim 11, characterized in that: The plurality of first vertical heat-conducting structures and the plurality of second vertical heat-conducting structures include a material with a thermal conductivity greater than 200 W / (m·K).

15. The heat dissipation structure according to claim 11, characterized in that: Further including: an additional thermal interface material over the stack of the plurality of dies, wherein the additional thermal interface material covers an entire surface of the stack; as well as A heat sink is above the other thermal interface material layer.

16. The heat dissipation structure according to claim 15, characterized in that: Further including: a plurality of conductive structures disposed in the bottom wafer layer; as well as a plurality of third vertical heat-conducting structures disposed in the bottom wafer layer and distributed between the plurality of conductive structures, wherein the plurality of third vertical heat-conducting structures are configured to conduct heat generated by the bottom wafer layer to the heat sink via the plurality of first vertical heat-conducting structures, the thermal interface material, the plurality of second vertical heat-conducting structures, and the other thermal interface materials.

17. The heat dissipation structure according to claim 16, characterized in that: The plurality of first vertical heat conductive structures, the plurality of second vertical heat conductive structures, the plurality of third vertical heat conductive structures, and the thermal interface material are configured to transfer heat away from the stack of the plurality of dies.

18. A heat dissipation structure, characterized in that: include: A plurality of wafer layers, wherein a wafer layer of the plurality of wafer layers comprises: one or more chips; and a rim portion surrounding the one or more wafers and comprising: a thermal interface material ring comprising a first material having a first thermal conductivity and surrounding the one or more chips, and a first thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the first thermally conductive structure extends vertically through the wafer layer and physically contacts the thermal interface material ring, and wherein the edge portion of the wafer layer further comprises: a dummy region located at the edge portion of the wafer layer, wherein the dummy region comprises a dielectric material disposed on and in physical contact with the thermal interface material ring, wherein the dielectric material has a third thermal conductivity lower than the first thermal conductivity; and a second heat-conducting structure extending laterally through the dielectric material of the dummy area; and A thermal interface material layer is located on the plurality of wafer layers, wherein the first heat conductive structure, the second heat conductive structure and the thermal interface material ring are configured to dissipate heat generated in the plurality of wafer layers through the edge portion of the wafer layer.

19. The heat dissipation structure according to claim 18, characterized in that: The one or more chips include memory chips.

20. The heat dissipation structure according to claim 18, characterized in that: The thermal interface material ring forms a continuous layer around the one or more wafers.

21. The heat dissipation structure according to claim 20, characterized in that: The continuous layer has a thickness between 0.3 mm and 0.8 mm.

22. The heat dissipation structure according to claim 18, characterized in that: The thermal interface material ring is located in a non-functional area of ​​the wafer layer.

23. The heat dissipation structure according to claim 18, characterized in that: The thermal interface material layer includes silver, aluminum nitride, silicon carbide or a combination thereof.

24. The heat dissipation structure according to claim 18, characterized in that: The thermal interface material layer includes a thermally conductive paste with a thermal conductivity between 1.5 W / (m·K) and 15 W / (m·K).

25. The heat dissipation structure according to claim 18, characterized in that: The thermal interface material layer has a thickness between 0.1 mm and 0.5 mm.

26. The heat dissipation structure according to claim 18, characterized in that: The first heat conducting structure, the thermal interface material ring, and the thermal interface material layer are arranged to form a heat dissipation path from a bottommost wafer layer of the plurality of wafer layers to the thermal interface material layer.

27. A heat dissipation structure, characterized in that: include: A stack of multiple wafer layers, wherein a wafer layer of the stack of multiple wafer layers comprises: one or more chips; and a non-functional area surrounding the one or more wafers and comprising: a thermal interface material ring comprising a first material having a first thermal conductivity; a first thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the first thermally conductive structure extends vertically through the wafer layer and physically contacts the thermal interface material ring; a dielectric material disposed on the thermal interface material ring and in physical contact with the thermal interface material ring, wherein the dielectric material has a third thermal conductivity lower than the first thermal conductivity; and a second thermally conductive structure extending laterally through the dielectric material; a thermal interface material layer on a topmost wafer layer in the stack of the plurality of wafer layers; and A heat sink is above the thermal interface material layer, wherein the first thermally conductive structure, the second thermally conductive structure, and the thermal interface material ring are configured to direct heat generated in the stack of the plurality of wafer layers toward the heat sink through the non-functional area of ​​the wafer layer.

28. The heat dissipation structure according to claim 27, characterized in that: The thermal interface material ring forms a continuous layer around the one or more wafers.

29. The heat dissipation structure according to claim 27, characterized in that: The thermal interface material layer includes silver, aluminum nitride, silicon carbide or a combination thereof.

30. The heat dissipation structure according to claim 27, characterized in that: The thermal interface material layer includes a thermally conductive paste with a thermal conductivity between 1.5 W / (m·K) and 15 W / (m·K).

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