Circuit and device for measuring time difference of second pulse signal

Abstract

The present application is applicable to the technical field of time-scale detection, and provides a circuit and device for measuring the time difference of a second pulse signal, including a phase detection unit, a time-voltage conversion unit, a voltage reset unit, and a voltage output unit. The phase detection unit performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal. The time-voltage conversion unit performs charging control on the integral capacitor contained therein based on the voltage conversion control signal, and the voltage reset unit performs discharge control on the integral capacitor, thereby obtaining a second voltage value of the voltage remaining at both ends of the integral capacitor. The voltage output unit reads the first voltage value after the integral capacitor is charged and the second voltage value after the integral capacitor is discharged. The time difference between the second pulse signal to be measured and the reference second pulse signal can be calculated based on the difference between the first voltage value and the second voltage value. The circuit structure of the present application is simple and the cost is low.

Description

Technical Field

[0001] The present application belongs to the technical field of time-scale detection, and in particular, relates to a circuit and a device for measuring the time difference of a second pulse signal. Background Art

[0002] With the rapid development of science and technology, people have put forward higher and higher requirements for precision time and time accuracy. The requirements for time synchronization in power systems, communication systems, transportation systems, etc. are constantly increasing, and time synchronization has received more and more attention and application. Pulse Per Second (PPS) signals are often used as time standards to access terminal devices that require time synchronization. In order to ensure the correct operation of large-scale system time synchronization networks, it is necessary to detect the accuracy of the pulse signal as a time mark to ensure the correctness of the clock synchronization equipment.

[0003] The prior art generally uses a pulse counting method based on a programmable logic controller (Field-Programmable Gate Array, FPGA) or a delay line timing method based on a time-to-digital converter to detect second pulse signals. Although the above two second pulse signal detection methods have high detection accuracy, the circuit structure of the detection device is complex and the cost is high. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a circuit and a device for measuring the time difference of a second pulse signal, so as to solve the problem of complex circuit structure and high cost in the existing second pulse signal detection device.

[0005] A first aspect of an embodiment of the present application provides a circuit for measuring a time difference of a second pulse signal, comprising: a phase detection unit, a time-to-voltage conversion unit, a voltage reset unit, and a voltage output unit;

[0006] The phase discrimination unit comprises a reference signal input terminal, a signal to be measured input terminal and an output terminal, wherein the reference signal input terminal is used to receive a reference second pulse signal, the signal to be measured input terminal is used to receive a second pulse signal to be measured, and the output terminal of the phase discrimination unit is electrically connected to the controlled terminal of the time-voltage conversion unit; the phase discrimination unit performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal, and outputs the voltage conversion control signal to the controlled terminal of the time-voltage conversion unit via the output terminal of the phase discrimination unit;

[0007] The time-to-voltage conversion unit comprises an input terminal, a controlled terminal, a voltage control terminal and an integral capacitor, wherein the input terminal of the time-to-voltage conversion unit is used to connect to a reference voltage source; when the time-to-voltage conversion unit detects that the voltage conversion control signal is a charging signal, the time-to-voltage conversion unit charges the integral capacitor, and when the time-to-voltage conversion unit detects that the voltage conversion control signal is a charging stop signal, the time-to-voltage conversion unit stops charging the integral capacitor;

[0008] The voltage reset unit comprises an input end and an output end, the input end of the voltage reset unit is used to receive a voltage reset signal, and the output end of the voltage reset unit and the voltage control end of the time voltage conversion unit are connected to the input end of the voltage output unit; when the voltage reset unit detects that the voltage reset signal is a discharge signal, the voltage reset unit controls the integral capacitor to discharge, and when the voltage reset signal is detected to be a discharge stop signal, the voltage reset unit controls the integral capacitor to stop discharging;

[0009] The voltage output unit includes an input end and an output end. The voltage output unit reads a first voltage value of the integral capacitor after charging stops and a second voltage value of the integral capacitor after discharging stops through its input end, and outputs the first voltage value and the second voltage value through its output end.

[0010] Furthermore, the time-to-voltage conversion unit further includes: a constant current source unit and a switch control unit;

[0011] The constant current source unit comprises a power supply end, an input end and an output end, the power supply end of the constant current source unit is connected to the first power supply, the input end of the constant current source is the input end of the time voltage conversion unit, and the output end of the constant current source unit is connected to the first end of the switch control unit;

[0012] The switch control unit includes a first end, a second end and a controlled end, the integrating capacitor includes a first end and a second end, the second end of the switch control unit is connected to the first end of the integrating capacitor, the controlled end of the switch control unit is the controlled end of the time-voltage conversion unit, the first end of the integrating capacitor is the voltage control end of the time-voltage conversion unit, and the second end of the integrating capacitor is grounded.

[0013] Further, the phase detection unit includes: an XOR gate;

[0014] The first input end of the XOR gate is the reference signal input end of the phase detection unit, the second input end of the XOR gate is the input end of the signal to be tested of the phase detection unit, and the output end of the XOR gate is the output end of the phase detection unit.

[0015] Furthermore, the constant current source unit includes: a first operational amplifier, a first resistor, a second resistor, a first switch tube, a second switch tube and a third switch tube;

[0016] The non-inverting input terminal of the first operational amplifier is the input terminal of the constant current source unit, the inverting input terminal of the first operational amplifier and the low potential terminal of the first switch tube are commonly connected to the first end of the second resistor, the second end of the second resistor is grounded, the output terminal of the first operational amplifier is connected to the first end of the first resistor, the second end of the first resistor is connected to the controlled end of the first switch tube, the high potential terminal of the first switch tube, the low potential terminal of the second switch tube and the controlled end of the second switch tube are commonly connected to the controlled end of the third switch tube, the high potential terminal of the second switch tube and the high potential terminal of the third switch tube are commonly connected as the power supply terminal of the constant current source unit, and the low potential terminal of the third switch tube is the output terminal of the constant current source unit.

[0017] Further, the switch control unit includes: a first diode and a common-phase buffer;

[0018] The anode of the first diode and the output end of the in-phase buffer are connected together as the first end of the switch control unit, the cathode of the first diode is the second end of the switch control unit, and the input end of the in-phase buffer is the controlled end of the switch control unit.

[0019] Furthermore, the voltage reset unit includes: a third resistor, a fourth resistor, a fifth resistor and a fourth switch tube;

[0020] The first end of the fourth resistor is the signal input end of the voltage reset unit, the second end of the fourth resistor and the first end of the fifth resistor are commonly connected to the controlled end of the fourth switch tube, the second end of the fifth resistor and the low potential end of the fourth switch tube are commonly connected to the ground, the high potential end of the fourth switch tube is connected to the second end of the third resistor, and the first end of the third resistor is the output end of the voltage reset unit.

[0021] Further, the voltage output unit includes: a second operational amplifier;

[0022] The non-inverting input terminal of the second operational amplifier is the input terminal of the voltage output unit, and the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier are connected together as the output terminal of the voltage output unit.

[0023] Further, the first switch tube is an NMOS tube, the second switch tube is a first PNP type transistor, and the third switch tube is a second PNP type transistor;

[0024] The gate of the NMOS tube is the controlled end of the first switch tube, the drain of the NMOS tube is the high potential end of the first switch tube, the source of the NMOS tube is the low potential end of the first switch tube, the base of the first PNP type transistor is the controlled end of the second switch tube, the emitter of the first PNP type transistor is the high potential end of the second switch tube, the collector of the first PNP type transistor is the low potential end of the second switch tube, the base of the second PNP type transistor is the controlled end of the third switch tube, the emitter of the second PNP type transistor is the high potential end of the third switch tube, and the collector of the second PNP type transistor is the low potential end of the third switch tube.

[0025] Furthermore, the fourth switch tube is an NPN transistor;

[0026] The base of the NPN transistor is the controlled end of the fourth switch tube, the collector of the NPN transistor is the high potential end of the fourth switch tube, and the emitter of the NPN transistor is the low potential end of the fourth switch tube.

[0027] A second aspect of the embodiments of the present application provides a device for measuring a time difference of a second pulse signal, comprising: a processing unit and the circuit for measuring a time difference of a second pulse signal described in the first aspect above;

[0028] The processing unit is connected to the output end of the voltage output unit;

[0029] The processing unit is used to calculate the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal based on the first voltage value and the second voltage value.

[0030] The circuit and device for measuring the time difference of a second pulse signal provided by the embodiment of the present application have the following beneficial effects:

[0031] The embodiment of the present application provides a circuit for measuring the time difference of a second pulse signal. The phase detector unit performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal. The time voltage conversion unit controls the charging of the integral capacitor contained therein based on the voltage conversion control signal, thereby converting the time difference between the second pulse signal to be measured and the reference second pulse signal into a corresponding voltage value. The voltage reset unit controls the discharge of the integral capacitor, thereby obtaining a second voltage value corresponding to the voltage remaining at both ends of the integral capacitor. The voltage output unit reads the first voltage value after the integral capacitor is charged and the second voltage value after the integral capacitor is discharged, thereby calculating the time difference between the second pulse signal to be measured and the reference second pulse signal based on the difference between the first voltage value and the second voltage value. It can be seen that the circuit structure of the present application is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 It is a structural block diagram of a circuit for measuring the time difference of a second pulse signal provided in an embodiment of the present application;

[0034] Figure 2 is a structural block diagram of a circuit for measuring a time difference of a second pulse signal provided by another embodiment of the present application;

[0035] Figure 3 It is a specific circuit diagram of a circuit for measuring the time difference of a second pulse signal provided in an embodiment of the present application;

[0036] Figure 4 It is a structural block diagram of a device for measuring the time difference of a second pulse signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] It should be noted that the term "comprising" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, a system, product or device comprising a series of units is not limited to the listed units, but may optionally include steps or units that are not listed, or may optionally include other units that are inherent to these products or devices. In addition, the terms "first", "second" and "third" are used to distinguish different objects, rather than to describe a specific order.

[0039] The embodiment of the present application provides a circuit for measuring the time difference of a second pulse signal. The phase detector unit performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal. The time voltage conversion unit controls the charging of the integral capacitor contained therein based on the voltage conversion control signal, thereby converting the time difference between the second pulse signal to be measured and the reference second pulse signal into a corresponding voltage value. The voltage reset unit controls the discharge of the integral capacitor, thereby obtaining a second voltage value corresponding to the voltage remaining at both ends of the integral capacitor. The voltage output unit reads the first voltage value after the integral capacitor is charged and the second voltage value after the integral capacitor is discharged, thereby calculating the time difference between the second pulse signal to be measured and the reference second pulse signal based on the difference between the first voltage value and the second voltage value. It can be seen that the circuit structure of the present application is simple and the cost is low.

[0040] Figure 1 This is a structural block diagram of a circuit for measuring the time difference of a second pulse signal provided by an embodiment of the present application. For the sake of convenience, only the part related to the embodiment of the present application is shown, which is described in detail as follows:

[0041] See also Figure 1 The circuit 100 for measuring the time difference of a second pulse signal provided by the embodiment of the present application includes: a phase detector unit 11, a time voltage conversion unit 12, a voltage reset unit 13 and a voltage output unit 14. Among them:

[0042] The phase detection unit 11 includes a reference signal input terminal, a signal to be measured input terminal and an output terminal. The reference signal input terminal of the phase detection unit 11 is used to receive a reference second pulse signal, and the signal to be measured input terminal of the phase detection unit 11 is used to receive the second pulse signal to be measured. The output terminal of the phase detection unit 11 is connected to the controlled terminal of the time-voltage conversion unit 12; the phase detection unit 11 performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal, and outputs the voltage conversion control signal to the controlled terminal of the time-voltage conversion unit 12.

[0043] The time-to-voltage conversion unit 12 includes an input terminal, a controlled terminal, a voltage control terminal, and an integral capacitor ( Figure 1 (not shown), the input end of the time-to-voltage conversion unit 12 is used to connect to a reference voltage source; when the time-to-voltage conversion unit 12 detects that the voltage conversion control signal is a charging signal, it charges the integral capacitor contained therein, and when the time-to-voltage conversion unit 12 detects that the voltage conversion control signal is a charging stop signal, it stops charging the integral capacitor contained therein.

[0044] The voltage reset unit 13 includes an input end and an output end. The input end of the voltage reset unit 13 is used to receive a voltage reset signal. The output end of the voltage reset unit 13 and the voltage control end of the time voltage conversion unit 12 are connected to the input end of the voltage output unit 14. When the voltage reset unit 13 detects that the voltage reset signal is a discharge signal, the integral capacitor in the time voltage conversion unit 12 is controlled to discharge. When the voltage reset signal is detected to be a discharge stop signal, the integral capacitor in the time voltage conversion unit 12 is controlled to stop discharging.

[0045] The voltage output unit 14 includes an input end and an output end. The voltage output unit 14 reads a first voltage value of the integral capacitor after charging stops and a second voltage value of the integral capacitor after discharging stops through its input end, and outputs the first voltage value and the second voltage value through its output end.

[0046] In the embodiment of the present application, the reference voltage source is used to output a preset reference voltage to the time voltage conversion unit 12. The voltage value of the preset reference voltage can be set according to actual needs and is not limited here.

[0047] In practical applications, the reset control signal can be determined according to the specific circuit structure of the voltage reset unit 13, and no limitation is made here. Exemplarily, as one embodiment of the present application, when the reset signal is a high-level signal, the reset signal can be considered as a discharge signal; when the reset signal is a low-level signal, the reset signal can be considered as a discharge stop signal, that is, when the integral capacitor needs to be discharged, a high-level signal is input to the voltage reset unit 13; when the integral capacitor needs to be stopped from being discharged, a low-level signal is input to the voltage reset unit 13. As another embodiment of the present application, when the reset signal is a low-level signal, the reset signal can be considered as a discharge signal; when the reset signal is a high-level signal, the reset signal can be considered as a discharge stop signal, that is, when the integral capacitor needs to be discharged, a low-level signal is input to the voltage reset unit 13; when the integral capacitor needs to be stopped from being discharged, a high-level signal is input to the voltage reset unit 13.

[0048] In the embodiment of the present application, the voltage conversion control signal obtained by the phase detector unit 11 performing an XOR operation on the reference second pulse signal and the second pulse signal to be measured is a pulse signal, the pulse width of the pulse signal is the time difference between the rising edge of the reference second pulse signal and the rising edge of the second pulse signal to be measured, the rising edge of the pulse signal is the charging signal, which is used to control the time voltage conversion unit 12 to charge the integral capacitor contained therein, the falling edge of the pulse signal is the charging stop signal, which is used to control the time voltage conversion unit 12 to stop charging the integral capacitor contained therein, the time voltage conversion unit 12 controls the charging of the integral capacitor based on the pulse signal, so that the pulse width of the pulse signal can be linearly converted into a corresponding voltage value, and the voltage output unit 14 reads and outputs the first voltage value after the integral capacitor is charged. It should be noted that, since there is usually a residual voltage at both ends of the integral capacitor, the voltage reset unit 13 is used to control the discharge of the integral capacitor, and the voltage output unit 14 is used to read and output the second voltage value of the integral capacitor after the discharge is completed, and the voltage difference between the first voltage value and the second voltage value is the voltage drop corresponding to the pulse width of the pulse signal. Therefore, the tester can calculate the time difference between the second pulse signal to be tested and the reference second pulse signal according to the difference between the first voltage value and the second voltage value and the preset conversion relationship between the voltage value and the time difference.

[0049] Figure 2 is a structural block diagram of a circuit for measuring the time difference of a second pulse signal provided by another embodiment of the present application. For the sake of convenience, only the part related to the embodiment of the present application is shown. Please refer to Figure 2 , relative to Figure 1 Corresponding to the embodiment, in a circuit for measuring the time difference of a second pulse signal provided by this embodiment, the time-to-voltage conversion unit 12 includes: a constant current source unit 121, a switch control unit 122 and an integrating capacitor C1.

[0050] The constant current source unit 121 includes a power supply end, an input end and an output end. The power supply end of the constant current source unit 121 is connected to the first power supply, the input end of the constant current source is the input end of the time voltage conversion unit 12, and the output end of the constant current source unit 121 is connected to the first end of the switch control unit 122.

[0051] The switch control unit 122 includes a first end, a second end and a controlled end, the integrating capacitor C1 includes a first end and a second end, the second end of the switch control unit 122 is connected to the first end of the integrating capacitor C1, the controlled end of the switch control unit 122 is the controlled end of the time-voltage conversion unit 12, the first end of the integrating capacitor C1 is the voltage control end of the time-voltage conversion unit 12, and the second end of the integrating capacitor C1 is grounded.

[0052] In this embodiment, the first power supply provides a power supply voltage VCC for the constant current source unit 121. If the switch control unit 122 detects that the voltage conversion control signal output by the phase detection unit 11 is a charging signal, the constant current source unit 121 is turned on to supply power to the integral capacitor C1, so that the constant current source unit 121 charges the integral capacitor C1; if the switch control unit 122 detects that the voltage conversion control signal output by the phase detection unit 11 is a charging stop signal, the constant current source unit 121 is turned off to supply power to the integral capacitor C1, so that the constant current source unit 121 stops charging the integral capacitor C1. At this time, the voltage output unit 14 reads the first voltage value of the first end of the integral capacitor C1 after charging is completed.

[0053] When the integrating capacitor C1 needs to be discharged, a discharge signal can be input to the voltage reset unit 13, and the voltage reset unit 13 turns on the path between the first end of the integrating capacitor C1 and the ground based on the discharge signal to control the integrating capacitor C1 to discharge; after the integrating capacitor C1 is discharged, a discharge stop signal can be output to the voltage reset unit 13, and the voltage reset unit 13 disconnects the path between the first end of the integrating capacitor C1 and the ground based on the discharge stop signal to control the integrating capacitor C1 to stop discharging, and the voltage output unit 14 reads the second voltage value of the first end of the integrating capacitor C1 after the discharge is completed.

[0054] Figure 3 This is a specific circuit diagram of a circuit for measuring the time difference of a second pulse signal provided by an embodiment of the present application. For the sake of convenience, only the part related to the embodiment of the present application is shown. Please refer to Figure 3 , relative to Figure 1 or Figure 2 Corresponding to the embodiment, in a circuit for measuring the time difference of a second pulse signal provided by this embodiment, the phase detection unit 11 includes: an XOR gate U1.

[0055] The first input terminal 1PPS_ref of the XOR gate U1 is the reference signal input terminal of the phase detection unit 11, the second input terminal 1PPS_dut of the XOR gate U1 is the test signal input terminal of the phase detection unit 11, and the output terminal of the XOR gate U1 is the output terminal of the phase detection unit.

[0056] Furthermore, the constant current source unit 121 includes: a first operational amplifier U2, a first resistor R1, a second resistor R2, a first switch tube Q1, a second switch tube Q2 and a third switch tube Q3.

[0057] The non-inverting input terminal of the first operational amplifier U2 is the input terminal of the constant current source unit 121, the inverting input terminal of the first operational amplifier U2 and the low potential terminal of the first switch tube Q1 are connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded, the output terminal of the first operational amplifier U2 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the controlled end of the first switch tube Q1, the high potential terminal of the first switch tube Q1, the low potential terminal of the second switch tube Q2 and the controlled end of the second switch tube Q2 are connected to the controlled end of the third switch tube Q3, the high potential terminal of the second switch tube Q2 and the high potential terminal of the third switch tube Q3 are connected to the power supply terminal of the constant current source unit 121, and the low potential terminal of the third switch tube Q3 is the output terminal of the constant current source unit 121.

[0058] Furthermore, the switch control unit 122 includes: a first diode D1 and a common-mode buffer U3.

[0059] The anode of the first diode D1 and the output end of the in-phase buffer U3 are connected together as the first end of the switch control unit 122 , the cathode of the first diode D1 is the second end of the switch control unit 122 , and the input end of the in-phase buffer U3 is the controlled end of the switch control unit 122 .

[0060] The embodiment of the present application adopts a switch control unit composed of a first diode D1 and a common-mode buffer U3, which not only has high control efficiency but also has low cost.

[0061] Furthermore, the voltage reset unit 13 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a fourth switch tube Q4.

[0062] A first end of the fourth resistor R4 is a signal input end of the voltage reset unit 13, a second end of the fourth resistor R4 and a first end of the fifth resistor R5 are connected to a controlled end of the fourth switch tube Q4, a second end of the fifth resistor R5 and a low potential end of the fourth switch tube Q4 are connected to ground, a high potential end of the fourth switch tube Q4 is connected to a second end of the third resistor R3, and a first end of the third resistor R3 is an output end of the voltage reset unit 13.

[0063] Furthermore, the voltage output unit 14 includes: a second operational amplifier U4.

[0064] The non-inverting input terminal of the second operational amplifier U4 is the input terminal of the voltage output unit 14 , and the inverting input terminal of the second operational amplifier U4 and the output terminal of the second operational amplifier U4 are connected together as the output terminal of the voltage output unit 14 .

[0065] It should be noted that, in the embodiment of the present application, the second operational amplifier U4 is a common operational amplifier, which is used as a voltage follower in the circuit.

[0066] As an embodiment of the present application, the first switch tube Q1 may be an NMOS tube, the second switch tube Q2 may be a first PNP type transistor, and the third switch tube Q3 may be a second PNP type transistor.

[0067] The gate of the NMOS tube is the controlled end of the first switch tube Q1, the drain of the NMOS tube is the high potential end of the first switch tube Q1, the source of the NMOS tube is the low potential end of the first switch tube Q1, the base of the first PNP type transistor is the controlled end of the second switch tube Q2, the emitter of the first PNP type transistor is the high potential end of the second switch tube Q2, the collector of the first PNP type transistor is the low potential end of the second switch tube Q2, the base of the second PNP type transistor is the controlled end of the third switch tube Q3, the emitter of the second PNP type transistor is the high potential end of the third switch tube Q3, and the collector of the second PNP type transistor is the low potential end of the third switch tube Q3.

[0068] It should be noted that, in the embodiment of the present application, the second switch tube Q2 and the third switch tube Q3 have the same characteristics and parameters.

[0069] As an embodiment of the present application, the fourth switch tube Q4 may be an NPN transistor.

[0070] The base of the NPN transistor is the controlled end of the fourth switch tube Q4 , the collector of the NPN transistor is the high potential end of the fourth switch tube Q4 , and the emitter of the NPN transistor is the low potential end of the fourth switch tube Q4 .

[0071] The following combination Figure 3 The specific working principle of the circuit 100 for measuring the time difference of a second pulse signal provided by the present application is described in detail:

[0072] like Figure 3 As shown, the first operational amplifier U2, the first resistor R1, the second resistor R2 and the first switch tube Q1 constitute a first-stage constant current source circuit. According to the "virtual short" and "virtual open" characteristics of the in-phase input terminal and the inverting input terminal of the first operational amplifier U2, the current flowing through the second resistor R2 Since the gate-source leakage current of the first switch tube Q1 is extremely small, the drain current I flowing through the first switch tube Q1 is D =I R2 The second switch tube Q2 and the third switch tube Q3 form a current mirror circuit. The second switch tube Q2 and the third switch tube Q3 work in the amplification state. D =I C +2I B =I C +2I C / β, where I B is the base current of the second switch tube Q2 and the third switch tube Q3, IC is the collector current of the third switch tube Q3, β is the AC amplification factor of the second switch tube Q2 and the third switch tube Q3, and since β>>1, I C ≈I D When the temperature changes and the current flowing through the third switch tube Q3 changes, since the current of the left branch of the current mirror flows completely through the second resistor R2, and since this current causes deep negative feedback of the first operational amplifier U2, the first operational amplifier U2 adjusts the first switch tube Q1 so that the current flowing through the second resistor R2 remains unchanged, that is, I R2 remains unchanged, that is, the collector current I C It can be seen that the temperature stability of the circuit can be improved by using the constant current source unit 121 including the first operational amplifier U2, and because the first operational amplifier U2 does not directly participate in the charging process of the integral capacitor C1, the first operational amplifier U2 can be a common operational amplifier, thereby reducing costs.

[0073] When the rising edges of the reference second pulse signal and the second pulse signal to be measured do not reach the two input terminals of the XOR gate U1, the two input terminals of the XOR gate U1 are both low level, and at this time, the XOR gate U1 outputs a low level signal; when the rising edges of the reference second pulse signal and the second pulse signal to be measured reach the two input terminals of the XOR gate U1 at different times, that is, at a certain moment, one input terminal of the XOR gate U1 is low level and the other input terminal is high level, the XOR gate U1 outputs a high level signal; when the rising edges of the reference second pulse signal and the second pulse signal to be measured reach the two input terminals of the XOR gate U1 at the same time, the two input terminals of the XOR gate U1 are both high level, and at this time, the XOR gate outputs a low level signal. It can be seen that the phase detection unit 11 outputs a differential pulse signal of the reference second pulse signal and the second pulse signal to be measured, and the pulse width of the pulse signal is the time difference between the edges of the reference second pulse signal and the second pulse signal to be measured.

[0074] Specifically, when the rising edges of the reference second pulse signal and the second pulse signal to be measured do not reach the two input terminals of the XOR gate U1, the XOR gate U1 outputs a low-level signal. At this time, the output terminal of the in-phase buffer U3 is turned on to the ground and the on-resistance is extremely low. The voltage drop of the collector current of the third switch tube Q3 through the in-phase buffer U3 is extremely small, and the first diode D1 is cut off; when the rising edges of the reference second pulse signal and the second pulse signal to be measured reach the two input terminals of the XOR gate U1 at different times, the XOR gate U1 outputs a high-level signal. At this time, the output terminal of the in-phase buffer U3 is closed and in a high-resistance state, the collector current of the third switch tube Q3 remains unchanged, but the potential increases, the first diode D1 is turned on, and the current output by the collector of the third switch tube Q3 charges the integral capacitor C1 through the first diode D1; when the rising edges of the reference second pulse signal and the second pulse signal to be measured reach the input terminal of the XOR gate U1 at the same time, the XOR gate U1 outputs a low-level signal. At this time, the first diode D1 is cut off, and the integral capacitor C1 stops charging. At this time, the voltage at the first terminal of the integrating capacitor C1 is Among them, t is the time difference between the reference second pulse signal and the second pulse signal to be measured, and V0 is the original residual voltage on the integrating capacitor C1. It can be seen that the voltage across the integrating capacitor C1 is related to the collector current I of the third switch tube Q3. C It has a linear integral relationship with time.

[0075] Since the second operational amplifier U4 is a voltage follower, when the integral capacitor C1 stops charging, the first voltage value after the integral capacitor C1 stops charging can be read from the output terminal of the second operational amplifier U4. The first voltage value is V C1 .

[0076] After reading the first voltage value, it is necessary to reset the voltage across the integration capacitor C1, and then obtain the second voltage value of the voltage originally remaining across the integration capacitor C1. In the embodiment of the present application, since the fourth switch tube Q4 is an NPN-type triode, a high-level signal can be input at the first end of the fourth resistor R4 to forward bias the emitter junction of the fourth switch tube Q4, thereby turning on the fourth switch tube Q4, so that the integration capacitor C1 is discharged to the ground through the third resistor R3 and the collector-emitter of the fourth switch tube Q4; after the discharge of the integration capacitor C1 is completed, a low-level signal can be input at the first end of the fourth resistor R4 to turn off the fourth switch tube Q4, thereby stopping the discharge of the integration capacitor C1. After the integration capacitor C1 stops discharging, the second discharge voltage value after the integration capacitor C1 stops discharging can be read from the output end of the second operational amplifier U4, and the first voltage value is V0.

[0077] Finally, based on the formula Calculate the time difference between the second pulse signal to be measured and the reference second pulse signal. Where t is the time difference between the second pulse signal to be measured and the reference second pulse signal, is the first voltage value, V0 is the second voltage value, C1 is the capacitance of the integral capacitor C1, I C is the collector current of the third switch tube Q3, V ref is the voltage value of the preset reference voltage output by the reference voltage source connected to the time voltage conversion unit 12, and R2 is the resistance value of the second resistor R2.

[0078] It should be noted that, in the embodiment of the present application, the original residual voltage of the integral capacitor C1 is related to the fourth switch tube Q4. Using an NPN transistor as the fourth switch tube Q4 can greatly reduce the cut-off leakage current of the switch tube at high temperature. When the charging of the integral capacitor C1 stops, the voltage across the integral capacitor C1 will not change significantly due to the leakage current of the switch tube, thereby improving the stability of the circuit.

[0079] The present application also provides a device for measuring the time difference of a second pulse signal, such as Figure 4 As shown, the device 1000 for measuring the time difference of a second pulse signal comprises: a processing unit 101 and the circuit 100 for measuring the time difference of a second pulse signal described in the above embodiment. Wherein:

[0080] The processing unit 101 is connected to the output terminal of the voltage output unit 14 .

[0081] The processing unit 101 is used for calculating the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal based on the first voltage value and the second voltage value.

[0082] In this embodiment, the processing unit 101 is specifically based on the formula Calculate the time difference between the second pulse signal to be measured and the reference second pulse signal. Where t is the time difference between the second pulse signal to be measured and the reference second pulse signal, is the first voltage value, V0 is the second voltage value, C1 is the capacitance of the integral capacitor C1, I C is the collector current of the third switch tube Q3, V ref is the voltage value of the preset reference voltage output by the reference voltage source connected to the time voltage conversion unit 12, and R2 is the resistance value of the second resistor R2.

[0083] In practical applications, the processing unit may be a data processing chip.

[0084] The device for measuring the time difference of a second pulse signal provided in this embodiment can directly output the time difference between the second pulse signal to be measured and the reference second pulse signal, without the need for manual calculation, thus saving labor costs.

[0085] As can be seen from the above, the circuit and device for measuring the time difference of a second pulse signal provided by the present embodiment, performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured through the phase discrimination unit to obtain a voltage conversion control signal, and controls the charging of the integral capacitor contained therein based on the voltage conversion control signal through the time voltage conversion unit, thereby converting the time difference between the second pulse signal to be measured and the reference second pulse signal into a corresponding voltage value, and controls the discharge of the integral capacitor through the voltage reset unit, thereby obtaining a second voltage value corresponding to the voltage remaining at both ends of the integral capacitor, and reading the first voltage value after the integral capacitor is charged and the second voltage value after the integral capacitor is discharged through the voltage output unit, thereby calculating the time difference between the second pulse signal to be measured and the reference second pulse signal based on the difference between the first voltage value and the second voltage value. It can be seen that the circuit structure of the present application is simple and the cost is low.

[0086] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A circuit for measuring the time difference of a second pulse signal, characterized in that: include: Phase detection unit, time voltage conversion unit, voltage reset unit and voltage output unit; The phase discrimination unit comprises a reference signal input terminal, a signal to be measured input terminal and an output terminal, wherein the reference signal input terminal is used to receive a reference second pulse signal, the signal to be measured input terminal is used to receive a second pulse signal to be measured, and the output terminal of the phase discrimination unit is electrically connected to the controlled terminal of the time-voltage conversion unit; the phase discrimination unit performs an XOR operation on the received reference second pulse signal and the second pulse signal to be measured to obtain a voltage conversion control signal, and outputs the voltage conversion control signal to the controlled terminal of the time-voltage conversion unit via the output terminal of the phase discrimination unit; The time-to-voltage conversion unit comprises an input terminal, a controlled terminal, a voltage control terminal and an integral capacitor, wherein the input terminal of the time-to-voltage conversion unit is used to connect to a reference voltage source; when the time-to-voltage conversion unit detects that the voltage conversion control signal is a charging signal, the time-to-voltage conversion unit charges the integral capacitor, and when the time-to-voltage conversion unit detects that the voltage conversion control signal is a charging stop signal, the time-to-voltage conversion unit stops charging the integral capacitor; The voltage reset unit comprises an input end and an output end, the input end of the voltage reset unit is used to receive a voltage reset signal, and the output end of the voltage reset unit and the voltage control end of the time voltage conversion unit are connected to the input end of the voltage output unit; when the voltage reset unit detects that the voltage reset signal is a discharge signal, the voltage reset unit controls the integral capacitor to discharge, and when the voltage reset signal is detected to be a discharge stop signal, the voltage reset unit controls the integral capacitor to stop discharging; The voltage output unit comprises an input end and an output end, the voltage output unit reads a first voltage value of the integral capacitor after charging stops and a second voltage value of the integral capacitor after discharging stops through its input end, and the voltage output unit outputs the first voltage value and the second voltage value through its output end; The time-to-voltage conversion unit further includes: a constant current source unit and a switch control unit; The constant current source unit comprises a power supply end, an input end and an output end, the power supply end of the constant current source unit is connected to the first power supply, the input end of the constant current source is the input end of the time voltage conversion unit, and the output end of the constant current source unit is connected to the first end of the switch control unit; The switch control unit includes a first end, a second end and a controlled end, the integration capacitor includes a first end and a second end, the second end of the switch control unit is connected to the first end of the integration capacitor, the controlled end of the switch control unit is the controlled end of the time-to-voltage conversion unit, the first end of the integration capacitor is the voltage control end of the time-to-voltage conversion unit, and the second end of the integration capacitor is grounded; The phase detection unit comprises: an XOR gate; The first input end of the XOR gate is the reference signal input end of the phase detection unit, the second input end of the XOR gate is the input end of the signal to be tested of the phase detection unit, and the output end of the XOR gate is the output end of the phase detection unit.

2. The circuit for measuring the time difference of a second pulse signal according to claim 1, characterized in that: The constant current source unit includes: a first operational amplifier, a first resistor, a second resistor, a first switch tube, a second switch tube and a third switch tube; The non-inverting input terminal of the first operational amplifier is the input terminal of the constant current source unit, the inverting input terminal of the first operational amplifier and the low potential terminal of the first switch tube are commonly connected to the first end of the second resistor, the second end of the second resistor is grounded, the output terminal of the first operational amplifier is connected to the first end of the first resistor, the second end of the first resistor is connected to the controlled end of the first switch tube, the high potential terminal of the first switch tube, the low potential terminal of the second switch tube and the controlled end of the second switch tube are commonly connected to the controlled end of the third switch tube, the high potential terminal of the second switch tube and the high potential terminal of the third switch tube are commonly connected as the power supply terminal of the constant current source unit, and the low potential terminal of the third switch tube is the output terminal of the constant current source unit.

3. The circuit for measuring the time difference of a second pulse signal according to claim 1, characterized in that: The switch control unit comprises: a first diode and a common-phase buffer; The anode of the first diode and the output end of the in-phase buffer are connected together as the first end of the switch control unit, the cathode of the first diode is the second end of the switch control unit, and the input end of the in-phase buffer is the controlled end of the switch control unit.

4. The circuit for measuring the time difference of a second pulse signal according to claim 1, characterized in that: The voltage reset unit includes: a third resistor, a fourth resistor, a fifth resistor and a fourth switch tube; The first end of the fourth resistor is the signal input end of the voltage reset unit, the second end of the fourth resistor and the first end of the fifth resistor are commonly connected to the controlled end of the fourth switch tube, the second end of the fifth resistor and the low potential end of the fourth switch tube are commonly connected to the ground, the high potential end of the fourth switch tube is connected to the second end of the third resistor, and the first end of the third resistor is the output end of the voltage reset unit.

5. The circuit for measuring the time difference of a second pulse signal according to claim 1, characterized in that: The voltage output unit includes: a second operational amplifier; The non-inverting input terminal of the second operational amplifier is the input terminal of the voltage output unit, and the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier are connected together as the output terminal of the voltage output unit.

6. The circuit for measuring the time difference of a second pulse signal according to claim 2, characterized in that: The first switch tube is an NMOS tube, the second switch tube is a first PNP type transistor, and the third switch tube is a second PNP type transistor; The gate of the NMOS tube is the controlled end of the first switch tube, the drain of the NMOS tube is the high potential end of the first switch tube, the source of the NMOS tube is the low potential end of the first switch tube, the base of the first PNP type transistor is the controlled end of the second switch tube, the emitter of the first PNP type transistor is the high potential end of the second switch tube, the collector of the first PNP type transistor is the low potential end of the second switch tube, the base of the second PNP type transistor is the controlled end of the third switch tube, the emitter of the second PNP type transistor is the high potential end of the third switch tube, and the collector of the second PNP type transistor is the low potential end of the third switch tube.

7. The circuit for measuring the time difference of a second pulse signal according to claim 4, characterized in that: The fourth switch tube is an NPN transistor; The base of the NPN transistor is the controlled end of the fourth switch tube, the collector of the NPN transistor is the high potential end of the fourth switch tube, and the emitter of the NPN transistor is the low potential end of the fourth switch tube.

8. A device for measuring the time difference of a second pulse signal, characterized in that: include: A processing unit and a circuit for measuring the time difference of a second pulse signal as claimed in any one of claims 1 to 7; The processing unit is connected to the output end of the voltage output unit; The processing unit is used to calculate the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal based on the first voltage value and the second voltage value.

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