Semiconductor memory device and process method

Abstract

The present invention discloses a semiconductor memory device having a multilayer bitline structure comprising a lower conductive material, a middle conductive material, an upper conductive material, and a top hard mask layer. The lower conductive material, the middle conductive material, and the upper conductive material are sequentially stacked to form a multilayer conductive structure. A bitline contact groove is also provided in the semiconductor substrate. The bitline is located on an insulating interlayer on the surface of the semiconductor substrate and in the bitline contact groove. The bitline located on the insulating interlayer has a large lateral contact area with the insulating interlayer, while the bitline located in the bitline contact groove has a small lateral contact area with the bottom of the bitline contact groove, thereby improving lateral isolation between the bitlines and reducing leakage. The manufacturing process of the present invention achieves a cross-sectional morphology with alternating lateral contact widths of different bitlines through a single etching process, without adding additional process steps.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device design and manufacturing technology, and in particular to a semiconductor memory device and a process method for the semiconductor memory device. Background Art

[0002] like Figure 1 Figure 2 shows a top-down view of a conventional semiconductor memory device. The figure includes multiple parallel word lines WL extending in a first direction. The word lines connect the polysilicon control gates of memory transistors, with contact plugs or device isolation layers between them. In a second direction, perpendicular to the word lines, run the memory's bit lines BL. The intersection of the bit lines BL and word lines WL forms the structural area of the memory transistors. The figure also features long, rod-like active areas ACT. In traditional memory device structures, these active areas ACT are typically oriented in either the first or second direction. However, with technological advancements and the demand for higher storage densities, today's active areas ACT are typically designed at an angle to the first or second direction, creating a tilted arrangement. Each active area ACT is parallel to the others and separated by a device isolation layer, typically formed as a trench structure. The circled area in the figure represents the bit line contact recess.

[0003] Figure 2 This is a cross-sectional view of an existing semiconductor memory device, that is, Figure 1 The AA line cross-section shown in the figure has the following structure:

[0004] In the semiconductor substrate, word lines WL extend in a first direction.

[0005] The bit line structure crosses over the word line and extends in the second direction perpendicular to the first direction, with an isolation layer between the bit line and the word line, that is, the bit line passes over the word line and intersects the word line perpendicularly, and the two are not on the same plane.

[0006] The word line extends in a first direction and is generally made of at least one material selected from polysilicon, metal silicide, and metal. A gate dielectric layer, generally an oxide layer, is located below the word line.

[0007] The active area ACT between the bit line BL and the word line WL includes an implantation region of the storage tube, and implantation regions of different doping types are located on both sides of the device isolation layer (trench).

[0008] The figure also has a bit line contact groove 3, which corresponds to the bit line contact groove 3 Figure 1 At the circle in FIG. 3 , the bit line contact is located in the bit line contact groove 3 .

[0009] Figure 3 yes Figure 1A cross-sectional view along line BB, where the cross-sectional structure of the word line can be seen.

[0010] Figure 4 This is a further enlarged view of the bitline connection. The bitline typically comprises a stacked structure consisting of a lower layer of conductive material, a middle layer of conductive material, an upper layer of conductive material, and a top hard mask layer. The lower layer of conductive material is typically composed of heavily doped polysilicon, while the middle / upper layers are typically composed of metal silicide and / or metal (such as tungsten, aluminum, titanium, or tantalum). The top hard mask layer is typically made of silicon nitride. The bitline is typically located in a recess 3 above the bitline, with the space in the recess outside the bitline filled with an isolation dielectric.

[0011] The bit line structure of a conventional semiconductor memory device has a relatively symmetrical shape in the semiconductor substrate, and its cross section does not have a significant width change. In the existing bit line structure, the interval SC between the bit lines is relatively small. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a semiconductor memory device, wherein the cross-sectional structure of the bit lines has a morphology with alternating lateral widths, which can increase the spacing between the bit lines and reduce leakage between the bit lines.

[0013] Another technical problem to be solved by the present invention is to provide a process method for the semiconductor memory device.

[0014] To solve the above problems, the semiconductor memory device of the present invention comprises:

[0015] A semiconductor substrate is provided with a device isolation layer in the semiconductor substrate, and a plurality of active regions are isolated between the device isolation layers; and an insulating interlayer is provided on the surface of the semiconductor substrate.

[0016] The semiconductor substrate further includes a plurality of word lines extending along a first direction and passing through the active region, and each word line is isolated from each other.

[0017] A plurality of bit lines are provided, wherein the plurality of bit lines pass through the active region in the semiconductor substrate and extend along a second direction; the second direction is perpendicular to the first direction.

[0018] The plurality of active regions are in strip shape and parallel to each other, and extend in the first direction or the second direction, or have an angle with the first direction and the second direction.

[0019] There is also a bit line above the bit line to lead out the bit line.

[0020] The semiconductor substrate surface also has bit line contact grooves, which are arranged at intervals, that is, each non-adjacent bit line is located on the insulating interlayer on the semiconductor substrate surface, and another non-adjacent bit line is located in the bit line contact groove, and is arranged in a cross-interval.

[0021] The bit line has a multi-layer structure, including a lower conductive material, a middle conductive material, an upper conductive material and a top hard mask layer; the lower conductive material, the middle conductive material and the upper conductive material are stacked in sequence to form a composite layer; the lower conductive material alternately contacts the insulating interlayer on the semiconductor substrate, or the bottom of the bit line contact groove.

[0022] The width of the contact surface between the lower conductive material of each bit line and the insulating interlayer and the bottom of the bit line contact groove in the cross section is alternating in size, that is, the lateral contact width between the lower conductive material of the bit line on the insulating interlayer and the insulating interlayer is large, while the lateral contact width between the lower conductive material of the bit line located in the bit line contact groove and the bottom of the bit line contact groove is small; so that the contact portion between the lower conductive material of each bit line and the insulating interlayer or the bottom of the bit line contact groove in the cross section is alternating in thickness.

[0023] A further improvement is that an isolation medium is provided between the bit line located in the bit line contact groove and the semiconductor substrate on the sidewall.

[0024] A further improvement is that the cross section of the lower conductive material of the bit line is an inverted trapezoid, or other geometric shapes with a larger top and smaller bottom.

[0025] A further improvement is that the lower conductive material is heavily doped polysilicon, the middle / upper conductive material is heavily doped polysilicon, metal silicide, metal nitride or one of the metals, and the top hard mask layer is an insulating dielectric layer, generally a silicon nitride layer.

[0026] A further improvement is that the metal is tungsten, aluminum, titanium or tantalum.

[0027] A further improvement is that the device isolation layer is trench isolation.

[0028] A further improvement is that the word line further has a first doping region and a second doping region on both sides, and the bottom surfaces of the first doping region and the second doping region are both located at a specific depth downward from the top surface of the active region.

[0029] A further improvement is that an insulating medium is filled between the bit lines.

[0030] In order to solve the above problems, the present invention also provides a method for manufacturing the semiconductor memory device, comprising the following steps:

[0031] Step 1: forming a device isolation layer in a semiconductor substrate, and defining a plurality of active regions by the device isolation layer.

[0032] Step 2: forming word line polysilicon along a first direction in the semiconductor substrate, implanting doping to form a first doping region and a second doping region, and forming a bit line along a second direction above the word line polysilicon.

[0033] Step 3: Etch a bit line contact groove in the semiconductor substrate to produce a bit line. The bit line comprises a four-layer structure from bottom to top, which is formed by sequentially depositing corresponding materials, including a lower conductive material, a middle conductive material, an upper conductive material, and a top hard mask layer. The lower conductive material and the upper conductive material are etched to form a morphology in which the lateral width of the lower conductive material in contact with the insulating interlayer or the bottom of the bit line contact groove changes alternately, that is, the bottom surface lateral width of the lower conductive material of the bit line located on the insulating interlayer is large, and the bottom surface lateral width of the lower conductive material of the bit line located in the bit line contact groove is small.

[0034] Step 4: Deposit insulating dielectric to complete the subsequent process of semiconductor memory.

[0035] A further improvement is that in step 1, the device isolation layer is formed by a trench process, wherein a trench is etched in the semiconductor substrate and then an insulating dielectric layer is filled in the trench.

[0036] A further improvement is that in step 2, the first doping region and the second doping region can be doped with impurities of the same doping type as the substrate, and the first doping region and the second doping region may have the same doping type; the first doping region and the second doping region can also form different injection depths through different ion injection parameters, thereby having different junction depths.

[0037] A further improvement is that in the step three, the etching of the upper conductive material, the middle conductive material and the lower conductive material forms a morphology in which the bottom lateral contact width of the bit line located on the insulating interlayer is large, and the bottom lateral contact width of the bit line located in the bit line contact groove is small, which is formed by synchronous etching; when the upper conductive material, the middle conductive material and the lower conductive material are etched, the etching of the upper conductive material, the middle conductive material and the lower conductive material of the bit line with a larger lateral contact width is stopped due to etching to the substrate, and to form a bit line with a smaller lateral contact width, that is, the bit line in the bit line contact groove, the lower conductive material, the middle conductive material and the upper conductive material need to continue to be etched downward, and there is also synchronous lateral etching in the etching process, forming a morphology in which the bottom lateral contact width of the bit line on the insulating dielectric layer is large, and the bottom lateral contact width of the bit line located in the bit line contact groove is small.

[0038] A further improvement is that the bottom lateral contact width of the bit line on the insulating dielectric layer is large, and the bottom lateral contact width of the bit line located in the bit line contact groove is small. This is achieved by adjusting the layout and opening an appropriate window size during etching.

[0039] A further improvement is that in step three, the lower conductive material is heavily doped polysilicon, the middle conductive material and the upper conductive material are one of metal silicide, metal nitride or metal, and the top hard mask layer is an insulating dielectric layer, preferably a silicon nitride layer.

[0040] A further improvement is that, in step three, the upper conductive material, the middle conductive material and the lower conductive material are etched using a dry etching process.

[0041] The semiconductor memory device of the present invention adjusts the cross-sectional structure of conventional bit lines by alternating the lateral contact widths between the underlying conductive material and the insulating interlayer or bit line contact grooves in different bit lines. This further increases the lateral spacing between the different bit lines, improves the lateral isolation between the bit lines, and thus further reduces leakage between the bit lines. The manufacturing process of the present invention achieves the cross-sectional topography of the bit lines (primarily the underlying conductive material) with alternating lateral contact widths in a single etching process, requiring only simple layout adjustments without adding additional process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a plan view of a semiconductor memory device.

[0043] Figure 2 is a cross-sectional view of a semiconductor memory device, and is Figure 1 Cross-sectional view at the midline AA.

[0044] Figure 3 is a cross-sectional view of a semiconductor memory device, and is Figure 1 Cross-sectional view of the midline BB.

[0045] Figure 4 This is a further enlarged view of the bit line structure.

[0046] Figure 5 It is a schematic diagram of the cross-sectional appearance of the bit line of the semiconductor memory device of the present invention.

[0047] Figure 6 This is a diagram showing the completion of the three-layer structure deposition of the bit line of the present invention.

[0048] Figures 7-8 It is a schematic diagram of the bit line etching process of the present invention.

[0049] Figure 9It is a plan view of the memory device of the present invention, wherein the bit lines show thickness variations.

[0050] Description of Reference Numerals

[0051] 1 is the substrate, 2 is the device isolation layer (isolation trench), 3 is the bit line contact groove, 4 is the word line polysilicon hard mask layer, 5 is the lower conductive material, 6 is the middle conductive material 1, 7 is the top hard mask layer, 8 is the upper conductive material, 9 is the insulating interlayer, ACT is the active area, BL is the bit line, WL is the word line, d, d1, d2 are the lateral widths between the bit lines, d3 is the lateral width of the upper top surface of the lower conductive material, d4 is the lateral width of the middle conductive material, d5 is the lateral width of the bottom surface of the middle conductive material, and BLS is the overall bit line structure. DETAILED DESCRIPTION

[0052] The structure of the semiconductor memory device described in the present invention is described below in conjunction with the accompanying drawings. It should be noted that the drawings in the specification are only used to illustrate the approximate position and morphology of each structural unit in conjunction with the specification. The sizes, proportions, and relative positions in the drawings do not represent actual parameters in the device manufacturing process and are only used to explain the technical solution of the present invention. At the same time, for the sake of brevity and clarity of explanation, only the inventive part of the present invention is highlighted in this application. Other structural parts of the memory device that are not the focus of the present invention are well-known technologies and will not be described in detail. In addition, other structural parts of the memory device that are not the focus of the present invention or are not involved in the present invention are not shown in the drawings of the specification.

[0053] The semiconductor memory device of the present invention is mainly aimed at the lead-out portion of the bit line, specifically, the structural morphology of the contact plug of the bit line is adjusted so that it has a geometric morphology of being larger at the top and smaller at the bottom in cross section, such as Figure 5 As shown, there is a bit line above the bit line polysilicon, and the bit line is led out.

[0054] The bit lines are multi-layer structures, including a lower conductive material, a middle conductive material, an upper conductive material and a top hard mask layer stacked in sequence; each bit line is spaced a certain distance apart.

[0055] In the prior art, the upper and lower conductive materials and the top hard mask layer of the bit line are basically aligned side by side, that is, the lateral widths of the layers are consistent, such as Figure 4 As shown in the cross-sectional morphology, due to the high storage density of existing memories, the lateral spacing between bit lines is small. The lateral spacing between the bit lines of this cross-sectional morphology is not optimized, that is, the isolation effect between them is not very good, which can easily cause leakage.

[0056] The cross-sectional morphology of the bit lines provided by the present invention is adjusted. The cross-sectional morphology of each bit line is mainly a morphology in which the width of the lower conductive material changes alternately. Figure 5 As shown, since the bit lines on the semiconductor substrate are alternately located on the insulating interlayer on the surface of the semiconductor substrate and in the bit line contact grooves in the semiconductor substrate, that is, the bottom lateral contact width d1 of the bit lines located on the insulating interlayer on the surface of the semiconductor substrate is large, while the bottom lateral contact width d2 of the bit lines located in the bit line contact grooves is small, d1>d2, each non-adjacent bit line has the same bottom lateral contact width, forming an alternating arrangement of large and small bits; the lateral distance between the bit lines is increased, the isolation effect between the bit lines is enhanced, and leakage is reduced.

[0057] Figure 5 In the bottom cross-section of the bit line shown in Figure 1, the cross-section of the lower conductive material is an inverted trapezoid. In reality, the cross-sections of the layers above also exhibit inverted trapezoidal shapes. This embodiment uses a trapezoidal shape as an example; other geometric shapes with similar top-larger, bottom-smaller structures are also applicable. The cross-sectional width of the top hard mask layer is not affected by the width of the contact surface between the upper and lower conductive materials.

[0058] Similar to the traditional structure, the lower conductive material is heavily doped polysilicon, the middle conductive material is one of metal silicide, metal nitride or metal, the upper conductive material is one of metal silicide, metal nitride or metal, and the top hard mask layer is an insulating dielectric layer, generally a silicon nitride layer.

[0059] This cross-sectional structure can increase the distance between the bit lines in the lateral direction, strengthen the isolation effect between the bit lines, and thus improve leakage.

[0060] The method for manufacturing a semiconductor memory device according to the present invention, with respect to a bit line, comprises the following steps:

[0061] Step 1: Complete the pre-processing in a semiconductor substrate, including forming a device isolation layer, defining multiple active areas using the device isolation layer, and other conventional steps. The device isolation layer is formed using a trench process, typically a shallow trench isolation process, in which trenches are etched in the semiconductor substrate and then filled with an insulating dielectric layer, such as silicon oxide. The semiconductor substrate also has an insulating interlayer, typically a silicon oxide layer, on its surface.

[0062] Each bit line contact groove is formed by etching on the surface of the semiconductor substrate.

[0063] Step 2: Wordline polysilicon is formed in the substrate along a first direction, and doped to form a first doped region and a second doped region. A bitline is also formed along a second direction above the wordline polysilicon. The first direction is perpendicular to the second direction, the wordline polysilicon is located in the lower layer, and the bitline polysilicon is located in the upper layer. The wordline and the bitline intersect perpendicularly and are not on the same plane. The first doped region and the second doped region can incorporate impurities of the same doping type as the substrate, and the first doped region and the second doped region can have the same doping type. The first doped region and the second doped region can also form different implantation depths by using different ion implantation parameters, thereby having different junction depths.

[0064] Step 3: Fabricate a bit line. The bit line comprises a four-layer structure from bottom to top, which is formed by sequentially depositing corresponding materials, including a lower conductive material, a middle conductive material, an upper conductive material, and a top hard mask layer. The above four-layer structure is formed by sequentially depositing, such as Figure 6 As shown, the upper conductive material is heavily doped polysilicon, and the middle conductive material and the lower conductive material are one of metal silicide, metal nitride or metal. For example, the middle conductive material is metal silicide, and the upper conductive material is metal. The top hard mask layer is an insulating dielectric layer, preferably made of silicon nitride. The bit lines are etched to form a morphology in which the lateral width of the contact surface at the bottom of the bit lines changes alternately, that is, the bottom lateral contact widths of two adjacent bit lines vary from large to small: the bottom lateral contact width d1 of the bit lines on the insulating interlayer on the surface of the semiconductor substrate is larger, while the bottom lateral contact width d2 of the bit lines located in the bit line contact groove is smaller.

[0065] In the present invention, the etching of the constituent materials of each layer of the bit line is carried out by using a dry etching process, so that different bit lines are formed with different bottom lateral contact widths, which is formed by synchronous etching. Figure 7 As shown, when etching the bit lines, the bit lines with a larger lateral contact width d1 are located at a higher position due to being located on the surface of the semiconductor substrate. The dry etching stops because it quickly etches the insulating interlayer on the surface of the substrate. The bit lines with a smaller lateral contact width d2 are located at a lower position in the bit line contact groove. The thickness of the underlying conductive material, such as polysilicon, is larger and has a larger etching amount. When etching continues downward and etching into the bit line contact groove, there is still a lateral etching amount, forming a cross-section of the underlying conductive material with a larger upper portion and a smaller lower portion, so that the lateral contact width d2 is smaller.

[0066] The alternating widths of the bottom lateral contact of the bit lines are achieved by adjusting the layout. By modifying the layout and appropriately adjusting the window size for etching the bit lines, this alternating width of the bottom lateral contact can be achieved. The specific window size parameters can be determined through a limited number of experiments.

[0067] By using the above process method, the lateral spacing between the bit lines is increased, the isolation effect is enhanced, and the leakage is reduced.

[0068] Step 4: depositing an insulating dielectric layer to complete the subsequent process of the semiconductor memory.

[0069] The above embodiment is one case listed in the present invention, that is, the lower conductive material presents a cross-sectional morphology of being larger at the top and smaller at the bottom. In some specific processes or other embodiments, it is also possible that after etching is completed, the cross-sectional structure of the lower conductive material does not have a significant change in thickness from top to bottom, which corresponds to Figure 5 The situation where d2 = d3 occurs in the example, which is also fully consistent with the technical concept of the present invention. However, whether d3 > d2 or d3 = d2, both d2 and d3 are smaller than the lateral width d4 of the middle conductive material. Of course, in either case, the lateral contact width d1 of the bit line located above the insulating interlayer is greater than d2, d3, and d4.

[0070] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that: include: A semiconductor substrate having a device isolation layer therein, wherein the device isolation layers are separated by a plurality of isolated active regions; The surface of the semiconductor substrate has an insulating interlayer; The semiconductor substrate further comprises a plurality of word lines extending along a first direction and passing through the active region, wherein the word lines are isolated from each other; a plurality of bit lines, the plurality of bit lines passing through the active region in the semiconductor substrate and extending along a second direction; the second direction is perpendicular to the first direction; The plurality of active regions are in strip shape and parallel to each other, and extend in the first direction or the second direction, or form an angle with the first direction or the second direction; The semiconductor substrate surface also has bit line contact grooves, and the bit line contact grooves are arranged at intervals, that is, the bit lines located on the insulating interlayer on the semiconductor substrate surface and the bit lines located in the bit line contact grooves are arranged alternately; The bit line has a multi-layer structure, comprising a lower conductive material, a middle conductive material, an upper conductive material, and a top hard mask layer; the lower conductive material, the middle conductive material, and the upper conductive material are stacked in sequence to form a composite layer; the lower conductive material alternately contacts the insulating interlayer on the semiconductor substrate, or the bottom of the bit line contact groove; the middle conductive material and the upper conductive material each comprise one of metal silicide, metal nitride, or metal; The lower conductive material of the bit line on the insulating interlayer has a first width in lateral contact with the insulating interlayer, and the lower conductive material of the bit line in the bit line contact groove has a second width in lateral contact with the bottom of the bit line contact groove; The first width is not equal to the second width.

2. The semiconductor memory device according to claim 1, wherein: A first lateral contact width between the lower conductive material of each bit line and the insulating interlayer and a second lateral contact width between the lower conductive material and the bottom of the bit line contact groove vary alternately in size in a cross section.

3. The semiconductor memory device according to claim 1, wherein: The cross section of the lower conductive material of the bit line is an inverted trapezoid, or other geometric shapes with a larger top and smaller bottom.

4. The semiconductor memory device according to claim 1, wherein: The top interface of the lower conductive material in the bit line is connected to the bottom interface of the middle conductive material, and the width of the top of the lower conductive material is smaller than the width of the bottom of the middle conductive material.

5. A semiconductor memory device, characterized in that: In a top view of a semiconductor substrate, the semiconductor memory device includes a plurality of parallel word lines extending along a first direction and a plurality of parallel bit lines extending along a second direction, wherein the plurality of parallel word lines are in one plane, and the plurality of parallel bit lines are in another plane above the word lines, and the word lines are perpendicular to the bit lines but do not intersect; The semiconductor substrate further comprises a plurality of active regions, the active regions being in the shape of rods and parallel to each other; The active area is located at the intersection of the word line and the bit line; The active area has a certain angle with the first direction or the second direction; the surface of the semiconductor substrate further has bit line contact grooves, and the bit line contact grooves are arranged at intervals in the first direction, that is, a bit line contact groove is placed for each bit line, and the bit line contact grooves in two adjacent different rows are staggered. The bit line contact grooves are also arranged at intervals in the second direction; The bit line is a structure with variable width, and the width of the bit line in the bit line contact groove is smaller than the width of the bit line outside the bit line contact groove.

6. The semiconductor memory device according to claim 5, wherein: The bit line is a multi-layer structure, including, from bottom to top, a lower layer of conductive material, a middle layer of conductive material, an upper layer of conductive material, and a top hard mask layer; each layer is stacked in sequence to form a bit line; the width of the lower layer of conductive material in the bit line is smaller than the width of the other layers above it, and the width of the lower layer of conductive material gradually narrows from its top surface to its bottom surface; the widths of the remaining layers are equal or unequal.

7. The semiconductor memory device according to claim 6, wherein: The lower bottom surface width of the lower conductive material of the bit line located outside the bit line contact groove is defined as d1, the lower bottom surface width of the lower conductive material of the bit line located in the bit line contact groove is defined as d2, the upper top surface width of the lower conductive material of the bit line located in the bit line contact groove is defined as d3, the contact width between the middle conductive material and the upper conductive material of the bit line located in the bit line contact groove is d4, and the width of the middle conductive material of the bit line located outside the bit line contact groove is defined as d5, wherein d1=d4=d5>d3>d2, or d5>d1=d4>d3>d2.

8. A method for manufacturing a semiconductor memory device according to claim 1, wherein: The steps include: Step 1: forming a device isolation layer in a semiconductor substrate, wherein the device isolation layer defines a plurality of active areas; Step 2: forming word line polysilicon along a first direction in the semiconductor substrate, and implanting doping to form a first doping region and a second doping region; Step 3: Etching a bit line contact groove in the semiconductor substrate, and forming a bit line along the second direction above the word line polysilicon, wherein the bit line comprises a four-layer structure from bottom to top, formed by sequentially depositing corresponding materials, including a lower conductive material, a middle conductive material, an upper conductive material, and a top hard mask layer; the lower conductive material and the upper conductive material are etched to form a morphology in which the lateral width of the lower conductive material in contact with the insulating interlayer or the bottom of the bit line contact groove alternates, i.e., the bottom surface of the lower conductive material of the bit line located on the insulating interlayer has a larger lateral width, while the bottom surface of the lower conductive material of the bit line located in the bit line contact groove has a smaller lateral width; Step 4: Deposit insulating dielectric to complete the subsequent process of semiconductor memory.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein: In the step three, the upper conductive material, the middle conductive material and the lower conductive material are etched to form a morphology in which the bottom lateral contact width of the bit line located on the insulating interlayer is large, and the bottom lateral contact width of the bit line located in the bit line contact groove is small, which is formed by synchronous etching; when the upper conductive material, the middle conductive material and the lower conductive material are etched, the upper conductive material, the middle conductive material and the lower conductive material of the bit line with a larger lateral contact width are stopped due to etching to the substrate, and to form a bit line with a smaller lateral contact width, that is, the bit line in the bit line contact groove, the lower conductive material, the middle conductive material and the upper conductive material need to continue to be etched downward, and there is also synchronous lateral etching in the etching process, forming a morphology in which the bottom lateral contact width of the bit line on the insulating interlayer is large, and the bottom lateral contact width of the bit line located in the bit line contact groove is small.

10. The method for manufacturing a semiconductor memory device according to claim 9, wherein: The morphology in which the bottom lateral contact width of the bit line on the insulating interlayer is large and the bottom lateral contact width of the bit line located in the bit line contact groove is small is achieved by adjusting the layout and opening an appropriate window size during etching.

Images