Semiconductor chip and semiconductor package including the semiconductor chip

Abstract

A semiconductor chip includes: a semiconductor substrate, a through electrode, an intermediate pad, an upper pad, and a redistribution wiring. The semiconductor substrate includes a first surface as an active surface and a second surface opposite to the first surface. The through electrode penetrates the semiconductor substrate and is arranged in at least one column along a first direction in the central portion of the semiconductor substrate. The intermediate pad is arranged in at least one column along the first direction in the edge portion of the second surface. The upper pad is arranged on the second surface and connected to the through electrode. The redistribution wiring is arranged on the second surface and connects the intermediate pad to the upper pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0079578 filed in the Korean Intellectual Property Office on Jul. 9, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a semiconductor package, and more particularly, to a semiconductor package having a structure in which semiconductor chips are stacked on a printed circuit board (PCB). Background Art

[0004] As electronic devices advance, they become smaller and lighter. Therefore, semiconductor packages used in electronic devices must also become smaller and lighter while still maintaining high reliability, high performance, and high capacity. Semiconductor chips are typically mounted in semiconductor packages on a printed circuit board (PCB) and are electrically connected to the PCB using bonding wires or connecting members. When large capacity is required, semiconductor packages can utilize a stacked structure in which multiple semiconductor chips are stacked and mounted on a PCB. Summary of the invention

[0005] Exemplary embodiments of the inventive concept provide a semiconductor chip having a large capacity and capable of maintaining signal characteristics having high speed and high reliability, and a semiconductor package including the semiconductor chip.

[0006] According to an exemplary embodiment of the present invention, a semiconductor chip includes: a semiconductor substrate, a through electrode, an intermediate pad, an upper pad, and a rewiring. The semiconductor substrate includes a first surface as an active surface and a second surface opposite to the first surface. The through electrode penetrates the semiconductor substrate and is arranged in at least one column along a first direction in the central portion of the semiconductor substrate. The intermediate pad is arranged in at least one column along the first direction in the edge portion of the second surface. The upper pad is arranged on the second surface and connected to the through electrode. The rewiring is arranged on the second surface and connects the intermediate pad to the upper pad.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package includes: a package substrate; an external connection terminal disposed on the bottom surface of the package substrate; and a first semiconductor chip disposed on the package substrate. The first semiconductor chip includes a first surface as an active surface and a second surface opposite to the first surface. The first semiconductor chip includes a through electrode disposed in a central portion of the first semiconductor chip, and an intermediate pad disposed in an edge portion of the second surface of the first semiconductor chip. The semiconductor package also includes at least one second semiconductor chip disposed on the first semiconductor chip. The at least one second semiconductor chip includes an active surface facing the same direction as the second surface of the first semiconductor chip, and a chip pad disposed on the active surface of the at least one second semiconductor chip. The intermediate pad is exposed. The semiconductor package also includes a redistribution wiring disposed on the second surface of the first semiconductor chip. The chip pad is connected to the intermediate pad by wiring, the intermediate pad is connected to the through electrode by the redistribution wiring, and the through electrode is connected to the external connection terminal.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package includes: a package substrate and a first semiconductor chip disposed on the package substrate. The active surface of the first semiconductor chip is connected to the package substrate through a through electrode. The semiconductor package also includes at least one second semiconductor chip disposed on the first semiconductor chip. The inactive surface of the at least one second semiconductor chip faces the first semiconductor chip, and the at least one second semiconductor chip is connected to the first semiconductor chip through wire bonding.

[0009] According to an exemplary embodiment of the present invention, a semiconductor package includes: a package substrate and a first semiconductor chip disposed on the package substrate. The first semiconductor chip includes: a through electrode disposed in a central portion of the first semiconductor chip; and an intermediate pad disposed on an inactive surface of the first semiconductor chip in an edge portion of the first semiconductor chip. The semiconductor package also includes: at least one second semiconductor chip disposed on the first semiconductor chip, and includes a chip pad disposed on an active surface of the at least one second semiconductor chip in an edge portion of the at least one second semiconductor chip, the active surface of the at least one second semiconductor chip facing the same direction as the inactive surface of the first semiconductor chip, and the intermediate pad is exposed. The semiconductor package also includes: a sealing material that seals the first semiconductor chip and the at least one second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1A is a perspective view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0012] Figure 1B is along Figure 1A A cross-sectional view taken along line II.

[0013] Figure 2A yes Figure 1A Top view of a first semiconductor chip in a semiconductor package.

[0014] Figure 2B and Figure 2C are along Figure 2A Cross-sectional views taken along line II-II' and line III-III'.

[0015] Figure 3A and Figure 3B yes Figure 2B An enlarged cross-sectional view of region A.

[0016] Figure 4A yes Figure 1A Top view of a package substrate in a semiconductor package.

[0017] Figure 4B yes Figure 1A A conceptual diagram of a wiring connection relationship between a first semiconductor chip and a package substrate in a semiconductor package.

[0018] Figure 5A The middle pad and the redistribution wiring are shown in detail. Figure 2C FIG. 5 is a cross-sectional view of a structure in which control regions in a first semiconductor chip are connected to each other.

[0019] Figure 5B Is used to describe Figure 1A Conceptual diagram of the signal transmission process in a semiconductor package.

[0020] Figure 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0021] 7A to 7C is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0022] Fig.7D yes Fig. 7A A cross-sectional view of a first semiconductor chip in a semiconductor package.

[0023] Fig. 8Ais a perspective view of a semiconductor package according to an embodiment.

[0024] Figure 8B is along Fig. 8A A cross-sectional view taken along line IV-IV'.

[0025] Fig.9A yes Fig. 8A Top view of a first semiconductor chip in a semiconductor package.

[0026] Fig. 9B is along Fig.9A A cross-sectional view taken along line V-V'.

[0027] Fig. 9C yes Fig. 8A A conceptual diagram of a wiring connection relationship between a first semiconductor chip and a package substrate in a semiconductor package.

[0028] Figures 10 to 12 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may represent like elements throughout the drawings.

[0030] It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0031] Spatially relative terms such as "below," "under," "lower," "below," "above," "upper," and the like may be used herein to facilitate description of the relationship of one element or feature relative to another element(s) or feature(s) as shown in the accompanying drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both above and below orientations. In addition, it will be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intermediate layers may also be present.

[0032] It should be understood that when a component such as a film, region, layer, or element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, connected to, coupled to, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or one or more intervening components may also be present.

[0033] It should also be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, in another exemplary embodiment, the "first" element in the exemplary embodiment can be described as the "second" element.

[0034] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0035] Furthermore, when two directions are described as being substantially parallel or perpendicular to each other, it will be understood that the two directions are exactly parallel or perpendicular to each other, or approximately parallel or perpendicular to each other within measurement error as would be understood by one of ordinary skill in the art.

[0036] Figure 1A is a perspective view of a semiconductor package 1000 according to an exemplary embodiment of the inventive concept. Figure 1B is along Figure 1A A cross-sectional view taken along line II. Figure 1A For the sake of convenience, the sealing material is not shown.

[0037] Reference Figure 1A and Figure 1B , a semiconductor package 1000 according to an exemplary embodiment may include a package substrate 100 , a first semiconductor chip 200 , a stacked chip group 300 , and a sealing material 400 .

[0038] The package substrate 100 may include a main body layer 101, an upper substrate pad 103, and a lower substrate pad 105. The main body layer 101 may be formed of any of a variety of materials. For example, depending on the type of the package substrate 100, the main body layer 101 may be formed of silicon, ceramics, organic materials, glass, epoxy resin, etc. In the semiconductor package 1000 according to an exemplary embodiment, the package substrate 100 may include an epoxy-based printed circuit board (PCB). Single-layer or multi-layer wiring may be formed in the main body layer 101. The upper substrate pad 103 and the lower substrate pad 105 may be electrically connected to each other through wiring.

[0039] The upper substrate pad 103 may be formed on the top surface of the body layer 101 and connected to the wiring of the body layer 101. The connection member 230 of the first semiconductor chip 200 may be disposed on the upper substrate pad 103. The lower substrate pad 105 may be formed on the bottom surface of the body layer 101 and connected to the wiring of the body layer 101. The external connection terminal 150 may be disposed on the lower substrate pad 105. A protective layer covering the wiring may be formed on the top and bottom surfaces of the body layer 101, and the upper substrate pad 103 and the lower substrate pad 105 may be exposed through the protective layer.

[0040] The external connection terminals 150 may be disposed on the bottom surface of the package substrate 100. The external connection terminals 150 may include, for example, solder balls. The external connection terminals 150 may include data signal (DQ) external connection terminals (eg, Figure 4A DQ external connection terminal 150D), command and address signal (C / A) external connection terminal (for example, Figure 4A The DQ external connection terminal and the C / A external connection terminal may be disposed in different areas on the bottom surface of the package substrate 100 (see, for example, Figure 4A ). The P / G external connection terminals may be randomly disposed between the DQ external connection terminals and between the C / A external connection terminals on the bottom surface of the package substrate 100.

[0041] The first semiconductor chip 200 may include a chip body layer 201, through electrodes 210, redistribution wirings 220, and connection members 230. The first semiconductor chip 200 may be stacked on the package substrate 100 such that the front side (eg, the front side) serving as an active surface is Figure 2B The front side Sf) of the package substrate 100 faces the package substrate 100 and may be mounted on the package substrate 100 through the connection member 230 and the bottom filler 245. The bottom filler 245 may include, for example, a non-conductive film (NCF). However, the material of the bottom filler 245 is not limited thereto.

[0042] The chip body layer 201 may include a semiconductor substrate (eg, Figure 3A semiconductor substrate 201s), circuit layer (eg, Figure 3A The circuit layer 201c) and the wiring layer (eg, Figure 3AThe through electrode 210 may penetrate at least a portion of the chip body layer 201, and the through electrode 210 may be arranged in the central portion of the first semiconductor chip 200 along the second direction (y direction). The through electrode 210 may be arranged in two columns along the second direction (y direction). For example, the through electrode 210 may include two portions arranged adjacent to each other in the central portion of the first semiconductor chip 200. However, the position where the through electrode 210 is arranged is not limited to the central portion. Moreover, the number of columns of the through electrode 210 is not limited to two columns. For example, the position of the through electrode 210 and the number of columns of the through electrode 210 may be changed to affect the wiring as needed (for example, Figure 4B The through electrode 210 may be connected to the upper pad 212, and the lower portion of the through electrode 210 may be connected to the lower pad 214. The through electrode 210 may penetrate the silicon substrate and thus may be referred to as a through silicon via (TSV).

[0043] Herein, when an element is described as being arranged in a plurality of columns along a specific direction, it should be understood that the element includes a plurality of parts corresponding to the plurality of columns, each part being arranged along a specific direction. Figure 2B and Figure 3A It can be seen that, in the exemplary embodiment, the through electrodes 210 are arranged in two columns along the second direction (y direction) (eg, the through electrodes 210 include two portions arranged along the second direction (y direction)).

[0044] Furthermore, when a plurality of identical elements are described as being arranged in a plurality of columns along a specific direction, it should be understood that the plurality of identical elements are divided into a plurality of groups corresponding to the plurality of columns, each group being arranged in a specific direction. When a plurality of different elements are described as being arranged in a plurality of columns along a specific direction, it should be understood that each of the plurality of different elements includes a plurality of parts corresponding to the plurality of columns, each of which is arranged in a specific direction.

[0045] The middle pad 222 may be disposed on a back surface (eg, Figure 2B The upper pad 212 may be disposed in the edge portion of the back side (Sb), and the upper pad 212 may be disposed in the center portion of the back side. The middle pad 222 may be disposed along the second direction (y direction) and may be disposed in three columns, such as Figure 2A The number of columns of the middle pads 222 may correspond to, for example, the number of second semiconductor chips 310, 320, and 330 stacked on the first semiconductor chip 200. The upper pads 212 may be arranged in two columns along the second direction (y direction), as shown in FIG. Figure 2AFor example, the number of columns of the upper pads 212 may correspond to the number of columns of the through electrodes 210 formed in the first semiconductor chip 200. However, according to an exemplary embodiment, the number of columns of the upper pads 212 and the number of columns of the through electrodes 210 may be different from each other.

[0046] like Figure 2A As shown, in an exemplary embodiment, the region in which the middle pad 222 is provided may be divided into a first region and a second region, and the region in which the upper pad 212 is provided may be divided into a third region corresponding to the first region and a fourth region corresponding to the second region. The middle pad 222 in the first region may be connected to the upper pad 212 in the third region through the rewiring 220, and the middle pad 222 in the second region may be connected to the upper pad 212 in the fourth region through the rewiring 220. The middle pad 222 provided in the first region may be configured to transmit a data signal (such as Figure 2A The middle pad 222 disposed in the second region may be configured to transmit command and address signals (eg, Figure 2A denoted by C / A representing the fourth area).

[0047] In an exemplary embodiment, the through electrode 210 is disposed in the center portion of the first semiconductor chip 200, and the middle pad 222 is disposed in the edge portion of the first semiconductor chip 200. In such an exemplary embodiment, with reference to the middle pad 222 and the through electrode 210, the middle pad 222 is disposed closer to the edge of the semiconductor chip 200 (see, e.g., Figure 2A and Figure 2C ).

[0048] The redistribution wiring 220 may be disposed on the back side of the first semiconductor chip 200, and may electrically connect the intermediate pad 222 to the upper pad 212. Therefore, the intermediate pad 222 may be electrically connected to the connection member 230 through the redistribution wiring 220, the upper pad 212, and the through-electrode 210, and finally electrically connected to the external connection terminal 150 of the package substrate 100.

[0049] When the first semiconductor chip 200 has the above structure, the wiring structure of the package substrate 100 connecting the second semiconductor chips 310, 320, and 330 to the external connection terminals 150 of the package substrate 100 can be short and balanced. Therefore, the semiconductor package 1000 according to the exemplary embodiment can reduce signal failure or signal delay caused by the load effect of the parasitic capacitance of the package substrate 100, and / or reduce the increase of unbalanced or wiring connection.

[0050] Reference FIG. 2A to FIG. 3B The detailed structure of the first semiconductor chip 200 is further described. Figure 4A and Figure 4B The wiring connection relationship from the first semiconductor chip 200 to the external connection terminals 150 of the package substrate 100 is described in detail.

[0051] Still refer to Figure 1A and Figure 1B , the stacked chipset 300 is stacked on the first semiconductor chip 200, and can be mounted by the adhesive member 341 and the first wiring to the third wiring 315, 325 and 335. The adhesive member 341 may include, for example, a die attach film (DAF). However, the adhesive member 341 is not limited to the DAF. The stacked chipset 300 may include three second semiconductor chips 310, 320 and 330, which may include, for example, a bottom second semiconductor chip 310, a middle second semiconductor chip 320 and a top second semiconductor chip 330. However, the number of second semiconductor chips included in the stacked chipset 300 is not limited to three. For example, in an exemplary embodiment, the stacked chipset 300 may include more or less than three second semiconductor chips.

[0052] The second semiconductor chips 310, 320, and 330 may be electrically connected to the first semiconductor chip 200 by wire bonding. Therefore, the front sides of the second semiconductor chips 310, 320, and 330, which are active surfaces, may face upward, and the first to third chip pads 312, 322, and 332 may be respectively disposed on the front sides of the second semiconductor chips 310, 320, and 330. The first to third chip pads 312, 322, and 332 of the second semiconductor chips 310, 320, and 330 may be electrically connected to the middle pad 222 of the first semiconductor chip 200 by the first to third wirings 315, 325, and 335. For example, the first chip pad 312 of the bottom second semiconductor chip 310 can be connected to the first intermediate pad 222-1 set at the innermost side along the first direction (x direction) through the first wiring 315, the second chip pad 322 of the middle second semiconductor chip 320 can be connected to the second intermediate pad 222-2 set in the middle along the first direction (x direction) through the second wiring 325, and the third chip pad 332 of the top second semiconductor chip 330 can be connected to the third intermediate pad 222-3 located at the outermost side along the first direction (x direction) through the third wiring 335.

[0053] The first chip pad to the third chip pad 312, 322 and 332 may include a DQ chip pad and a C / A chip pad. According to an exemplary embodiment, the first chip pad to the third chip pad 312, 322 and 332 may include a P / G chip pad. For example, the P / G chip pad may be disposed at an edge portion of the second semiconductor chip 310, 320 and 330, at a position where the DQ chip pad and the C / A chip pad are disposed. However, exemplary embodiments are not limited thereto. For example, in an exemplary embodiment, the P / G chip pad may be disposed at an edge portion different from the edge portion of the second semiconductor chip 310, 320 and 330, at a position where the DQ chip pad and the C / A chip pad are disposed. The P / G chip pad may be directly connected to the P / G substrate pad of the package substrate 100 by wiring without passing through the first semiconductor chip 200. Hereinafter, exemplary embodiments in which the first chip pad to the third chip pad 312, 322 and 332 include a DQ chip pad and a C / A chip pad are described.

[0054] like Figure 1A and Figure 1B As shown, the first semiconductor chip 200 may have the same size and shape as the second semiconductor chips 310, 320, and 330. However, exemplary embodiments are not limited thereto. For example, according to exemplary embodiments, the first semiconductor chip 200 may have a different size from the second semiconductor chips 310, 320, and 330. FIG. 7A to FIG. 7D Detailed Description An exemplary embodiment in which the first semiconductor chip 200 has a size different from that of the second semiconductor chips 310 , 320 , and 330 is described.

[0055] The sealing material 400 can protect the first semiconductor chip 200 and the stacked chipset 300 from external physical impact and electrical impact by sealing the first semiconductor chip 200 and the stacked chipset 300. In the semiconductor package 1000 according to an exemplary embodiment, the sealing material 400 can cover the side surfaces of the first semiconductor chip 200 and the stacked chipset 300, the side surfaces of the bottom filler 245 and the adhesive member 341, and the top surface of the top second semiconductor chip 330. The sealing material 400 can be formed by a polymer such as a resin. For example, the sealing material 400 can be formed by an epoxy molding compound (EMC). According to an exemplary embodiment, when the sealing material 400 is formed by a molded bottom fill (MUF) process, the sealing material 400 can be filled between the first semiconductor chip 200 and the package substrate 100 instead of filling the bottom filler 245.

[0056] In the semiconductor package 1000 according to an exemplary embodiment, the first semiconductor chip 200 may be a master chip, and the stacked chip group 300 and the second semiconductor chips 310, 320, and 330 may be slave chips. Figure 5A and Figure 5B Describe the master chip and slave chip in detail.

[0057] In the semiconductor package 1000 according to the exemplary embodiment, the first semiconductor chip 200 as the master chip may be mounted on the package substrate 100 through the connection member 230, and the second semiconductor chips 310, 320, and 330 as the slave chips may be mounted on the first semiconductor chip 200 through the first to third wirings 315, 325, and 335. The second semiconductor chips 310, 320, and 330 may be connected to the through-electrode 210 provided in the central portion of the first semiconductor chip 200 through the first to third wirings 315, 325, and 335, the middle pad 222 of the first semiconductor chip 200, the heavy wiring 220, and the upper pad 212, and may be connected to the package substrate 100 through the connection member 230.

[0058] Therefore, in the semiconductor package 1000 according to the exemplary embodiment, the second semiconductor chips 310, 320 and 330 are electrically connected to the external connection terminals 150 provided on the bottom surface of the package substrate 100 by using the first semiconductor chip 200, and the wiring connection to the DQ external connection terminal and the C / A external connection terminal based on the first semiconductor chip 200 is short and balanced. Therefore, the signal delay phenomenon and the load phenomenon caused by the capacitance can be greatly improved. As a result, the semiconductor package 1000 according to the exemplary embodiment can realize an electronic device or an electronic system that operates at a high speed and has an effective high signal integrity (SI) characteristic.

[0059] Figure 2A yes Figure 1A FIG. 1 is a top view of a first semiconductor chip 200 in a semiconductor package 1000 . Figure 2B and Figure 2C are along Figure 2A Cross-sectional views taken along line II-II' and line III-III'.

[0060] Reference FIG. 2A to FIG. 2C , the upper pads 212 , the middle pads 222 , and the redistribution wiring 220 may be disposed on the back side Sb of the first semiconductor chip 200 .

[0061] The upper pads 212 may be formed on the through-electrodes 210. The upper pads 212 may be disposed in the center portion of the back side Sb of the first semiconductor chip 200 along the second direction (y direction) and arranged in two columns. The middle pads 222 may be disposed in the edge portion of the back side Sb of the first semiconductor chip 200 in three columns along the second direction (y direction). For example, the middle pads 222 may include three pads disposed adjacent to each other in the edge portion of the back side Sb of the first semiconductor chip 200. Figure 2A As shown, the upper pad 212 may be one of a plurality of upper pads 212, and the upper pad 212 may be divided into a plurality of C / A upper pads and a plurality of DQ upper pads based on regions. Figure 2A In the figure, the area of ​​the C / A upper pad and the area of ​​the DQ upper pad are indicated by dotted lines. The middle pad 222 may also be one of a plurality of middle pads 222, and the middle pad 222 may be divided into a plurality of C / A middle pads and a plurality of DQ middle pads according to the area according to the upper pad 212.

[0062] exist Figure 2A , the redistribution wiring 220 is shown as if it is directly connected to the middle pad 222. However, the exemplary embodiment is not limited thereto, and such connection may be a conceptual electrical connection. For example, in the exemplary embodiment, the redistribution wiring 220 and the middle pad 222 may be connected to each other through the control region 250 provided in the chip body layer 201, as shown in FIG. Figure 2C or Figure 5A As shown. The redistribution wiring 220 can be connected to the upper pad 212. Figure 2A In the example, for ease of explanation, the upper pad 212 of the first column close to the middle pad 222 is connected to the middle pad 222 through the redistribution 220, but it should be understood that the upper pad 212 of the second column can also be connected to the middle pad 222 through the redistribution 220. Figure 2C , the redistribution wiring 220 connected to the two upper pads 212 is shown by a dotted line. The redistribution wiring 220 may be covered by a passivation layer 225 disposed on the chip body layer 201.

[0063] The through electrode 210 may penetrate at least a portion of the chip body layer 201. The upper portion of the through electrode 210 may be connected to the upper pad 212, and the lower portion of the through electrode 210 may be connected to the lower pad 214. The connecting member 230 may be disposed on the lower pad 214. The connecting member 230 may include a microbump. According to an exemplary embodiment, the connecting member 230 may include a metal filler and a microbump. The through electrode 210 may be arranged in two columns along the second direction (y direction). For example, the through electrode 210 may include two portions along the second direction (y direction). However, the exemplary embodiment is not limited thereto. For example, in an exemplary embodiment, the through electrode 210 may be arranged in one column or at least three columns. Reference will be made to Figure 3A and Figure 3B The detailed structure of the through electrode 210 is further described.

[0064] The first semiconductor chip 200 may include a control area 250 and a cell area 260 in the chip body layer 201. A control device may be provided in the control area 250, and a memory device may be provided in the cell area 260. For example, a dynamic random access memory (DRAM) device may be provided in the cell area 260. However, the type of memory device provided in the cell area 260 is not limited to a DRAM device. According to an exemplary embodiment, the first semiconductor chip 200 may include only the control area 250, such as Fig.7D shown.

[0065] Figure 3A and Figure 3B yes Figure 2B An enlarged cross-sectional view of region A.

[0066] Reference Figure 3A The chip body layer 201 of the first semiconductor chip 200 may include a semiconductor substrate 201s, a circuit layer 201c, a wiring layer 201l, an upper protection layer 201u and a lower protection layer 201d.

[0067] The semiconductor substrate 201s may include a semiconductor material, such as a group IV material or a group III-V compound. In the first semiconductor chip 200 according to an exemplary embodiment, the semiconductor substrate 201s may include a silicon substrate. The semiconductor substrate 201s may include a first surface Ssf as an active surface and a second surface Ssb as an inactive surface. In the above description of the first semiconductor chip 200, the outer surface facing the same direction as the first surface Ssf is referred to as the front side Sf, and the outer surface facing the same direction as the second surface Ssb is referred to as the back side Sb.

[0068] The circuit layer 201c may be disposed on the first surface Ssf of the semiconductor substrate 201s. A plurality of circuit devices such as transistors may be included in the circuit layer 201c. The type of semiconductor chip may be determined according to the circuit devices included in the circuit layer 201c. For example, in the semiconductor package 1000 according to the exemplary embodiment, a DRAM device and a control device may be included in the circuit layer 201c of the first semiconductor chip 200. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, only the control device may be included in the circuit layer 201c of the first semiconductor chip 200.

[0069] The wiring layer 2011 may be disposed on the bottom surface of the circuit layer 201c, and may include an intermetallic insulating layer 201l-1, a wiring 201l-3, and a vertical plug 201l-2. The wiring 201l-3 may be formed as at least one layer in the intermetallic insulating layer 201l-1. The wiring 201l-3 may be electrically connected to the circuit device in the circuit layer 201c, and electrically connected to the lower pad 214 on the bottom surface of the wiring layer 201l. The vertical plug 201l-2 may connect the wiring 201l-3 of a different layer or the wiring 201l-3 to the lower pad 214.

[0070] The through electrode 210 may penetrate the semiconductor substrate 201s and the circuit layer 201c. The through electrode 210 may include a wiring metal layer 210m in the central region of the through electrode 210 and a barrier metal layer 210b in the outer region (e.g., disposed adjacent to the wiring metal layer 210m). The wiring metal layer 210m may include, for example, at least one metal selected from tungsten (W), aluminum (Al), and copper (Cu). The barrier metal layer 210b may include, for example, at least one metal selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). However, the materials of the wiring metal layer 210m and the barrier metal layer 210b are not limited thereto.

[0071] The spacer insulating layer 213 may be disposed between the through electrode 210 and the semiconductor substrate 201s and between the through electrode 210 and the circuit layer 201c. The spacer insulating layer 213 may prevent circuit devices in the semiconductor substrate 201s and the circuit layer 201c from directly contacting the through electrode 210.

[0072] In the semiconductor package 1000 according to an exemplary embodiment, the through-electrode 210 may have a through-hole intermediate structure, for example, Figure 3A For example, the through-electrode 210 may be classified as having a through-hole first structure, a through-hole middle structure, and a through-hole last structure. The through-hole first structure refers to a structure in which the through-electrode is formed before the circuit layer 201c is formed, the through-hole middle structure refers to a structure in which the through-electrode is formed after the circuit layer 201c is formed and before the wiring layer 2011 is formed, and the through-hole last structure refers to a structure in which the through-electrode is formed after the wiring layer 2011 is formed.

[0073] Reference Figure 3B , the first semiconductor chip 200 ′ according to an exemplary embodiment may be Figure 3A The difference between the first semiconductor chip 200 and the through-electrode 210' is that the through-electrode 210' has a through-hole structure. Figure 3BIn the first semiconductor chip 200 ′ of the exemplary embodiment, the through electrode 210 ′ may penetrate the circuit layer 201 c and the wiring layer 201 l , and the through electrode 210 ′ may be directly connected to the lower pad 214 without being relayed by the wiring layer 201 l .

[0074] Figure 4A yes Figure 1A FIG. 1 is a top view of a package substrate 100 in a semiconductor package 1000 . Figure 4B yes Figure 1A A conceptual diagram of a wiring connection relationship between a first semiconductor chip 200 and a package substrate 100 in a semiconductor package 1000 is shown.

[0075] Reference Figure 4A and Figure 4B In the semiconductor package 1000 according to the exemplary embodiment, a plurality of external connection terminals 150 may be arranged on the bottom surface of the package substrate 100 in a two-dimensional (2D) array structure. As described above, these external connection terminals 150 may be distinguishably arranged according to regions based on functions. For example, the DQ external connection terminal 150D may be arranged at the upper portion of the package substrate 100, and the C / A external connection terminal 150C may be arranged at the lower portion of the package substrate 100. Figure 4A , the region of the DQ external connection terminals 150D and the region of the C / A external connection terminals 150C are separated by dotted lines. The arrangement structure of the external connection terminals 150 may conform to a standardized arrangement structure.

[0076] For ease of explanation, Figure 4A The external connection terminal 150 is shown by a dotted line in FIG. Figure 4A The top view of FIG. 1 shows the top surface of the package substrate 100, and the external connection terminal 150 is not actually visible in this view. Reference mark SM is displayed at the corner of the top surface of the package substrate 100. The portion of the package substrate 100 close to the reference mark SM is defined as the upper portion, and the portion of the package substrate 100 away from the reference mark SM is defined as the lower portion.

[0077] Figure 4B The conceptual diagram may show the top surface of the package substrate 100 when the first semiconductor chip 200 is stacked on the package substrate 100. The wiring 130 of the package substrate 100 is schematically shown. For example, from the upper pad 212 or the connection member (e.g., Figure 1AThe distance from the DQ upper pad 212DQ to the external connection terminal 150 provided on the bottom surface of the package substrate 100 is schematically shown as a wiring 130. The DQ upper pad 212DQ may be connected to the DQ external connection terminal 150D provided at the upper portion of the package substrate 100, and the C / A upper pad 212C / A may be connected to the C / A external connection terminal 150C provided at the lower portion of the package substrate 100.

[0078] The upper pad 212 and the through electrode 210 are arranged in the central portion of the first semiconductor chip 200 along the second direction (y direction), and the connecting member 230 is correspondingly arranged. Therefore, the length of the wiring 130 connecting the connecting member 230 to the external connection terminal 150 of the package substrate 100 can be reduced, and the structure of the wiring 130 can be balanced.

[0079] In addition, Figure 4B In FIG. 1 , the upper pads 212 and the through electrodes 210 are arranged in two rows in the central portion of the first semiconductor chip 200 along the second direction (y direction). Figure 4B In the embodiment, the first group of upper pads 212 and through electrodes 210 are arranged in a first group (e.g., C / A group) in the central part of the first semiconductor chip 200 along the second direction (y direction), and the second group of upper pads 212 and through electrodes 210 are arranged in a second group (e.g., DQ group) in the central part of the first semiconductor chip 200 adjacent to the first group along the second direction (y direction). However, the arrangement positions and column numbers of the upper pads 212 and through electrodes 210 are not limited thereto. For example, the arrangement positions and column numbers of the upper pads 212 and through electrodes 210 may be appropriately determined so that the length of the wiring 130 from the connecting member 230 to the external connection terminal 150 divided according to the region is the desired length.

[0080] Referring to the comparative example, when the first semiconductor chip does not include a through electrode, the active surfaces of all the first semiconductor chips and the second semiconductor chips 310, 320 and 330 may face upward. The first semiconductor chip may be mounted on the package substrate by wire bonding. Therefore, in the package substrate, the wiring structure from the substrate pad connected to the wiring to the external connection terminal is unbalanced, and the length of the wiring may increase. When the length of the wiring of the package substrate increases, the load effect caused by the parasitic capacitance generated in the package substrate may increase, and the signal may be delayed. Therefore, the high-speed operation of the semiconductor package and the electronic device or electronic system including the semiconductor package may be hindered, and the reliability may be reduced.

[0081] However, in the semiconductor package 1000 according to the exemplary embodiment, the first semiconductor chip 200 includes the through-electrode 210 provided in the center portion, and the upper pad 212, the middle pad 222, and the redistribution wiring 220 provided on the back surface, and the first semiconductor chip 200 is mounted on the package substrate 100 through the connection member 230. Therefore, problems that may occur in the structure in which the first semiconductor chip is provided on the package substrate 100 by wire bonding can be effectively solved or alleviated.

[0082] Figure 5A The middle pad 222 and the redistribution wiring 220 are shown in detail. Figure 2C FIG. 2 is a cross-sectional view of a structure in which control regions 250 in a first semiconductor chip 200 are connected to each other.

[0083] Reference Figure 5A , the middle pad 222 of the first semiconductor chip 200 can be connected to the circuit device of the control area 250 through the internal wiring 255 of the chip body layer 201. The redistribution wiring 220 of the first semiconductor chip 200 can be connected to the circuit device of the control area 250 through the internal wiring 255. As a result, the middle pad 222 can be electrically connected to the redistribution wiring 220 through the control area 250.

[0084] The control area 250 can improve the characteristics of signal transmission to and / or from the second semiconductor chips 310, 320, and 330 by performing, for example, reshaping, retiming, redriving, etc. on the signal through the circuit devices included in the control area 250. The control area 250 can be referred to as a buffer based on the function performed. By connecting the intermediate pad 222 to the rewiring 220 through the control area 250, the interval between the intermediate pads 222 can be adjusted, and thus an electrical short circuit can be prevented between the first wiring to the third wiring 315, 325, and 335 connected to the intermediate pad 222.

[0085] Figure 5B Is used to describe Figure 1A A conceptual diagram of a signal transmission process in a semiconductor package 1000 is shown.

[0086] Reference Figure 5BIn the semiconductor package 1000 according to the exemplary embodiment, the first semiconductor chip 200 may be a master chip, and the second semiconductor chips 310, 320, and 330 may be slave chips. Herein, the master chip may refer to a chip that generates a clock signal, and the slave chip may refer to a chip that receives a clock signal generated by the master chip. For example, the first semiconductor chip 200 may read information of the second semiconductor chips 310, 320, and 330 or write information about the second semiconductor chips 310, 320, and 330 using the clock signal. The second semiconductor chips 310, 320, and 330 may respond to a request of the first semiconductor chip 200.

[0087] The package substrate 100 may send signals and / or power to or receive signals and / or power from an external electronic device through the external connection terminals 150 on the lower substrate pads 105. The signal may include, for example, a data signal, a command signal, an address signal, etc. The package substrate 100 may send signals and / or power to or receive signals and / or power from the first semiconductor chip 200 through the upper substrate pads 103 and the connection members 230.

[0088] The first semiconductor chip 200 may include a through electrode 210, a rewiring 220, an intermediate pad 222, a connecting member 230, a control area 250, and an internal wiring 255. Circuit devices such as transistors may be provided in the control area 250. The control area 250 may be used as a buffer circuit and / or a control circuit. The internal wiring 255 may be electrically connected to the circuit devices of the control area 250. The control area 250 of the first semiconductor chip 200 may be connected to the package substrate 100 through the internal wiring 255, the rewiring 220, the through electrode 210, and the connecting member 230. The first semiconductor chip 200 may directly send a signal to the package substrate 100 or receive a signal from the package substrate 100 without passing through another semiconductor chip. Based on such a signal transmission characteristic of the first semiconductor chip 200, the first semiconductor chip 200 may be referred to as a master chip.

[0089] The second semiconductor chips 310, 320, and 330 may be electrically connected to the circuit devices of the control region 250 through the first to third wirings 315, 325, and 335, the intermediate pads 222, and the internal wirings 255, and are also connected to the package substrate 100 through the internal wirings 255, the redistribution wirings 220, the through electrodes 210, and the connection members 230. As a result, the second semiconductor chips 310, 320, and 330 may transmit or receive signals to or from the package substrate 100 through the control region 250 of the first semiconductor chip 200. Based on such signal transmission characteristics of the second semiconductor chips 310, 320, and 330, the second semiconductor chips 310, 320, and 330 may be referred to as slave chips.

[0090] Figure 6 is a cross-sectional view of a semiconductor package 1000a according to an exemplary embodiment of the inventive concept. Figures 1A to 5B Further description of the details described.

[0091] Reference Figure 6 , the semiconductor package 1000a according to the exemplary embodiment may be Figure 1A The difference between the semiconductor package 1000 and the stacked chipset 300a is that the stacked chipset 300a has a stepped stacking structure (similar to, for example, Figure 1B For example, in the stacked structure of the semiconductor package 1000 Figure 6 In the semiconductor package 1000a of the exemplary embodiment of the present invention, the bottom second semiconductor chip 310a of the stacked chip group 300a may be stacked on the first semiconductor chip 200 by the adhesive member 341, as shown in FIG. Figure 1A As in the semiconductor package 1000 of the present invention, the first intermediate pad 222 - 1 of the first semiconductor chip 200 may be electrically connected to the first intermediate pad 222 - 1 of the first semiconductor chip 200 through the first wiring 315 .

[0092] The middle second semiconductor chip 320a may be stacked on the bottom second semiconductor chip 310a through the adhesive member 341 and electrically connected to the second middle pad 222-2 of the first semiconductor chip 200 through the second wiring 325. Figure 1A Unlike the semiconductor package 1000, the middle second semiconductor chip 320a is not aligned with the bottom second semiconductor chip 310a in the third direction (z direction), but can be shifted and stacked in the first direction (x direction) so that the first chip pad 312 of the bottom second semiconductor chip 310a is exposed.

[0093] For example, in Figure 1A In an exemplary embodiment of (see also Figure 1B ), the middle second semiconductor chip 320 is stacked on the bottom second semiconductor chip 310 and aligned with the bottom second semiconductor chip 310, thereby covering the first chip pad 312 of the bottom second semiconductor chip 310. Figure 6 In the exemplary embodiment of FIG. 5 , the first chip pad 312 of the bottom second semiconductor chip 310 a is exposed because the middle second semiconductor chip 320 a is not aligned with the bottom second semiconductor chip 310 a and thus does not cover the first chip pad 312 .

[0094] The top second semiconductor chip 330a may be stacked on the middle second semiconductor chip 320a by the adhesive member 341, and electrically connected to the third middle pad 222-3 of the first semiconductor chip 200 by the third wiring 335. Similar to the middle second semiconductor chip 320a, the top second semiconductor chip 330a may be shifted and stacked in the first direction (x direction) so that the second chip pad 322 of the middle second semiconductor chip 312a is exposed. That is, similar to the middle second semiconductor chip 320a, the top second semiconductor chip 330a may be stacked in a stepped manner.

[0095] For example, in Figure 1A In an exemplary embodiment of (see also Figure 1B ), the top second semiconductor chip 330 is stacked on and aligned with the middle second semiconductor chip 320, thereby covering the second chip pad 322 of the middle second semiconductor chip 310. Figure 6 In the exemplary embodiment of FIG. 5 , the second chip pad 322 of the middle second semiconductor chip 320 a is exposed because the top second semiconductor chip 330 a is not aligned with the middle second semiconductor chip 320 a and thus does not cover the second chip pad 322 .

[0096] In accordance with Figure 6 In the semiconductor package 1000a of the exemplary embodiment of the present invention, since the stacked chipset 300a has a stepped stacking structure, the first chip pads 312 and the second chip pads 322 of the bottom second semiconductor chip 310a and the middle second semiconductor chip 320a are exposed, which can facilitate the wire bonding process between the first wiring 315 and the second wiring 325 and the first chip pads 312 and the second chip pads 322 and the stacking process of the bottom second semiconductor chip, the middle second semiconductor chip and the top second semiconductor chips 310a to 330a. Therefore, according to Figure 6 The semiconductor package 1000 a of the exemplary embodiment may implement a highly reliable semiconductor package having a low connection defect rate between the first and second wirings 315 and 325 and the first and second chip pads 312 and 322 .

[0097] 7A to 7C 1000b to 1000d are cross-sectional views of semiconductor packages 1000b to 1000d according to exemplary embodiments of the inventive concept. Fig.7D yes Fig. 7A is a cross-sectional view of a first semiconductor chip 200a in a semiconductor package 1000b, and corresponds to Figure 2C (because Figure 2C yes Figure 1A). Hereinafter, for the sake of convenience of explanation, the reference to the first semiconductor chip 200 previously referred to may be omitted. Figures 1A to 6 Further description of the details described.

[0098] Reference Fig. 7A and Fig.7D In terms of the structure of the first semiconductor chip 200a, the semiconductor package 1000b according to the exemplary embodiment may be similar to Figure 1A For example, in accordance with the semiconductor package 1000 Fig. 7A In the semiconductor package 1000b of the exemplary embodiment of the present invention, the first semiconductor chip 200a may include only the control area 250 in the chip body layer 201a, and does not include the cell area in which the memory device is disposed. Therefore, the first semiconductor chip 200a does not perform a memory function of storing data. For example, the first semiconductor chip 200a may perform only a buffering or control function of signal transmission to and / or from the second semiconductor chips 310, 320, and 330 through the control area 250.

[0099] Since the first semiconductor chip 200a includes only the control region 250, the size of the first semiconductor chip 200a may be smaller than the size of the second semiconductor chips 310, 320, and 330. However, exemplary embodiments are not limited thereto. For example, according to exemplary embodiments, even when the first semiconductor chip 200a includes only the control region 250, the size of the first semiconductor chip 200a may be substantially the same as the size of the second semiconductor chips 310, 320, and 330.

[0100] When the first semiconductor chip 200a includes only the control region 250 and is smaller than the second semiconductor chips 310, 320, and 330, the through electrode 210 may be disposed slightly toward an edge portion of the first semiconductor chip 200a in the first direction (x direction) rather than being disposed at a central portion of the first semiconductor chip 200a. For example, the through electrode 210 may be disposed closer to an edge portion of the first semiconductor chip 200a than to a central portion of the first semiconductor chip 200a. Figure 1A In the first semiconductor chip 200 of the semiconductor package 1000, the through electrodes 210 may be arranged in two columns along the second direction (y direction). However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, the number of columns of the through electrodes 210 is not limited to two columns.

[0101] Reference Figure 7B , the semiconductor package 1000c according to the exemplary embodiment may be Fig. 7AThe semiconductor package 1000b is different in that a support chip 500 is further disposed on the package substrate 100. For example, in the semiconductor package 1000c according to the exemplary embodiment, the support chip 500 may be disposed on the package substrate 100 between the package substrate 100 and the stacked chipset 300.

[0102] The support chip 500 may be stacked on the package substrate 100 through the adhesive member 341 to support the stacked chip group 300 together with the first semiconductor chip 200a′. Fig. 7A According to the first semiconductor chip 200 a of the semiconductor package 1000 b , the first semiconductor chip 200 a ′ may include only the control region 250 . Figure 7B The first semiconductor chip 200a′ of the semiconductor package 1000c may be smaller than Fig. 7A The semiconductor package 1000b of the present invention further comprises a first semiconductor chip 200a.

[0103] Since the first semiconductor chip 200a' includes only the control area 250, the outer area where the through electrode 210 is set along the first direction (x direction) may not be required (for example, because the unit area does not require additional space). Therefore, when a plurality of identical first semiconductor chips 200a' are manufactured in one wafer, the size of the first semiconductor chip 200a' can be reduced to manufacture more first semiconductor chips 200a'. However, since the size of the first semiconductor chip 200a' is small and space for the middle pad 222 needs to be ensured, the support function of the first semiconductor chip 200a' for the stacked chipset 300 may be weakened. Therefore, the support chip 500 can be arranged between the stacked chipset 300 and the packaging substrate 100 to enhance the support function for the stacked chipset 300.

[0104] For example, in an exemplary embodiment, when the size of the first semiconductor chip 200a' is reduced so that the first semiconductor chip 200a' may not provide sufficient support for the stacked chip group 300 stacked thereon, a support chip 500 may be further provided to provide additional support.

[0105] Since the support chip 500 performs only a support function for the stacked chipset 300, the support chip 500 may be formed of a relatively cheap material such as glass or resin. The support chip 500 may be formed of a material capable of buffering a difference in thermal expansion coefficient between the package substrate 100 and the stacked chipset 300.

[0106] Reference Figure 7C , the semiconductor package 1000d according to the exemplary embodiment may have Figure 6 and Figure 7BFor example, the semiconductor package 1000d according to the exemplary embodiment may further include a support chip 500 disposed on the package substrate 100 and located between the package substrate 100 and the stacked chipset 300a, and may have a stepped stack structure of the stacked chipset 300a.

[0107] For example, in the semiconductor package 1000d according to the exemplary embodiment, the first semiconductor chip 200a' may include only the control area 250, and may be smaller than the bottom second semiconductor chip 310a, the middle second semiconductor chip 320a, and the top second semiconductor chip 330a. Therefore, in order to support the support function of the stacked chipset 300a of the first semiconductor chip 200a', the support chip 500 may be provided on the package substrate 100. In addition, the bottom second semiconductor chip 310a, the middle second semiconductor chip 320a, and the top second semiconductor chip 330a in the stacked chipset 300a may be stacked in a stepped structure so that the first chip pad 312 and the second chip pad 322 are exposed. Therefore, the connection defects between the first wiring 315 and the second wiring 325 and the first chip pad 312 and the second chip pad 322 may be reduced, and thus the reliability of the semiconductor package 1000d may be improved.

[0108] Fig. 8A is a perspective view of a semiconductor package 1000 e according to an exemplary embodiment of the inventive concept. Figure 8B is along Fig. 8A A cross-sectional view taken along line IV-IV'. Fig.9A yes Fig. 8A FIG. 1 is a top view of a first semiconductor chip 200 b in a semiconductor package 1000 e. Fig. 9B is along Fig.9A A cross-sectional view taken along line V-V'. Fig. 9C yes Fig. 8A A conceptual diagram of the wiring connection relationship between the first semiconductor chip 200b and the package substrate 100a in the semiconductor package 1000e. For ease of explanation, the previously referenced FIG. 1A to FIG. 7D Further description of the details described.

[0109] Reference 8A to 9C In terms of the arrangement structure of the first semiconductor chip 200 b and the stacked chip group 300 b , the semiconductor package 1000 e according to the exemplary embodiment may be similar to Figure 1A In addition, in terms of the structure of the wiring 130a of the package substrate 100a, the semiconductor package 1000e according to the exemplary embodiment may be different from the semiconductor package 1000 of the exemplary embodiment. Figure 1A The semiconductor package 1000 is different.

[0110] For example, something like Figure 1A According to the first semiconductor chip 200 of the semiconductor package 1000, in the semiconductor package 1000e according to the exemplary embodiment, the first semiconductor chip 200b may include a chip body layer 201, a through electrode 210, a redistribution wiring 220 and a connecting member 230. The first semiconductor chip 200 may include a control area 250 and a cell area 260 in the chip body layer 201. According to an exemplary embodiment, the first semiconductor chip 200b may only include the control area 250 in the chip body layer 201 (for example, in an exemplary embodiment, the first semiconductor chip 200b does not include the cell area 260). The middle pad 222 and the upper pad 212 may be disposed on the back side Sb of the first semiconductor chip 200b and connected to each other through the redistribution wiring 220.

[0111] and Figure 1A The difference between the first semiconductor chip 200 of the semiconductor package 1000 and the first semiconductor chip 200b is that in the first semiconductor chip 200b, the through electrodes 210 and the upper pads 212 may be arranged in two columns along the first direction (x direction). Figure 1A The difference between the first semiconductor chip 200 of the semiconductor package 1000 and the first semiconductor chip 200 is that the middle pads 222 can be arranged in three rows along the first direction (x direction). Figure 1A In the first semiconductor chip 200 of the semiconductor package 1000, the direction in which the through-electrode 210 and the upper pad 212 are arranged and the direction in which the middle pad 222 is arranged may be the second direction (y direction). 8A to 9C In the first semiconductor chip 200b of the semiconductor package 1000e of the exemplary embodiment, the direction in which the through-electrode 210 and the upper pad 212 are provided and the direction in which the middle pad 222 is provided may be the first direction (x direction). Since the direction in which the upper pad 212 is provided and the direction in which the middle pad 222 is provided are the first direction (x direction), the redistribution wiring 220 may connect the upper pad 212 and the middle pad 222 in the second direction (y direction).

[0112] The second semiconductor chips 310b, 320b, and 330b of the stacked chipset 300b stacked on the first semiconductor chip 200b may be electrically connected to the first semiconductor chip 200b by wire bonding. Since the middle pad 222 of the first semiconductor chip 200b is arranged along the first direction (x direction), the first chip pads to the third chip pads 312, 322, and 332 of the second semiconductor chips 310b, 320b, and 330b may also be arranged along the first direction (x direction). According to an exemplary embodiment, the second semiconductor chips 310b, 320b, and 330b of the stacked chipset 300b may have a configuration such as Figure 6 FIG. 1 is a schematic diagram of a stepped stacking structure in a semiconductor package 1000 a.

[0113] As a result, according to 8A to 9C The structure of the semiconductor package 1000e of the exemplary embodiment may correspond to Figure 1A The first semiconductor chip 200 and the stacked chip group 300 of the semiconductor package 1000 are rotated about 90° on the package substrate 100. For example, 8A to 9C The first semiconductor chip 200b and the second semiconductor chips 310b, 320b, and 330b of the stacked chip group 300b of the semiconductor package 1000e may be respectively Figure 1A The first semiconductor chip 200b of the semiconductor package 1000 and the second semiconductor chips 310, 320 and 330 of the stacked chip group 300 are the same. The first semiconductor chip 200b and the second semiconductor chips 310b, 320b and 330b of the stacked chip group 300b may be compared to Figure 1A The semiconductor package 1000 is stacked on the package substrate 100 a in a structure rotated by about 90°.

[0114] In the semiconductor package 1000e, since the through-electrode 210 and the upper pad 212 of the first semiconductor chip 200b are arranged in the center portion along the first direction (x direction), the lower pad 214 and the connecting member 230 may also be arranged in the center portion along the first direction (x direction). Therefore, the structure of the wiring 130a from the connecting member 230 to the external connection terminal 150 arranged on the bottom surface of the package substrate 100a may be as follows. Fig. 9C shown.

[0115] For example, something like Figure 1A In the package substrate 100 of the semiconductor package 1000, among the external connection terminals 150 of the package substrate 100a, the DQ external connection terminal 150D may be disposed at the upper portion, and the C / A external connection terminal 150C may be disposed at the lower portion. The upper pad 212 of the first semiconductor chip 200b and the corresponding connection member 230 may be disposed in the central portion of the first semiconductor chip 200b along the first direction (x direction). Fig. 9C As shown in the dashed rectangle in FIG. 1 , a plurality of DQ upper pads 212DQ and a plurality of C / A upper pads 212C / A may be separately arranged in the first direction (x direction). Based on this arrangement structure of the upper pads 212 and the corresponding connection members 230, the wiring 130a of the package substrate 100a may extend in two directions in the second direction (y direction) in the central portion corresponding to the upper pads 212.

[0116] The DQ upper pad 212DQ is provided in the upper portion of the first semiconductor chip 200b corresponding to the upper portion where the DQ external connection terminal 150D is provided, and the C / A upper pad 212C / A is provided in the upper portion of the first semiconductor chip 200b corresponding to the lower portion where the C / A external connection terminal 150C is provided. Therefore, the length of the wiring 130a can be reduced, and the structure of the wiring 130a can be balanced. Therefore, the signal delay phenomenon and the load phenomenon of the capacitance of the semiconductor package 1000e according to the exemplary embodiment can be improved, and thus an electronic device or an electronic system that operates at a high speed while having improved SI characteristics can be realized.

[0117] Figures 10 to 12 1 is a cross-sectional view of semiconductor packages 1000g to 1000i according to an exemplary embodiment of the inventive concept. Figures 1A to 9C Further description of the details described.

[0118] Reference Fig.10 , the semiconductor package 1000g according to the exemplary embodiment may be Figure 1A The difference between the semiconductor package 1000 and the stacked chip group 300b is that the stacked chip group 300b includes only one second semiconductor chip 310. Fig.10 In the semiconductor package 1000g of the exemplary embodiment of the present invention, the stacked chipset 300b may be stacked on the first semiconductor chip 200d, and the stacked chipset 300b includes only one second semiconductor chip 310. When the stacked chipset 300b includes only one second semiconductor chip 310, only one column of the middle pads 222b may be provided on the back side of the first semiconductor chip 200d and connected to the first chip pads 312 of one second semiconductor chip 310. The first chip pads 312 of the second semiconductor chip 310 and the middle pads 222b may be connected to each other through the first wiring 315.

[0119] The through electrodes 210, the upper pads 212, the lower pads 214, and the connecting members 230 may be arranged in two columns along the second direction (y direction). However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, according to the exemplary embodiment, since the middle pads 222b are arranged in only one column, the through electrodes 210, the upper pads 212, the lower pads 214, and the connecting members 230 may be arranged in one column along the second direction (y direction).

[0120] Reference Fig.11 , the semiconductor package 1000h according to the exemplary embodiment may be Figure 1AThe difference of the semiconductor package 1000 is that the stacked chip group 300c includes seven second semiconductor chips 310, 320, 330, 340, 350, 360 and 370, and further includes a supporting chip 500. Fig.11 In the semiconductor package 1000 h of the exemplary embodiment, the stacked chip group 300 c may be stacked on the first semiconductor chip 200 e and the supporting chip 500 , and the stacked chip group 300 c includes seven second semiconductor chips 310 , 320 , 330 , 340 , 350 , 360 , and 370 . When the stacked chipset 300c includes seven second semiconductor chips 310, 320, 330, 340, 350, 360 and 370, seven columns (e.g., 222-1, 222-2, 222-3, 222-4, 222-5, 222-6 and 222-7) of intermediate pads 222c can be arranged on the back side of the first semiconductor chip 200e corresponding to the chip pads 312, 322, 332, 342, 352, 362 and 372 of the seven second semiconductor chips 310, 320, 330, 340, 350, 360 and 370. Chip pads 312, 322, 332, 342, 352, 362 and 372 of second semiconductor chips 310, 320, 330, 340, 350, 360 and 370 may be connected to the intermediate pad 222c through first to seventh wirings 315, 325, 335, 345, 355, 365 and 375, respectively.

[0121] Similar to Fig.7D In the semiconductor package 1000h, the first semiconductor chip 200e may include only the control area 250 because the capacity may be sufficient when the stacked chip group 300c includes seven second semiconductor chips 310, 320, 330, 340, 350, 360, and 370. However, it is not completely excluded that the first semiconductor chip 200e includes a cell area. For example, in the case of Fig.11 In an exemplary embodiment of the present invention, the first semiconductor chip 200e may or may not include a unit area. When the middle pads 222c are arranged in seven columns, the exposed area of ​​the back side of the first semiconductor chip 200e increases, and thus the support function for the stacked chipset 300c may be weakened. Therefore, the support chip 500 may be arranged between the stacked chipset 300c and the package substrate 100. According to an exemplary embodiment, when the first semiconductor chip 200e is large and has sufficient support function for the stacked chipset 300c, the support chip 500 may be omitted.

[0122] The through electrodes 210, the upper pads 212, the lower pads 214, and the connecting members 230 may be arranged in two columns along the second direction. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, since the middle pads 222b are arranged in seven columns, the through electrodes 210, the upper pads 212, the lower pads 214, and the connecting members 230 may be arranged in at least three columns along the second direction (y direction).

[0123] refer to Fig.12 In terms of the structure of the stacked chipset 300d, the semiconductor package 1000i according to the exemplary embodiment may be Fig.11 The semiconductor package 1000h is different. For example, in Fig.12 In the semiconductor package 1000i of the exemplary embodiment of the present invention, the stacked chip group 300d may include seven second semiconductor chips 310, 320, 330, 340, 350, 360, and 370. The seven second semiconductor chips 310, 320, 330, 340, 350, 360, and 370 include four upper second semiconductor chips 340, 350, 360, and 370 shifted in the first direction and stacked on the top second semiconductor chip 330.

[0124] like Fig.12 As shown, in an exemplary embodiment, the lower second semiconductor chips 310, 320 and 330 are stacked and aligned with each other, the upper second semiconductor chips 340, 350, 360 and 370 are stacked and aligned with each other, and the upper second semiconductor chips 340, 350, 360 and 370 are stacked on top of the lower second semiconductor chips 310, 320 and 330 and are not aligned with the lower second semiconductor chips 310, 320 and 330.

[0125] The third chip pad 332 and the middle chip pads 336, 337, 338, and 339 may be disposed on the top surface of the top second semiconductor chip 330 (e.g., the top second semiconductor chip among the three lower second semiconductor chips 310, 320, and 330). The chip pads 342, 352, 362, and 372 of the upper four second semiconductor chips 340, 350, 360, and 370 may be connected to the middle chip pads 336, 337, 338, and 339 through the fourth to seventh wirings 345, 355, 365, and 375. Therefore, the upper four second semiconductor chips 340, 350, 360, and 370 may be connected to the third middle pad 222-3 of the first semiconductor chip 200a through the third wiring 335 and the top second semiconductor chip 330, and connected to the package substrate 100 through the heavy wiring 220, the through electrode 210, and the connection member 230.

[0126] Similar to Fig.7DThe first semiconductor chip 200a is Fig.12 In the semiconductor package 1000i of the exemplary embodiment of the present invention, the first semiconductor chip 200a may include only the control area 250. However, the exemplary embodiment is not limited thereto. For example, according to an embodiment, the first semiconductor chip 200a included in the semiconductor package 1000i may include a cell area. In an exemplary embodiment, when the size of the first semiconductor chip 200a is reduced and the exposed area of ​​the back side is increased, the support chip 500 may be disposed between the stacked chipset 300d and the package substrate 100 to provide additional support. However, according to an exemplary embodiment, the support chip 500 may be omitted from the semiconductor package 1000i.

[0127] Although the stacked chipset includes one, three, or seven second semiconductor chips in the above exemplary embodiments, it should be understood that the number of second semiconductor chips included in the stacked chipset is not limited thereto.

[0128] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor chip, comprising: A semiconductor substrate including a first surface as an active surface and a second surface opposite to the first surface; through electrodes penetrating the semiconductor substrate and arranged in at least one column along a first direction in a central portion of the semiconductor substrate; intermediate pads arranged in at least one column along the first direction in an edge portion of the second surface, wherein an area where the intermediate pads are arranged is divided into a first area and a second area in the first direction, wherein the intermediate pads arranged in the first area are configured to transmit data signals, and the intermediate pads arranged in the second area are configured to transmit command and address signals; an upper pad disposed on the second surface and connected to the through-electrode; and A redistribution wiring is disposed on the second surface and connects the middle pad to the upper pad.

2. The semiconductor chip according to claim 1, in, The number of the at least one column of the intermediate pads is equal to the number of additional semiconductor chips disposed on the semiconductor substrate, The area where the upper pad is provided is divided into a third area corresponding to the first area and a fourth area corresponding to the second area in the first direction, The middle pad in the first region is connected to the upper pad in the third region through the redistribution wiring, and the middle pad in the second region is connected to the upper pad in the fourth region through the redistribution wiring.

3. The semiconductor chip according to claim 1, further comprising: At least one of a control region or a cell region is disposed on the semiconductor substrate.

4. The semiconductor chip according to claim 1, further comprising: A wiring layer is disposed on the first surface; as well as a connecting member disposed on a bottom surface of the wiring layer, The through-electrode is connected to the connection member through the wiring layer.

5. A semiconductor package, comprising: Package substrate; External connection terminals are arranged on the bottom surface of the packaging substrate; A first semiconductor chip is disposed on the package substrate, wherein the first semiconductor chip includes a first surface as an active surface and a second surface opposite to the first surface, wherein the first semiconductor chip includes: a through electrode provided in a central portion of the first semiconductor chip; and an intermediate pad disposed in an edge portion of the second surface of the first semiconductor chip; at least one second semiconductor chip disposed on the first semiconductor chip, wherein the at least one second semiconductor chip comprises an active surface facing the same direction as the second surface of the first semiconductor chip, and a chip pad disposed on the active surface of the at least one second semiconductor chip, wherein the middle pad is exposed; and A redistribution wiring is arranged on the second surface of the first semiconductor chip, wherein the chip pad is connected to the intermediate pad via wiring, the intermediate pad is connected to the through electrode via the rewiring, and the through electrode is connected to the external connection terminal, The middle pad is one of the middle pads. In which, the area where the multiple intermediate pads are set is divided into a first area and a second area in the first direction, wherein a first group of intermediate pads among the multiple intermediate pads configured to transmit data signals is set in the first area, and a second group of intermediate pads among the multiple intermediate pads configured to transmit command and address signals is set in the second area.

6. The semiconductor package according to claim 5, wherein: The first semiconductor chip further includes: an upper pad disposed on the second surface in a central portion of the first semiconductor chip and connected to the through-electrode, Wherein, the rewiring connects the middle pad to the upper pad.

7. The semiconductor package according to claim 6, in, The area where the upper pad is provided is divided into a third area corresponding to the first area and a fourth area corresponding to the second area in the first direction, The region where the external connection terminals are provided is divided into a fifth region corresponding to the first region and a sixth region corresponding to the second region in a second direction substantially perpendicular to the first direction.

8. The semiconductor package according to claim 5, wherein: The area where the external connection terminals are disposed is divided into two areas according to the type of transmitted signals.

9. The semiconductor package according to claim 5, in, The intermediate pad is one of a plurality of intermediate pads arranged in at least one column along a first direction, and the through-electrode is one of a plurality of through-electrodes arranged in at least one column along the first direction, The number of columns of the plurality of middle pads is equal to the number of the at least one second semiconductor chip.

10. The semiconductor package according to claim 5, wherein The first semiconductor chip includes at least one of a control region or a cell region.

11. The semiconductor package according to claim 5, further comprising: a supporting chip, disposed between the at least one second semiconductor chip and the packaging substrate, The first semiconductor chip is smaller than the at least one second semiconductor chip.

12. The semiconductor package according to claim 5, wherein: The first semiconductor chip further includes: Semiconductor substrates; a wiring layer disposed on a bottom surface of the semiconductor substrate; and a connecting member disposed on a bottom surface of the wiring layer, The bottom surface of the semiconductor substrate corresponds to the first surface of the first semiconductor chip, and the through-electrode penetrates the semiconductor substrate and is connected to the connection member through the wiring layer.

13. The semiconductor package according to claim 5, wherein: The first semiconductor chip is a master chip, and the at least one second semiconductor chip is a slave chip.

14. A semiconductor package, comprising: Package substrate; A first semiconductor chip is disposed on the packaging substrate. wherein the active surface of the first semiconductor chip is connected to the packaging substrate via a through electrode; and at least one second semiconductor chip disposed on the first semiconductor chip, wherein the inactive surface of the at least one second semiconductor chip faces the first semiconductor chip, and the at least one second semiconductor chip is connected to the first semiconductor chip by wire bonding, Wherein, the first semiconductor chip comprises: a plurality of intermediate pads arranged in an edge portion of the inactive surface of the first semiconductor chip along a first direction or a second direction, Wherein, the area where the multiple intermediate pads are set is divided into a first area and a second area in the first direction or the second direction, wherein a first group of intermediate pads among the multiple intermediate pads configured to transmit data signals are set in the first area, and a second group of intermediate pads among the multiple intermediate pads configured to transmit command and address signals are set in the second area.

15. The semiconductor package according to claim 14, wherein: The first semiconductor chip further includes: Semiconductor substrates; a wiring layer disposed on the bottom surface of the semiconductor substrate; a connecting member disposed on a bottom surface of the wiring layer, The through electrode is one of a plurality of through electrodes penetrating the semiconductor substrate. wherein the plurality of through electrodes are arranged in a central portion of the semiconductor substrate along a first direction or along a second direction substantially perpendicular to the first direction; an upper pad disposed in an inactive surface of the first semiconductor chip in a central portion of the semiconductor substrate, wherein the upper pad is connected to at least one of the through electrodes; and A redistribution wiring is disposed on the inactive surface of the first semiconductor chip and connects at least one of the intermediate pads to the upper pad.

16. The semiconductor package according to claim 15, further comprising: external connection terminals are provided on the bottom surface of the package substrate, The area where the external connection terminals are provided is divided into two areas in the second direction according to the type of the transmitted signal.

17. The semiconductor package according to claim 15, in, The intermediate pads are arranged in at least one row, and the through electrodes are arranged in at least one row, The number of columns of the middle pads is equal to the number of the at least one second semiconductor chip.

18. The semiconductor package according to claim 15, further comprising: external connection terminals are provided on the bottom surface of the package substrate, The area where the upper pad is provided is divided into a third area corresponding to the first area and a fourth area corresponding to the second area in the first direction or the second direction. The region where the external connection terminals are provided is divided into a fifth region corresponding to the first region and a sixth region corresponding to the second region in the second direction.

19. The semiconductor package according to claim 18, wherein: When the middle pad and the upper pad are divided in the first direction, the first wiring of the packaging substrate connected to the external connection terminal in the fifth area and the second wiring of the packaging substrate connected to the external connection terminal in the sixth area extend in relative directions in the first direction.

20. The semiconductor package according to claim 18, wherein When the middle pad and the upper pad are divided in the second direction, the first wiring of the packaging substrate connected to the external connection terminal in the fifth area and the second wiring of the packaging substrate connected to the external connection terminal in the sixth area extend along the second direction in the central part of the packaging substrate.

21. A semiconductor package, comprising: Package substrate; A first semiconductor chip is disposed on the packaging substrate. Wherein, the first semiconductor chip comprises: a through electrode provided in a central portion of the first semiconductor chip; and an intermediate pad disposed on an inactive surface of the first semiconductor chip in an edge portion of the first semiconductor chip; at least one second semiconductor chip disposed on the first semiconductor chip and comprising a chip pad disposed on an active surface of the at least one second semiconductor chip in an edge portion of the at least one second semiconductor chip, wherein an active surface of the at least one second semiconductor chip faces the same direction as an inactive surface of the first semiconductor chip, and the intermediate pad is exposed; and a sealing material, sealing the first semiconductor chip and the at least one second semiconductor chip, The middle pad is one of the middle pads. In which, the area where the multiple intermediate pads are set is divided into a first area and a second area in the first direction, wherein a first group of intermediate pads among the multiple intermediate pads configured to transmit data signals is set in the first area, and a second group of intermediate pads among the multiple intermediate pads configured to transmit command and address signals is set in the second area.

22. The semiconductor package according to claim 21, further comprising: Connecting components; an upper pad disposed on the inactive surface of the first semiconductor chip and connected to the through-electrode; as well as A redistribution wiring is provided on the inactive surface of the first semiconductor chip, The chip pad is connected to the middle pad through wiring, the middle pad is connected to the upper pad through the redistribution wiring, and the through-electrode is connected to a connection member.

23. The semiconductor package according to claim 21, further comprising: external connection terminals are provided on the bottom surface of the package substrate, The area where the external connection terminals are arranged is divided into two areas according to the type of the transmitted signal.

24. The semiconductor package according to claim 21, in, The at least one second semiconductor chip is one of a plurality of second semiconductor chips, and the middle pad is one of a plurality of middle pads arranged in at least one column, The plurality of second semiconductor chips are aligned in a vertical direction and stacked on the first semiconductor chip in a stepped structure. The number of columns of the middle pads is equal to the number of the second semiconductor chips.

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