Semiconductor Devices

Abstract

A semiconductor device includes a substrate, a through hole penetrating the substrate, a through hole insulating film formed along the inner wall of the through hole, and a core plug filling the through hole, wherein the residual stress of the through hole insulating film is 60MPa to 100MPa.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0081443 filed on Jul. 13, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] When developing a three-dimensional (3D) package that mounts multiple semiconductor chips in a single semiconductor package, a through silicon via (TSV) structure may be used to communicatively connect the semiconductor chips to each other. The TSV structure may penetrate a substrate or a die to vertically form an electrical connection between semiconductor chips.

[0005] The formation of the TSV structure may cause stress to be applied to nearby areas. Therefore, a semiconductor pattern is formed at a certain distance from the TSV structure. In this way, the semiconductor pattern can be protected from such stress. The area between the semiconductor pattern and the TSV structure can be called an exclusion zone. If the size of the exclusion zone can be minimized, the performance and efficiency of the semiconductor device can be improved. Summary of the invention

[0006] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including a substrate, a via penetrating the substrate, a via insulating film formed along an inner wall of the via, and a core plug filling the via, wherein the via insulating film has a residual stress of 60 MPa to -100 MPa.

[0007] According to an exemplary embodiment of the present invention, there is provided a semiconductor device, comprising: a packaging substrate; a first semiconductor substrate stacked on the packaging substrate; and a first through silicon via (TSV) structure penetrating the first semiconductor substrate and electrically connected to the packaging substrate, the first TSV structure comprising a first through via penetrating the first semiconductor substrate, a first through via insulating film formed along an inner wall of the first through via, and a first core plug filling the first through via, wherein a ratio of OH bonds to Si-O bonds in the first through via insulating film is 2 to 13.

[0008] According to an exemplary embodiment of the present invention, there is provided a semiconductor device, comprising: a substrate, comprising a first region and a second region; a first through-hole via, penetrating the substrate in the first region; a second through-hole via, penetrating the substrate in the second region; a first through-hole insulating film, formed along an inner wall of the first through-hole; a second through-hole insulating film, formed along an inner wall of the second through-hole; a first core plug, filling the first through-hole; and a second core plug, filling the second through-hole, wherein a residual stress of the first through-hole insulating film is less than a residual stress of the second through-hole insulating film.

[0009] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a through hole in a substrate; forming a through hole insulating film covering the bottom and side surfaces of the through hole by atomic layer deposition (ALD); forming a core plug filling the through hole on the through hole insulating film; performing annealing; revealing the upper surfaces of the through hole insulating film and the core plug by planarization; and removing a lower portion of the substrate to reveal the core plug at the bottom of the through hole.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device is provided, including: a substrate having a first region and a second region; a first exclusion zone arranged adjacent to the first region; a second exclusion zone arranged adjacent to the second region; a first through-hole insulating film arranged adjacent to the first exclusion zone; a second through-hole insulating film arranged adjacent to the second exclusion zone; a first barrier metal arranged adjacent to the first through-hole insulating film; a second barrier metal arranged adjacent to the second through-hole insulating film; and a core plug arranged between the first barrier metal and the second barrier metal, wherein the residual stress of each of the first through-hole insulating film and the second through-hole insulating film is +60MPa to -100MPa. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0014] Figure 3 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 4 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Figure 5is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0017] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 is a diagram for explaining an intermediate stage of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0020] Fig.19 , Fig. 20 , Fig.21 , Fig. 22 and Fig.23 are diagrams for explaining intermediate stages of a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] In the following, reference will be made to Figure 1 and Figure 2 A semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0022] Figure 1 is a cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 2 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0023] refer to Figure 1 and Figure 2 , a semiconductor device according to an exemplary embodiment of the inventive concept includes a substrate 100 and a through silicon via (TSV) structure 230 .

[0024] The first direction X may be a direction along the horizontal direction. The second direction Y may be another direction along the horizontal direction intersecting the first direction X. For example, the first direction X may be perpendicular to the second direction Y.

[0025] The third direction Z may be a direction intersecting both the first direction X and the second direction Y. The third direction Z may be, for example, perpendicular to both the first direction X and the second direction Y. The third direction Z may be, for example, a vertical direction.

[0026] The first direction X, the second direction Y, and the third direction Z may all be orthogonal to each other.

[0027] The substrate 100 may be a semiconductor wafer. In an exemplary embodiment of the present invention, the substrate 100 includes silicon (Si). In other exemplary embodiments of the present invention, the substrate 100 may include an elemental semiconductor such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In an exemplary embodiment of the present invention, the substrate 100 may have a silicon-on-insulator (SOI) structure. For example, the substrate 100 may include a buried oxide (BOX) layer.

[0028] The substrate 100 may include a TSV structure 230 therein. The substrate 100 may further include an exclusion zone 110 adjacent to the TSV structure 230. The exclusion zone 110 may be a region of the substrate 100 where no semiconductor pattern is formed.

[0029] For example, the exclusion zone 110 may be a region in which semiconductor elements such as transistors are not formed. The exclusion zone 110 is provided to prevent semiconductor elements near the TSV structure 230 from being adversely affected by stress.

[0030] For example, since stress may be transferred to the periphery of the TSV structure 230 in the process of forming the TSV structure 230 , the mobility of carriers in the substrate at the periphery of the TSV structure 230 may change.

[0031] Therefore, the semiconductor element formed adjacent to the TSV structure 230 may perform operations different from its original design. In this case, the reliability of the entire semiconductor device may be significantly reduced. Therefore, the exclusion zone 110 is included.

[0032] In other words, the exclusion zone 110 is a region adjacent to the TSV structure 230 , in which the mobility of carriers may vary due to stress. Therefore, the semiconductor element may not be formed in the exclusion zone 110 .

[0033] The exclusion zone 110 may surround the periphery of the TSV structure 230. The exclusion zone 110 is a region defined by a preset standard, and may be a region where the mobility of carriers changes by a specific value or changes by a larger value due to stress. The setting of the exclusion zone 110 may be based on previously obtained experimental data. The previous experimental data may be data on the mobility of specific carriers.

[0034] However, the semiconductor device according to the exemplary embodiment of the inventive concept is not limited thereto. For example, the setting of the exclusion zone 110 may be performed based on various criteria. In other words, the setting method of the exclusion zone 110 is not limited as long as it can determine that the size of the area around the TSV structure 230 is large enough to keep the adjacent semiconductor elements from being affected by stress.

[0035] Since the TSV structure 230 completely passes through the substrate 100 , it may be formed deeply along the third direction Z. For example, the TSV structure 230 may have a depth in the third direction Z of 1 μm to 120 μm.

[0036] The TSV structure 230 may include a through via 201 , a through via insulating film 200 , a barrier metal 210 , and a core plug 220 .

[0037] The through-hole 201 may be formed on the substrate 100 along the third direction Z. The through-hole 201 may completely penetrate the substrate 100. The cross-section of the through-hole 201 along the horizontal direction may be circular, but the inventive concept is not limited thereto. For example, the cross-section of the through-hole 201 along the horizontal direction may be elliptical.

[0038] exist Figure 1 and Figure 2 , the diameter of the through hole 201 is shown as being constant along the third direction Z, but the inventive concept is not limited thereto. For example, the diameter of the through hole 201 may narrow in the downward direction. In other words, the through hole 201 may taper. In this case, the through hole 201 may taper as a whole, or may taper partially such as the inlet portion.

[0039] The through-hole insulating film 200 may be formed along the inner wall of the through-hole 201. The through-hole insulating film 200 may be conformally formed along the inner wall of the through-hole 201. The through-hole insulating film 200 may be formed by atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD). Therefore, the thickness of the through-hole insulating film 200 may be uniform along the inner wall of the through-hole 201. The through-hole insulating film 200 may include an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

[0040] Since the through hole insulating film 200 is formed along the inner wall of the through hole 201, the horizontal cross section of the through hole insulating film 200 may have a ring shape. In other words, the through hole insulating film 200 may be formed into a cylindrical structure filling only a portion of the through hole 201 and having a hollow center.

[0041] The barrier metal 210 may be formed along the inner wall of the hollow via insulating film 200 in the through via 201. The barrier metal 210 may include a conductor. The barrier metal 210 may include, for example, W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

[0042] The barrier metal 210 may be located between the core plug 220 and the via insulating film 200 to enhance interface characteristics between the core plug 220 and the via insulating film 200 .

[0043] Since the barrier metal 210 is formed along the inner wall of the via insulating film 200, the horizontal cross-section of the barrier metal 210 may have a ring shape like the via insulating film 200. In other words, the barrier metal 210 fills only a portion of the penetration via 201 and may be formed of a cylindrical structure having a hollow center.

[0044] The core plug 220 may completely fill the penetration through hole 201. The core plug 220 may be formed on the barrier metal 210. Since the inner side of the core plug 220 is not empty, it may be in the form of a rod. The horizontal cross-section of the core plug 220 may have a circular shape.

[0045] Since the core plug 220 is used as a wiring, the core plug 220 may include a conductor. The core plug 220 may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, but is not limited thereto.

[0046] In the semiconductor device according to an exemplary embodiment of the inventive concept, the barrier metal 210 and the core plug 220 may be formed by, but not limited to, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

[0047] The core plug 220 may also be formed by electroplating after first forming a seed layer.

[0048] In this embodiment, although the TSV structure 230 is shown as being formed in the substrate 100 , the inventive concept is not limited thereto. For example, the TSV structure 230 may also be formed in a structure such as an interlayer insulating film instead of the substrate 100 .

[0049] Since the via insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD instead of CVD, the via insulating film 200 may have a residual stress lower than that of an insulating film formed by CVD.

[0050] For example, the residual stress of the through-hole insulating film 200 of the TSV structure 230 according to this embodiment may be +60 MPa to -100 MPa. Here, the direction of the residual stress may determine whether it is tensile stress or compressive stress. Tensile stress may be stress along a first direction (e.g., a pulling direction) due to the contraction of the material, and compressive stress may be stress along a second direction (e.g., a pushing direction) due to the expansion of the material.

[0051] In contrast, in the case of a via insulating film formed by CVD, the via insulating film may have a residual stress of about +180 MPa. In other words, the via insulating film 200 of the semiconductor device according to the exemplary embodiment of the inventive concept may have a very low residual stress compared to the via insulating film formed by CVD.

[0052] When the substrate 100 is a silicon substrate, such residual stress can be checked by performing Raman measurement on the substrate 100 around the TSV structure 230. In other words, since the degree of shift of the silicon peak is proportional to the applied stress, the residual stress can be measured by using Raman spectroscopy. For example, the residual stress can be measured by measuring the peak position of silicon in a stress-free state and comparing the degree of shift of the peak position caused by stress.

[0053] Since the through-hole insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD instead of CVD, it may have a different binding configuration from an insulating film formed by CVD.

[0054] For example, the through hole insulating film 200 may include a silicon oxide film or a silicon oxynitride film. In this case, the ratio of OH bonds to Si-O bonds in the through hole insulating film 200 (eg, the number of OH bonds / the number of Si-O bonds) may be 13 to 2.0.

[0055] In contrast, the ratio of OH bonds to Si-O bonds in the through-hole insulating film formed by CVD may be about 15.9. In other words, in the through-hole insulating film 200 of the semiconductor device according to the exemplary embodiment of the inventive concept, the ratio of OH bonds to Si-O bonds may be less than that of the through-hole insulating film formed by CVD.

[0056] The ratio of the OH bond and the Si-O bond in the via insulating film can be checked by Fourier transform infrared (FT-IR) spectroscopy measurement. FT-IR spectroscopy measurement can be a method using white light in the infrared range, where the white light can be phase modulated using an interferometer.

[0057] Since the through-hole insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD instead of CVD, the through-hole insulating film 200 may have a hardness different from that of the insulating film formed by CVD. In other words, the hardness of the through-hole insulating film 200 of the TSV structure 230 according to the present embodiment may be greater than that of the insulating film formed by CVD.

[0058] For example, based on the Vickers hardness, the hardness of the through-hole insulating film 200 of the TSV structure 230 according to the embodiment may be 5.0 to 7.2. In contrast, the hardness of the through-hole insulating film formed by CVD may be about 4.6. In other words, the through-hole insulating film 200 of the TSV structure 230 according to the present embodiment may be harder than the through-hole insulating film formed by CVD.

[0059] The hardness can be checked by an indentation test. In other words, the local resistance exhibited by a material when its surface is pressed into a certain indentation with a constant load can be the hardness.

[0060] Generally, the exclusion zone 110 formed around the TSV structure 230 may be provided to eliminate the influence of stress change caused by the formation process of the TSV structure 230. The stress change may be mainly caused by the difference in coefficient of thermal expansion (CTE) between the via insulating film 200, the core plug 220 and the substrate 100 and the contraction of the via insulating film 200.

[0061] In other words, in a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept described later, annealing may be performed to increase the conductivity of the core plug 220. In this case, since the core plug 220, the via insulating film 200, and the substrate 100 have different thermal expansion coefficients from each other, they may expand at different rates and may shrink when cooled again, and thus residual stress may be formed in such a process.

[0062] In addition, due to the above-mentioned annealing, the via insulating film formed by CVD may shrink greatly. Therefore, the space in which the core plug can expand during annealing can be further increased, which can further greatly contribute to the stress change after future annealing.

[0063] In the semiconductor device according to the present embodiment, the through-hole insulating film 200 can be formed by ALD or PE-ALD to prevent shrinkage of the through-hole insulating film. Therefore, compared with the shrinkage degree of the through-hole insulating film formed by CVD, in the through-hole insulating film 200 of the semiconductor device according to the present embodiment, the shrinkage caused by annealing can be significantly reduced.

[0064] Therefore, stress change of the substrate 100 adjacent to the TSV structure 230 of the semiconductor device is minimized, and the size of the exclusion zone 110 may also be minimized. Therefore, the integration and reliability of the semiconductor device may be greatly increased.

[0065] In the following, reference will be made to Figure 3 A semiconductor device according to an exemplary embodiment of the present invention is described. The above description will be simplified or omitted. Figure 1 and Figure 2 Repeating part of the description.

[0066] Figure 3 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0067] refer to Figure 3 , a semiconductor device according to an exemplary embodiment of the inventive concept includes a substrate 100 , a front end of line (FEOL) structure 130 , and a back end of line (BEOL) structure 140 .

[0068] The TSV structure 230 may include a core plug 220 penetrating the substrate 100 and the FEOL structure 130 , and a barrier metal 210 surrounding the core plug 220 .

[0069] The substrate 100 may be a semiconductor wafer. In an exemplary embodiment of the present inventive concept, the substrate 100 may include Si, Ge, SiC, GaAs, InAs, or InP. Alternatively, the substrate 100 may have an SOI structure. However, the present inventive concept is not limited thereto.

[0070] In an exemplary embodiment of the present inventive concept, the substrate 100 may include a conductive region such as an impurity-doped well or an impurity-doped structure. In addition, the substrate 100 may have various element isolation structures such as a shallow trench isolation (STI) structure.

[0071] The bottom surface 120B of the substrate 100 may be covered with a lower insulating film 122. The lower insulating layer 122 may include a silicon oxide layer, a silicon nitride layer, a polymer, or a combination thereof.

[0072] The FEOL structure 130 includes a plurality of various individual devices 132 and an interlayer insulating film 134. The plurality of individual devices 132 may include various microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), system large scale integrated circuits (LSIs), image sensors such as CMOS imaging sensors (CISs), micro-electromechanical systems (MEMSs), active devices, passive devices, etc.

[0073] The plurality of individual devices 132 may be electrically connected to the conductive region of the substrate 100. In addition, each of the plurality of individual devices 132 may be electrically isolated from other devices by an interlayer insulating film 134.

[0074] exist Figure 3 , the barrier metal 210 , the via insulating film 200 , and the core plug 220 may include a first portion covered by the substrate 100 and a second portion covered by the interlayer insulating film 134 .

[0075] The BEOL structure 140 includes a multi-layer wiring structure 146 including a plurality of metal wiring layers 142 and a plurality of contact plugs 144. The multi-layer wiring structure 146 may be connected to the TSV structure 230.

[0076] In an exemplary embodiment of the inventive concept, the BEOL structure 140 may further include other multi-layer wiring structures including a plurality of metal wiring layers and a plurality of contact plugs in other regions on the substrate 100 .

[0077] The BEOL structure 140 may include a plurality of wiring structures for connecting the individual devices 132 included in the FEOL structure 130 to other wirings. The multilayer wiring structure 146 included in the BEOL structure 140 and other wiring structures in the BEOL structure 140 may be insulated from each other by a metal interlayer insulating film 148.

[0078] In an exemplary embodiment of the inventive concept, the BEOL structure 140 may further include a sealing ring for protecting a plurality of wiring structures in the BEOL structure 140 and other structures below the BEOL structure 140 from external impact or moisture.

[0079] The top surface 30T of the TSV structure 230 that passes through the substrate 100 and the FEOL structure 130 is connected to the metal wiring layer 142 of the multi-layer wiring structure 146 included in the BEOL structure 140 .

[0080] An upper insulating film 150 is formed on the metal interlayer insulating film 148. The upper insulating film 150 may be a silicon oxide layer, a silicon nitride layer, a polymer, or a combination thereof.

[0081] A hole 150H is formed in the upper insulating film 150 through which a bonding pad 152 connected to the multilayer wiring structure 146 is exposed. The bonding pad 152 may be connected to the upper connection terminal 154 via the hole 150H. The bottom surface 30B of the TSV structure 230 is connected to the lower connection terminal 156.

[0082] The upper connection terminal 154 and the lower connection terminal 156 are not limited to Figure 3, and may have the shapes of solder balls, solder bumps, rewiring structures, or connection pads, respectively. In an exemplary embodiment of the inventive concept, at least one of the upper connection terminals 154 and the lower connection terminals 156 may be omitted.

[0083] The process of forming the BEOL structure 140, the upper connection terminal 154, and the lower connection terminal 156 is performed after forming the TSV structure 230. The process of forming the BEOL structure 140, the upper connection terminal 154, or the lower connection terminal 156 may involve a thermal process.

[0084] For example, during formation of the multilayer wiring structure 146 included in the BEOL structure 140 , or during formation of the upper connection terminal 154 or the lower connection terminal 156 , a thermal budget may be applied to the via insulating film 200 wrapping the periphery of the core plug 220 , and thermal stress may be applied thereto.

[0085] In the semiconductor device according to the present embodiment, the via insulating film 200 is formed by ALD or PE-ALD, and despite the thermal budget, the volume change of the via insulating film 200 may not be large. Therefore, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 can be minimized.

[0086] In the following, reference will be made to Figure 4 A semiconductor device according to an exemplary embodiment of the present invention is described. The above description will be simplified or omitted. Figures 1 to 3 Repeating part of the description.

[0087] Figure 4 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0088] refer to Figure 4 , the TSV structure 230 of the semiconductor device according to the exemplary embodiment of the inventive concept is formed after the FEOL structure 130 and the BEOL structure 140 are formed. Therefore, the TSV structure 230 is formed to penetrate the substrate 100, the interlayer insulating film 134 of the FEOL structure 130, and the metal interlayer insulating film 148 of the BEOL structure 140. The core plug 220, the via insulating film 200, and the barrier metal 210 of the TSV structure 230 include a first portion surrounded by the substrate 100, a second portion surrounded by the interlayer insulating film 134, and a third portion surrounded by the metal interlayer insulating film 148.

[0089] To electrically connect the TSV structure 230 and the upper connection terminal 154, an upper wiring 158 extends between the TSV structure 230 and the upper connection terminal 154 on the BEOL structure 140. The TSV structure 230 may be connected to the upper wiring 158 through the upper insulating film 150 and may be connected to the upper connection terminal 154 through the upper wiring 158.

[0090] The process of forming the upper wiring 158, the upper connection terminal 154, and the lower connection terminal 156 is performed after forming the TSV structure 230, and the process of forming the upper wiring 158, the upper connection terminal 154, or the lower connection terminal 156 may involve a thermal process. When performing such a thermal process, a thermal budget is applied to the through hole insulating film 200 surrounding the periphery of the core plug 220, and thermal stress may be applied thereto.

[0091] In the semiconductor device according to the present embodiment, the via insulating film 200 is formed by ALD or PE-ALD, and despite the thermal budget, the volume change of the via insulating film 200 may not be large. Therefore, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 can be minimized.

[0092] In the following, reference will be made to Figure 5 A semiconductor device according to an exemplary embodiment of the present invention is described. The above description will be simplified or omitted. Figures 1 to 4 Repeating part of the description.

[0093] Figure 5 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0094] refer to Figure 5 In the semiconductor device according to the exemplary embodiment of the inventive concept, the TSV structure 230 extends to penetrate the substrate 100. After the TSV structure 230 is formed, the FEOL structure 130 and the BEOL structure 140 are formed on the TSV structure 230 and the substrate 100. The TSV structure 230 may be connected to the multi-layer wiring structure 146 of the BEOL structure 140 via the connection wirings 136 and 138 included in the FEOL structure 130.

[0095] In the manufacturing process of the semiconductor device according to the exemplary embodiment of the inventive concept, the through-hole insulating film 200 may be formed by ALD or PF-ALD. Therefore, although a heat treatment (such as annealing) is subsequently performed, the volume change of the through-hole insulating film 200 may not be large. Therefore, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 can be minimized.

[0096] In the following, reference will be made to Figure 6A semiconductor device according to an exemplary embodiment of the present invention is described. The above description will be simplified or omitted. Figures 1 to 5 Repeating part of the description.

[0097] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0098] refer to Figure 6 , a semiconductor device according to an exemplary embodiment of the inventive concept may include a package substrate 1210 and integrated circuit elements 100 a and 100 b mounted on the package substrate 1210 .

[0099] In some embodiments of the present inventive concept, the package substrate 1210 may be a printed circuit board in which the wiring structure 212 is formed.

[0100] although Figure 6 A semiconductor device in which two integrated circuit elements 100 a and 100 b are mounted is shown, but the present invention is not limited thereto. For example, various numbers of integrated circuit elements 100 a and 100 b may be mounted vertically or horizontally on the package substrate 1210 .

[0101] exist Figure 6 In the figure, for convenience, the integrated circuit elements 100a and 100b are shown in a form in which some components are omitted. However, at least one of the integrated circuit elements 100a and 100b may have Figures 1 to 5 At least one of the semiconductor device structures shown.

[0102] The package substrate 1210 is formed with a plurality of connection terminals 214 connected to the internal wiring structure 212 for electrical connection with the outside. In an exemplary embodiment of the present inventive concept, the plurality of connection terminals 214 may be formed of solder balls, but is not limited thereto.

[0103] The electrical connection between the package substrate 1210 and the integrated circuit element 100b, or the electrical connection between two adjacent integrated circuit elements 100a and 100b can be performed through the core plug 220 formed in the integrated circuit element 100b. The TSV structure 230 is composed of the core plug 220, the barrier metal 210 surrounding the core plug 220, and the through-hole insulating film 200 surrounding the barrier metal 210.

[0104] The semiconductor device according to the exemplary embodiment of the inventive concept may include a molding film 1220 for molding at least one of the integrated circuit elements 100a and 100b. In the exemplary embodiment of the inventive concept, the molding film 1220 may be formed of a polymer. For example, the molding film 1220 may be made of epoxy molding compound (EMC).

[0105] In the following, reference will be made to Figure 1 , Figure 2 and Figure 7 A semiconductor device according to an exemplary embodiment of the inventive concept is described. Some repeated parts of the above description will be simplified or omitted.

[0106] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0107] refer to Figure 7 , a semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 100 , a first TSV structure 230 , a second TSV structure 630 , and an exclusion zone 110 .

[0108] The substrate 100 may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be adjacent to each other, or may be spaced apart from each other.

[0109] The first TSV structure 230 of the first region R1 may be Figure 1 and Figure 2 The first TSV structure 230 may include a first through via 201 , a first through via insulating film 200 , a first barrier metal 210 , and a first core plug 220 .

[0110] The first through via 201, the first through hole insulating film 200, the first barrier metal 210, and the first core plug 220 may have the same Figure 1 and Figure 2 The structures of the through via 201, the through-hole insulating film 200, the barrier metal 210 and the core plug 220 are the same.

[0111] The fourth direction X1, the fifth direction Y1, and the sixth direction Z1 of the first region R1 may be respectively Figure 1 and Figure 2 The first direction X, the second direction Y and the third direction Z are in the same direction.

[0112] The seventh direction X2 of the second region R2 may be a direction along the horizontal direction. The eighth direction Y2 of the second region R2 may be another direction along the horizontal direction intersecting with the seventh direction X2. For example, the seventh direction X2 may be perpendicular to the eighth direction Y2.

[0113] The ninth direction Z2 of the second region R2 may be a direction intersecting both the seventh direction X2 and the eighth direction Y2. The ninth direction Z2 may be, for example, perpendicular to both the seventh direction X2 and the eighth direction Y2. The ninth direction Z2 may be, for example, a vertical direction.

[0114] The seventh direction X2, the eighth direction Y2, and the ninth direction Z2 may all be orthogonal to each other.

[0115] The seventh direction X2, the eighth direction Y2, and the ninth direction Z2 of the second region R2 may be the same as or different from the fourth direction X1, the fifth direction Y1, and the sixth direction Z1 of the first region R1, respectively.

[0116] The second through via 601 of the second region R2 may be formed in the same size as the first through via 201 of the first region R1. In other words, the width of the second through via 601 in the seventh direction X2 may be the same as the width of the first through via 201 in the fourth direction X1.

[0117] The second via insulating film 600 may be formed along the inner wall of the second through via hole 601. The second via insulating film 600 may be formed of an oxide film, a nitride film, a carbonized film, a polymer, or a combination thereof.

[0118] In an exemplary embodiment of the present inventive concept, the second through hole insulating film 600 may be formed using a CVD process. For example, the second through hole insulating film 600 may be formed to have a thickness of about 1000 to 1000 mm. However, the present embodiment is not limited thereto.

[0119] For example, the second through hole insulating film 600 may be formed of ozone / tetraethyl orthosilicate (OESOS) by a sub-atmospheric CVD process. 3 The present invention also provides a method for forming an oxide film by using a high aspect ratio process (HARP) based on TEOS. However, the present embodiment is not limited thereto.

[0120] The first through-hole insulating film 200 may be formed by ALD or PE-ALD and have a first thickness T1. The second through-hole insulating film 600 may be formed by CVD and have a second thickness T2 greater than the first thickness T1. Therefore, the volume of the remaining area of ​​the first through-hole 201 may be greater than the volume of the remaining area of ​​the second through-hole 601. However, the present embodiment is not limited thereto.

[0121] The second barrier metal 610 may be formed along the inner wall of the hollow second via insulating film 600 in the second through via 601. The second barrier metal 610 may include a conductor. The second barrier metal 610 may include, for example, W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

[0122] The second core plug 620 may completely fill the second through via 601. The second core plug 620 may be formed on the second barrier metal 610. The second core plug 620 may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, but is not limited thereto.

[0123] The first core plug 220 may have a fifth thickness T5, and the second core plug 620 may have a sixth thickness T6. The fifth thickness T5 may be greater than the sixth thickness T6. This may be attributed to the fact that although the first through-hole 201 and the second through-hole 601 have the same width, the first thickness T1 and the second thickness T2 are different from each other. However, the present embodiment is not limited thereto.

[0124] The exclusion zone 110 of the first region R1 may be formed to have a third thickness T3 from the first TSV structure 230. The exclusion zone 110 of the second region R2 may be formed to have a fourth thickness T4 from the second TSV structure 630. The fourth thickness T4 may be greater than the third thickness T3. The size of the exclusion zone 110 may be determined by the mobility of carriers in the substrate 100. Therefore, the configuration in which the exclusion zone 110 of the first region R1 is smaller than the exclusion zone 110 of the second region R2 may mean that the region in which the mobility of carriers in the substrate 100 is affected is narrower in the first region R1 than in the second region R2.

[0125] This may be attributed to the difference in characteristics between the first through-hole insulating film 200 and the second through-hole insulating film 600. For example, the first through-hole insulating film 200 may have a lower residual stress than the second through-hole insulating film 600. The residual stress of the first through-hole insulating film 200 may be +60 MPa to -100 MPa. In contrast, the residual stress of the second through-hole insulating film 600 may be +180 MPa.

[0126] In addition, the ratio of OH bonds to Si-O bonds (eg, the number of OH bonds / the number of Si-O bonds) of the first through hole insulating film 200 may be 13 to 2.0. In contrast, the ratio of OH bonds to Si-O bonds of the second through hole insulating film 600 may be about 15.9.

[0127] In addition, the hardness of the first through hole insulating film 200 may be 5.0 to 7.2. In contrast, the hardness of the second through hole insulating film 600 may be about 4.6.

[0128] These characteristics can be attributed to the fact that the first via insulating film 200 is formed by ALD or PE-ALD, and the second via insulating film 600 is formed by CVD.

[0129] In the semiconductor device according to the present embodiment, since the first through hole insulating film 200 is formed by ALD or PE-ALD, the stress change of the substrate 100 adjacent to the TSV structure 230 in the first region R1 is minimized, and thus the size of the exclusion zone 110 can be minimized. Therefore, the integration and reliability of the semiconductor device can be greatly increased.

[0130] However, the second region R2 may be relatively less important than the first region R1 in view of the size of the exclusion zone 110. In this case, the second via insulating film 600 may be formed by CVD.

[0131] In the following, reference will be made to Figures 8 to 18 A method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention is described. Figures 1 to 7 Repeating part of the description.

[0132] Figures 8 to 18 are diagrams for explaining intermediate stages of a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0133] refer to Figure 8 After forming the FEOL structure 130 on the substrate 100 and forming the first polishing stop layer 135 on the FEOL structure 130, a mask pattern 137 is formed on the first polishing stop layer 135. A hole 137H for partially exposing the upper surface of the first polishing stop layer 135 may be formed in the mask pattern 137.

[0134] In an exemplary embodiment of the present inventive concept, the first polishing stop layer 135 may be made of a silicon nitride film or a silicon oxynitride film. The first polishing stop layer 135 may be formed to have a thickness of about 200 to 300 mm. However, the present inventive concept is not limited thereto. The first polishing stop layer 135 may be formed using a CVD process.

[0135] The mask pattern 137 may be made of a photoresist film.

[0136] An exclusion zone 110 may be provided in the substrate 100 and the FEOL structure 130. The exclusion zone 110 may be a region in which semiconductor elements such as the plurality of individual devices 132 are not formed.

[0137] Next, refer to Fig. 9 , using mask pattern 137 (see Figure 8 ) as an etching mask, the first polishing stop layer 135 and the interlayer insulating film 134 are etched, and then the substrate 100 is etched to form a through hole 201. The through hole 201 includes a first hole 201a formed in the substrate 100 at a predetermined depth and a second hole 201b formed through the interlayer insulating film 134 to communicate with the first hole 201a.

[0138] The through hole 201 may be formed using an anisotropic etching process. In an exemplary embodiment of the inventive concept, the through hole 201 may be formed to have a width 22W of about 10 μm or less from the sidewall of the substrate 100. In an exemplary embodiment of the inventive concept, the through hole 201 may be formed to have a depth 22D of about 50 to 100 μm from the upper surface of the interlayer insulating film 134. However, the width 22W and the depth 22D of the through hole 201 are not limited thereto and may be formed to various sizes.

[0139] The substrate 100 is exposed through the first hole 201a of the through hole 201, and the interlayer insulating film 134 is exposed through the second hole 201b of the through hole 201. In other embodiments of the present inventive concept, the through hole 201 may be formed using a laser drilling technique.

[0140] After forming the through hole 201 , the mask pattern 137 is removed to expose the upper surface of the first polishing stop layer 135 .

[0141] Then, refer to Fig.10 , a through hole insulating film 200 is formed to cover the inner side wall and the bottom surface of the through hole 201.

[0142] The via insulating film 200 is formed to cover the surface of the substrate 100 exposed in the via hole 201 and the surface of the interlayer insulating film 134 and the surface of the first polishing stop layer 135 .

[0143] The via insulating film 200 may be formed by ALD or PE-ALD. The via insulating film 200 may be conformally formed along the inner wall of the via hole 201. The thickness of the via insulating film 200 may be a seventh thickness Ta.

[0144] Then, refer to Fig.11 , a barrier metal 210 is formed on the via insulating film 200 inside and outside the via hole 201 .

[0145] The barrier metal 210 may be formed using a PVD process or a CVD process.

[0146] In an exemplary embodiment of the present inventive concept, the barrier metal 210 may include a single film formed of one material or a multi-film formed of at least two materials. In an exemplary embodiment of the present inventive concept, the barrier metal 210 may include W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or SiB. For example, the barrier metal 210 may have a thickness of about 50 to 100 mm. The TaN film has a thickness of about 1000 to Stacked structure of Ta films.

[0147] Then, refer to Fig.12, a seed film 220S is formed on the barrier metal 210 inside and outside the through hole 201.

[0148] The seed film 220S may be used as an electroplating seed for later forming a core plug.

[0149] The seed film 220S may be formed of Cu, a Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu. The seed film 220S may be formed using a PVD process. However, the inventive concept is not limited thereto.

[0150] Then, refer to Fig.13 , a core film 220P is formed on the barrier metal 210 to fill the remaining space of the through hole 201 .

[0151] The process of forming the core film 220P can be the same as that of reference Fig.12 The process of forming the barrier metal 210 is described as being performed in-situ. However, the pressure when forming the barrier metal 210 may be different from the pressure when forming the core film 220P.

[0152] The core film 220P may be formed to cover the barrier metal 210 inside and outside the through hole 201 .

[0153] The core film 220P may be formed by an electroplating process. In other words, a metal film is grown from the seed film 220S, and the core film 220P for filling the through hole 201 is formed on the barrier metal 210 .

[0154] The main material of the core film 220P may be formed of Cu or W. In an exemplary embodiment of the present inventive concept, the core film 220P may be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, but is not limited thereto.

[0155] The core film 220P may be formed through an electroplating process. The electroplating process may be performed at any temperature of about 10 to 65° C. For example, the electroplating process may be performed at room temperature.

[0156] Then, refer to Fig.14 and Fig.15 , annealing 50 may be performed.

[0157] The annealing 50 may be a heat treatment process for increasing the conductivity of the core film 220P. For example, since the core film 220P is formed through an electroplating process, the size of the grains is small and the conductivity may be low.

[0158] Since the core film 220P is later used as a wiring to the core plug 220, higher conductivity is required. Therefore, the size of the crystal grains can be increased by recrystallizing the core film 220P through annealing 50. Therefore, the grain boundaries of the crystals of the core film 220P are reduced, and the conductivity of the core film 220P can be greatly increased.

[0159] The thickness of the via insulating film 200 can be reduced by such annealing 50. For example, the seventh thickness Ta can be reduced to the eighth thickness Tb. At this time, since the via insulating film 200 is an insulating film formed by ALD or PE-ALD, it can shrink relatively less than an insulating film formed by CVD.

[0160] Fig.15 The graph (a) in FIG. 1 may be a through-hole insulating film 200 before annealing 50, Fig.15 Graph (b) in FIG. 5 may be the through-hole insulating film 200 after annealing 50. Through annealing 50, additional bonding may be performed in dangling bonds and porous regions of the through-hole insulating film 200 before annealing 50. Therefore, the configuration of the through-hole insulating film 200 may become denser and harder.

[0161] Since the via insulating film 200 of the method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept is formed by ALD or PE-ALD, the via insulating film 200 can be relatively harder and denser than a via insulating film formed by CVD. In addition, the degree of shrinkage caused by annealing 50 can be lower.

[0162] Then, refer to Fig.16 The first polishing stop layer 135 is used as a stop point to polish the core film 220P by a chemical mechanical polishing (CMP) process. Fig.14 The resulting product is polished, thereby revealing the first polish stop layer 135 .

[0163] Therefore, the via insulating film 200 , the barrier metal 210 , and the portion of the core film 220P outside the via hole 201 are removed, and the core plug 220 as a part of the core film 220P remains on the barrier metal 210 in the via hole 201 .

[0164] Then, refer to Fig.17 , the first polishing stop layer 135 can be removed (see Fig.16 ).

[0165] exist Figures 14 to 16 An example of performing CMP after performing annealing 50 is provided in FIG. 5 , but the inventive concept is not limited thereto. CMP may also be performed and then annealing 50 may be performed.

[0166] In other words, the resultant structure obtained by forming the core plug 220 in the through hole 201 is annealed. Therefore, metal particles constituting the core plug 220 grow by the heat treatment, and the roughness on the exposed surface of the core plug 220 may be deteriorated. The portion of the metal particles grown by the heat treatment that protrudes outside the through hole 201 may be removed again by the CMP process.

[0167] At this time, the first polishing stop layer 135 (see Fig.16 ), and the upper surface of the interlayer insulating film 134 of the FEOL structure 130 may be exposed to the outside. In an exemplary embodiment of the inventive concept, the heat treatment may be performed at a temperature of about 300 to 500°C.

[0168] A TSV structure 230 including the core plug 220 , the barrier metal 210 surrounding the core plug 220 , and the through-hole insulating film 200 remains in the through-hole 201 .

[0169] Then, refer to Fig.18 , a lower portion of the substrate 100 is removed to form a through via 201 .

[0170] The lower portion of the substrate 100 may be a portion forming a bottom surface of the through hole 201. When the lower portion of the substrate 100 is removed, the through hole 201 may become a through-through hole 201 penetrating through the substrate 100.

[0171] At this time, the lower portions of the via insulating film 200, the barrier metal 210, and the core plug 220 located below the via hole 201 may also be removed. Therefore, the bottom surfaces of the via insulating film 200, the barrier metal 210, and the core plug 220 may be exposed to the outside.

[0172] In the method of manufacturing a semiconductor device according to the present embodiment, by forming the through-hole insulating film 200 by ALD or PE-ALD, shrinkage of the through-hole insulating film 200 due to the annealing 50 can be minimized. Therefore, the provision of the exclusion zone 110 can be minimized. Therefore, the integration and reliability of the semiconductor device can be increased.

[0173] In the following, reference will be made to Figures 8 to 10 and Figures 19 to 23 A method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept is described. Some repeated parts of the above description will be simplified or omitted.

[0174] Figures 19 to 23 are diagrams for explaining intermediate stages of a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0175] Corresponds to Figures 8 to 10 Steps and Figures 8 to 10 Therefore, for convenience, we will start from Fig.10The following steps are described.

[0176] refer to Fig.19 , a pre-annealing 51 is performed on the via insulating film 200 .

[0177] The pre-annealing 51 may shrink the via insulating film 200 of the seventh thickness Ta to the ninth thickness Tc. By the pre-annealing 51, the space within the via hole 201 may become wider than before.

[0178] Next, refer to Fig. 20 , a barrier metal 210 is formed on the via insulating film 200 inside and outside the via hole 201 .

[0179] The barrier metal 210 may be formed using a PVD process or a CVD process. In an exemplary embodiment of the present inventive concept, the barrier metal 210 may include W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

[0180] Then, refer to Fig.21 , a seed film 220S is formed on the barrier metal 210 inside and outside the through hole 201. The seed film 220S may be formed of Cu, Cu alloy, Co, Ni, Ru, Co / Cu or Ru / Cu. The seed film 220S may be formed using a PVD process. However, the inventive concept is not limited thereto.

[0181] Then, refer to Fig. 22 , a core film 220P is formed on the barrier metal 210 to fill the remaining space of the through hole 201. The main material of the core film 220P may be formed of Cu or W. In an exemplary embodiment of the present inventive concept, the core film 220P may be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W or a W alloy, but is not limited thereto. The core film 220P may be formed by an electroplating process.

[0182] Then, refer to Fig.23 , annealing 50 may be performed.

[0183] The annealing 50 may be a heat treatment process for increasing the conductivity of the core film 220P. For example, since the core film 220P is formed through an electroplating process, the size of the grains is small and the conductivity may be low.

[0184] The via insulating film 200 may shrink from the ninth thickness Tc to the tenth thickness Td by the annealing 50. However, since the via insulating film 200 is in a state already shrunk by the pre-annealing 51, the shrinkage due to the annealing 50 may not be large.

[0185] Therefore, the core film 220P may not expand to a greater extent than when the pre-annealing 51 is not performed. This is because, in the absence of the pre-annealing 51, the core film 220P is formed in a state where the through-hole insulating film 200 has not shrunk to the ninth thickness Tc. Therefore, the through-hole insulating film 200 shrinks greatly due to the annealing 50, and the core film 220P may expand by a space corresponding to the shrinkage of the through-hole insulating film 200. However, when the pre-annealing 51 is performed, since the through-hole insulating film 200 has already shrunk to the ninth thickness Tc, the core film 220P may be formed to be larger than when the pre-annealing 51 is not performed.

[0186] Therefore, the expansion rate when annealing 50 is performed later can be lower, and the shrinkage degree can be lower again when the temperature drops after annealing 50. Since the stress formed by TSV structure 230 is proportional to the shrinkage degree, in the method of manufacturing a semiconductor according to this embodiment, a lower stress can be applied to minimize exclusion zone 110.

[0187] Then, similar to Figures 16 to 18 , a CMP process and a process of forming the through via 201 may be performed.

[0188] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor device, comprising: substrate; a through hole penetrating the substrate; a first through-hole insulating film formed along an inner wall of the through-hole; a second through hole insulating film; as well as core plug, filling the through hole, Wherein, the residual stress of the first through-hole insulating film is 60MPa to -100Mpa, and A ratio of OH bonds to Si—O bonds in the first through hole insulating film is smaller than a ratio of OH bonds to Si—O bonds in the second through hole insulating film.

2. The semiconductor device according to claim 1, wherein The first via hole insulating film includes a silicon oxide film or a silicon oxynitride film.

3. The semiconductor device according to claim 2, wherein: A ratio of OH bonds to Si—O bonds in the first via hole insulating film is 2 to 13.

4. The semiconductor device according to claim 1, wherein: The substrate includes Si.

5. The semiconductor device according to claim 1, wherein The first via hole insulating film has a hardness of 5.0 to 7.

2.

6. The semiconductor device according to claim 1, wherein The residual stress is measured by Raman spectroscopy.

7. The semiconductor device according to claim 1, further comprising: A barrier metal is formed between the first via insulating film and the core plug.

8. The semiconductor device according to claim 7, wherein: The barrier metal includes W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni or NiB.

9. The semiconductor device according to claim 1, wherein: The first via hole insulating film is conformally formed along an inner wall of the via hole.

10. A semiconductor device comprising: Package substrate; A first semiconductor substrate, stacked on the packaging substrate; a first through silicon via (TSV) structure, penetrating the first semiconductor substrate and electrically connected to the package substrate, the first TSV structure comprising a first through hole penetrating the first semiconductor substrate, a first through hole insulating film formed along an inner wall of the first through hole, and a first core plug filling the first through hole; a second semiconductor substrate, stacked on the first semiconductor substrate; as well as a second TSV structure penetrating the second semiconductor substrate and electrically connected to the first semiconductor substrate or the packaging substrate, wherein the ratio of OH bonds to Si-O bonds in the first through-hole insulating film is 2 to 13, The second TSV structure includes a second through-hole penetrating the second semiconductor substrate, a second through-hole insulating film formed along an inner wall of the second through-hole, and a second core plug filling the second through-hole, and A ratio of OH bonds to Si—O bonds in the first through hole insulating film is smaller than a ratio of OH bonds to Si—O bonds in the second through hole insulating film.

11. The semiconductor device according to claim 10, wherein: A ratio of OH bonds to Si—O bonds in the second via hole insulating film is 2 to 13.

12. The semiconductor device according to claim 10, wherein: The residual stress of the first via insulating film is 60 MPa to -100 MPa.

13. The semiconductor device according to claim 10, wherein: The first via hole insulating film has a hardness of 5.0 to 7.

2.

14. A semiconductor device comprising: A substrate including a first region and a second region; a first through-via penetrating the substrate in the first region; a second through-via penetrating the substrate in the second region; a first through-hole insulating film formed along an inner wall of the first through-hole; a second through-hole insulating film formed along an inner wall of the second through-hole; a first core plug filling the first through-hole; and a second core plug, filling the second through-hole, wherein the residual stress of the first through-hole insulating film is smaller than the residual stress of the second through-hole insulating film, The ratio of OH bonds to Si-O bonds in the first through-hole insulating film is smaller than the ratio of OH bonds to Si-O bonds in the second through-hole insulating film.

15. The semiconductor device according to claim 14, wherein: The first via insulating film has a harder hardness than the second via insulating film.

16. The semiconductor device according to claim 14, further comprising: a first exclusion zone formed in the substrate around the first through via; as well as a second exclusion zone formed in the substrate around the second through via, The first exclusion zone and the second exclusion zone are regions where no semiconductor pattern is formed.

17. The semiconductor device according to claim 16, wherein: An area of ​​the first exclusion zone is smaller than an area of ​​the second exclusion zone.

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