Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device, comprising: forming a first wiring layer on a substrate, the first wiring layer including a first metal wiring and a first interlayer insulating film surrounding the first metal wiring, forming a first via layer on the first wiring layer, the first via layer including a first via electrically connected to the first metal wiring and a second interlayer insulating film surrounding the first via; and forming a second wiring layer on the first via layer, the second wiring layer including a second metal wiring electrically connected to the first via and a third interlayer insulating film surrounding the second metal wiring, wherein the third interlayer insulating film contains deuterium and is formed by chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire disclosure of Korean Patent Application No. 10-2018-0083916, entitled “Method of Manufacturing Semiconductor Device”, filed in the Korean Intellectual Property Office on July 19, 2018, is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a method for manufacturing a semiconductor device. Background Art

[0004] As the size of semiconductor devices shrinks faster with the development of electronic technology, high integration and low power consumption of semiconductor chips are required. Summary of the invention

[0005] An embodiment relates to a method for manufacturing a semiconductor device, the method comprising: forming a first wiring layer on a substrate, the first wiring layer comprising a first metal wiring and a first interlayer insulating film surrounding the first metal wiring, forming a first via layer on the first wiring layer, the first via layer comprising a first via electrically connected to the first metal wiring and a second interlayer insulating film surrounding the first via; and forming a second wiring layer on the first via layer, the second wiring layer comprising a second metal wiring electrically connected to the first via and a third interlayer insulating film surrounding the second metal wiring, wherein the third interlayer insulating film contains deuterium and is formed by chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

[0006] An embodiment also relates to a method for manufacturing a semiconductor device, the method comprising: forming a first wiring layer on a substrate, the first wiring layer comprising a first metal wiring and a first interlayer insulating film surrounding the first metal wiring; and forming a second wiring layer, the second wiring layer comprising a first through-hole on the first wiring layer electrically connected to the first metal wiring, a second metal wiring on the first through-hole and electrically connected to the first through-hole, and a second interlayer insulating film surrounding the first through-hole and the second metal wiring, wherein the second interlayer insulating film contains deuterium and is formed by chemical vapor deposition using a first gas containing deuterium.

[0007] An embodiment also relates to a method for manufacturing a semiconductor device, the method comprising: forming a first interlayer insulating film including a first groove on a substrate; forming a first metal wiring filling the first groove; forming a first etch stop film covering the first interlayer insulating film and the first metal wiring; forming a second interlayer insulating film on the first etch stop film, the second interlayer insulating film including a second groove penetrating the first etch stop film; forming a first through hole filling the second groove; forming a second metal wiring on the first through hole; and forming a third interlayer insulating film on the second interlayer insulating film to cover the side surface and upper surface of the second metal wiring, wherein the third interlayer insulating film includes deuterium and is formed by chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a view for explaining a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an example embodiment;

[0010] Figures 2 to 7 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments;

[0011] Figure 8 shows a view for explaining a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an example embodiment;

[0012] Fig. 9 and Fig.10 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments;

[0013] Fig.11 and Fig.12 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments;

[0014] Figures 13 to 16 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments; and

[0015] Fig.17 and Fig.18 are views showing intermediate manufacturing stages, which are used to explain a method for manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0016] In the following, reference Figure 1 , a semiconductor device manufactured by a semiconductor device manufacturing method according to example embodiments will be described.

[0017] Figure 1 is a view for explaining a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an example embodiment;

[0018] refer to Figure 1 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to example embodiments includes a substrate 100 , a first wiring layer 110 , a first via layer 120 , and a second wiring layer 130 .

[0019] The substrate 100 may be a structure in which a base substrate and an epi-layer (epitaxial layer) are stacked one on the other. The substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for display or a semiconductor on insulator (SOI) substrate.

[0020] In addition, the substrate 100 may include a conductive pattern. For example, the conductive pattern may be a metal wiring or a contact, a gate electrode of a transistor, a source / drain of a transistor, or a diode.

[0021] The first wiring layer 110 may be formed on the substrate 100. The first wiring layer 110 may include, for example, a first metal wiring 111, a first barrier film 112, a first capping film 113, and a first interlayer insulating film 114.

[0022] The first interlayer insulating film 114 may be formed on the substrate 100. The first interlayer insulating film 114 may be formed to surround the first metal wiring 111. The first interlayer insulating film 114 may include a first trench T1 formed therein.

[0023] The first interlayer insulating film 114 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. The first interlayer insulating film 114 may include a low-k dielectric material to improve a coupling shape between wirings.

[0024] The low-k dielectric material may include, for example, one or more of the following: flowable oxide (FOX), tetraethyl orthosilicate (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, or a porous polymer material.

[0025] The first barrier film 112 may be formed along the sidewalls and bottom surface of the first trench T1. The first barrier film 112 may block elements included in the first metal wiring 111 from diffusing into the first interlayer insulating film 114, etc., or block oxygen included in the first interlayer insulating film 114 from diffusing into the first metal wiring 111.

[0026] The first barrier film 112 may include, for example, one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), or niobium nitride (NbN).

[0027] The first metal wiring 111 may be formed within the first trench T1 by filling the first trench T1. The first metal wiring 111 may be formed on the first barrier film 112. The first metal wiring 111 may be electrically connected to a conductive pattern that may be included in the substrate 100.

[0028] The first metal wiring 111 may include one or more of copper (Cu), carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr). In example embodiments, the first metal wiring 111 includes copper (Cu).

[0029] A liner film may be formed between the first metal wiring 111 and the first barrier film 112 .

[0030] The backing film may include, for example, one or more of the following: ruthenium (Ru), platinum (Pt), iridium (Ir), and rhodium (Rh). The above-mentioned noble metal may include, for example, at least one of the following: ruthenium (Ru), platinum (Pt), iridium (Ir), or rhodium (Rh).

[0031] The first capping film 113 may be formed on an upper surface of the first metal wiring 111. The first capping film 113 may, for example, be in direct contact with the first barrier film 112 within the first trench (T1).

[0032] In addition, despite Figure 1 It is illustrated that the first cover film 113 completely covers the upper surface of the first metal wiring 111 , but according to example embodiments, the first cover film 113 may be formed to cover only a portion of the upper surface of the first metal wiring 111 .

[0033] The first capping film 113 may include, for example, one or more of cobalt (Co), ruthenium (Ru), or manganese (Mn).

[0034] The first via layer 120 may be formed on the first wiring layer 110. The first via layer 120 may include a first via 121, a first via barrier film 122, a second interlayer insulating film 124, and a first etch stopper film 125.

[0035] The first etch stopper film 125 may be formed on the first wiring layer 110. The first etch stopper film 125 may include, for example, one or more of silicon nitride, silicon oxynitride, or silicon carbonitride.

[0036] The second interlayer insulating film 124 may be formed on the first etch stopper film 125. The second interlayer insulating film 124 and the first etch stopper film 125 may be formed to surround a side surface of the first through hole 121.

[0037] The second interlayer insulating film 124 may include a second trench T2 formed in the second interlayer insulating film 124. The second trench T2 may penetrate the second interlayer insulating film 124 and the first etch stopper film 125 to be formed so that the first capping film 113 may be exposed.

[0038] Second interlayer insulating film 124 may include, for example, the same material as first interlayer insulating film 114, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. According to example embodiments, second interlayer insulating film 124 may include a different material from first interlayer insulating film 114.

[0039] The first via barrier film 122 may be formed along the sidewalls and bottom surface of the second trench T2. The first via barrier film 122 may include, for example, one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), or niobium nitride (NbN).

[0040] The first via 121 may be formed in the second trench T2 by filling the second trench T2. The first via 121 may be formed on the first via barrier film 122. The first via 121 may be electrically connected to the first metal wiring 111.

[0041] The first through hole 121 may include one or more of copper (Cu), carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr). In example embodiments, the first through hole 121 includes copper (Cu).

[0042] The second wiring layer 130 may be formed on the first via layer 120. The second wiring layer 130 may include a second metal wiring 131, a second barrier film 132, a second capping film 133, and a third interlayer insulating film 134.

[0043] The third interlayer insulating film 134 may be formed on the first via layer 120. The third interlayer insulating film 134 may be formed to surround the second metal wiring 131.

[0044] The third interlayer insulating film 134 may be formed to be in direct contact with the second interlayer insulating film 124. According to example embodiments, an etch stop film may be formed between the third interlayer insulating film 134 and the second interlayer insulating film 124.

[0045] The third interlayer insulating film 134 may be formed to cover the upper surface of the second metal wiring 131. According to example embodiments, the upper surface of the third interlayer insulating film 134 may be formed on the same plane as the upper surface of the second cover film 133 formed on the second metal wiring 131.

[0046] The third interlayer insulating film 134 may be formed by chemical vapor deposition (CVD), etc. A method of forming the third interlayer insulating film 134 will be described in detail below.

[0047] The third interlayer insulating film 134 may include deuterium (D). In addition, the third interlayer insulating film 134 may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0048] The first interlayer insulating film 114 and the second interlayer insulating film 124 may not include, for example, deuterium (D) exceeding its naturally occurring amount. For example, a material to which deuterium (D) is added may not be used in forming the first interlayer insulating film 114 and the second interlayer insulating film 124 .

[0049] The second barrier film 132 may be formed on the first via hole 121 and the first via barrier film 122. In addition, a portion of the second barrier film 132 may be formed on the second interlayer insulating film 124.

[0050] The second barrier film 132 may include, for example, one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), or niobium nitride (NbN).

[0051] The second metal wiring 131 may be formed on the second barrier film 132. The second metal wiring 131 may be formed to completely overlap the second barrier film 132. The second metal wiring 131 may be electrically connected to the first via 121.

[0052] Second metal wiring 131 may include one or more of copper (Cu), carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr). In example embodiments, second metal wiring 131 includes copper (Cu).

[0053] Second capping film 133 may be formed on an upper surface of second metal wiring 131. Second capping film 133 may include, for example, one or more of cobalt (Co), ruthenium (Ru), or manganese (Mn).

[0054] like Figure 1 As shown, the second barrier film 132, the second metal wiring 131, and the second capping film 133 may have a stacked shape, showing a sequential stacking one on top of another. Therefore, the sidewalls of the second barrier film 132, the second metal wiring 131, and the second capping film 133 may be formed to contact the third interlayer insulating film, respectively. According to example embodiments, the second barrier film 132 may be formed along the sidewalls of the second metal wiring 131.

[0055] In the following, reference will be made to Figures 1 to 7 A method for manufacturing a semiconductor device according to example embodiments is described.

[0056] Figures 2 to 7 are views showing intermediate manufacturing stages, which are used to explain a method for manufacturing a semiconductor device according to an example embodiment;

[0057] refer to Figure 2 , a first interlayer insulating film 114 may be formed on the substrate 100. The first interlayer insulating film 114 may be formed by, for example, chemical vapor deposition (CVD), spin coating, thermal CVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or the like.

[0058] Next, the first trench T1 may be formed in the first interlayer insulating film 114 by etching the first interlayer insulating film 114 using the mask pattern. As a result, the first interlayer insulating film 114 including the first trench T1 may be formed on the substrate 100 .

[0059] although Figure 2 It is illustrated that the first trench T1 is formed such that the substrate 100 is not exposed by the first trench T1 , but according to example embodiments, the first trench T1 may be formed to expose the substrate 100 by penetrating the first interlayer insulating film 114 .

[0060] According to example embodiments, the first trench T1 may be formed by etching the etch stopper film and the first interlayer insulating film 114 using a mask pattern after the etch stopper film and the first interlayer insulating film 114 are sequentially stacked on the substrate 100 .

[0061] refer to Figure 3 , a first barrier film 112 may be formed in the first trench T1 along the sidewall and bottom surface of the first trench T1 .

[0062] Next, as the first metal wiring 111 is formed on the first barrier film 112 and then the first capping film 113 is formed on the first metal wiring 111 to fill the first trench T1 , the first wiring layer 110 may be formed.

[0063] refer to Figure 4 , a first etch stopper film 125 and a second interlayer insulating film 124 may be sequentially stacked on the first wiring layer 110 .

[0064] The first etch stopper film 125 may be formed using, for example, chemical vapor deposition (CVD), etc. The second interlayer insulating film 124 may be formed using, for example, chemical vapor deposition (CVD), spin coating, thermal CVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), etc.

[0065] Next, a second trench T2 may be formed in the second interlayer insulating film 124 by etching the second interlayer insulating film 124 and the first etch stopper film 125 using a mask pattern to expose the first capping film 113. As a result, the second interlayer insulating film 124 including the second trench T2 may be formed on the first wiring layer 110.

[0066] refer to Figure 5 , a first via barrier film 122 may be formed in the second trench T2 along the sidewall and the bottom surface of the second trench T2 .

[0067] Next, as the first via hole 121 is formed on the first via barrier film 122 to fill the second trench T2 , the first via layer 120 may be formed.

[0068] refer to Figure 6 , the second barrier film material 132 a , the second metal wiring material 131 a , and the second capping film material 133 a may be sequentially stacked on the first via layer 120 .

[0069] refer to Figure 7 , a stack of a second barrier film 132, a second metal wiring 131, and a second covering film 133 can be formed by etching the second barrier film material 132a, the second metal wiring material 131a, and the second covering film material 133a using a mask pattern, and the second barrier film 132, the second metal wiring 131, and the second covering film 133 are stacked on the first through-hole layer 120 in a sequential order.

[0070] For ease of explanation, Figure 7 Two stacks of the second barrier film 132 , the second metal wiring 131 , and the second capping film 133 are shown stacked in sequential order on the first via layer 120 and offset.

[0071] Return to reference Figure 1 , a third interlayer insulating film 134 may be formed on the first via layer 120. For example, the third interlayer insulating film 134 may be formed to cover the side surface and the upper surface of the second metal wiring 131. For example, the third interlayer insulating film 134 may be formed to cover the side wall of the second barrier film 132, the side wall of the second metal wiring 131, and the side wall and the upper surface of the second capping film 133.

[0072] The third interlayer insulating film 134 may be formed using, for example, chemical vapor deposition (CVD), thermal CVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), etc. When the third interlayer insulating film 134 is formed using, for example, HDP-CVD, the third interlayer insulating film 134 may be formed at a process temperature lower than 450°C.

[0073] For example, the third interlayer insulating film 134 may be formed by CVD using a first gas containing deuterium (D) (eg, one or more deuterium atoms) and a second gas containing hydrogen (H) (eg, one or more hydrogen atoms). As a result, the third interlayer insulating film 134 may include deuterium (D).

[0074] The first gas may include, for example, one or more of the following: SiD 4 , D 2 , D 2 O. HD 3 、Si 2 D 6 or (C 2 H 5 ) 3 SiD.

[0075] The second gas may include, for example, SiH 4 .

[0076] According to example embodiments, in addition to the first gas containing deuterium (D) and the second gas containing hydrogen (H), a carrier gas may be used. The carrier gas may include, for example, one or more of the following: Ar, O 2 、N 2 , H 2 , D 2 , D 2 O. HD 3 ND 3 ,NDHe,O 3 NH 3 , Kr or Xe.

[0077] Supplying the first gas containing deuterium (D) and the second gas containing hydrogen (H) and performing CVD may be performed simultaneously. As a result, deuterium (D) may be supplied through the second metal wiring 131, the first via 121, and the first metal wiring 111 while the third interlayer insulating film 134 is formed by CVD.

[0078] By forming the third interlayer insulating film 134 through CVD using hydrogen (H) and deuterium (D), the reliability of the semiconductor device can be enhanced and the characteristics of the film material can be improved.

[0079] It can be manufactured by the above manufacturing method Figure 1 Although the present specification describes that CVD using hydrogen (H) and deuterium (D) is used to form an interlayer insulating film surrounding a metal wiring, according to example embodiments, another dielectric film such as a gate insulating film may be formed by CVD using hydrogen (H) and deuterium (D).

[0080] In the following, reference will be made to Figure 8 A method for manufacturing a semiconductor device according to an example embodiment is described. Figures 1 to 7 The differences between the method for manufacturing a semiconductor device shown in .

[0081] Figure 8 is a view for explaining a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an example embodiment;

[0082] refer to Figure 8 , in execution Figure 7 After the process shown in , the third interlayer insulating film 134 may be formed on the first via layer 120. According to the present example embodiment, an air gap 235 may be formed within the third interlayer insulating film 134.

[0083] An air gap 235 may be formed between two stacks that are shifted from each other and formed by sequentially stacking the second barrier film 132 , the second metal wiring 131 , and the second capping film 133 . Thus, an air gap 235 may be formed between two second metal wirings 131 within the second wiring layer 230 .

[0084] In the following, reference will be made to Fig. 9 and Fig.10 A method for manufacturing a semiconductor device according to an example embodiment is described. Figures 1 to 7 The differences between the method for manufacturing a semiconductor device shown in .

[0085] Fig. 9 and Fig.10 are views showing intermediate manufacturing stages, which are used to explain a method for manufacturing a semiconductor device according to an example embodiment;

[0086] refer to Fig. 9 , in execution Figure 5 After the process shown in , a second etch stopper film 335 and a third interlayer insulating film 334 may be sequentially stacked on the first via layer 120 .

[0087] The third interlayer insulating film 334 may be formed by CVD using a first gas including deuterium (D) and a second gas including hydrogen (H).

[0088] Next, a third trench T3 may be formed in the third interlayer insulating film 334 by etching the third interlayer insulating film 334 and the second etch stopper film 335 using a mask pattern to expose the upper surface of the first via hole 121. As a result, a third interlayer insulating film 334 including the third trench T3 may be formed on the first via layer 120.

[0089] refer to Fig.10 , a second barrier film 332 may be formed in the third trench T3 along the sidewall and bottom surface of the third trench T3 .

[0090] Next, as the second metal wiring 331 is formed on the second barrier film 332 and then the second capping film 333 is formed on the second metal wiring 331 to fill the third trench T3 , the second wiring layer 330 may be formed.

[0091] In this case, for example, the upper surface of the second cover film 333 may be formed on the same plane as the upper surface of the third interlayer insulating film 334 .

[0092] In the following, reference will be made to Fig.11 and Fig.12 A method for manufacturing a semiconductor device according to an example embodiment is described. Figures 1 to 7The differences between the method for manufacturing a semiconductor device shown in .

[0093] Fig.11 and Fig.12 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments;

[0094] refer to Fig.11 , in execution Figure 3 After the process shown in , the first etch stopper film 425 and the third interlayer insulating film 434 may be sequentially stacked on the first wiring layer 110 .

[0095] The third interlayer insulating film 434 may be formed by CVD using a first gas including hydrogen (D) and a second gas including hydrogen (H).

[0096] Next, a fourth trench T4 and a fifth trench T5 on the fourth trench T4 may be formed in the third interlayer insulating film 434 by etching the third interlayer insulating film 434 and the first etch stopper film 425 using a mask pattern to expose the upper surface of the first capping film 113 .

[0097] The fourth trench T4 may be formed in the lower portion 434a of the third interlayer insulating film, and the fifth trench T5 may be formed in the upper portion 434b of the third interlayer insulating film. The width of the fifth trench T5 may be formed to be greater than that of the fourth trench T4.

[0098] According to example embodiments, the fourth trench T4 may be formed first, and then the fifth trench T5 may be formed. In another example embodiment, the fifth trench T5 may be formed first, and then the fourth trench T4 may be formed.

[0099] refer to Fig.12 , a second barrier film 432 may be formed in the fourth trench T4 and the fifth trench T5 along the sidewall and the bottom surface of each of the fourth trench T4 and the fifth trench T5 .

[0100] Next, a first via hole 421 may be formed on the second barrier film 432 to fill the fourth trench T4 , and a second metal wiring 431 may be formed on the second barrier film 432 and the first via hole 421 to fill the fifth trench T5 .

[0101] The first via 421 and the second metal wiring 431 may be formed by the same process. The first via 421 and the second metal wiring 431 may include the same material.

[0102] Next, as the second capping film 433 is formed on the second metal wiring 431 , the second wiring layer 430 may be formed.

[0103] In the following, reference will be made to Figures 13 to 16 A method for manufacturing a semiconductor device according to an example embodiment is described. Figures 1 to 7 The differences between the method for manufacturing a semiconductor device shown in .

[0104] Fig.13 and Fig.16 are views showing intermediate manufacturing stages, which are used to explain a method for manufacturing a semiconductor device according to an example embodiment;

[0105] refer to Fig.13 , in manufacturing Figure 1 After the semiconductor device shown in , a third etch stopper film 545 and a fourth interlayer insulating film 544 may be sequentially stacked on the second wiring layer 130 .

[0106] The third etch stop film 545 may include, for example, one or more of the following: silicon nitride, silicon oxynitride, silicon carbonitride, etc. The fourth interlayer insulating film 544 may include the same material as the first interlayer insulating film 114 and the second interlayer insulating film 124, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0107] Each of the third etching stopper film 545 and the fourth interlayer insulating film 544 can be formed, for example, by CVD or the like.

[0108] Next, a sixth trench T6 may be formed in the fourth interlayer insulating film 544 by etching the fourth interlayer insulating film 544, the third etch stopper film 545, and a portion of the third interlayer insulating film 134 using a mask pattern to expose the upper surface of the second capping film 133. As a result, the fourth interlayer insulating film 544 including the sixth trench T6 may be formed on the second wiring layer 130.

[0109] refer to Fig.14 , a second via barrier film 542 may be formed in the sixth trench T6 along the sidewall and the bottom surface of the sixth trench T6.

[0110] Next, as the second via hole 541 is formed on the second via barrier film 542 to fill the sixth trench T6 , a second via layer 540 may be formed.

[0111] The second via 541 may be electrically connected to the second metal wiring 131. For example, the second via 541 may include one or more of carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr).

[0112] refer to Fig.15 , a fourth etch stopper film 555 and a fifth interlayer insulating film 554 may be sequentially stacked on the second via layer 540 .

[0113] The fourth etch stop film 555 may include, for example, one or more of the following: silicon nitride, silicon oxynitride, silicon carbon nitride, etc. The fifth interlayer insulating film 554 may include the same material as the first interlayer insulating film 114, the second interlayer insulating film 124, and the fourth interlayer insulating film 544, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0114] Each of the fourth etching stopper film 555 and the fifth interlayer insulating film 554 can be formed, for example, by CVD or the like.

[0115] Next, a seventh trench T7 may be formed in the first interlayer insulating film 554 by etching the fifth interlayer insulating film 554 and the fourth etch stopper film 555 using a mask pattern to expose the upper surface of the second via hole 541. As a result, a fifth interlayer insulating film 554 including the seventh trench T7 may be formed on the second via layer 540.

[0116] refer to Fig.16 , a third barrier film 552 may be formed in the seventh trench T7 along the sidewall and the bottom surface of the seventh trench T7.

[0117] Next, as the third metal wiring 551 is formed on the third barrier film 552 and then the third capping film 553 is formed on the third metal wiring 551 to fill the seventh trench T7 , the third wiring layer 550 may be formed.

[0118] The third metal wiring 551 may be electrically connected to the second via 541. The third metal wiring 551 may include, for example, one or more of carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr).

[0119] In example embodiments, for example, an upper surface of the third capping film 553 may be formed on the same plane as an upper surface of the fifth interlayer insulating film 554 .

[0120] In the following, reference will be made to Fig.17 and Fig.18 A method for manufacturing a semiconductor device according to an example embodiment is described. Figures 1 to 7 The differences between the method for manufacturing a semiconductor device shown in .

[0121] Fig.17 and Fig.18 are views showing intermediate manufacturing stages for explaining a method for manufacturing a semiconductor device according to example embodiments;

[0122] refer to Fig.17 , in manufacturing Figure 1 After the semiconductor device shown in , a third etch stopper film 655 and a sixth interlayer insulating film 654 may be sequentially stacked on the second wiring layer 130 .

[0123] Next, an eighth trench T8 and a ninth trench T9 on the eighth trench T8 may be formed in the sixth interlayer insulating film 654 by etching the sixth interlayer insulating film 654 and the third etch stopper film 655 using a mask pattern to expose the upper surface of the second capping film 133 .

[0124] The eighth trench T8 may be formed in the third interlayer insulating film 134 and the sixth interlayer insulating film 654, and the ninth trench T9 may be formed in the sixth interlayer insulating film 654. The width of the ninth trench T9 may be formed to be greater than that of the eighth trench T8.

[0125] According to example embodiments, the eighth trench T8 may be formed first, and then the ninth trench T9 may be formed. In another example embodiment, the ninth trench T9 may be formed first, and then the eighth trench T8 may be formed.

[0126] refer to Fig.18 , a fourth barrier film 652 may be formed in the eighth trench T8 and the ninth trench T9 along the sidewall and the bottom surface of each of the eighth trench T8 and the ninth trench T9.

[0127] Next, a third via hole 641 may be formed on the fourth barrier film 652 to fill the eighth trench T8 , and a fourth metal wiring 651 may be formed on the fourth barrier film 652 and the third via hole 641 to fill the ninth trench T9 .

[0128] Each of the third via 641 and the fourth metal wiring 651 may be electrically connected to the second metal wiring 131 .

[0129] The third via 641 and the fourth metal wiring 651 may be formed by the same process. The third via 641 and the fourth metal wiring 651 may include the same material.

[0130] Next, as a fourth capping film 653 is formed on the fourth metal wiring 651, a fourth wiring layer 650 can be formed.

[0131] In the present example embodiment, an upper surface of the fourth cover film 653 may be formed on the same plane as an upper surface of the sixth interlayer insulating film 654 .

[0132] By way of summary and review, leakage etc. may occur due to the reduction in space between circuit constituent elements (e.g., wiring). In order to enhance element operation characteristics in semiconductor integrated circuits, attention is paid to hydrogen passivation of dielectric films (e.g., gate insulating films or interlayer insulating films), leakage, and film material characteristics regarding dielectric films.

[0133] As described above, embodiments can provide a method for manufacturing a semiconductor device that enhances the characteristics of a film material in a dielectric film. According to example embodiments, a dielectric film surrounding a metal wiring can be formed by chemical vapor deposition (CVD) using hydrogen (H) and deuterium (D), which can enhance reliability.

[0134] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a general descriptive sense only, and not for purposes of limitation. In some cases, as will be appreciated by those of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a first wiring layer on a substrate, the first wiring layer including a first metal wiring and a first interlayer insulating film surrounding the first metal wiring; forming a first via layer on the first wiring layer, the first via layer including a first via electrically connected to the first metal wiring and a second interlayer insulating film surrounding the first via; and forming a second wiring layer on the first via layer, the second wiring layer including a second metal wiring electrically connected to the first via and a third interlayer insulating film surrounding the second metal wiring, wherein the third interlayer insulating film contains deuterium and is formed by chemical vapor deposition using a first gas and a second gas containing hydrogen, the first gas comprising one or more of the following: SiD4, D2, D2O, HD3, Si2D6, or (C2H5)3SiD, and Forming the second wiring layer includes: forming the second metal wiring on the first via layer, the forming of the second metal wiring comprising forming a second metal wiring material on the second interlayer insulating film and then patterning the second metal wiring material; and After patterning the second metal wiring material, the third interlayer insulating film is formed to surround the second metal wiring.

2. The method according to claim 1, further comprising: After forming the second wiring layer, forming a second via layer on the second wiring layer, the second via layer including a second via electrically connected to the second metal wiring and a fourth interlayer insulating film surrounding the second via; as well as A third wiring layer is formed on the second via layer, the third wiring layer including a third metal wiring electrically connected to the second via and a fifth interlayer insulating film surrounding the third metal wiring.

3. The method according to claim 2, wherein: Forming the third wiring layer includes: forming the fifth interlayer insulating film on the second via layer; forming a second trench by etching the fifth interlayer insulating film; and The third metal wiring is formed to fill the second trench.

4. The method according to claim 1, further comprising: After forming the second wiring layer, forming a sixth interlayer insulating film on the second wiring layer; forming a third trench by etching the sixth interlayer insulating film and forming a fourth trench on the third trench; as well as A third via is formed filling the third trench and electrically connected to the second metal wiring, and a fourth metal wiring is formed filling the fourth trench and electrically connected to the third via.

5. The method according to claim 1, further comprising: An air gap is formed in the third interlayer insulating film.

6. The method according to claim 1, wherein: The third interlayer insulating film is formed by plasma enhanced chemical vapor deposition at a temperature lower than 450°C.

7. The method according to claim 1, wherein: A deuterium source is not used when forming the second interlayer insulating film so that the second interlayer insulating film does not contain added deuterium, and The third interlayer insulating film is in direct contact with the second interlayer insulating film.

8. A method for manufacturing a semiconductor device, the method comprising: forming a first interlayer insulating film including a first trench on a substrate; forming a first metal wiring filling the first trench; forming a first etching stopper film covering the first interlayer insulating film and the first metal wiring; forming a second interlayer insulating film on the first etch stop film, the second interlayer insulating film including a second trench penetrating the first etch stop film; forming a first through hole filling the second trench; forming a second metal wiring material on the second interlayer insulating film and the first through hole, and then patterning the second metal wiring material to form a second metal wiring on the first through hole; as well as After patterning the second metal wiring material, forming a third interlayer insulating film on the second interlayer insulating film to cover the side surface and the upper surface of the second metal wiring, wherein the third interlayer insulating film includes deuterium and is formed by chemical vapor deposition using a first gas and a second gas different from the first gas, The first gas includes one or more of the following: SiD4, D2, D2O, HD3, Si2D6 or (C2H5)3SiD, and The second gas includes hydrogen.

9. The method according to claim 8, further comprising: After forming the third interlayer insulating film, forming a second etching stopper film covering the third interlayer insulating film; forming a fourth interlayer insulating film on the second etch stopper film, the fourth interlayer insulating film including a third trench penetrating a portion of the third interlayer insulating film and the second etch stopper film; forming a second through hole filling the third trench; forming a fifth interlayer insulating film including a fourth trench on the fourth interlayer insulating film; and A third metal wiring is formed filling the fourth trench.

10. The method according to claim 8, wherein: The first to third interlayer insulating films include silicon oxide, The first etch stop film includes silicon nitride, and A deuterium source is not used when forming the first interlayer insulating film and the second interlayer insulating film, so that the first interlayer insulating film and the second interlayer insulating film do not contain added deuterium.

11. The method according to claim 8, wherein: Forming the third interlayer insulating film further includes: A carrier gas containing one or more of the following is used: Ar, O2, N2, H2, D2, D2O, ND3, NDHe, O3, NH3, Kr or Xe.

12. The method according to claim 8, further comprising: An air gap is formed in the third interlayer insulating film.

13. A semiconductor device comprising: substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and comprising copper; a first insulating layer disposed on the first interlayer insulating layer, comprising at least one of silicon nitride, silicon oxynitride and silicon carbonitride; a second interlayer insulating layer disposed on the first insulating layer; a contact structure, passing through the second interlayer insulating layer and the first insulating layer and contacting the lower wiring, the contact structure comprising tungsten; a third interlayer insulating layer, disposed on the second interlayer insulating layer and contacting the second interlayer insulating layer; a first upper wiring disposed in the third interlayer insulating layer and contacting the contact structure, the first upper wiring comprising aluminum; as well as a second insulating layer disposed on and contacting the third interlayer insulating layer, wherein the second insulating layer comprises at least one of silicon nitride, silicon oxynitride and silicon carbonitride, wherein the third interlayer insulating layer includes deuterium, and A top surface of the first upper wiring is disposed lower than a top surface of the third interlayer insulating layer.

14. The semiconductor device according to claim 13, further comprising a second upper wiring disposed adjacent to the first upper wiring and disposed in the third interlayer insulating layer, The third interlayer insulating layer includes an air gap disposed between the first upper wiring and the second upper wiring. 15 . The semiconductor device according to claim 13 , wherein the top surface and side surfaces of the first upper wiring are in contact with the third interlayer insulating layer. 16 . The semiconductor device according to claim 13 , wherein a bottom surface of the first upper wiring is substantially coplanar with a top surface of the second interlayer insulating layer. 17 . The semiconductor device according to claim 13 , wherein a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer.

18. The semiconductor device according to claim 13, wherein the first upper wiring includes a first wiring pattern, a second wiring pattern, and a third wiring pattern, the second wiring pattern is disposed on the first wiring pattern, the third wiring pattern is disposed on the second wiring pattern, A bottom surface of the first wiring pattern of the first upper wiring contacts a top surface of the contact structure and a top surface of the second interlayer insulating layer, and A top surface of the third wiring pattern of the first upper wiring contacts the third interlayer insulating layer. 19 . The semiconductor device according to claim 18 , wherein a side surface of each of the first wiring pattern, the second wiring pattern, and the third wiring pattern of the first upper wiring contacts the third interlayer insulating layer. 20 . The semiconductor device according to claim 13 , wherein a bottom surface of the first insulating layer contacts a top surface of the lower wiring. 21 . The semiconductor device of claim 13 , wherein a top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer.

22. The semiconductor device according to claim 13, further comprising a third upper wiring that passes through a portion of the third interlayer insulating layer and the second insulating layer and contacts a top surface of the first upper wiring, in, The third upper wiring extends over a top surface of the third interlayer insulating layer.

23. A semiconductor device comprising: substrate; a first interlayer insulating layer disposed on the substrate; A lower wiring disposed in the first interlayer insulating layer; a first insulating layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the first insulating layer; a contact structure, passing through the second interlayer insulating layer and the first insulating layer, and contacting the lower wiring; a third interlayer insulating layer, disposed on the second interlayer insulating layer and contacting the second interlayer insulating layer; a first upper wiring disposed in the third interlayer insulating layer and contacting the contact structure; as well as a second insulating layer disposed on and contacting the third interlayer insulating layer, wherein the lower wiring is electrically connected to the substrate, A top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer and contacts a bottom surface of the first insulating layer, A top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer, The third interlayer insulating layer includes deuterium, A bottom surface of the first upper wiring contacts a top surface of the contact structure and a top surface of the second interlayer insulating layer; as well as A top surface and a side surface of the first upper wiring are in contact with the third interlayer insulating layer. 24 . The semiconductor device according to claim 23 , wherein a top surface of the first upper wiring is disposed lower than a top surface of the third interlayer insulating layer.

25. The semiconductor device according to claim 23, further comprising a second upper wiring disposed adjacent to the first upper wiring and disposed in the third interlayer insulating layer, in, The third interlayer insulating layer includes an air gap disposed between the first upper wiring and the second upper wiring.

26. The semiconductor device according to claim 23, further comprising a third upper wiring that passes through a portion of the third interlayer insulating layer and the second insulating layer and contacts a top surface of the first upper wiring, in, The third upper wiring extends over a top surface of the third interlayer insulating layer. 27 . The semiconductor device according to claim 23 , wherein each of the first insulating layer and the second insulating layer includes at least one of silicon nitride, silicon oxynitride, and silicon carbonitride. 28 . The semiconductor device according to claim 23 , wherein the lower wiring comprises copper, the first upper wiring comprises aluminum, and the contact structure comprises tungsten.

29. A semiconductor device comprising: substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and electrically connected to the substrate; a first insulating layer disposed on the first interlayer insulating layer and comprising at least one of silicon nitride, silicon oxynitride and silicon carbonitride; A second interlayer insulating layer, disposed on the first insulating layer; a contact structure, passing through the second interlayer insulating layer and the first insulating layer, and contacting the lower wiring; A second insulating layer, disposed on the second interlayer insulating layer; a third interlayer insulating layer, disposed on the second insulating layer; as well as an upper wiring disposed in the second insulating layer and the third interlayer insulating layer and contacting the contact structure, wherein a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer and contacts a bottom surface of the first insulating layer, A top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer, The third interlayer insulating layer includes deuterium, The contact structure contacts the first insulating layer and is spaced apart from the second insulating layer, The top surface of the upper wiring is substantially coplanar with the top surface of the third interlayer insulating layer, A side surface of the upper wiring contacts the third interlayer insulating layer and the second insulating layer, and A width of a top surface of the upper wiring is greater than a width of a bottom surface of the upper wiring. 30 . The semiconductor device according to claim 29 , wherein the lower wiring comprises copper, the upper wiring comprises aluminum, and the contact structure comprises tungsten.

31. A semiconductor device comprising: substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and electrically connected to the substrate; an insulating layer disposed on the first interlayer insulating layer and comprising at least one of silicon nitride, silicon oxynitride and silicon carbonitride; a second interlayer insulating layer, disposed on the insulating layer; as well as an upper wiring disposed in the insulating layer and the second interlayer insulating layer and contacting the lower wiring, the upper wiring including a first portion and a second portion disposed on the first portion, wherein the top surface of the lower wiring is substantially coplanar with the top surface of the first interlayer insulating layer and contacts the bottom surface of the insulating layer, The second interlayer insulating layer includes deuterium, A side surface of the first portion of the upper wiring contacts the insulating layer and the second interlayer insulating layer, A top surface of the second portion of the upper wiring is substantially coplanar with a top surface of the second interlayer insulating layer, a bottom surface of the second portion of the upper wiring contacts a top surface of the first portion of the upper wiring and the second interlayer insulating layer, A width of a bottom surface of the second portion of the upper wiring is greater than a width of a top surface of the first portion of the upper wiring. 32 . The semiconductor device according to claim 31 , wherein the lower wiring comprises copper, and the second portion of the upper wiring comprises aluminum.

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