Light receiving element and ranging module

Abstract

The present invention provides a light-receiving element and a distance-measuring module capable of improving performance. The light-receiving element comprises an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes: a first voltage application portion to which a first voltage is applied; a second voltage application portion to which a second voltage different from the first voltage is applied; a first charge detection portion disposed around the first voltage application portion; a second charge detection portion disposed around the second voltage application portion; and a through-electrode extending through the semiconductor layer. The through-electrode applies a third voltage to a predetermined film formed on the surface of the semiconductor layer on the on-chip lens side. The present invention can be applied, for example, to light-receiving elements that generate distance information using a ToF method.

Description

Technical Field

[0001] The present invention relates to a light receiving element and a distance measuring module, and in particular to a light receiving element and a distance measuring module capable of improving characteristics. Background Art

[0002] Distance measurement systems using indirect ToF (Time of Flight) are already known. These systems require sensors that can quickly distribute signal charges generated by receiving light reflected from an object using active light emitted by an LED (Light Emitting Diode) or laser at a specific phase, to different areas.

[0003] Therefore, a technique has been proposed that generates a current in a sensor substrate by directly applying a voltage to the substrate, thereby modulating a wide area within the substrate at high speed (see, for example, Patent Document 1). This type of sensor is also called a CAPD (Current Assisted Photonic Demodulator) sensor.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-86904

[0005] However, it is difficult to obtain a CAPD sensor with sufficient characteristics using the above-mentioned techniques.

[0006] For example, the above-mentioned CAPD sensor is a surface illumination type sensor in which wiring and the like are arranged on the surface of the substrate on the side that receives light from the outside.

[0007] To ensure sufficient photoelectric conversion area, it's preferable to have no components, such as wiring, that would obstruct the optical path of incident light on the light-receiving side of the PD (photodiode), or photoelectric conversion unit. However, in surface-illuminated CAPD sensors, depending on their structure, charge extraction wiring, various control lines, and signal lines may have to be placed on the light-receiving side of the PD, limiting the photoelectric conversion area. This can result in insufficient photoelectric conversion area, and pixel sensitivity and other characteristics may be compromised.

[0008] Furthermore, when using CAPD sensors in locations exposed to external light, the external light component becomes a noise component for indirect ToF methods that use active light for distance measurement. Therefore, in order to obtain distance information with a sufficient signal-to-noise ratio (SN ratio), it is necessary to ensure a sufficient saturation signal (Qs). However, in surface-illuminated CAPD sensors, due to limitations in wiring layout, methods other than wiring capacitance, such as the provision of additional transistors, are necessary to ensure capacitance.

[0009] Furthermore, in surface-illuminated CAPD sensors, a signal extraction unit called a Tap is arranged on the side of the substrate where light is incident. On the other hand, when considering the photoelectric conversion within the Si substrate, although there are differences in the attenuation rate depending on the wavelength of the light, the proportion of photoelectric conversion caused on the light incident surface side is high. Therefore, in surface-type CAPD sensors, the probability of photoelectric conversion may become higher in the Inactive Tap area, which is the Tap area where no signal charge is distributed, among the Tap areas where the signal extraction unit is provided. In indirect ToF sensors, since distance measurement information is obtained using the signal distributed to each charge storage area according to the phase of the active light, the component that is directly photoelectrically converted in the Inactive Tap area becomes noise, resulting in the possibility of deterioration of distance measurement accuracy. In other words, the characteristics of the CAPD sensor may be degraded. Summary of the Invention

[0010] The present invention has been made in view of such circumstances, and an object of the present invention is to improve the characteristics.

[0011] A light-receiving element according to a first embodiment of the present invention includes: an on-chip lens; a wiring layer; and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer including: a first voltage applying portion to which a first voltage is applied; a second voltage applying portion to which a second voltage different from the first voltage is applied; a first charge detection portion arranged around the first voltage applying portion; a second charge detection portion arranged around the second voltage applying portion; and a through-electrode passing through the semiconductor layer, through which a third voltage is applied to a prescribed film formed on the surface of the semiconductor layer on the on-chip lens side.

[0012] In a first embodiment of the present invention, an on-chip lens is provided; a wiring layer; and a semiconductor layer arranged between the on-chip lens and the wiring layer, wherein the semiconductor layer is provided with: a first voltage applying portion to which a first voltage is applied; a second voltage applying portion to which a second voltage different from the first voltage is applied; a first charge detection portion arranged around the first voltage applying portion; a second charge detection portion arranged around the second voltage applying portion; and a through electrode passing through the semiconductor layer, through which a third voltage is applied to a prescribed film formed on the surface of the semiconductor layer on the on-chip lens side.

[0013] A second embodiment of the present invention provides a ranging module, comprising: a light-receiving element; a light source for emitting illumination light whose brightness varies periodically; and a light-emission control unit for controlling the timing of emitting the illumination light, wherein the light-receiving element comprises: an on-chip lens; a wiring layer; and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer comprising: a first voltage-applying unit to which a first voltage is applied; a second voltage-applying unit to which a second voltage different from the first voltage is applied; a first charge detection unit arranged around the first voltage-applying unit; a second charge detection unit arranged around the second voltage-applying unit; and a through-electrode extending through the semiconductor layer, through which a third voltage is applied to a predetermined film formed on the surface of the semiconductor layer on the on-chip lens side.

[0014] In a second embodiment of the present invention, a light-receiving element is provided; a light source for irradiating irradiation light whose brightness varies periodically; and a light-emitting control unit for controlling the irradiation timing of the irradiation light, wherein the light-receiving element is provided with an on-chip lens; a wiring layer; and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer being provided with: a first voltage applying unit to which a first voltage is applied; a second voltage applying unit to which a second voltage different from the first voltage is applied; a first charge detection unit arranged around the first voltage applying unit; a second charge detection unit arranged around the second voltage applying unit; and a through electrode passing through the semiconductor layer, through which a third voltage is applied to a prescribed film formed on the surface of the on-chip lens side of the semiconductor layer.

[0015] According to the first and second aspects of the present invention, characteristics can be improved.

[0016] In addition, the present invention is not limited to the above-mentioned effects, and any effects described in this disclosure may be possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram showing a configuration example of a light-receiving element.

[0018] Figure 2 A diagram showing an example of a pixel structure.

[0019] Figure 3 This is a diagram showing a partial structural example of a signal extraction portion of a pixel.

[0020] Figure 4 This is a diagram explaining the improvement in sensitivity.

[0021] Figure 5 This is a diagram explaining the improvement in charge separation efficiency.

[0022] Figure 6 This is a diagram explaining the improvement in electron extraction efficiency.

[0023] Figure 7 This is a diagram explaining the moving speed of a signal carrier in the surface irradiation type.

[0024] Figure 8 This is a diagram explaining the moving speed of a signal carrier in a back-illuminated type.

[0025] Figure 9 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0026] Figure 10 This diagram explains the relationship between pixels and on-chip lenses.

[0027] Figure 11 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0028] Figure 12 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0029] Figure 13 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0030] Figure 14 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0031] Figure 15 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0032] Figure 16 A diagram showing another structural example of a pixel.

[0033] Figure 17 A diagram showing another structural example of a pixel.

[0034] Figure 18 A diagram showing another structural example of a pixel.

[0035] Figure 19 A diagram showing another structural example of a pixel.

[0036] Figure 20 A diagram showing another structural example of a pixel.

[0037] Figure 21 A diagram showing another structural example of a pixel.

[0038] Figure 22 A diagram showing another structural example of a pixel.

[0039] Figure 23 A diagram showing another structural example of a pixel.

[0040] Figure 24 A diagram showing another structural example of a pixel.

[0041] Figure 25 A diagram showing another structural example of a pixel.

[0042] Figure 26 A diagram showing another structural example of a pixel.

[0043] Figure 27 A diagram showing another structural example of a pixel.

[0044] Figure 28 A diagram showing another structural example of a pixel.

[0045] Figure 29 A diagram showing another structural example of a pixel.

[0046] Figure 30 A diagram showing another structural example of a pixel.

[0047] Figure 31 is a diagram showing an equivalent circuit of a pixel.

[0048] Figure 32 is a diagram showing another equivalent circuit of a pixel.

[0049] Figure 33 This figure shows an example of the arrangement of voltage supply lines using a Periodic arrangement.

[0050] Figure 34 This figure shows an example of the arrangement of voltage supply lines using a mirror arrangement.

[0051] Figure 35 This figure explains the characteristics of the Periodic configuration and the Mirror configuration.

[0052] Figure 36 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0053] Figure 37 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0054] Figure 38 It is a cross-sectional view of a plurality of pixels in the ninth embodiment.

[0055] Figure 39 It is a cross-sectional view of a plurality of pixels in Modification 1 of the ninth embodiment.

[0056] Figure 40 It is a cross-sectional view of a plurality of pixels in the fifteenth embodiment.

[0057] Figure 41It is a cross-sectional view of a plurality of pixels in the tenth embodiment.

[0058] Figure 42 This is a diagram illustrating five metal films of a multilayer wiring layer.

[0059] Figure 43 This is a diagram illustrating five metal films of a multilayer wiring layer.

[0060] Figure 44 This is a diagram illustrating a polysilicon layer.

[0061] Figure 45 It is a diagram showing a modified example of a reflective member formed on a metal film.

[0062] Figure 46 It is a diagram showing a modified example of a reflective member formed on a metal film.

[0063] Figure 47 This is a diagram illustrating the substrate structure of a light-receiving element.

[0064] Figure 48 It is a cross-sectional view of a plurality of pixels in the eighteenth embodiment.

[0065] Figure 49 yes Figure 48 A top view of multiple pixels.

[0066] Figure 50 It is a plan view showing an example of the arrangement of penetrating electrodes and insulating films in a four-tap pixel structure.

[0067] Figure 51 It is a top view of a pixel having a 2-tap pixel structure according to a modification of the eighteenth embodiment.

[0068] Figure 52 It is a top view of a pixel having a 4-tap pixel structure according to a modification of the eighteenth embodiment.

[0069] Figure 53 A diagram illustrating driving with a negative bias applied.

[0070] Figure 54 Graphs showing driving in which a negative bias is applied at different timings.

[0071] Figure 55 Graphs showing driving in which a negative bias is applied at different timings.

[0072] Figure 56 It is a cross-sectional view of a plurality of pixels in the nineteenth embodiment.

[0073] Figure 57 It is a cross-sectional view of a plurality of pixels in the twentieth embodiment.

[0074] Figure 58 It is a plan view showing the positional relationship between the pixel array unit and the peripheral circuit unit.

[0075] Figure 59 It is a cross-sectional view of a plurality of pixels in the twenty-first embodiment.

[0076] Figure 60 It is a cross-sectional view of a plurality of pixels in the twenty-second embodiment.

[0077] Figure 61 It is a cross-sectional view of a plurality of pixels in the twenty-third embodiment.

[0078] Figure 62 It is a cross-sectional view of a plurality of pixels in the twenty-fourth embodiment.

[0079] Figure 63 It is a cross-sectional view of a plurality of pixels in the twenty-fifth embodiment.

[0080] Figure 64 This is a block diagram showing a configuration example of a distance measurement module.

[0081] Figure 65 This is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0082] Figure 66 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0083] Description of reference numerals:

[0084] 1: Light-receiving element; 20: Pixel array unit; 21: Tap drive unit; 22: Vertical drive unit; 51: Pixel; 61: Substrate; 62: On-chip lens; 66: Fixed charge film; 71-1, 71-2, 71: N+ semiconductor region; 73-1, 73-2, 73: P+ semiconductor region; 441-1, 441-2, 441: Separation region; 471-1, 471-2, 471: Separation region; 631: Reflection unit; 721: Transfer transistor; 722: FD; 723: Reset transistor; 724: Amplification transistor; 725: Select transistor; 727: Additional capacitor; 728: Switching transistor; 741: Voltage supply line; 811: Multilayer wiring layer; 812: Interlayer insulating film; 813: Power supply line; 814: Voltage application wiring; 815: Reflection unit; 816: Voltage application wiring Line; 817: control line; M1 to M5: metal film; 1001 (1001A, 1001B): through electrode; 1002 (1002A, 1002B): insulating film; 1003: gap; 1011: voltage application wiring; 1021: DTI; 1022: insulating film; 1041: peripheral circuit portion; 1051: DTI; 1052: insulating film; 1061: through electrode; 1 062: Insulating film; 1063: Voltage application wiring; 1071: P+ semiconductor region; 1101: Through electrode; 1102: Insulating film; 1103: Transparent conductive film; 1111: Voltage application wiring; 1161: Through electrode; 1162: Insulating film; 1163: Voltage application wiring; 5000: Distance measuring module; 5011: Light emitting unit; 5012: Light emitting control unit; 5013: Light receiving unit. DETAILED DESCRIPTION

[0085] Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.

[0086] (First embodiment)

[0087] (Structural Example of Light Receiving Element)

[0088] This technology improves characteristics such as pixel sensitivity by adopting a back-illuminated CAPD sensor structure.

[0089] The present technology can also be applied to, for example, a light-receiving element constituting a distance-measuring system that measures distance using an indirect ToF method, an imaging device having such a light-receiving element, and the like.

[0090] For example, distance measurement systems can be applied to in-vehicle systems that are installed in a vehicle and measure the distance to an object located outside the vehicle, or to gesture recognition systems that measure the distance to an object such as a user's hand and recognize the user's gesture based on the measurement results. In this case, the results of gesture recognition can be used, for example, to operate a car navigation system.

[0091] Figure 1 This is a block diagram showing a configuration example of an embodiment of a light-receiving element to which the present technology is applied.

[0092] Figure 1 The light receiving element 1 shown is a back-illuminated CAPD sensor, and is provided in, for example, an imaging device having a distance measuring function.

[0093] The light-receiving element 1 includes a pixel array section 20 formed on a semiconductor substrate (not shown) and a peripheral circuit section integrated on the same semiconductor substrate as the pixel array section 20. The peripheral circuit section includes, for example, a tap driver 21, a vertical driver 22, a column processor 23, a horizontal driver 24, and a system controller 25.

[0094] The light receiving element 1 is further provided with a signal processing unit 31 and a data storage unit 32. The signal processing unit 31 and the data storage unit 32 may be mounted on the same substrate as the light receiving element 1 or may be arranged on a different substrate from the light receiving element 1 in the imaging device.

[0095] The pixel array unit 20 is configured such that pixels 51, which generate charges corresponding to the amount of received light and output signals corresponding to the charges, are arranged two-dimensionally in a matrix in row and column directions. Specifically, the pixel array unit 20 includes a plurality of pixels 51 that perform photoelectric conversion on incident light and output signals corresponding to the resulting charges. Here, the row direction refers to the horizontal direction in which the pixels 51 are arranged, and the column direction refers to the vertical direction in which the pixels 51 are arranged. In the figure, the row direction is horizontal, and the column direction is vertical.

[0096] Pixel 51 receives externally incident light, particularly infrared light, performs photoelectric conversion, and outputs a pixel signal corresponding to the resulting charge. Pixel 51 has a first tap TA, to which a predetermined voltage MIX0 (first voltage) is applied and detects the photoelectrically converted charge; and a second tap TB, to which a predetermined voltage MIX1 (second voltage) is applied and detects the photoelectrically converted charge.

[0097] The tap driving unit 21 supplies a predetermined voltage MIX0 to the first tap TA of each pixel 51 in the pixel array unit 20 via a predetermined voltage supply line 30, and supplies a predetermined voltage MIX1 to the second tap TB via the predetermined voltage supply line 30. Thus, two voltage supply lines 30 are arranged in one pixel column of the pixel array unit 20: a voltage supply line 30 for transmitting the voltage MIX0 and a voltage supply line 30 for transmitting the voltage MIX1.

[0098] In the pixel array unit 20, for the matrix-shaped pixel arrangement, pixel drive lines 28 are wired along the row direction for each pixel row, and two vertical signal lines 29 are wired along the column direction for each pixel column. For example, the pixel drive lines 28 transmit drive signals for driving when reading signals from the pixels. Figure 1 In FIG. 1 , the pixel drive line 28 is shown as one wiring line, but the number is not limited to one. One end of the pixel drive line 28 is connected to an output end of the vertical drive unit 22 corresponding to each row.

[0099] The vertical drive unit 22 is composed of a shift register, an address decoder, and the like, and drives all pixels of the pixel array unit 20 simultaneously or drives each pixel of the pixel array unit 20 in units of rows. In other words, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, constitutes a drive unit that controls the operation of each pixel of the pixel array unit 20.

[0100] The signals output from each pixel 51 in the pixel row in response to the drive control of the vertical drive unit 22 are input to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the pixel signals output from each pixel 51 via the vertical signal line 29 and temporarily holds the pixel signals after the signal processing.

[0101] Specifically, the column processing unit 23 performs noise removal processing, AD (Analog to Digital) conversion processing, and the like as signal processing.

[0102] The horizontal drive unit 24, which is composed of a shift register, an address decoder, etc., sequentially selects unit circuits corresponding to pixel columns of the column processing unit 23. Through the selection scanning of the horizontal drive unit 24, pixel signals processed for each unit circuit in the column processing unit 23 are sequentially output.

[0103] The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the driving of the tap driving unit 21, vertical driving unit 22, column processing unit 23, and horizontal driving unit 24 based on the various timing signals generated by the timing generator.

[0104] The signal processing unit 31 has at least a calculation processing function and performs various signal processing such as calculation processing based on the pixel signal output from the column processing unit 23. The data storage unit 32 temporarily stores data required for signal processing by the signal processing unit 31.

[0105] (Structural Example of Pixel)

[0106] Next, a configuration example of a pixel provided in the pixel array section 20 will be described. Figure 2 As shown.

[0107] Figure 2 FIG. 2 shows a cross section of one pixel 51 provided in the pixel array unit 20 . The pixel 51 receives light incident from the outside, particularly infrared light, performs photoelectric conversion, and outputs a signal corresponding to the resulting charge.

[0108] The pixel 51 includes a substrate 61 composed of a P-type semiconductor layer such as a silicon substrate, and an on-chip lens 62 formed on the substrate 61 .

[0109] For example, the thickness of the substrate 61 in the longitudinal direction of the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 61, is 20 μm or less. Of course, the thickness of the substrate 61 may be greater than 20 μm, and the thickness can be set according to the target characteristics of the light receiving element 1.

[0110] The substrate 61 is, for example, a high-resistance P-Epi substrate with a substrate concentration of 1E+13 or less, and the resistance (resistivity) of the substrate 61 is, for example, 500 [Ωcm] or more.

[0111] Here, regarding the relationship between the substrate concentration of the substrate 61 and the resistance, for example, when the substrate concentration is 6.48E+12 [cm 3 ], the resistance is 2000 [Ωcm], and the substrate concentration is 1.30E+13 [cm 3 ], the resistance is 1000[Ωcm], and the substrate concentration is 2.59E+13[cm 3 ] when the resistance is 500 [Ωcm] and the substrate concentration is 1.30E+14 [cm 3 ] when the resistance is 100 [Ωcm], etc.

[0112] exist Figure 2 In the figure, the upper surface of substrate 61 is the back surface of substrate 61 and is the light incident surface of substrate 61 from outside. On the other hand, the lower surface of substrate 61 is the surface of substrate 61 and forms a multilayer wiring layer (not shown). A fixed charge film 66 composed of a single layer film or a stacked film with a positive fixed charge is formed on the light incident surface of substrate 61. On the upper surface of fixed charge film 66, an on-chip lens 62 is formed to focus light incident from outside and allow it to enter substrate 61. Fixed charge film 66 puts the light incident surface side of substrate 61 into a hole accumulation state, thereby suppressing the generation of dark current.

[0113] Furthermore, in the pixel 51, an inter-pixel light shielding film 63-1 and an inter-pixel light shielding film 63-2 are formed at the end portions of the pixel 51 on the fixed charge film 66 to prevent crosstalk between adjacent pixels. Hereinafter, unless it is necessary to specifically distinguish between the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2, they will be simply referred to as the inter-pixel light shielding film 63.

[0114] In this example, light from the outside enters the substrate 61 via the on-chip lens 62, and the inter-pixel light-shielding film 63 is formed to prevent the light from entering the region of other pixels adjacent to the pixel 51 in the substrate 61. In other words, light from the outside that enters the on-chip lens 62 and travels toward the other pixels adjacent to the pixel 51 is shielded by the inter-pixel light-shielding film 63-1 and the inter-pixel light-shielding film 63-2, thereby preventing it from entering the other adjacent pixels.

[0115] Since the light-receiving element 1 is a back-illuminated CAPD sensor, the light incident surface of the substrate 61 is the so-called back surface, and no wiring layer consisting of wiring, etc., is formed on this back surface. In addition, a wiring layer is formed by laminating the portion of the surface of the substrate 61 opposite to the light incident surface. This wiring layer includes wiring for driving transistors formed in the pixels 51 and wiring for reading signals from the pixels 51.

[0116] On the side of the substrate 61 opposite to the light incident surface, that is, on the inner side of the lower surface in the figure, an oxide film 64, a signal extraction portion 65-1, and a signal extraction portion 65-2 are formed. The signal extraction portion 65-1 corresponds to Figure 1 The first tap TA described in the above description is equivalent to the signal extraction unit 65-2. Figure 1 The second tap TB is described in .

[0117] In this example, an oxide film 64 is formed in the center of the pixel 51 near the surface of the substrate 61 opposite to the light incident surface. A signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed at both ends of the oxide film 64 .

[0118] Here, the signal extraction portion 65-1 includes an N+ semiconductor region 71-1, which is an N-type semiconductor region, and an N- semiconductor region 72-1 having a lower donor impurity concentration than the N+ semiconductor region 71-1; a P+ semiconductor region 73-1, which is a P-type semiconductor region, and a P- semiconductor region 74-1 having a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Examples of donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) and arsenic (As), which are relative to Si. Examples of acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B), which are relative to Si. Elements that serve as donor impurities are called donor elements, and elements that serve as acceptor impurities are called acceptor elements.

[0119] exist Figure 2In the embodiment, an N+ semiconductor region 71-1 is formed on the inner side of the surface of the substrate 61 opposite to the light incident surface, adjacent to the right side of the oxide film 64. Furthermore, an N− semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure so as to cover (surround) the N+ semiconductor region 71-1.

[0120] Furthermore, a P+ semiconductor region 73-1 is formed on the right side of the N+ semiconductor region 71-1. In addition, a P- semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 in the figure so as to cover (surround) the P+ semiconductor region 73-1.

[0121] Furthermore, an N+ semiconductor region 71-1 is formed on the right side of the P+ semiconductor region 73-1. In addition, an N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure so as to cover (surround) the N+ semiconductor region 71-1.

[0122] Similarly, the signal extraction portion 65-2 includes: an N+ semiconductor region 71-2 which is an N-type semiconductor region and an N- semiconductor region 72-2 having a lower donor impurity concentration than the N+ semiconductor region 71-2; and a P-type semiconductor region P+ semiconductor region 73-2 and a P- semiconductor region 74-2 having a lower acceptor impurity concentration than the P+ semiconductor region 73-2.

[0123] exist Figure 2 In the embodiment, an N+ semiconductor region 71-2 is formed on the inner side of the surface of the substrate 61 opposite to the light incident surface, adjacent to the left side of the oxide film 64. Furthermore, an N− semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the figure so as to cover (surround) the N+ semiconductor region 71-2.

[0124] Furthermore, a P+ semiconductor region 73-2 is formed on the left side of the N+ semiconductor region 71-2. Furthermore, a P- semiconductor region 74-2 is formed above the P+ semiconductor region 73-2 in the figure so as to cover (surround) the P+ semiconductor region 73-2.

[0125] Furthermore, an N+ semiconductor region 71-2 is formed on the left side of the P+ semiconductor region 73-2. Also, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the figure so as to cover (surround) the N+ semiconductor region 71-2.

[0126] On the inner portion of the surface of the substrate 61 opposite to the light incident surface, at the end portion of the pixel 51 , an oxide film 64 having the same structure as that of the center portion of the pixel 51 is formed.

[0127] Hereinafter, when there is no need to particularly distinguish between the signal extraction unit 65 - 1 and the signal extraction unit 65 - 2 , they are also simply referred to as the signal extraction unit 65 .

[0128] In the following, when there is no need to distinguish between the N+ semiconductor region 71 - 1 and the N+ semiconductor region 71 - 2 , they are simply referred to as the N+ semiconductor region 71 . When there is no need to distinguish between the N− semiconductor region 72 - 1 and the N− semiconductor region 72 - 2 , they are simply referred to as the N− semiconductor region 72 .

[0129] Furthermore, hereinafter, when there is no need to distinguish the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, they are simply referred to as the P+ semiconductor region 73, and when there is no need to distinguish the P- semiconductor region 74-1 and the P- semiconductor region 74-2, they are simply referred to as the P- semiconductor region 74.

[0130] Furthermore, in substrate 61, a separating portion 75-1 is formed by an oxide film or the like between N+ semiconductor region 71-1 and P+ semiconductor region 73-1 to separate these regions. Similarly, a separating portion 75-2 is formed by an oxide film or the like between N+ semiconductor region 71-2 and P+ semiconductor region 73-2 to separate these regions. Hereinafter, when there is no need to specifically distinguish between separating portion 75-1 and separating portion 75-2, they will be simply referred to as separating portion 75.

[0131] The N+ semiconductor region 71 provided on the substrate 61 functions as a charge detection unit for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carrier generated by photoelectric conversion based on the substrate 61. In addition to the N+ semiconductor region 71, an N- semiconductor region 72 having a low donor impurity concentration is also included, which can be understood as a charge detection unit. Furthermore, the P+ semiconductor region 73 functions as a voltage application unit for injecting a large amount of carrier current into the substrate 61, that is, directly applying a voltage to the substrate 61 to generate an electric field within the substrate 61. In addition, in addition to the P+ semiconductor region 73, a P- semiconductor region 74 having a low acceptor impurity concentration is also included, which can be understood as a voltage application unit.

[0132] In the pixel 51 , a floating diffusion region FD (Floating Diffusion) portion (hereinafter particularly also referred to as FD portion A) not shown is directly connected to the N+ semiconductor region 71 - 1 . The FD portion A is further connected to the vertical signal line 29 via an amplifier transistor not shown.

[0133] Similarly, another FD portion (hereinafter, particularly also referred to as FD portion B) different from FD portion A is directly connected to N+ semiconductor region 71-2, and FD portion B is further connected to vertical signal line 29 via an amplifier transistor (not shown). Here, FD portion A and FD portion B are connected to different vertical signal lines 29.

[0134] For example, to measure the distance to an object using an indirect ToF method, an imaging device equipped with a light-receiving element 1 emits infrared light toward the object. When this infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 61 of the light-receiving element 1 receives the incident reflected light (infrared light) and performs photoelectric conversion. The tap driver 21 drives the first tap TA and second tap TB of the pixel 51, distributing a signal corresponding to the charge DET obtained through photoelectric conversion to the FD section A and FD section B.

[0135] For example, at a certain moment, the tap driving unit 21 applies voltage to the two P+ semiconductor regions 73 via contacts, etc. Specifically, for example, the tap driving unit 21 applies a voltage of MIX0 = 1.5 V to the P+ semiconductor region 73-1 serving as the first tap TAP, and applies a voltage of MIX1 = 0 V to the P+ semiconductor region 73-2 serving as the second tap TB.

[0136] Then, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move toward the P+ semiconductor region 73-2, and electrons move toward the P+ semiconductor region 73-1.

[0137] Therefore, in this state, infrared light (reflected light) from the outside is incident on the substrate 61 through the on-chip lens 62. When the infrared light is photoelectrically converted into pairs of electrons and holes in the substrate 61, the resulting electrons are guided toward the P+ semiconductor region 73-1 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-1.

[0138] In this case, electrons generated by photoelectric conversion are used as a signal carrier for detecting a signal corresponding to the amount of infrared light incident on the pixel 51 , that is, the amount of infrared light received.

[0139] Thus, charges corresponding to the electrons moving into the N+ semiconductor region 71 - 1 are accumulated in the N+ semiconductor region 71 - 1 , and the charges are detected by the column processing unit 23 via the FD unit A, the amplifier transistor, the vertical signal line 29 , and the like.

[0140] That is, the accumulated charge DET0 in the N+ semiconductor region 71-1 is transferred to the FD portion A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge DET0 transferred to the FD portion A is read out by the column processing section 23 via the amplifier transistor and the vertical signal line 29. The column processing section 23 then performs processing such as A / D conversion on the readout signal, and the resulting pixel signal is supplied to the signal processing section 31.

[0141] This pixel signal represents the amount of charge corresponding to the electrons detected in the N+ semiconductor region 71 - 1 , that is, the amount of charge DET0 accumulated in the FD portion A. In other words, the pixel signal represents the amount of infrared light received by the pixel 51 .

[0142] In this case, similarly to the case of the N+ semiconductor region 71-1, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-2 may also be appropriately used for distance measurement.

[0143] Furthermore, at the next moment, a voltage is applied to the two P+ semiconductor regions 73 via contacts or the like by the tap driving unit 21 so as to generate an electric field in the opposite direction to the electric field generated so far in the substrate 61. Specifically, for example, a voltage of MIX0 = 0 V is applied to the P+ semiconductor region 73-1 serving as the first tap TA, and a voltage of MIX1 = 1.5 V is applied to the P+ semiconductor region 73-2 serving as the second tap TB.

[0144] As a result, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61 , and current flows from the P+ semiconductor region 73 - 2 to the P+ semiconductor region 73 - 1 .

[0145] In this state, infrared light (reflected light) from the outside is incident on the substrate 61 through the on-chip lens 62. When the infrared light is photoelectrically converted into pairs of electrons and holes in the substrate 61, the resulting electrons are guided toward the P+ semiconductor region 73-2 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-2.

[0146] Thus, charges corresponding to the electrons moving into the N+ semiconductor region 71 - 2 are accumulated in the N+ semiconductor region 71 - 2 , and the charges are detected by the column processing unit 23 via the FD unit B, the amplifier transistor, the vertical signal line 29 , and the like.

[0147] That is, the accumulated charge DET1 in the N+ semiconductor region 71-2 is transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charge DET1 transferred to the FD portion B is read out by the column processing section 23 via the amplifier transistor and the vertical signal line 29. The column processing section 23 then performs processing such as A / D conversion on the readout signal, and the resulting pixel signal is supplied to the signal processing section 31.

[0148] In this case, similarly to the case of the N+ semiconductor region 71-2, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-1 may also be appropriately used for distance measurement.

[0149] In this way, when pixel signals obtained by photoelectric conversion in different periods are obtained in the same pixel 51 , the signal processing unit 31 calculates distance information indicating the distance to the object based on these pixel signals and outputs the calculated distance information to the subsequent stage.

[0150] This method of allocating signal carriers to different N+ semiconductor regions 71 and calculating distance information based on signals corresponding to these signal carriers is called an indirect ToF method.

[0151] When Figure 2 When the signal extraction portion 65 in the pixel 51 is observed from the top to the bottom, that is, from the direction perpendicular to the substrate 61, for example, Figure 3 As shown in FIG. 1 , a structure is formed in which the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71. Figure 3 In, with Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are appropriately omitted.

[0152] exist Figure 3 In the example shown in FIG, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly closer to the end side from the center of the pixel 51. In particular, two signal extraction portions 65 are formed in the pixel 51.

[0153] Furthermore, a rectangular P+ semiconductor region 73 is formed at the center of each signal extraction portion 65. With this P+ semiconductor region 73 as the center, the P+ semiconductor region 73 is surrounded by a rectangular, more specifically, rectangular frame-shaped N+ semiconductor region 71. In other words, the N+ semiconductor region 71 is formed to surround the P+ semiconductor region 73.

[0154] Furthermore, in the pixel 51, an on-chip lens 62 is formed so as to focus infrared light incident from the outside on the center portion of the pixel 51, that is, the portion indicated by the arrow A11. In other words, the infrared light incident from the outside on the on-chip lens 62 is focused by the on-chip lens 62 on the position indicated by the arrow A11, that is, Figure 2 The oxide film 64 Figure 2 Upper middle position.

[0155] Therefore, infrared light is focused between the signal extraction section 65 - 1 and the signal extraction section 65 - 2 , thereby preventing infrared light from entering adjacent pixels 51 and causing crosstalk, and preventing infrared light from directly entering the signal extraction section 65 .

[0156] For example, if infrared light directly enters the signal extraction section 65 , the charge separation efficiency, ie, Cmod (Contrast between active and inactive tap), and the modulation contrast will decrease.

[0157] Here, the signal extraction section 65 that reads out a signal corresponding to the charge DET obtained by photoelectric conversion, that is, the signal extraction section 65 that should detect the charge DET obtained by photoelectric conversion, is also called an active tap.

[0158] On the contrary, the signal extraction section 65 that does not basically read out a signal corresponding to the charge DET obtained by photoelectric conversion, that is, the signal extraction section 65 that is not an active tap, is also called an inactive tap.

[0159] In the above example, the signal extraction section 65 that applies a voltage of 1.5 V to the P+ semiconductor region 73 is an active tap, and the signal extraction section 65 that applies a voltage of 0 V to the P+ semiconductor region 73 is a passive tap.

[0160] Cmod is calculated using the following equation (1). Cmod represents the percentage of charge generated by photoelectric conversion of incident infrared light that can be detected in the N+ semiconductor region 71 of the signal extraction section 65, which serves as the active tap. In other words, it is an indicator of whether a signal corresponding to the charge can be extracted, and represents the charge separation efficiency. In equation (1), I0 is the signal detected by one of the two charge detection sections (P+ semiconductor region 73), and I1 is the signal detected by the other.

[0161] Cmod={|I0-I1| / (I0+I1)}×100……(1)

[0162] Therefore, for example, when infrared light incident from the outside enters the passive tap region and undergoes photoelectric conversion within the passive tap, there is a high probability that the signal carriers, i.e., electrons, generated by the photoelectric conversion will move to the N+ semiconductor region 71 within the passive tap. Consequently, the charges of some of the electrons obtained by the photoelectric conversion cannot be detected in the N+ semiconductor region 71 within the active tap, and Cmod, i.e., the charge separation efficiency, decreases.

[0163] Therefore, in pixel 51, by focusing infrared light near the center of pixel 51, located approximately equidistant from the two signal extraction units 65, the probability of externally incident infrared light being photoelectrically converted in the passive tap region can be reduced, thereby improving charge separation efficiency. Furthermore, modulation contrast can also be improved in pixel 51. In other words, electrons obtained through photoelectric conversion can be easily guided to N+ semiconductor region 71 within the active tap.

[0164] According to the light receiving element 1 as described above, the following effects can be obtained.

[0165] Specifically, first, since the light receiving element 1 is a back-illuminated type, quantum efficiency (QE)×aperture ratio (FF (Fill Factor)) can be maximized, and the distance measurement characteristics of the light receiving element 1 can be improved.

[0166] For example, Figure 4 As shown by arrow W11 , a typical surface illumination type image sensor is formed such that wiring 102 and wiring 103 are formed on the light incident surface side of PD 101 , which is a photoelectric conversion unit, on which light from the outside is incident.

[0167] Therefore, for example, part of light that is incident from the outside at a certain angle to the PD 101 as indicated by arrows A21 and A22 is blocked by the wiring 102 and the wiring 103 and does not enter the PD 101 .

[0168] In contrast, a back-illuminated image sensor has wirings 105 and 106 formed on a surface of a PD 104 serving as a photoelectric conversion unit opposite to a light incident surface where light from outside is incident, as indicated by arrow W12 .

[0169] Therefore, compared to surface-illuminated systems, a sufficient aperture ratio can be ensured. Specifically, light incident from the outside at a certain angle to PD 104, as indicated by arrows A23 and A24, can enter PD 104 without being blocked by wiring. This allows for greater light reception, improving pixel sensitivity.

[0170] The effect of improving pixel sensitivity by adopting such a back-illuminated type can also be obtained in the light-receiving element 1 of the back-illuminated CAPD sensor.

[0171] Furthermore, in a surface-illuminated CAPD sensor, for example, as indicated by arrow W13, a signal extraction unit 112, called a tap, is formed on the light incident surface side of the PD 111, which serves as a photoelectric converter. More specifically, a P+ semiconductor region and an N+ semiconductor region are formed as the tap. Furthermore, the surface-illuminated CAPD sensor is configured such that wiring 113, contacts connected to the signal extraction unit 112, and wiring 114, such as metal, are formed on the light incident surface side.

[0172] Therefore, for example, not only is a portion of light incident from the outside at a certain angle relative to PD111 as shown by arrows A25 and A26 blocked by wiring 113 and the like and does not enter PD111, but light incident perpendicularly to PD111 as shown by arrow A27 is also blocked by wiring 114 and does not enter PD111.

[0173] In contrast, a back-illuminated CAPD sensor is configured such that, for example, as indicated by arrow W14, a signal extraction unit 116 is formed on the surface of the photoelectric converter PD 115 opposite to the light incident surface where light from the outside is incident. Furthermore, wiring 117, contacts connected to the signal extraction unit 116, and wiring 118 such as metal are formed on the surface of the PD 115 opposite to the light incident surface.

[0174] Here, PD115 and Figure 2 The signal taking-out portion 116 corresponds to the substrate 61 shown in FIG. Figure 2 The signal extraction unit 65 shown corresponds to this.

[0175] In a back-illuminated CAPD sensor of this structure, a sufficient aperture ratio can be ensured compared to a front-illuminated CAPD sensor, thereby maximizing quantum efficiency (QE) × aperture ratio (FF) and improving ranging characteristics.

[0176] That is, for example, light incident from the outside at a certain angle to PD 115 as indicated by arrows A28 and A29 enters PD 115 without being blocked by wiring. Similarly, light incident perpendicularly to PD 115 as indicated by arrow A30 enters PD 115 without being blocked by wiring or the like.

[0177] In this way, back-illuminated CAPD sensors can receive not only light incident at a certain angle, but also light incident perpendicularly to the PD 115, which, in front-illuminated sensors, is reflected by wiring connected to the signal extraction unit (tap). This allows for greater light reception and improves pixel sensitivity. In other words, it maximizes quantum efficiency (QE) x aperture ratio (FF), resulting in improved ranging characteristics.

[0178] In particular, when the tap is arranged near the center of the pixel instead of at the outer edge of the pixel, a sufficient aperture ratio cannot be ensured in the surface-illuminated CAPD sensor, resulting in a decrease in the sensitivity of the pixel. However, in the light-receiving element 1 of the back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured regardless of the arrangement position of the tap, thereby improving the sensitivity of the pixel.

[0179] Furthermore, in the back-illuminated light-receiving element 1, since the signal extraction portion 65 is formed near the surface of the substrate 61 opposite to the light incident surface where infrared light from the outside is incident, the occurrence of photoelectric conversion of infrared light in the passive tap region can be reduced. This can improve Cmod, or charge separation efficiency.

[0180] Figure 5 Pixel cross-sectional views showing front-illuminated and back-illuminated CAPD sensors.

[0181] exist Figure 5 In the surface-illuminated CAPD sensor on the left, in the figure, the upper side of the substrate 141 is the light incident surface, and a wiring layer 152 including multiple layers of wiring, an inter-pixel light shielding portion 153, and an on-chip lens 154 are stacked on the light incident surface side of the substrate 141.

[0182] exist Figure 5 In the back-illuminated CAPD sensor on the right side, in the figure, a wiring layer 152 including wiring of multiple layers is formed on the lower side of the substrate 142 opposite to the light incident surface, and an inter-pixel shading portion 153 and an on-chip lens 154 are stacked on the upper side of the substrate 142 serving as the light incident surface.

[0183] In addition, Figure 5 The medium gray trapezoidal shape indicates a region where infrared light is collected by the on-chip lens 154 and the light intensity is high.

[0184] For example, in a surface-illuminated CAPD sensor, a region R11 containing an inactive tap and an active tap exists on the light-incident side of substrate 141. Therefore, a large portion of light directly enters the inactive tap, and if photoelectric conversion occurs in the inactive tap, the signal carrier generated by this photoelectric conversion cannot be detected in the N+ semiconductor region of the active tap.

[0185] In surface-illuminated CAPD sensors, the intensity of infrared light is high in region R11 near the light incident surface of substrate 141, increasing the probability of photoelectric conversion of infrared light within region R11. This increases the amount of infrared light incident near the passive tap, increasing the number of signal carriers that cannot be detected by the active tap, reducing charge separation efficiency.

[0186] In contrast, in a back-illuminated CAPD sensor, a region R12 where passive taps and active taps exist is located at a position of the substrate 142 away from the light incident surface, that is, near the surface opposite to the light incident surface. Figure 2 The substrate 61 shown corresponds.

[0187] In this example, since the region R12 is provided on the surface of the substrate 142 opposite to the light incident surface and the region R12 is located away from the light incident surface, the intensity of the incident infrared light is relatively weak near the region R12 .

[0188] The signal carrier obtained by photoelectric conversion in an area with strong infrared light intensity, such as near the center of the substrate 142 or near the light incident surface, is guided to the active tap by the electric field generated in the substrate 142 and detected in the N+ semiconductor area of ​​the active tap.

[0189] On the other hand, near region R12, which includes the passive tap, the intensity of incident infrared light is relatively weak, so the probability of photoelectric conversion of infrared light within region R12 is reduced. Specifically, because the amount of infrared light incident near the passive tap is small, the number of signal carriers (electrons) generated near the passive tap through photoelectric conversion and moving toward the passive tap's N+ semiconductor region is reduced, thereby improving charge separation efficiency. Consequently, ranging characteristics can be improved.

[0190] Furthermore, in the back-illuminated light-receiving element 1 , since the substrate 61 can be made thinner, the extraction efficiency of electrons (charges) as signal carriers can be improved.

[0191] For example, in a surface irradiation type CAPD sensor, since the aperture ratio cannot be sufficiently ensured, Figure 6As shown by arrow W31 , in order to ensure higher quantum efficiency and suppress the decrease in quantum efficiency×aperture ratio, the substrate 171 needs to be thickened to a certain extent.

[0192] As a result, in the region near the surface opposite to the light incident surface within the substrate 171, such as the region R21, the potential slope becomes gentle, and the electric field in the direction perpendicular to the substrate 171 becomes weak. In this case, the movement speed of the signal carrier slows down, and therefore, the time required from photoelectric conversion to detection of the signal carrier in the N+ semiconductor region of the active tap becomes longer. In addition, Figure 6 , the arrows in the substrate 171 represent the electric field in the substrate 171 in a direction perpendicular to the substrate 171 .

[0193] Furthermore, when the substrate 171 is thick, the distance that the signal carrier travels from a position in the substrate 171 away from the active tap to the N+ semiconductor region in the active tap becomes longer. Consequently, the time required from photoelectric conversion at a position away from the active tap to detection of the signal carrier in the N+ semiconductor region of the active tap further increases.

[0194] Figure 7 The relationship between the position in the thickness direction of the substrate 171 and the moving speed of the signal carrier is shown. The region R21 corresponds to the diffusion current region.

[0195] Thus, when substrate 171 becomes thicker, for example, when the driving frequency is high, that is, when the tap (signal extraction unit) switches between active and passive states at high speed, electrons generated in locations far from the active tap, such as region R21, cannot be fully introduced into the N+ semiconductor region of the active tap. In other words, if the tap is active for a short time, electrons (charges) generated in regions such as region R21 may not be detected by the N+ semiconductor region of the active tap, resulting in reduced electron extraction efficiency.

[0196] In contrast, in a back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured, so that, for example, Figure 6 As shown by the arrow W32, even if the substrate 172 is thinned, sufficient quantum efficiency × aperture ratio can be ensured. Figure 2 The arrows in the substrate 172 correspond to the substrate 61 , and the electric field in the direction perpendicular to the substrate 172 is represented.

[0197] Figure 8 The relationship between the position in the thickness direction of the substrate 172 and the moving speed of the signal carrier is shown.

[0198] As the thickness of substrate 172 is reduced in a direction perpendicular to substrate 172, the electric field perpendicular to substrate 172 becomes stronger, effectively utilizing only the electrons (charges) in the drift current region, where the signal carrier moves quickly, and not the electrons in the diffusion current region, where the signal carrier moves slowly. By utilizing only the electrons (charges) in the drift current region, the time required from photoelectric conversion to detection of the signal carrier in the N+ semiconductor region of the active tap is shortened. Furthermore, as the thickness of substrate 172 is reduced, the distance the signal carrier travels to the N+ semiconductor region within the active tap is also shortened.

[0199] Therefore, in a back-illuminated CAPD sensor, even when the driving frequency is high, signal carriers (electrons) generated in various regions within the substrate 172 can be sufficiently introduced into the N+ semiconductor region of the active tap, thereby improving the electron extraction efficiency.

[0200] Furthermore, by reducing the thickness of the substrate 172 , sufficient electron extraction efficiency can be ensured even at a high driving frequency, thereby improving high-speed driving resistance.

[0201] In particular, in a back-illuminated CAPD sensor, a voltage can be applied directly to substrate 172, i.e., substrate 61. This allows for a faster response time between active and passive tap switching, enabling high drive frequency. Furthermore, the ability to apply a voltage directly to substrate 61 widens the modulatable region within substrate 61.

[0202] Furthermore, in the back-illuminated light-receiving element 1 (CAPD sensor), a sufficient aperture ratio can be obtained, and thus pixels can be miniaturized accordingly, and the miniaturization resistance of pixels can be improved.

[0203] Furthermore, by configuring the light receiving element 1 as a back-illuminated type, the design of BEOL (Back End Of Line) capacitance can be liberalized, thereby increasing the degree of freedom in designing the saturation signal quantity (Qs).

[0204] (Modification 1 of the first embodiment)

[0205] (Structural Example of Pixel)

[0206] In addition, the above is to take out the signal portion 65 in the substrate 61 as shown in FIG. Figure 3 As shown, the case where the N+ semiconductor region 71 and the P+ semiconductor region 73 are rectangular regions is described as an example. However, the shapes of the N+ semiconductor region 71 and the P+ semiconductor region 73 when viewed from a direction perpendicular to the substrate 61 may be any shapes.

[0207] Specifically, for example Figure 9As shown, the N+ semiconductor region 71 and the P+ semiconductor region 73 may be circular. Figure 9 in Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0208] Figure 9 The N+ semiconductor region 71 and the P+ semiconductor region 73 are shown when the portion of the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0209] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly toward the edge of the pixel 51. Specifically, two signal extraction portions 65 are formed in the pixel 51.

[0210] Furthermore, in each signal extraction portion 65 , a circular P+ semiconductor region 73 is formed at its center. The P+ semiconductor region 73 is surrounded by a circular, more specifically, annular N+ semiconductor region 71 , with the P+ semiconductor region 73 as the center.

[0211] Figure 10 Is in Figure 9 The illustrated plan view shows a portion of the pixel array section 20 in which the pixels 51 of the signal extraction section 65 are two-dimensionally arranged in a matrix, with the on-chip lens 62 overlapping.

[0212] like Figure 10 As shown, the on-chip lens 62 is formed in units of pixels. In other words, a unit area where one on-chip lens 62 is formed corresponds to one pixel.

[0213] In addition, Figure 2 In the embodiment, a separation portion 75 formed of an oxide film or the like is arranged between the N+ semiconductor region 71 and the P+ semiconductor region 73 , but the separation portion 75 is optional.

[0214] (Variation 2 of the First Embodiment)

[0215] (Structural Example of Pixel)

[0216] Figure 11 It is a plan view showing a modified example of the planar shape of the signal extraction portion 65 in the pixel 51 .

[0217] The planar shape of the signal extraction portion 65 is formed as Figure 3 The rectangle shown, Figure 9 In addition to the circular shape shown, it can also be formed into Figure 11 The octagonal shape shown.

[0218] also, Figure 11A plan view is shown in which a separation portion 75 formed of an oxide film or the like is formed between the N+ semiconductor region 71 and the P+ semiconductor region 73 .

[0219] Figure 11 The line AA' shown here indicates the Figure 37 The cross-sectional line, BB' line represents the following Figure 36 cross-section line.

[0220] (Second embodiment)

[0221] (Structural Example of Pixel)

[0222] Furthermore, the above description takes as an example the structure in which the P+ semiconductor region 73 in the signal extraction portion 65 is surrounded by the N+ semiconductor region 71 , but the N+ semiconductor region may also be surrounded by the P+ semiconductor region.

[0223] In this case, the pixel 51 is, for example, Figure 12 In addition, Figure 12 in Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0224] Figure 12 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0225] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, a signal extraction portion 65-1 is formed in a portion slightly above the center of the pixel 51, and a signal extraction portion 65-2 is formed in a portion slightly below the center of the pixel 51. In particular, in this example, the formation position of the signal extraction portion 65 in the pixel 51 is aligned with the position of the pixel 51. Figure 3 Same situation as the location.

[0226] In the signal taking-out section 65-1, Figure 3 The rectangular N+ semiconductor region 201-1 corresponding to the N+ semiconductor region 71-1 is formed in the center of the signal extraction portion 65-1. Figure 3 The P+ semiconductor region 73-1 shown is surrounded by a rectangular, more specifically, rectangular frame-shaped, P+ semiconductor region 202-1. That is, the P+ semiconductor region 202-1 is formed to surround the N+ semiconductor region 201-1.

[0227] Similarly, in the signal taking-out section 65-2, Figure 3The rectangular N+ semiconductor region 201-2 corresponding to the N+ semiconductor region 71-2 shown in FIG. 2 is formed in the center of the signal extraction portion 65-2. Figure 3 The P+ semiconductor region 73 - 2 is shown surrounded by a rectangle, more specifically, a rectangular frame-shaped P+ semiconductor region 202 - 2 .

[0228] In the following, when there is no need to distinguish between the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2, they are simply referred to as the N+ semiconductor region 201. In the following, when there is no need to distinguish between the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2, they are simply referred to as the P+ semiconductor region 202.

[0229] The signal taking-out portion 65 is formed as Figure 12 In the case of the structure shown, it is also formed as Figure 3 As in the case of the structure shown, the N+ semiconductor region 201 functions as a charge detection unit that detects the amount of signal carrier, and the P+ semiconductor region 202 functions as a voltage application unit for directly applying a voltage to the substrate 61 to generate an electric field.

[0230] (Variation 1 of the Second Embodiment)

[0231] (Structural Example of Pixel)

[0232] In addition, with Figure 9 Even in the case where the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202 , the shapes of the N+ semiconductor region 201 and the P+ semiconductor region 202 may be any shapes.

[0233] That is, for example, Figure 13 As shown in FIG. 2 , the N+ semiconductor region 201 and the P+ semiconductor region 202 are formed into a circular shape. Figure 13 in Figure 12 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0234] Figure 13 The N+ semiconductor region 201 and the P+ semiconductor region 202 are shown when the portion of the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0235] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly toward the edge of the pixel 51. Specifically, two signal extraction portions 65 are formed in the pixel 51.

[0236] Furthermore, in each signal extraction portion 65 , a circular N+ semiconductor region 201 is formed at its center. The N+ semiconductor region 201 is surrounded by a circular, more specifically, annular P+ semiconductor region 202 .

[0237] (Third embodiment)

[0238] (Structural Example of Pixel)

[0239] Furthermore, the N+ semiconductor region and the P+ semiconductor region formed in the signal extraction portion 65 may also be linear (rectangular).

[0240] In this case, for example, pixel 51 is Figure 14 In addition, Figure 14 in Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0241] Figure 14 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0242] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, a signal extraction portion 65-1 is formed in a portion slightly above the center of the pixel 51, and a signal extraction portion 65-2 is formed in a portion slightly below the center of the pixel 51. In particular, in this example, the formation position of the signal extraction portion 65 in the pixel 51 is the same as that in FIG. Figure 3 Same situation as the location.

[0243] In the signal taking-out section 65-1, Figure 3 The linear P+ semiconductor region 231 corresponding to the P+ semiconductor region 73-1 is formed at the center of the signal extraction portion 65-1. Figure 3 The N+ semiconductor region 71-1 shown corresponds to the linear N+ semiconductor region 232-1 and the N+ semiconductor region 232-2. That is, the P+ semiconductor region 231 is formed at a position sandwiched between the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2.

[0244] In the following, when there is no need to particularly distinguish between the N+ semiconductor region 232 - 1 and the N+ semiconductor region 232 - 2 , they are simply referred to as the N+ semiconductor region 232 .

[0245] exist Figure 3In the example, the P+ semiconductor region 73 is formed to be surrounded by the N+ semiconductor region 71, but in Figure 14 In the example, a P+ semiconductor region 231 is formed to be sandwiched between two adjacent N+ semiconductor regions 232 .

[0246] Similarly, in the signal taking-out section 65-2, Figure 3 The linear P+ semiconductor region 233 corresponding to the P+ semiconductor region 73-2 is formed at the center of the signal extraction portion 65-2. Figure 3 The N+ semiconductor region 71 - 2 shown corresponds to the linear N+ semiconductor region 234 - 1 and the linear N+ semiconductor region 234 - 2 .

[0247] In the following, when there is no need to particularly distinguish between the N+ semiconductor region 234 - 1 and the N+ semiconductor region 234 - 2 , they are simply referred to as the N+ semiconductor region 234 .

[0248] exist Figure 14 In the signal extraction section 65, the P+ semiconductor region 231 and the P+ semiconductor region 233 serve as Figure 3 The voltage applying portion corresponding to the P+ semiconductor region 73 shown in the figure functions as the voltage applying portion, and the N+ semiconductor region 232 and the N+ semiconductor region 234 function as the voltage applying portion corresponding to the P+ semiconductor region 73. Figure 3 The charge detection portion functions as shown in the N+ semiconductor region 71. In this case, for example, both the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2 are connected to the FD portion A.

[0249] In addition, the horizontal lengths of the linear P+ semiconductor region 231 , N+ semiconductor region 232 , P+ semiconductor region 233 and N+ semiconductor region 234 in the figure may be arbitrary lengths, and these regions may not have the same length.

[0250] (Fourth embodiment)

[0251] (Structural Example of Pixel)

[0252] Furthermore, in Figure 14 In the example, the structure in which the P+ semiconductor region 231 and the P+ semiconductor region 233 are sandwiched between the N+ semiconductor region 232 and the N+ semiconductor region 234 is described as an example, but conversely, the shape in which the N+ semiconductor region is sandwiched between the P+ semiconductor region can also be formed.

[0253] In such a case, for example, pixel 51 is Figure 15 In addition, Figure 15 in Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0254] Figure 15 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0255] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly closer to the end of the pixel 51 from the center. In particular, in this example, the formation positions of the two signal extraction portions 65 in the pixel 51 are aligned with each other. Figure 3 Same situation as the location.

[0256] In the signal taking-out section 65-1, Figure 3 The linear N+ semiconductor region 261 corresponding to the N+ semiconductor region 71-1 is formed at the center of the signal extraction portion 65-1. Figure 3 The P+ semiconductor region 73-1 shown corresponds to the linear P+ semiconductor region 262-1 and the P+ semiconductor region 262-2. That is, the N+ semiconductor region 261 is formed at a position sandwiched between the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2.

[0257] In the following, when there is no need to particularly distinguish between the P+ semiconductor region 262 - 1 and the P+ semiconductor region 262 - 2 , they are simply referred to as the P+ semiconductor region 262 .

[0258] Similarly, in the signal taking-out section 65-2, Figure 3 The linear N+ semiconductor region 263 corresponding to the N+ semiconductor region 71-2 is formed at the center of the signal extraction portion 65-2. Figure 3 The P+ semiconductor region 73 - 2 shown corresponds to the linear P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 .

[0259] In the following, when there is no need to particularly distinguish between the P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 , they are simply referred to as the P+ semiconductor region 264 .

[0260] exist Figure 15 In the signal extraction portion 65, the P+ semiconductor region 262 and the P+ semiconductor region 264 serve as Figure 3The voltage applying portion corresponding to the P+ semiconductor region 73 shown in the figure functions as the voltage applying portion, and the N+ semiconductor region 261 and the N+ semiconductor region 263 function as the voltage applying portion corresponding to the P+ semiconductor region 73. Figure 3 The charge detection portion corresponding to the N+ semiconductor region 71 shown in the figure functions. In addition, the horizontal lengths of the linear N+ semiconductor region 261, P+ semiconductor region 262, N+ semiconductor region 263, and P+ semiconductor region 264 in the figure can be any length, and these regions do not have to be the same length.

[0261] (Fifth embodiment)

[0262] (Structural Example of Pixel)

[0263] Furthermore, in the above description, an example is described in which two signal extraction sections 65 are provided in each pixel constituting the pixel array section 20 . However, the number of signal extraction sections provided in a pixel may be one or three or more.

[0264] For example, when a signal extraction portion is formed in the pixel 51, the structure of the pixel is as follows. Figure 16 In addition, Figure 16 in Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0265] Figure 16 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0266] In this example, a pixel 51 provided in the pixel array unit 20 and pixels 291 - 1 to 291 - 3 adjacent to the pixel 51 are shown with different reference numerals, and one signal extraction unit is formed in each of these pixels.

[0267] That is, in the pixel 51, a signal extraction portion 65 is formed in the central portion of the pixel 51. Furthermore, a circular P+ semiconductor region 301 is formed at the center of the signal extraction portion 65, and the P+ semiconductor region 301 is surrounded by a circular, more specifically, annular, N+ semiconductor region 302, with the P+ semiconductor region 301 as the center.

[0268] Here, the P+ semiconductor region 301 and Figure 3 The P+ semiconductor region 73 shown in FIG. 1 functions as a voltage applying portion. Figure 3The P+ semiconductor region 301 and the N+ semiconductor region 302 may have any shape.

[0269] Furthermore, pixels 291 - 1 to 291 - 3 located around the pixel 51 also have the same structure as that of the pixel 51 .

[0270] Specifically, for example, a signal extraction portion 303 is formed in the center of pixel 291-1. Furthermore, a circular P+ semiconductor region 304 is formed at the center of signal extraction portion 303. This P+ semiconductor region 304 is surrounded by a circular, more specifically, annular, N+ semiconductor region 305, centered around the P+ semiconductor region 304.

[0271] These P+ semiconductor region 304 and N+ semiconductor region 305 correspond to the P+ semiconductor region 301 and the N+ semiconductor region 302 , respectively.

[0272] In the following, when there is no need to particularly distinguish between the pixels 291 - 1 to 291 - 3 , they are simply referred to as pixels 291 .

[0273] In this way, when each pixel forms a signal extraction unit (tap), when the distance to the object is to be measured using the indirect ToF method, several adjacent pixels are used to calculate distance information based on pixel signals obtained for these pixels.

[0274] For example, when focusing on pixel 51, while the signal extraction unit 65 of pixel 51 is set as an active tap, each pixel is driven so that the signal extraction units 303 of several pixels 291 adjacent to pixel 51, including, for example, pixel 291-1, become passive taps.

[0275] As an example, the pixel 291 - 1 and the pixel 291 - 3 are driven so that the signal extraction portions of the pixels adjacent to the pixel 51 in the vertical direction and the horizontal direction in the figure become passive taps.

[0276] Thereafter, when the applied voltage is switched so that the signal extraction section 65 of the pixel 51 becomes a passive tap, the signal extraction sections 303 of several pixels 291 adjacent to the pixel 51 including the pixel 291 - 1 become active taps.

[0277] Then, distance information is calculated based on the pixel signal read out from the signal extraction section 65 when the signal extraction section 65 is in the active tap state and the pixel signal read out from the signal extraction section 303 when the signal extraction section 303 is in the active tap state.

[0278] In this manner, even when the number of signal extraction units (tap) provided in a pixel is set to one, it is possible to perform distance measurement using mutually adjacent pixels by the indirect ToF method.

[0279] (Sixth embodiment)

[0280] (Structural Example of Pixel)

[0281] Furthermore, as described above, three or more signal extraction portions (taps) may be provided in each pixel.

[0282] For example, when four signal extraction units (taps) are provided in a pixel, the pixel structure of each pixel in the pixel array unit 20 is as follows: Figure 17 In addition, Figure 17 in Figure 16 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0283] Figure 17 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0284] Figure 17 The cross-sectional view of the CC' line shown is as described later. Figure 36 shown.

[0285] In this example, the pixel 51 and the pixel 291 provided in the pixel array unit 20 are shown, and four signal extraction units are formed in each of these pixels.

[0286] That is, in pixel 51, a signal taking-out section 331-1, a signal taking-out section 331-2, a signal taking-out section 331-3, and a signal taking-out section 331-4 are formed at positions between the center of pixel 51 and the ends of pixel 51, that is, at the lower left position, the upper left position, the upper right position, and the lower right position of the center of pixel 51 in the figure.

[0287] The above-mentioned signal extraction units 331-1 to 331-4 are Figure 16 The signal extraction unit 65 shown corresponds to this.

[0288] For example, in the signal extraction portion 331 - 1 , a circular P+ semiconductor region 341 is formed at its center. The P+ semiconductor region 341 is surrounded by a circular, more specifically, annular N+ semiconductor region 342 , with the P+ semiconductor region 341 as the center.

[0289] Here, the P+ semiconductor region 341 and Figure 16The P+ semiconductor region 301 shown in FIG. 1 functions as a voltage applying portion. Figure 16 The P+ semiconductor region 341 and the N+ semiconductor region 342 may have any shape.

[0290] Furthermore, signal extraction sections 331-2 through 331-4 have the same structure as signal extraction section 331-1, each including a P+ semiconductor region functioning as a voltage application section and an N+ semiconductor region functioning as a charge detection section. Furthermore, pixel 291, formed around pixel 51, has the same structure as pixel 51.

[0291] In addition, hereinafter, when there is no need to particularly distinguish between the signal extraction unit 331 - 1 to the signal extraction unit 331 - 4 , they are also simply referred to as the signal extraction unit 331 .

[0292] In this way, when four signal extraction units are provided in each pixel, for example, when distance measurement is performed using an indirect ToF method, distance information is calculated using the four signal extraction units in the pixel.

[0293] As an example, when focusing on pixel 51, pixel 51 is driven, for example, while signal extraction section 331-1 and signal extraction section 331-3 are set as active taps, signal extraction section 331-2 and signal extraction section 331-4 are set as passive taps.

[0294] Thereafter, the voltage applied to each signal extraction section 331 is switched. That is, the pixel 51 is driven so that the signal extraction section 331-1 and the signal extraction section 331-3 become passive taps, and the signal extraction section 331-2 and the signal extraction section 331-4 become active taps.

[0295] Then, the distance information is calculated based on the pixel signals read out from the signal taking-out section 331-1 and the signal taking-out section 331-3 when the signal taking-out section 331-1 and the signal taking-out section 331-3 are set as active taps, and the pixel signals read out from the signal taking-out section 331-2 and the signal taking-out section 331-4 when the signal taking-out section 331-2 and the signal taking-out section 331-4 are set as active taps.

[0296] (Seventh embodiment)

[0297] (Structural Example of Pixel)

[0298] Furthermore, a signal extraction portion (tap) may be shared between adjacent pixels in the pixel array section 20 .

[0299] In this case, each pixel of the pixel array section 20 is, for example, Figure 18 In addition, Figure 18 in Figure 16 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0300] Figure 18 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0301] In this example, a pixel 51 and a pixel 291 provided in the pixel array unit 20 are shown, and two signal extraction units are formed in each of these pixels.

[0302] For example, in the pixel 51 , the signal extraction portion 371 is formed at the upper end portion of the pixel 51 in the figure, and the signal extraction portion 372 is formed at the lower end portion of the pixel 51 in the figure.

[0303] Signal extraction unit 371 is shared by pixel 51 and pixel 291-1. That is, signal extraction unit 371 serves as a tap for pixel 51 and also serves as a tap for pixel 291-1. Furthermore, signal extraction unit 372 is shared by pixel 51 and a pixel (not shown) adjacent to the lower side of pixel 51 in the figure.

[0304] In the signal taking-out portion 371, a Figure 14 The linear P+ semiconductor region 381 corresponding to the P+ semiconductor region 231 shown in FIG. Moreover, a linear P+ semiconductor region 381 is formed at the upper and lower positions of the P+ semiconductor region 381 in such a manner as to sandwich the P+ semiconductor region 381. Figure 14 The N+ semiconductor region 232 shown corresponds to a linear N+ semiconductor region 382 - 1 and an N+ semiconductor region 382 - 2 .

[0305] In particular, in this example, the P+ semiconductor region 381 is formed at the boundary between the pixel 51 and the pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in the region within the pixel 51, and the N+ semiconductor region 382-2 is formed in the region within the pixel 291-1.

[0306] Here, the P+ semiconductor region 381 functions as a voltage application unit, and the N+ semiconductor regions 382-1 and 382-2 function as charge detection units. Hereinafter, when there is no need to specifically distinguish between the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2, they will be simply referred to as the N+ semiconductor region 382.

[0307] The P+ semiconductor region 381 and the N+ semiconductor region 382 may have any shape. Furthermore, the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 may be connected to the same FD portion or to different FD portions.

[0308] A linear P+ semiconductor region 383 , an N+ semiconductor region 384 - 1 , and an N+ semiconductor region 384 - 2 are formed in the signal extraction portion 372 .

[0309] These P+ semiconductor region 383, N+ semiconductor region 384-1, and N+ semiconductor region 384-2 correspond to P+ semiconductor region 381, N+ semiconductor region 382-1, and N+ semiconductor region 382-2, respectively, and have the same configuration, shape, and function. Hereinafter, when there is no need to specifically distinguish between N+ semiconductor region 384-1 and N+ semiconductor region 384-2, they are simply referred to as N+ semiconductor region 384.

[0310] When the signal extraction unit (tap) is shared between adjacent pixels as described above, it is also possible to Figure 3 The same operation as in the example shown is performed by indirect ToF ranging.

[0311] In such Figure 18 When a signal extraction unit is shared among pixels as shown, the distance between the paired P+ semiconductor regions for generating an electric field, i.e., the distance between P+ semiconductor regions 381 and 383, for example, becomes longer. In other words, by sharing a signal extraction unit among pixels, the distance between the P+ semiconductor regions can be maximized.

[0312] This makes it difficult for current to flow between the P+ semiconductor regions, thereby reducing the power consumption of the pixel and contributing to miniaturization of the pixel.

[0313] In addition, while the example described here illustrates a signal extraction section shared by two adjacent pixels, a signal extraction section may also be shared by three or more adjacent pixels. Furthermore, when a signal extraction section is shared by two or more adjacent pixels, only the charge detection section for detecting a signal carrier or only the voltage application section for generating an electric field may be shared within the signal extraction section.

[0314] (Eighth Embodiment)

[0315] (Structural Example of Pixel)

[0316] Furthermore, it is not necessary to particularly provide an on-chip lens and an inter-pixel light shielding portion for each pixel such as the pixel 51 provided in the pixel array section 20 .

[0317] Specifically, for example, the pixel 51 can be formed as Figure 19 In addition, Figure 19 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0318] Figure 19 The structure of the pixel 51 shown is different from that of the pixel 51 in that the on-chip lens 62 is not provided. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0319] exist Figure 19 The pixel 51 shown does not have an on-chip lens 62 on the light incident side of the substrate 61, thereby further reducing the attenuation of infrared light incident from the outside on the substrate 61. This increases the amount of infrared light that can be received by the substrate 61, and improves the sensitivity of the pixel 51.

[0320] (Variation 1 of the Eighth Embodiment)

[0321] (Structural Example of Pixel)

[0322] In addition, the structure of the pixel 51 may be formed as follows, for example Figure 20 In addition, Figure 20 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0323] Figure 20 The structure of the pixel 51 shown is different from that of the pixel 51 in that the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2 are not provided. Figure 2 The pixel 51 shown is different from the Figure 2 The structure of pixel 51 is the same.

[0324] exist Figure 20 In the example shown, since the inter-pixel shading film 63 is not provided on the light incident surface side of the substrate 61, the crosstalk suppression effect is reduced, but since the infrared light shielded by the inter-pixel shading film 63 also enters the substrate 61, the sensitivity of the pixel 51 can be improved.

[0325] Furthermore, it is of course also possible to provide neither the on-chip lens 62 nor the inter-pixel light shielding film 63 in the pixel 51 .

[0326] (Variation 2 of the Eighth Embodiment)

[0327] (Structural Example of Pixel)

[0328] In addition, for example Figure 21As shown in FIG, the thickness of the on-chip lens in the optical axis direction can also be optimized. Figure 21 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0329] Figure 21 The structure of the pixel 51 shown is different from that of the pixel 51 in that an on-chip lens 411 is provided instead of the on-chip lens 62. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0330] exist Figure 21 In the pixel 51 shown, an on-chip lens 411 is formed on the light incident surface side of the substrate 61, that is, on the upper side in the figure. Figure 2 Compared with the on-chip lens 62 shown, the thickness in the optical axis direction, that is, the thickness in the vertical direction in the figure, is thinner.

[0331] Typically, the thickness of the on-chip lens provided on the surface of substrate 61 contributes to the collection of light incident on the on-chip lens. However, by thinning on-chip lens 411, the transmittance can be increased accordingly, thereby improving the sensitivity of pixel 51. Therefore, the thickness of on-chip lens 411 can be appropriately determined based on the thickness of substrate 61, the position where infrared light is to be collected, and other factors.

[0332] (Ninth embodiment)

[0333] (Structural Example of Pixel)

[0334] Furthermore, a separation region may be provided between pixels formed in the pixel array unit 20 to improve separation characteristics between adjacent pixels and suppress crosstalk.

[0335] In such a case, the pixel 51 is, for example, Figure 22 In addition, Figure 22 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0336] Figure 22 The structure of the pixel 51 shown is different from that of the pixel 51 in that the separation region 441-1 and the separation region 441-2 are provided in the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0337] exist Figure 22In the illustrated pixel 51, a separation region 441-1 and a separation region 441-2 are formed by a light-shielding film or the like at the boundaries between the pixel 51 and other adjacent pixels within the substrate 61, i.e., at the left and right ends of the pixel 51 in the figure. The separation regions 441-1 and 441-2 are separated from each other by a light-shielding film or the like. Hereinafter, when there is no need to specifically distinguish between the separation regions 441-1 and 441-2, they will be referred to simply as the separation regions 441.

[0338] For example, when forming the isolation region 441, a long groove (trench) is formed in the substrate 61 with a predetermined depth from the light incident surface side of the substrate 61, that is, the upper side in the figure, toward the lower side in the figure (perpendicular to the surface of the substrate 61), and a light shielding film is embedded in the groove portion to form the isolation region 441. The isolation region 441 functions as a pixel isolation region, shielding infrared light that enters the substrate 61 from the light incident surface and is directed toward other pixels adjacent to the pixel 51.

[0339] By forming the buried isolation region 441 in this manner, the infrared light separation characteristics between pixels can be improved, and the occurrence of crosstalk can be suppressed.

[0340] (Variation 1 of the Ninth Embodiment)

[0341] (Structural Example of Pixel)

[0342] Furthermore, in the case where the pixel 51 forms a buried separation region, for example, Figure 23 As shown in FIG. 4 , a separation region 471-1 and a separation region 471-2 may be provided that penetrate the entire substrate 61. Figure 23 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0343] Figure 23 The structure of the pixel 51 shown is different from that of the pixel 51 in that the separation region 471-1 and the separation region 471-2 are provided in the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure. That is, Figure 23 The pixel 51 shown is constructed as follows: Figure 22 The separation region 441 of the pixel 51 shown is replaced by a separation region 471 - 1 and a separation region 471 - 2 .

[0344] exist Figure 23In the illustrated pixel 51, a separation region 471-1 and a separation region 471-2 are formed by a light-shielding film or the like at the boundaries between the pixel 51 and other adjacent pixels within the substrate 61, i.e., at the left and right ends of the pixel 51 in the figure. These separation regions 471-1 and 471-2 penetrate the entire substrate 61. Hereinafter, when there is no need to specifically distinguish between the separation regions 471-1 and 471-2, they will be simply referred to as the separation regions 471.

[0345] For example, when forming the isolation region 471, long grooves (trench) are formed on the surface of the substrate 61 opposite to the light incident surface, that is, the lower surface in the figure, extending upward in the figure. These grooves are formed so as to penetrate the substrate 61 until they reach the light incident surface of the substrate 61. Furthermore, the isolation region 471 is formed by embedding a light shielding film in the grooves thus formed.

[0346] Such a buried isolation region 471 can also improve the infrared light separation characteristics between pixels and suppress the occurrence of crosstalk.

[0347] (Tenth embodiment)

[0348] (Structural Example of Pixel)

[0349] Furthermore, the thickness of the substrate forming the signal extraction portion 65 can be determined based on various characteristics of the pixel and the like.

[0350] Thus, for example Figure 24 As shown, the substrate 501 constituting the pixel 51 can be made larger than Figure 2 The substrate 61 shown is thick. Figure 24 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0351] Figure 24 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 501 is provided instead of the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0352] That is, in Figure 24 In the illustrated pixel 51, an on-chip lens 62 and a fixed charge film 66 are formed on the light incident side of the substrate 501, and a light shielding film 63 is formed between pixels. Furthermore, an oxide film 64, a signal extraction portion 65, and a separator 75 are formed near the surface of the substrate 501 opposite the light incident side.

[0353] The substrate 501 is composed of a P-type semiconductor substrate with a thickness of, for example, 20 μm or more. The substrate 501 and the substrate 61 differ only in thickness. The positions where the oxide film 64, the signal extraction portion 65 and the separation portion 75 are formed are the same in the substrate 501 and the substrate 61.

[0354] Furthermore, the film thicknesses of various layers (films) formed appropriately on the light incident surface side of the substrate 501 and the substrate 61 may be optimized according to the characteristics of the pixel 51 .

[0355] (Eleventh embodiment)

[0356] (Structural Example of Pixel)

[0357] Furthermore, in the above, an example in which the substrate constituting the pixel 51 is constituted by a P-type semiconductor substrate has been described, but for example, Figure 25 As shown in FIG, it is composed of an N-type semiconductor substrate. Figure 25 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0358] Figure 25 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 531 is provided instead of the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0359] exist Figure 25 In the illustrated pixel 51 , an on-chip lens 62 , a fixed charge film 66 , and an inter-pixel light shielding film 63 are formed on the light incident surface side of a substrate 531 composed of an N-type semiconductor layer such as a silicon substrate.

[0360] Furthermore, an oxide film 64, a signal extraction portion 65, and a separator 75 are formed near the surface of the substrate 531 on the side opposite to the light incident surface. The oxide film 64, the signal extraction portion 65, and the separator 75 are formed at the same positions in the substrate 531 and the substrate 61, and the structure of the signal extraction portion 65 is also the same in the substrate 531 and the substrate 61.

[0361] The thickness of the substrate 531 in the longitudinal direction in the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 531 , is 20 μm or less, for example.

[0362] The substrate 531 is a high-resistance N-Epi substrate with a substrate concentration of 1E+13 or less, and the resistance (resistivity) of the substrate 531 is, for example, 500 [Ωcm] or more. This reduces power consumption in the pixel 51.

[0363] Here, regarding the relationship between the substrate concentration of the substrate 531 and the resistance, for example, when the substrate concentration is 2.15E+12 [cm 3 ], the resistance is 2000[Ωcm], and the substrate concentration is 4.30E+12[cm 3 ], the resistance is 1000[Ωcm], and the substrate concentration is 8.61E+12[cm 3 ] when the resistance is 500[Ωcm], and when the substrate concentration is 4.32E+13[cm 3 ] when the resistance is 100 [Ωcm], etc.

[0364] Thus, even if the substrate 531 of the pixel 51 is set as an N-type semiconductor substrate, Figure 2 The same actions as in the example shown can also achieve the same effects.

[0365] (Twelfth embodiment)

[0366] (Structural Example of Pixel)

[0367] Furthermore, with reference Figure 24 The same as the example described above, the thickness of the N-type semiconductor substrate can also be determined based on various characteristics of the pixel.

[0368] Thus, for example, Figure 26 As shown, the substrate 561 constituting the pixel 51 is made Figure 25 The substrate 531 shown is thick. Figure 26 in Figure 25 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0369] Figure 26 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 561 is provided instead of the substrate 531. Figure 25 The pixel 51 shown is different from the Figure 25 The pixel 51 has the same structure.

[0370] That is, in Figure 26 In the illustrated pixel 51, an on-chip lens 62, a fixed charge film 66, and an inter-pixel light shielding film 63 are formed on the light incident surface side of a substrate 561. Furthermore, an oxide film 64, a signal extraction portion 65, and a separation portion 75 are formed near the surface of the substrate 561 opposite to the light incident surface side.

[0371] Substrate 561 is composed of an N-type semiconductor substrate with a thickness of, for example, 20 μm or more. The only difference between substrate 561 and substrate 531 is the thickness of the substrate. The positions where the oxide film 64, the signal extraction portion 65 and the separation portion 75 are formed are the same in substrate 561 and substrate 531.

[0372] (Thirteenth embodiment)

[0373] (Structural Example of Pixel)

[0374] Furthermore, for example, by applying a bias voltage to the light incident surface side of the substrate 61 , the electric field in the direction perpendicular to the surface of the substrate 61 (hereinafter also referred to as the Z direction) within the substrate 61 may be strengthened.

[0375] In this case, the pixel 51 is formed as, for example Figure 27 In addition, Figure 27 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0376] Figure 27 A represents Figure 2 In the pixel 51 shown, the arrow in the substrate 61 of the pixel 51 indicates the intensity of the electric field in the Z direction in the substrate 61 .

[0377] In contrast, Figure 27 B shows the structure of the pixel 51 when a bias (voltage) is applied to the light incident surface of the substrate 61 . Figure 27 The structure of pixel 51 of B is basically the same as Figure 2 The pixel 51 shown has the same structure, but a P+ semiconductor region 601 is newly formed on the interface on the light incident surface side of the substrate 61 .

[0378] By applying a voltage of 0 V or less (negative bias) to the P + semiconductor region 601 formed on the light incident surface side interface of the substrate 61 from inside or outside the pixel array unit 20 , the electric field in the Z direction is strengthened. Figure 27 The arrows in the substrate 61 of the pixel 51 of B represent the intensity of the electric field in the Z direction in the substrate 61. Figure 27 The thickness ratio of the arrow drawn in the substrate 61 of B Figure 27 The arrows for pixel A 51 are thicker, and the electric field in the Z direction is stronger. Thus, by applying a negative bias to the P+ semiconductor region 601 formed on the light incident surface side of the substrate 61 to strengthen the electric field in the Z direction, the electron extraction efficiency in the signal extraction unit 65 can be improved.

[0379] Furthermore, the structure for applying a voltage to the light incident surface of substrate 61 is not limited to the structure provided with P+ semiconductor region 601, and may be any other structure. For example, a negative bias voltage may be applied by forming a transparent electrode film laminated between the light incident surface of substrate 61 and on-chip lens 62 and applying a voltage to the transparent electrode film.

[0380] (Fourteenth embodiment)

[0381] (Structural Example of Pixel)

[0382] Furthermore, in order to increase the sensitivity of the pixel 51 to infrared rays, a large-area reflective member may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0383] In such a case, the pixel 51 is, for example, Figure 28 In addition, Figure 28 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0384] Figure 28 The structure of the pixel 51 shown is different from that of the pixel 51 in that a reflective member 631 is provided on the surface of the substrate 61 opposite to the light incident surface. Figure 2 The pixel 51 is different, and other aspects are the same Figure 2 The pixel 51 has the same structure.

[0385] exist Figure 28 In the example of FIG, a reflecting member 631 that reflects infrared light is provided so as to cover the entire surface of the substrate 61 opposite to the light incident surface.

[0386] The reflective member 631 may be any member as long as it has a high reflectivity for infrared light. For example, a metal such as copper or aluminum provided in a multilayer wiring layer stacked on the surface of the substrate 61 opposite to the light incident surface may be used as the reflective member 631. Alternatively, a reflective structure such as polysilicon or an oxide film may be formed on the surface of the substrate 61 opposite to the light incident surface to serve as the reflective member 631.

[0387] Thus, by providing the reflective member 631 in the pixel 51, infrared light that enters the substrate 61 from the light incident surface via the on-chip lens 62 but passes through the substrate 61 without undergoing photoelectric conversion is reflected by the reflective member 631 and reenters the substrate 61. This increases the amount of infrared light that undergoes photoelectric conversion in the substrate 61, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel 51 to infrared light.

[0388] (Fifteenth embodiment)

[0389] (Structural Example of Pixel)

[0390] Furthermore, in order to suppress erroneous detection of light in nearby pixels, a light shielding member having a large area may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0391] In this case, the pixel 51 can be configured, for example, to Figure 28 The reflecting member 631 shown is replaced by a light shielding member. Figure 28In the pixel 51 shown, the reflective member 631 covering the entire surface of the substrate 61 opposite to the light incident surface is used as a light shielding member 631' for shielding infrared light. Figure 28 The reflective component 631 of pixel 51 is replaced.

[0392] The light-shielding member 631' can be any member as long as it has a high infrared light shielding rate. For example, a metal such as copper or aluminum provided in a multilayer wiring layer stacked on the side opposite to the light incident surface of the substrate 61 can be used as the light-shielding member 631'. Alternatively, a light-shielding structure such as polysilicon or an oxide film can be formed on the side opposite to the light incident surface of the substrate 61 to serve as the light-shielding member 631'.

[0393] By providing light shielding member 631' on pixel 51, infrared light that enters substrate 61 from the light incident surface via on-chip lens 62, passes through substrate 61 without undergoing photoelectric conversion, and is prevented from being scattered by the wiring layer and entering nearby pixels. This prevents erroneous light detection in nearby pixels.

[0394] In addition, the light shielding member 631 ′ can also serve as the reflecting member 631 by being formed of a material containing metal, for example.

[0395] (Sixteenth embodiment)

[0396] (Structural Example of Pixel)

[0397] Furthermore, a P-well region composed of a P-type semiconductor region may be provided instead of the oxide film 64 in the substrate 61 of the pixel 51 .

[0398] In such a case, the pixel 51 is, for example, Figure 29 In addition, Figure 29 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0399] Figure 29 The structure of the pixel 51 shown is different from that of the pixel 51 in that a P-well region 671, a separation portion 672-1, and a separation portion 672-2 are provided instead of the oxide film 64. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0400] exist Figure 29In the example, a P-well region (Pwell) 671 composed of a P-type semiconductor region is formed on the side of the substrate 61 opposite to the light incident surface, that is, in the central part of the inner side of the lower side in the figure. In addition, between the P-well region 671 and the N+ semiconductor region 71-1, a separation portion 672-1 for separating these regions is formed by an oxide film or the like. Similarly, between the P-well region 671 and the N+ semiconductor region 71-2, a separation portion 672-2 for separating these regions is also formed by an oxide film or the like. Figure 29 In the illustrated pixel 51 , the P − semiconductor region 74 is a region wider in the upper direction of the figure than the N − semiconductor region 72 .

[0401] (Seventeenth embodiment)

[0402] (Structural Example of Pixel)

[0403] Furthermore, in addition to the oxide film 64 in the substrate 61 of the pixel 51 , a P-well region composed of a P-type semiconductor region may be provided.

[0404] In such a case, the pixel 51 is, for example, Figure 30 In addition, Figure 30 in Figure 2 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0405] Figure 30 The structure of the pixel 51 shown is different from that of the pixel 51 in that a new P-well region 701 is provided. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure. Figure 30 In the example, a P-well region 701 composed of a P-type semiconductor region is formed on the upper side of the oxide film 64 in the substrate 61.

[0406] As described above, according to the present invention, by configuring the CAPD sensor as a back-illuminated type, characteristics such as pixel sensitivity can be improved.

[0407] (Equivalent Circuit Structure Example of Pixel)

[0408] Figure 31 denoted as an equivalent circuit of the pixel 51 .

[0409] The pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplifying transistor 724A, and a selecting transistor 725A for the signal taking-out portion 65 - 1 including the N + semiconductor region 71 - 1 and the P + semiconductor region 73 - 1 .

[0410] Furthermore, the pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplifying transistor 724B, and a selecting transistor 725B for the signal taking-out portion 65 - 2 including the N + semiconductor region 71 - 2 and the P + semiconductor region 73 - 2 .

[0411] The tap driver 21 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is 1.5 V, and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 serve as voltage application sections to which the first voltage or the second voltage is applied.

[0412] The N+ semiconductor regions 71 - 1 and 71 - 2 are charge detection portions that detect and accumulate charges generated by photoelectric conversion of light incident on the substrate 61 .

[0413] When the drive signal TRG supplied to the gate electrode is activated, the transfer transistor 721A is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-1 to the FD 722A. When the drive signal TRG supplied to the gate electrode is activated, the transfer transistor 721B is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-2 to the FD 722B.

[0414] FD722A temporarily holds the charge DET0 supplied from the N+ semiconductor region 71-1. FD722B temporarily holds the charge DET1 supplied from the N+ semiconductor region 71-2. Figure 2 The FD part A described above corresponds to FD722B, and the FD part B corresponds to FD722B.

[0415] When the drive signal RST supplied to its gate electrode becomes active, the reset transistor 723A is turned on in response, thereby resetting the potential of the FD 722A to a predetermined level (power supply voltage VDD). When the drive signal RST supplied to its gate electrode becomes active, the reset transistor 723B is turned on in response, thereby resetting the potential of the FD 722B to a predetermined level (power supply voltage VDD). Furthermore, when the reset transistors 723A and 723B are activated, the transfer transistors 721A and 721B are also activated simultaneously.

[0416] The amplifier transistor 724A is connected to the vertical signal line 29A via the source electrode via the select transistor 725A, thereby forming a load MOS transistor and a source follower circuit for the constant current source circuit portion 726A connected to one end of the vertical signal line 29A. The amplifier transistor 724B is connected to the vertical signal line 29B via the source electrode via the select transistor 725B, thereby forming a load MOS transistor and a source follower circuit for the constant current source circuit portion 726B connected to one end of the vertical signal line 29B.

[0417] The selection transistor 725A is connected between the source of the amplifier transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate electrode is activated, the selection transistor 725A is turned on and outputs the pixel signal output from the amplifier transistor 724A to the vertical signal line 29A.

[0418] The selection transistor 725B is connected between the source of the amplifier transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate electrode is activated, the selection transistor 725B turns on and outputs the pixel signal output from the amplifier transistor 724B to the vertical signal line 29B.

[0419] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by, for example, the vertical drive section 22 .

[0420] (Another equivalent circuit structure example of a pixel)

[0421] Figure 32 Another equivalent circuit of the pixel 51 is shown.

[0422] exist Figure 32 In, with Figure 31 The corresponding parts are marked with the same reference numerals, and their descriptions are omitted as appropriate.

[0423] Figure 32 The equivalent circuit for Figure 31 In the equivalent circuit of FIG, an additional capacitor 727 and a switching transistor 728 for controlling the connection between the additional capacitor and the switching transistor 728 are added to both the signal extraction units 65-1 and 65-2.

[0424] Specifically, the additional capacitor 727A is connected between the transfer transistor 721A and the FD 722A via the switching transistor 728A, and the additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B via the switching transistor 728B.

[0425] When the drive signal FDG supplied to the gate electrode is activated, the switching transistor 728A is turned on, thereby connecting the additional capacitor 727A to the FD 722A. When the drive signal FDG supplied to the gate electrode is activated, the switching transistor 728B is turned on, thereby connecting the additional capacitor 727B to the FD 722B.

[0426] For example, when incident light is high in intensity, the vertical drive unit 22 activates the switching transistors 728A and 728B to connect the FD 722A to the additional capacitor 727A and the FD 722B to the additional capacitor 727B. This allows more charge to be stored during high illumination.

[0427] On the other hand, at low illumination with a small amount of incident light, the vertical drive unit 22 sets the switching transistors 728A and 728B to an inactive state, and disconnects the additional capacitors 727A and 727B from the FDs 722A and 722B, respectively.

[0428] like Figure 31 As in the equivalent circuit of , the additional capacitor 727 can be omitted, but by providing the additional capacitor 727 and using them separately according to the amount of incident light, a high dynamic range can be ensured.

[0429] (Arrangement Example of Voltage Supply Lines)

[0430] Next, refer to Figures 33 to 35 , the configuration of the voltage supply lines for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the voltage application section of the signal extraction section 65 of each pixel 51 will be described. Figure 33 and Figure 34 The voltage supply line 741 is shown with Figure 1 The voltage supply line 30 shown corresponds.

[0431] In addition, Figure 33 and Figure 34 In the embodiment, the structure of the signal extraction unit 65 of each pixel 51 adopts Figure 9 The circular structure shown is used for illustration, but other structures are of course possible.

[0432] Figure 33 A is a plan view showing a first arrangement example of the voltage supply lines.

[0433] In the first arrangement example, with respect to the plurality of pixels 51 arranged two-dimensionally in a matrix, the voltage supply line 741 - 1 or 741 - 2 is arranged in the vertical direction between two pixels adjacent in the horizontal direction (at the boundary).

[0434] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, which is one of the two signal extraction sections 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, which is the other of the two signal extraction sections 65 in the pixel 51.

[0435] In this first arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are arranged in two pixel columns. Therefore, in the pixel array section 20 , the number of arranged voltage supply lines 741 is substantially equal to the number of columns of pixels 51 .

[0436] Figure 33 B is a plan view showing a second arrangement example of the voltage supply lines.

[0437] In the second arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are arranged in the vertical direction with respect to one pixel column of a plurality of pixels 51 arranged two-dimensionally in a matrix.

[0438] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, which is one of the two signal extraction sections 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, which is the other of the two signal extraction sections 65 in the pixel 51.

[0439] In this second arrangement example, two voltage supply lines 741-1 and 741-2 are arranged for one pixel column, so four voltage supply lines 741 are arranged for two pixel columns. In the pixel array section 20, the number of voltage supply lines 741 arranged is approximately twice the number of columns of pixels 51.

[0440] exist Figure 33 In the configuration examples A and B, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, which is a Periodic configuration (periodic configuration) that is periodically repeated relative to the pixels arranged in the vertical direction.

[0441] exist Figure 33 In the first configuration example of A, the number of voltage supply lines 741 - 1 and 741 - 2 arranged with respect to the pixel array section 20 can be reduced.

[0442] Figure 33Compared with the first configuration example, although the second configuration example of B has more wiring lines, the number of signal extraction units 65 connected to one voltage supply line 741 is 1 / 2, so the load on the wiring can be reduced, which is effective in high-speed driving and when the total number of pixels in the pixel array unit 20 is large.

[0443] Figure 34 A is a plan view showing a third arrangement example of the voltage supply lines.

[0444] The third configuration example is Figure 33 This is the same as the first configuration example of A, and is an example in which two voltage supply lines 741 - 1 and 741 - 2 are configured for two pixel columns.

[0445] The third configuration example is Figure 33 The difference from the first arrangement example of A is that, in the two pixels arranged in the vertical direction, the signal extraction sections 65-1 and 65-2 are connected to different destinations.

[0446] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, but in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1.

[0447] Figure 34 B is a plan view showing a fourth arrangement example of the voltage supply lines.

[0448] The fourth configuration example is Figure 33 The second configuration example of B is the same as that of FIG. 1 , and is an example in which two voltage supply lines 741 - 1 and 741 - 2 are configured for two pixel columns.

[0449] The fourth configuration example is Figure 33 The second arrangement example of B is different in that the signal extraction sections 65-1 and 65-2 are connected to different destinations in two pixels arranged in the vertical direction.

[0450] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, but in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1.

[0451] exist Figure 34 In the third arrangement example of A, the number of voltage supply lines 741 - 1 and 741 - 2 arranged with respect to the pixel array section 20 can be reduced.

[0452] Figure 34 Compared with the third configuration example, although the fourth configuration example of B has more wiring lines, the number of signal extraction parts 65 connected to one voltage supply line 741 is 1 / 2, so the wiring load can be reduced, which is effective in high-speed driving and when the total number of pixels in the pixel array part 20 is large.

[0453] Figure 34 Both the arrangement examples A and B are mirror arrangements (mirror arrangements) in which the pixels are mirror-inverted with respect to the connection destination of two pixels adjacent to each other vertically (in the vertical direction).

[0454] In the Periodic configuration, such as Figure 35 As shown in Figure 1, the voltages applied to the two adjacent signal extraction units 65 across the pixel boundary are different, causing charge exchange between adjacent pixels. This improves charge transfer efficiency compared to a mirror configuration, but results in worse crosstalk between adjacent pixels.

[0455] On the other hand, in the Mirror configuration, if Figure 35 As shown in Figure B, the voltage applied to two adjacent signal extraction units 65 across a pixel boundary is the same, thus suppressing the exchange of charge between adjacent pixels. Therefore, the charge transfer efficiency is lower than that of the Periodic configuration, but the crosstalk characteristics between adjacent pixels are better than those of the Periodic configuration.

[0456] (Cross-sectional Structure of Multiple Pixels in Fourteenth Embodiment)

[0457] exist Figure 2 In the cross-sectional structure of the pixel shown in FIG. 1 , the multilayer wiring layer formed on the surface side opposite to the light incident surface of the substrate 61 is omitted from illustration.

[0458] Therefore, in the following, in the several embodiments described above, cross-sectional views of a plurality of adjacent pixels are shown without omitting the multilayer wiring layer.

[0459] First, in Figure 36 and Figure 37 Shown in Figure 28 A cross-sectional view of a plurality of pixels according to a fourteenth embodiment is shown.

[0460] Figure 28 The fourteenth embodiment shown has a pixel structure including a large-area reflective member 631 on the side of the substrate 61 opposite to the light incident surface.

[0461] Figure 36 Equivalent to Figure 11 The cross-sectional view at the BB' line, Figure 37 Equivalent to Figure 11 The cross-sectional view at line A-A' of Figure 17 The cross-sectional view at the CC' line can also be Figure 36 shown.

[0462] like Figure 36 As shown, in each pixel 51 , an oxide film 64 is formed in the center portion, and a signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed on both sides of the oxide film 64 .

[0463] In the signal extraction section 65-1, an N+ semiconductor region 71-1 and an N− semiconductor region 72-1 are formed around the P+ semiconductor region 73-1 and the P− semiconductor region 74-1, surrounding these regions. The P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are in contact with the multilayer wiring layer 811. The P− semiconductor region 74-1 is arranged above the P+ semiconductor region 73-1 (on the side of the on-chip lens 62) to cover the P+ semiconductor region 73-1, while the N− semiconductor region 72-1 is arranged above the N+ semiconductor region 71-1 (on the side of the on-chip lens 62) to cover the N+ semiconductor region 71-1. In other words, the P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are arranged on the multilayer wiring layer 811 side within the substrate 61, while the N− semiconductor region 72-1 and the P− semiconductor region 74-1 are arranged on the side of the on-chip lens 62 within the substrate 61. Furthermore, between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1, a separation portion 75-1 is formed by an oxide film or the like to separate these regions.

[0464] In the signal extraction section 65-2, an N+ semiconductor region 71-2 and an N− semiconductor region 72-2 are formed around the P+ semiconductor region 73-2 and the P− semiconductor region 74-2, surrounding the P+ semiconductor region 73-2 and the P− semiconductor region 74-2. The P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are in contact with the multilayer wiring layer 811. The P− semiconductor region 74-2 is arranged above the P+ semiconductor region 73-2 (on the side of the on-chip lens 62) to cover the P+ semiconductor region 73-2, while the N− semiconductor region 72-2 is arranged above the N+ semiconductor region 71-2 (on the side of the on-chip lens 62) to cover the N+ semiconductor region 71-2. In other words, the P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are arranged on the multilayer wiring layer 811 side within the substrate 61, while the N− semiconductor region 72-2 and the P− semiconductor region 74-2 are arranged on the side of the on-chip lens 62 within the substrate 61. Furthermore, a separation portion 75 - 2 is also formed between the N + semiconductor region 71 - 2 and the P + semiconductor region 73 - 2 by an oxide film or the like to separate these regions.

[0465] The oxide film 64 is also formed between the N+ semiconductor region 71-1 of the signal extraction portion 65-1 of a given pixel 51 and the N+ semiconductor region 71-2 of the signal extraction portion 65-2 of the adjacent pixel 51, which is a boundary region between adjacent pixels 51.

[0466] On the light incident surface side of the substrate 61 ( Figure 36 and Figure 37 A fixed charge film 66 is formed at the interface of the upper surface in the middle.

[0467] like Figure 36 As shown, when the on-chip lens 62 formed for each pixel on the light incident surface side of the substrate 61 is divided in the height direction into a raised portion 821 whose thickness increases uniformly throughout the entire pixel and a curved surface portion 822 whose thickness varies depending on the position within the pixel, the thickness of the raised portion 821 is formed to be thinner than the thickness of the curved surface portion 822. The thicker the raised portion 821, the more easily obliquely incident light is reflected by the inter-pixel light shielding film 63. Therefore, by thinning the raised portion 821, even obliquely incident light can be taken into the substrate 61. Furthermore, the thicker the curved surface portion 822, the more effectively it can focus incident light at the center of the pixel.

[0468] A multilayer wiring layer 811 is formed on the side of the substrate 61 opposite to the light incident surface where the on-chip lens 62 is formed for each pixel. In other words, the substrate 61 as a semiconductor layer is arranged between the on-chip lens 62 and the multilayer wiring layer 811. The multilayer wiring layer 811 is composed of five layers of metal films M1 to M5 and an interlayer insulating film 812 therebetween. Figure 36In the figure, the outermost metal film M5 among the five metal films M1 to M5 of the multilayer wiring layer 811 is located in an invisible position because it is not shown in the figure, but it is located in the position from which it is connected. Figure 36 The cross-sectional view of the cross-sectional view observed in different directions is Figure 37 .

[0469] like Figure 37 As shown, the pixel transistor Tr is formed in the pixel boundary region of the interface portion between the multilayer wiring layer 811 and the substrate 61. The pixel transistor Tr is Figure 31 and Figure 32 Any one of the transfer transistor 721 , reset transistor 723 , amplification transistor 724 , and selection transistor 725 shown.

[0470] The metal film M1 closest to the substrate 61 among the five metal films M1 to M5 of the multilayer wiring layer 811 includes a power supply line 813 for supplying a power supply voltage, a voltage application wiring 814 for applying a predetermined voltage to the P+ semiconductor region 73-1 or 73-2, and a reflective member 815 as a member for reflecting incident light. Figure 36 In the metal film M1, the wiring other than the power line 813 and the voltage application wiring 814 becomes the reflective component 815. In order to prevent the drawing from becoming complicated, some of the reference numerals are omitted. The reflective component 815 is a virtual wiring set for the purpose of reflecting incident light, which is equivalent to Figure 28 The reflecting member 815 is arranged below the N+ semiconductor regions 71-1 and 71-2 in such a manner as to overlap with the N+ semiconductor regions 71-1 and 71-2 of the charge detection portion when viewed from above. Figure 28 In the case where the reflecting member 631 of the fourteenth embodiment is replaced with the light shielding member 631' of the fifteenth embodiment, Figure 36 Part of the reflective component 815 becomes the light shielding component 631'.

[0471] Furthermore, in the metal film M1, a charge extraction wiring ( ) connecting the N+ semiconductor region 71 and the transfer transistor 721 is formed in order to transfer the charge accumulated in the N+ semiconductor region 71 to the FD 722. Figure 36 (not shown in the figure).

[0472] In this example, the reflective member 815 (reflective member 631 ) and the charge extraction wiring are arranged in the same layer of the metal film M1 , but they are not necessarily limited to being arranged in the same layer.

[0473] The metal film M2, which is the second layer from the substrate 61 side, includes, for example, a voltage application wiring 816 connected to the voltage application wiring 814 of the metal film M1, a control line 817 for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, a drive signal FDG, and the like, and a ground line. Furthermore, an FD 722B and an additional capacitor 727A are formed in the metal film M2.

[0474] In the metal film M3 which is the third layer from the substrate 61 side, for example, the vertical signal line 29 , a VSS wiring for shielding, and the like are formed.

[0475] In the fourth and fifth metal films M4 and M5 from the substrate 61 side, for example, voltage supply lines 741-1 and 741-2 are formed for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 as the voltage applying portion of the signal extraction portion 65. Figure 33 、 Figure 34 ).

[0476] In addition, the planar configuration of the five metal films M1 to M5 of the multilayer wiring layer 811 will be referred to. Figure 42 and Figure 43 This will be described later.

[0477] (Cross-sectional Structure of Multiple Pixels in Ninth Embodiment)

[0478] Figure 38 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 22 FIG. 1 is a cross-sectional view of a pixel structure according to a ninth embodiment.

[0479] Figure 22 The ninth embodiment shown is a pixel structure in which a long groove (trench) is formed in the pixel boundary portion within the substrate 61 from the back side (light incident surface) of the substrate 61 to a predetermined depth and a light shielding film is buried to form a separation area 441.

[0480] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0481] (Cross-sectional Structure of Multiple Pixels in Modification 1 of Ninth Embodiment)

[0482] Figure 39 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 23 FIG. 1 is a cross-sectional view of a pixel structure according to a first modification of the ninth embodiment.

[0483] Figure 23The modified example 1 of the ninth embodiment shown has a pixel structure in which a separation region 471 penetrating the entire substrate 61 is provided at a pixel boundary portion within the substrate 61 .

[0484] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0485] (Cross-sectional Structure of Multiple Pixels in Sixteenth Embodiment)

[0486] Figure 40 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 29 A cross-sectional view of a pixel structure according to a sixteenth embodiment is shown.

[0487] Figure 29 The sixteenth embodiment shown has a structure in which a P-well region 671 is provided in the central portion of the inner side of the substrate 61, on the side opposite to the light incident surface, that is, the lower side in the figure. Furthermore, a separation portion 672-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 is formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. The P-well region 671 is also formed at the pixel boundary portion on the lower side of the substrate 61.

[0488] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0489] (Cross-sectional Structure of Multiple Pixels in Tenth Embodiment)

[0490] Figure 41 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 24 FIG. 1 is a cross-sectional view of a pixel structure according to a tenth embodiment.

[0491] Figure 24 The tenth embodiment shown has a pixel structure in which a thick substrate 501 is provided instead of the substrate 61 .

[0492] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0493] (Example of Planar Arrangement of Five-Layer Metal Films M1 to M5)

[0494] Next, refer to Figure 42 and Figure 43 right Figures 36 to 41An example of a planar arrangement of five metal films M1 to M5 of the multilayer wiring layer 811 will be described.

[0495] Figure 42 A represents a planar configuration example of the first metal film M1 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0496] Figure 42 B shows a planar configuration example of the second metal film M2 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0497] Figure 42 C represents a planar configuration example of the third metal film M3 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0498] Figure 43 A represents a planar configuration example of the fourth metal film M4 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0499] Figure 43 B shows a planar configuration example of the fifth metal film M5 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0500] In addition, Figure 42 A to C and Figure 43 In A and B, the dotted line represents the area of ​​pixel 51, and the Figure 11 The regions of the octagonal signal extraction portions 65-1 and 65-2 are shown.

[0501] exist Figure 42 A to C and Figure 43 In A and B of FIG. 1 , the longitudinal direction of the drawing is the vertical direction of the pixel array section 20 , and the lateral direction of the drawing is the horizontal direction of the pixel array section 20 .

[0502] like Figure 42 As shown in FIG. 1A , a reflective member 631 that reflects infrared light is formed on the metal film M1 that is the first layer of the multilayer wiring layer 811. In the region of the pixel 51, two reflective members 631 are formed with respect to the signal extraction portions 65-1 and 65-2, respectively. The two reflective members 631 of the signal extraction portion 65-1 are formed symmetrically with respect to the two reflective members 631 of the signal extraction portion 65-2 with respect to the vertical direction.

[0503] Furthermore, a pixel transistor wiring region 831 is provided between the reflective members 631 of adjacent pixels 51 in the horizontal direction. Wiring is formed in the pixel transistor wiring region 831 to connect the pixel transistors Tr such as the transfer transistor 721, the reset transistor 723, the amplifier transistor 724, or the select transistor 725. The wiring for the pixel transistors Tr is also formed symmetrically in the vertical direction with respect to the center line (not shown) between the two signal extraction units 65-1 and 65-2.

[0504] Furthermore, wiring such as a ground line 832, a power line 833, and a ground line 834 is formed between the reflective members 631 of adjacent pixels 51 in the vertical direction. These wirings are also formed symmetrically in the vertical direction with respect to the midline between the two signal extraction units 65-1 and 65-2.

[0505] In this way, the first metal film M1 is symmetrically arranged in the region on the signal extraction portion 65-1 side and the region on the signal extraction portion 65-2 side within the pixel. This allows for evenly adjusting the wiring load in the signal extraction portions 65-1 and 65-2. This reduces driving variations between the signal extraction portions 65-1 and 65-2.

[0506] In the first metal film M1, a large-area reflective member 631 is formed below the signal extraction portions 65-1 and 65-2 formed on the substrate 61. This allows infrared light that enters the substrate 61 via the on-chip lens 62 but passes through the substrate 61 without undergoing photoelectric conversion to be reflected by the reflective member 631 and re-enters the substrate 61. This increases the amount of infrared light that undergoes photoelectric conversion within the substrate 61, thereby improving the quantum efficiency (QE), or in other words, the sensitivity of the pixel 51 to infrared light.

[0507] On the other hand, in the first metal film M1, by disposing a light shielding member 631' in the same region as the reflective member 631 instead of the reflective member 631, infrared light that enters the substrate 61 from the light incident surface via the on-chip lens 62, passes through the substrate 61 without undergoing photoelectric conversion, and is prevented from being scattered in the wiring layer and incident on nearby pixels. This prevents erroneous light detection in nearby pixels.

[0508] like Figure 42 As shown in FIG. 8B , in the metal film M2 serving as the second layer of the multilayer wiring layer 811, a control line region 851 is provided between the signal extraction portions 65-1 and 65-2. Control lines 841 to 844, etc., which transmit predetermined signals in the horizontal direction, are formed in the control line region 851. For example, the control lines 841 to 844 transmit the drive signal TRG, the drive signal RST, the select signal SEL, or the drive signal FDG.

[0509] By arranging the control line region 851 between the two signal extraction sections 65, the influence on the signal extraction sections 65-1 and 65-2 becomes equal, and the driving variation between the signal extraction sections 65-1 and 65-2 can be reduced.

[0510] Furthermore, a capacitor region 852, where FD 722B and additional capacitor 727A are formed, is located in a predetermined region of the second metal film M2, separate from the control line region 851. In capacitor region 852, the metal film M2 is patterned into a comb-like shape to form FD 722B and additional capacitor 727A.

[0511] By disposing the FD 722B or the additional capacitor 727A in the second-layer metal film M2 , the pattern of the FD 722B or the additional capacitor 727A can be freely arranged according to desired wiring capacitance in design, thereby improving the degree of design freedom.

[0512] like Figure 42 As shown in FIG. 3 , in the metal film M3 serving as the third layer of the multilayer wiring layer 811, at least a vertical signal line 29 is formed for transmitting the pixel signal output from each pixel 51 to the column processing unit 23. To increase the readout speed of the pixel signal, three or more vertical signal lines 29 can be arranged for each pixel column. In addition to the vertical signal line 29, a shielded wiring can also be arranged to reduce coupling capacitance.

[0513] In the fourth and fifth metal films M4 and M5 of the multilayer wiring layer 811 , voltage supply lines 741 - 1 and 741 - 2 are formed for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73 - 1 and 73 - 2 of the signal extraction portion 65 of each pixel 51 .

[0514] Figure 43 The metal films M4 and M5 shown in A and B represent the use of Figure 33 A shows the case of the voltage supply line 741 of the first configuration example.

[0515] The voltage supply line 741-1 of the metal film M4 is connected to the voltage applying wiring 814 (eg, Figure 36 ) is connected, and the voltage applying wiring 814 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1 of the pixel 51. Similarly, the voltage supply line 741-2 of the metal film M4 is connected to the voltage applying wiring 814 (for example, Figure 36 ) is connected, and the voltage applying wiring 814 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2 of the pixel 51.

[0516] The voltage supply lines 741-1 and 741-2 of the metal film M5 are connected to the tap driver 21 in the periphery of the pixel array unit 20. The voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 are connected at predetermined positions on both metal films in a planar region via a through-hole (not shown). A predetermined voltage MIX0 or MIX1 from the tap driver 21 is transmitted through the voltage supply lines 741-1 and 741-2 of the metal film M5, supplied to the voltage supply lines 741-1 and 741-2 of the metal film M4, and then supplied from the voltage supply lines 741-1 and 741-2 to the voltage application wiring 814 of the metal film M1 via the metal films M3 and M2.

[0517] By setting the light receiving element 1 as a back-illuminated CAPD sensor, for example Figure 43 As shown in A and B of FIG, the voltage supply lines 741-1 and 741-2 for applying a predetermined voltage MIX0 or MIX1 to the signal extraction unit 65 of each pixel 51 can be arranged in a vertical direction, and the wiring width and layout of the drive wiring can be freely designed. In addition, wiring suitable for high-speed driving and wiring that takes load reduction into consideration can be achieved.

[0518] (Example of Planar Arrangement of Pixel Transistors)

[0519] Figure 44 Yes Figure 42 A is a plan view showing the overlap between the first metal film M1 and the polysilicon layer formed thereon, such as the gate electrode of the pixel transistor Tr.

[0520] Figure 44 A is to make Figure 44 The metal film M1 of C and Figure 44 The top view of the polysilicon layer of B coincides with the top view of Figure 44 B is a top view of only the polysilicon layer. Figure 44 C is a top view of only the metal film M1. Figure 44 The top view of the metal film M1 of C and Figure 42 The same top view as shown in A, but with hatching omitted.

[0521] As reference Figure 42 As described in FIG. 1A , a pixel transistor wiring region 831 is formed between the reflective components 631 of each pixel.

[0522] The pixel transistors Tr corresponding to the signal taking-out sections 65-1 and 65-2 are, for example, Figure 44 It is configured in the pixel transistor wiring area 831 as shown in B.

[0523] exist Figure 44In B, with the middle line (not shown) of the two signal taking-out parts 65-1 and 65-2 as a reference, the gate electrodes of reset transistors 723A and 723B, transfer transistors 721A and 721B, switching transistors 728A and 728B, selection transistors 725A and 725B, and amplification transistors 724A and 724B are formed from the side close to the middle line.

[0524] connect Figure 44 The wiring between the pixel transistors Tr of the metal film M1 shown in C is also formed symmetrically in the vertical direction with respect to the middle line (not shown) between the two signal extraction portions 65-1 and 65-2.

[0525] In this way, by symmetrically arranging the plurality of pixel transistors Tr in the pixel transistor wiring region 831 in the region on the signal extraction section 65-1 side and the region on the signal extraction section 65-2 side, driving variations between the signal extraction sections 65-1 and 65-2 can be reduced.

[0526] (Modification of Reflection Member 631)

[0527] Next, refer to Figure 45 and Figure 46 A modification of the reflective member 631 formed on the metal film M1 will be described.

[0528] In the above example, if Figure 42 As shown in FIG. 1A , a large-area reflective member 631 is arranged in a region surrounding the signal extraction portion 65 within the pixel 51 .

[0529] In contrast, the reflective member 631 is, for example, Figure 45 As shown in Figure A, a grid-shaped pattern can also be used. Forming the reflective component 631 in a grid-shaped pattern eliminates pattern anisotropy and reduces the XY anisotropy of the reflective capability. In other words, forming the reflective component 631 in a grid-shaped pattern reduces the reflection of incident light in a biased area, facilitating isotropic reflection, thereby improving ranging accuracy.

[0530] Alternatively, in addition, the reflective member 631 may be, for example, Figure 45 As shown in FIG. 1B , the reflective member 631 may be arranged in a stripe pattern. By forming the reflective member 631 in a stripe pattern, the pattern of the reflective member 631 can also be used as a wiring capacitor, thereby achieving a structure that maximizes the dynamic range.

[0531] in addition, Figure 45 B is an example of a vertical stripe shape, but a horizontal stripe shape may also be used.

[0532] Alternatively, in addition, the reflective member 631 may be, for example, Figure 45 As shown in FIG. 3 , the reflective member 631 is disposed only in the center region of the pixel, more specifically, only between the two signal extraction units 65. Thus, by forming the reflective member 631 in the center region of the pixel instead of forming the reflective member 631 at the pixel ends, the reflective member 631 can improve the sensitivity of the center region of the pixel, and can suppress the component reflected toward adjacent pixels when oblique light is incident, thereby achieving a structure that prioritizes suppression of crosstalk.

[0533] In addition, the reflective member 631 is, for example, Figure 46 As shown in A, a part of the pattern may be arranged in a comb-tooth shape, thereby allocating a part of the metal film M1 to the wiring capacitance of the FD722 or the additional capacitor 727. Figure 46 In Figure A, the comb-teeth shape within the solid circled regions 861 to 864 constitutes at least a portion of the FD 722 or the additional capacitor 727. The FD 722 or the additional capacitor 727 can also be appropriately separated and arranged in the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflective member 631, the FD 722, or the additional capacitor 727.

[0534] Figure 46 B shows the pattern of the metal film M1 without the reflective member 631. To increase the amount of infrared light photoelectrically converted in the substrate 61 and improve the sensitivity of the pixel 51, the reflective member 631 is preferably provided, but it is also possible to adopt a structure without the reflective member 631.

[0535] Figure 45 and Figure 46 The arrangement example of the reflecting member 631 shown can also be applied to the light shielding member 631 ′.

[0536] (Example of substrate structure of light-receiving element)

[0537] Figure 1 The light receiving element 1 can be used Figure 47 Any one of the substrate structures A to C.

[0538] Figure 47 A shows an example in which the light receiving element 1 is constituted by a semiconductor substrate 911 and a supporting substrate 912 thereunder.

[0539] In this case, a pixel array region 951 corresponding to the pixel array unit 20 , a control circuit 952 for controlling each pixel in the pixel array region 951 , and a logic circuit 953 including a signal processing circuit for pixel signals are formed on the upper semiconductor substrate 911 .

[0540] The control circuit 952 includes the aforementioned tap driving unit 21, vertical driving unit 22, horizontal driving unit 24, and the like. The logic circuit 953 includes a column processing unit 23 that performs A / D conversion processing on pixel signals, a signal processing unit 31 that performs distance calculation processing based on the ratio of pixel signals obtained by two or more signal extraction units 65 within a pixel, calibration processing, and the like.

[0541] Alternatively, in addition, the light receiving element 1 may be Figure 47 As shown in FIG. 1B , a structure may be formed in which a first semiconductor substrate 921 having a pixel array region 951 and a control circuit 952 and a second semiconductor substrate 922 having a logic circuit 953 are stacked. Furthermore, the first semiconductor substrate 921 and the second semiconductor substrate 922 are electrically bonded, for example, via a through hole or a Cu-Cu metal bond.

[0542] Alternatively, in addition, the light receiving element 1 may be Figure 47 As shown in FIG. 3 , a first semiconductor substrate 931 having only a pixel array region 951 formed therein and a second semiconductor substrate 932 having a regional control circuit 954 formed therein, which includes a control circuit for controlling each pixel and a signal processing circuit for processing pixel signals, arranged per pixel or per region of multiple pixels, can be stacked. The first semiconductor substrate 931 and the second semiconductor substrate 932 are electrically bonded, for example, via a through-hole or a Cu-Cu metal bond.

[0543] like Figure 47 By providing a control circuit and a signal processing circuit per pixel or per region, as in the case of the light-receiving element 1 of FIG. 1 , it is possible to set the optimal drive timing and gain for each divided control unit, thereby obtaining optimized distance information regardless of distance and reflectivity. Furthermore, by driving only a portion of the pixel array region 951 rather than the entire region to calculate distance information, power consumption can be reduced depending on the operating mode.

[0544] (Eighteenth embodiment)

[0545] (Structural Example of Pixel)

[0546] Next, other embodiments other than the first to seventeenth embodiments described above will be described. For example, when the thickness of substrate 61 is increased, there is a risk that the electric field in the photoelectric conversion region, which is far away from the P+ semiconductor region 73 (voltage application unit) and the N+ semiconductor region 71 (charge detection unit), will weaken. Therefore, the following embodiments describe structures that strengthen the electric field in the photoelectric conversion region, improve quantum efficiency (QE), and achieve high-speed driving.

[0547] Figure 48 It is a cross-sectional view of a pixel according to the eighteenth embodiment.

[0548] Figure 48 and the above Figure 36 Equally, it means equivalent to Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0549] exist Figure 48 In, for and Figure 36 In the cross-sectional view of a plurality of pixels according to the fourteenth embodiment, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0550] Will Figure 48 The structure of the pixel 51 of the eighteenth embodiment is the same as Figure 36 Compared to the structure of the pixel 51 of the fourteenth embodiment shown, a through electrode 1001 is newly formed at the pixel boundary portion, which is the boundary portion between adjacent pixels 51, penetrating the substrate 61, which is a P-type semiconductor layer, to separate the adjacent pixels 51, and an insulating film 1002 is newly formed to cover the outer periphery (sidewall) of the through electrode 1001. The through electrode 1001 is formed of a metal material such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or polycrystalline silicon. The insulating film 1002 is formed of, for example, silicon oxide (SiO2) or silicon oxynitride (SiON). The material of the insulating film 1002 may also include an oxide or nitride containing at least one of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti), or an oxide or nitride containing at least one of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). The through-electrode 1001 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Alternatively, the through-electrode 1001 including the peripheral insulating film 1002 and the insulating film 1002 may constitute the pixel separator.

[0551] The through-electrode 1001 is electrically connected to a voltage applying wiring 1011 of the metal film M1, which is the metal film closest to the substrate 61 of the multilayer wiring layer 811. A predetermined bias (voltage) is applied to the through-electrode 1001 via the voltage applying wiring 1011. Here, the bias applied to the through-electrode 1001 is a voltage lower than the voltage applied to the P+ semiconductor region 73 of the signal extraction portion 65, which serves as a passive tap. In the above example, since 0 V is applied to the P+ semiconductor region 73 of the signal extraction portion 65, which serves as a passive tap, the bias voltage is a voltage lower than 0 V, that is, a negative bias voltage.

[0552] A groove can be formed from the surface side or back side of the substrate 61 to the opposite side of the substrate by dry etching, etc. After the insulating film 1002 is formed, the through electrode 1001 and the insulating film 1002 are formed by burying polysilicon or metal material to form the through electrode 1001.

[0553] Figure 49 Yes Figure 48 A top view of multiple pixels 51 viewed from above.

[0554] like Figure 49 As shown, the through electrodes 1001 are arranged in a lattice pattern at the boundary between adjacent pixels 51 , and the insulating film 1002 is formed so as to cover the side walls of the through electrodes 1001 .

[0555] In the pixel 51 of the eighteenth embodiment, a through-electrode 1001 is formed at the boundary of the pixel 51 as a pixel separator, and a negative bias is applied to the through-electrode 1001. This strengthens the electric field in the planar direction toward the signal extraction portion 65 (tap), achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance to high-speed driving is enhanced.

[0556] in addition, Figure 49 The top view of a pixel 51 having two signal extraction units 65, i.e., a so-called 2-tap pixel structure, and a pixel 51 having four signal extraction units, i.e., a so-called 4-tap pixel structure, is shown as follows: Figure 50 shown.

[0557] Figure 50 Yes Figure 17 FIG. 1 is a plan view showing an example of the arrangement of the through electrode 1001 and the insulating film 1002 in the four-tap pixel structure shown.

[0558] When the pixel 51 has a 4-tap pixel structure, as in the 2-tap case, the through-electrodes 1001 are arranged in a grid-like manner at the boundary portions of adjacent pixels 51 , and the insulating film 1002 is formed to cover the outer periphery (side wall) of the through-electrode 1001 .

[0559] (Variation 1 of the Eighteenth Embodiment)

[0560] (Structural Example of Pixel)

[0561] exist Figure 48 and Figure 49 In the pixel 51 of the eighteenth embodiment shown in FIG. 1 , the penetrating electrode 1001 and the insulating film 1002 are formed on the pixel boundary portion of the entire circumference of the pixel 51. However, as shown in FIG. Figure 51 and Figure 52 As shown, the penetrating electrode 1001 and the insulating film 1002 may be formed by dividing the periphery of the pixel 51 into two halves.

[0562] Figure 51 It is a top view of a pixel according to a modification of the eighteenth embodiment in which the pixel 51 has a two-tap pixel structure.

[0563] When the pixel 51 has a 2-tap pixel structure, a gap portion 1003 is provided at the pixel boundary portion intersecting with the center line (not shown) of the two signal taking-out portions 65, so that the through electrode 1001 and the insulating film 1002 are divided into a through electrode 1001A and an insulating film 1002A on the signal taking-out portion 65 side on one side, and a through electrode 1001B and an insulating film 1002B on the signal taking-out portion 65 side on the other side.

[0564] From the perspective of a single pixel unit, the through electrode 1001 and the insulating film 1002 of the pixel 51 are based on the middle line of the two signal taking-out portions 65, and are composed of a through electrode 1001A and an insulating film 1002A arranged at the pixel boundary portion on one side of the signal taking-out portion 65, and a through electrode 1001B and an insulating film 1002B arranged at the pixel boundary portion on the other side of the signal taking-out portion 65.

[0565] Figure 52 It is a top view of a pixel according to a modified example of the eighteenth embodiment in which the pixel 51 has a four-tap pixel structure.

[0566] When the pixel 51 has a 4-tap pixel structure, for example, by providing a gap portion 1003 on the pixel boundary portion that intersects with a middle line (not shown) that divides the four signal take-out portions 65 into two units in the vertical direction or the horizontal direction, the through electrode 1001 and the insulating film 1002 are divided into the through electrode 1001A and the insulating film 1002A on the side of the specified two signal take-out portions 65, and the through electrode 1001B and the insulating film 1002B on the side of the remaining two signal take-out portions 65. Figure 52 A structural example is shown in which a gap portion 1003 is provided at a pixel boundary portion intersecting with a center line that divides the four signal extraction portions 65 into two units in the vertical direction.

[0567] like Figure 51 and Figure 52 As shown, even when a gap 1003 is provided at the boundary between adjacent pixels 51, quantum efficiency (QE) and high-speed driving can be improved by applying a negative bias to the through-electrode 1001 via the voltage applying wiring 1011. Furthermore, the high-speed driving resistance is improved.

[0568] In addition, in a modified example in which a gap portion 1003 is provided on a portion of the pixel separation portion, similar to the structure of the pixel separation portion in which the gap portion 1003 is not provided and surrounds the entire circumference of the pixel, a negative bias can be applied to both the through electrodes 1001A and 1001B at the same time or at different times.

[0569] Figure 53 This diagram explains driving when negative bias voltages are applied to the through electrodes 1001A and 1001B at different timings when the pixel 51 has a two-tap pixel structure.

[0570] For example Figure 53 As shown in A, a positive voltage is applied to the P+ semiconductor region 73-1 of the signal extraction section 65-1. When the signal extraction section 65-1 is set as an active tap, a negative bias is applied to the through electrode 1001B of the pixel isolation section as the passive tap side.

[0571] On the other hand, Figure 53 As shown in FIG. 1B , a positive voltage is applied to the P+ semiconductor region 73-2 of the signal extraction unit 65-2. When the signal extraction unit 65-2 is configured as an active tap, a negative bias is applied to the through electrode 1001A of the pixel isolation unit, which is the passive tap side. Application of the negative bias can be performed by, for example, the tap driver 21.

[0572] In this way, by applying a negative bias to the pixel separation section on the passive tap side opposite to the signal extraction section 65 configured as an active tap, the electric field in the planar direction from the passive tap side toward the active tap side is strengthened, thereby achieving improved quantum efficiency (QE) and high-speed driving. In addition, the tolerance for high-speed driving is improved.

[0573] Figure 54 and Figure 55 This diagram shows a drive in which a negative bias voltage is applied at different timings to a plurality of pixels 51 arranged two-dimensionally in a matrix.

[0574] Figure 54 This is the case where pixel 51 has a 2-tap pixel structure. Figure 55 The case where the pixel 51 has a 4-tap pixel structure is shown.

[0575] Since the through electrodes 1001A and 1001B each share two pixels 51 adjacent in the vertical direction, when the two pixels 51 adjacent in the vertical direction are set as the first pixel 51 and the second pixel 51, the signal extraction portion 65 on the lower side of the first pixel 51 and the signal extraction portion 65 on the upper side of the second pixel 51 simultaneously become active taps, and correspondingly, a negative bias is applied to the pixel separation portion (through electrode 1001A or 1001B) on the passive tap side. Therefore, in the two pixels 51 adjacent in the vertical direction, the positions of the signal extraction portion 65 that becomes the active tap and the signal extraction portion 65 that becomes the passive tap are opposite. This drive can be achieved by Figure 34 The third and fourth configuration examples of the voltage supply lines shown in A and B are implemented.

[0576] (Nineteenth embodiment)

[0577] (Structural Example of Pixel)

[0578] Figure 56 It is a cross-sectional view of a pixel according to the nineteenth embodiment.

[0579] Figure 56 and the above Figure 36 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0580] exist Figure 56 In, for and Figure 36 In the cross-sectional view of a plurality of pixels according to the fourteenth embodiment, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0581] Will Figure 56 The structure of the pixel 51 of the nineteenth embodiment is the same as Figure 36 For comparison, in the structure of the pixel 51 of the fourteenth embodiment shown, a DTI (Deep Trench Isolation) 1021 is newly formed at the boundary between adjacent pixels 51, extending from the surface of the substrate 61, which is the P-type semiconductor layer, on the multilayer wiring layer 811 side, to a predetermined depth. This DTI 1021 is separated from the adjacent pixels 51, and an insulating film 1022 is newly formed to cover the outer periphery (sidewalls) of the DTI 1021. The DTI 1021 is formed of, for example, a metal material such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or polycrystalline silicon. The insulating film 1022 is formed of, for example, silicon oxide (SiO2) or silicon oxynitride (SiON). The material of the insulating film 1022 may also include an oxide or nitride containing at least one of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti), or an oxide or nitride containing at least one of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). The DTI 1021 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Alternatively, the DTI 1021, including the peripheral insulating film 1022, and the insulating film 1022 may constitute the pixel separator.

[0582] The DTI 1021 is electrically connected to the voltage applying wiring 1011 of the metal film M1, which is the metal film closest to the substrate 61 in the multilayer wiring layer 811, and a negative bias is applied to the DTI 1021 via the voltage applying wiring 1011. Here, the negative bias applied to the DTI 1021 is a voltage lower than the voltage applied to the P+ semiconductor region 73 of the signal extraction portion 65 of the passive tap.

[0583] A groove can be formed to a specified depth from the surface side of the substrate 61 (the multilayer wiring layer 811 side) by dry etching, etc. After the insulating film 1022 is formed, DTI1021 and the insulating film 1022 are formed by burying polysilicon or metal material to become DTI1021.

[0584] Will Figure 56 The structure of the pixel 51 of the nineteenth embodiment is the same as Figure 48 When compared with the structure of the pixel 51 of the eighteenth embodiment shown in FIG, the pixel 51 of the nineteenth embodiment has the same point in that a pixel separation portion is provided at the pixel boundary portion to separate the P-type semiconductor layer, i.e., the substrate 61, and a negative bias is applied to the pixel separation portion by means of the voltage applying wiring 1011. Figure 48 The pixel 51 of the eighteenth embodiment shown is different in that the DTI 1021 and the insulating film 1022 do not penetrate the substrate 61 but are formed only from the back side of the substrate 61 to a position with a predetermined depth.

[0585] The top view of the DTI 1021 and the insulating film 1022 is omitted, but the DTI 1021 and Figure 49 Similarly, the DTI 1021 is arranged in a lattice pattern at the boundary portions of the two-dimensionally arranged pixels 51 , and the insulating film 1022 is formed so as to cover the side walls of the DTI 1021 .

[0586] According to the pixel 51 of the nineteenth embodiment, a DTI 1021 serving as a pixel separator is formed at the boundary of the pixel 51, and a negative bias is applied to the DTI 1021. This strengthens the electric field in the planar direction toward the signal extraction unit 65 (tap), thereby improving quantum efficiency (QE) and enabling high-speed driving. Furthermore, the tolerance for high-speed driving is enhanced.

[0587] (Twentieth embodiment)

[0588] (Structural Example of Pixel)

[0589] Figure 57 It is a cross-sectional view of a pixel according to the twentieth embodiment.

[0590] exist Figure 57 In, for and Figure 36 In the cross-sectional view of a plurality of pixels according to the fourteenth embodiment, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0591] Figure 57 is equivalent to Figure 11 The cross-sectional view of the plurality of pixels along the line BB' is a cross-sectional view of the pixel array unit 20 in which the pixels 51 are arranged two-dimensionally in a matrix and a peripheral circuit unit 1041 therearound. The peripheral circuit unit 1041 is shown in FIG. Figure 1 The above-mentioned structure is formed by, for example, a tap driving section 21 and a vertical driving section 22 .

[0592] Figure 58 It is a plan view showing the positional relationship between the pixel array unit 20 and the peripheral circuit unit 1041 .

[0593] like Figure 58 As shown, the pixel array section 20 is composed of an effective pixel area 1042 in which a plurality of pixels 51 are arranged and a surrounding OPB pixel area 1043. Furthermore, a peripheral circuit section 1041 is arranged on the periphery of the pixel array section 20. A plurality of electrode pads 1045 serving as input and output terminals of the light-receiving element 1 are formed on the peripheral circuit section 1041.

[0594] return Figure 57 In the effective pixel area 1042 of the pixel array unit 20, pixels 51 are arranged in a matrix, and the pixels 51 output signals corresponding to the amount of incident light. In the OPB pixel area 1043, light-shielding pixels 51X are arranged, in which an inter-pixel light-shielding film 63 is formed on the entire area of ​​the pixel area. Except for the opening portion (except the pixel boundary portion) of each pixel 51 in the effective pixel area 1042, the inter-pixel light-shielding film 63 is formed on the fixed charge film 66 of the pixel array unit 20 and the peripheral circuit unit 1041. In addition, Figure 57 In the example shown, the light-shielding pixels 51X form two columns or two rows, but may also form one column or one row, or may form three or more columns or three or more rows.

[0595] Will Figure 57 The structure of the pixel 51 of the twentieth embodiment is the same as Figure 36For comparison, the structure of the pixel 51 of the fourteenth embodiment shown in FIG. 1 is a structure in which a DTI (Deep Trench Isolation) 1051 is newly formed at the boundary between adjacent pixels 51, extending from the light incident surface of the P-type semiconductor layer, i.e., the substrate 61, to a predetermined depth. This structure separates the adjacent pixels 51, and an insulating film 1052 is newly formed to cover the periphery (sidewalls) of the DTI 1051. The DTI 1051 is formed, for example, from a metal material such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or from polycrystalline silicon. The insulating film 1052 is formed, for example, from silicon oxide (SiO2) or silicon oxynitride (SiON). The material of the insulating film 1052 may also include an oxide or nitride containing at least one of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti), or an oxide or nitride containing at least one of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). The DTI 1051 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Alternatively, the DTI 1051, including the peripheral insulating film 1052, and the insulating film 1052 may constitute the pixel separator. The DTI 1051 and the insulating film 1052 are also formed on the boundary portion between the adjacent light-shielded pixels 51X in the OPB pixel region 1043 , similarly to the pixel 51 .

[0596] A groove can be formed to a specified depth from the light incident surface side of the substrate 61 (on-chip lens 62 side) by dry etching, etc. After forming the insulating film 1052, DTI1051 and the insulating film 1052 are formed by burying polysilicon or metal material to become DTI1051.

[0597] The top view of DTI 1051 and insulating film 1052 is omitted, but Figure 49 Similarly, the DTIs 1051 are arranged in a lattice pattern at the boundary portions of the two-dimensionally arranged pixels 51 , and the insulating film 1052 is formed so as to cover the side walls of the DTIs 1051 .

[0598] The DTI 1051 is connected to the inter-pixel light shielding film 63 on the light incident surface side of the substrate 61. The inter-pixel light shielding film 63 is also connected to a through electrode 1061 formed in the peripheral circuit portion 1041. The through electrode 1061 is connected to the voltage application wiring 1063 of the multilayer wiring layer 811. The outer periphery (side wall) of the through electrode 1061 is covered with an insulating film 1062.

[0599] A negative bias (negative voltage) is supplied to the voltage applying wiring 1063 formed in the multilayer wiring layer 811 of the peripheral circuit portion 1041 , and a negative bias is applied to the DTI 1051 via the through electrode 1061 and the inter-pixel light shielding film 63 .

[0600] Will Figure 57 The structure of the pixel 51 of the twentieth embodiment is the same as Figure 48 When comparing the structures of the pixel 51 of the eighteenth embodiment shown, the common point is that the pixel 51 of the twentieth embodiment is provided with a pixel separation portion on the pixel boundary portion of the pixel 51 to separate the P-type semiconductor layer, i.e., the substrate 61, and a negative bias is applied to the pixel separation portion by means of a prescribed voltage application wiring.

[0601] On the other hand, and Figure 48 The pixel 51 of the eighteenth embodiment shown differs in that the DTI 1051 and insulating film 1052 do not penetrate the substrate 61 but are formed only from the light incident surface side of the substrate 61 to a predetermined depth. Furthermore, a negative bias is applied to the DTI 1051, which serves as the pixel isolation portion, from a voltage application wiring 1063 formed in the peripheral circuit section 1041, located outside the pixel array section 20, via the penetrating electrode 1061 formed in the peripheral circuit section 1041 and the inter-pixel light shielding film 63 on the upper surface of the fixed charge film 66. In addition to applying the negative bias to the DTI 1051 from the voltage application wiring 1063 in the peripheral circuit section 1041 via the inter-pixel light shielding film 63, a negative bias can also be applied to the DTI 1051 by supplying the negative bias to the inter-pixel light shielding film 63 on the upper surface of the fixed charge film 66 from outside the light-receiving element 1.

[0602] According to the pixel 51 of the twentieth embodiment, a DTI 1051 serving as a pixel separator is formed at the boundary of the pixel 51, and a negative bias is applied to the DTI 1051. This strengthens the electric field in the planar direction toward the signal extraction unit 65 (tap), thereby improving quantum efficiency (QE) and enabling high-speed driving. Furthermore, the tolerance for high-speed driving is enhanced.

[0603] (Twenty-first embodiment)

[0604] (Structural Example of Pixel)

[0605] Figure 59 It is a cross-sectional view of a pixel according to the twenty-first embodiment.

[0606] Figure 59 and the above Figure 36 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0607] exist Figure 59 In, for and Figure 36 In the cross-sectional view of a plurality of pixels according to the fourteenth embodiment, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0608] Will Figure 59 The structure of the pixel 51 of the twenty-first embodiment is the same as Figure 36 In comparison with the structure of the pixel 51 of the fourteenth embodiment shown, a high-concentration P-type semiconductor region, namely, a P+ semiconductor region 1071, is newly formed by, for example, ion implantation, over the entire region in the depth direction of the substrate 61 at the boundary portion between adjacent pixels 51. The P+ semiconductor region 1071 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51.

[0609] The P+ semiconductor region 1071 is electrically connected to the voltage applying wiring 1011 of the metal film M1 , which is the metal film closest to the substrate 61 in the multilayer wiring layer 811 . A negative bias is applied to the P+ semiconductor region 1071 via the voltage applying wiring 1011 .

[0610] The top view of the P+ semiconductor region 1071 is omitted, but the P+ semiconductor region 1071 and Figure 49 Likewise, the boundary portions of the two-dimensionally arranged pixels 51 are formed in a lattice pattern.

[0611] In the pixel 51 of the twenty-first embodiment, a P+ semiconductor region 1071 serving as a pixel separator is formed at the boundary between adjacent pixels 51, and a negative bias is applied to the P+ semiconductor region 1071. This strengthens the electric field in the planar direction toward the signal extraction unit 65 (tap), achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance for high-speed driving is enhanced.

[0612] In the eighteenth to twenty-first embodiments described above, a negative bias is applied to the pixel separator formed at the pixel boundary of the pixel 51. Here, the negative bias is a voltage lower than the voltage (0V) applied to the P+ semiconductor region 73 of the signal extraction section 65, which serves as a passive tap. This strengthens the electric field in the plane direction of the signal extraction section 65 (tap), thereby achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance to high-speed driving is improved.

[0613] (Twenty-second embodiment)

[0614] (Structural Example of Pixel)

[0615] Next, in addition to the eighteenth to twenty-first embodiments described above, other embodiments will be further described.

[0616] In the above-mentioned eighteenth to twenty-first embodiments, a structure is described in which a negative bias voltage is applied to a pixel separation portion formed on the boundary portion of adjacent pixels 51 to enhance the electric field in the plane direction. The following twenty-second to twenty-fifth embodiments describe a structure in which the electric field in the depth direction perpendicular to the substrate 61 is enhanced.

[0617] Figure 60 It is a cross-sectional view of a pixel according to the twenty-second embodiment.

[0618] Figure 60 and the above Figure 36 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0619] exist Figure 60 In, for and Figure 36 In the cross-sectional view of a plurality of pixels according to the fourteenth embodiment, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0620] Will Figure 60 The structure of the pixel 51 of the twenty-second embodiment is the same as Figure 36 For comparison, the structure of the pixel 51 of the fourteenth embodiment shown in the figure has a newly formed through-electrode 1101 that penetrates the P-type semiconductor layer, i.e., the substrate 61, at the boundary portion between adjacent pixels 51, i.e., the pixel boundary portion, to separate the adjacent pixels 51. The through-electrode 1101 is formed by, for example, a metal material such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or polycrystalline silicon. The insulating film 1102 is formed by, for example, silicon oxide (SiO2) or silicon oxynitride (SiON). The material of the insulating film 1102 may also include an oxide or nitride containing at least one of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti), or an oxide or nitride containing at least one of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). The through-electrode 1101 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Alternatively, the through-electrode 1101 including the peripheral insulating film 1102 and the insulating film 1102 may be considered to constitute the pixel separator.

[0621] A groove can be formed from the surface side or back side of the substrate 61 to the opposite side of the substrate by dry etching, etc. After the insulating film 1102 is formed, the through electrode 1101 and the insulating film 1102 are formed by burying polysilicon or metal material to become the through electrode 1101.

[0622] A transparent conductive film 1103 is formed on the upper surface of the fixed charge film 66 formed on the light incident surface of the substrate 61 of each pixel 51. The transparent conductive film 1103 is connected to the through electrode 1101 at the boundary portion of the pixel 51. Materials such as ITO (Indium-tin-oxide), ZnO, SnO, Cd2 SnO4, or TiO2:Nb can be used as the transparent conductive film 1103.

[0623] The through electrode 1101 is electrically connected to a voltage applying wiring 1111 of the metal film M1, which is the metal film closest to the substrate 61 in the multilayer wiring layer 811. A negative bias is applied to the voltage applying wiring 1111. The negative bias from the voltage applying wiring 1111 is applied to the fixed charge film 66 via the through electrode 1101 and the transparent conductive film 1103.

[0624] According to the pixel 51 of the twenty-second embodiment, a through electrode 1101 serving as a pixel separator is formed at the boundary portion of the pixel 51, and a transparent conductive film 1103 is formed on the upper surface of the fixed charge film 66. A negative bias voltage supplied from the voltage application wiring 1111 of the multilayer wiring layer 811 is then applied to the fixed charge film 66 via the through electrode 1101 and the transparent conductive film 1103. This strengthens the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap), achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance to high-speed driving is improved.

[0625] Furthermore, if the fixed charge film 66 is not formed on the light incident surface of the substrate 61 in the pixel 51, an insulating film composed of an oxide film or the like may be formed on the light incident surface of the substrate 61, and a negative bias may be applied to the insulating film via the through electrode 1101 and the transparent conductive film 1103. The insulating film is not limited to a single-layer film and may also be a laminated film.

[0626] (Twenty-third embodiment)

[0627] (Structural Example of Pixel)

[0628] Figure 61 It is a cross-sectional view of a pixel according to the twenty-third embodiment.

[0629] Figure 61 and Figure 60 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0630] exist Figure 61 About and Figure 60 In the cross-sectional view of a plurality of pixels in the twenty-second embodiment shown, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0631] Will Figure 61 The structure of the pixel 51 of the twenty-third embodiment is the same as Figure 60 When compared with the structure of the pixel 51 of the twenty-second embodiment shown, the pixel 51 of the twenty-third embodiment has in common that a through electrode 1101 and an insulating film 1102 covering the outer periphery (sidewall) of the through electrode 1101 are formed at the boundary portion of the pixel 51. Furthermore, the through electrode 1101 is electrically connected to a voltage applying wiring 1111 of the metal film M1 of the multilayer wiring layer 811 closest to the substrate 61, and a negative bias is supplied to the voltage applying wiring 1111.

[0632] On the other hand, Figure 60 In the pixel 51 of the twenty-second embodiment shown in FIG. 1 , a transparent conductive film 1103 is formed on the upper surface of the fixed charge film 66. However, Figure 61 The twenty-third embodiment differs in that the transparent conductive film 1103 is not formed, and the inter-pixel light shielding film 63 penetrates the fixed charge film 66 and is connected to the through electrode 1101. The inter-pixel light shielding film 63 is formed of a metal material such as tungsten (W), aluminum (Al), or copper (Cu), and has light shielding properties and electrical conductivity.

[0633] According to the pixel 51 of this twenty-third embodiment, a through electrode 1101 serving as a pixel separator is formed at the boundary portion of the pixel 51, and the through electrode 1101 is connected to the inter-pixel light shielding film 63. Then, a negative bias voltage supplied from the voltage application wiring 1111 of the multi-layer wiring layer 811 is applied to the fixed charge film 66 via the through electrode 1101 and the inter-pixel light shielding film 63. In this way, the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap) can be strengthened, and improvement in quantum efficiency (QE) and high-speed driving can be achieved. In addition, the tolerance to high-speed driving is improved.

[0634] Furthermore, if the fixed charge film 66 is not formed on the light incident surface of the substrate 61 in the pixel 51, an insulating film composed of an oxide film or the like may be formed on the light incident surface of the substrate 61, and a negative bias may be applied to the insulating film via the through electrode 1101 and the inter-pixel light shielding film 63. The insulating film is not limited to a single-layer film and may also be a laminated film.

[0635] (Twenty-fourth embodiment)

[0636] (Structural Example of Pixel)

[0637] Figure 62 It is a cross-sectional view of a pixel according to the twenty-fourth embodiment.

[0638] Figure 62 and Figure 60 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0639] exist Figure 62 In, for and Figure 60 In the cross-sectional view of a plurality of pixels in the twenty-second embodiment shown, corresponding parts are denoted by the same reference numerals, and description of the parts will be appropriately omitted.

[0640] Will Figure 62 The structure of the pixel 51 of the twenty-fourth embodiment is the same as Figure 60 When comparing the structure of the pixel 51 of the twenty-second embodiment shown, the common point is that the pixel 51 of the twenty-fourth embodiment forms a transparent conductive film 1103 on the upper surface of the fixed charge film 66, and the difference is that the through electrode 1101 and the insulating film 1102 are not formed in the boundary portion with the adjacent pixel 51.

[0641] according to Figure 62 In the twenty-fourth embodiment, since the through-electrode 1101 is not formed in the pixel array section 20, a negative bias cannot be applied from the through-electrode 1101. Therefore, in the twenty-fourth embodiment, a negative bias is supplied to the transparent conductive film 1103 via the through-electrode 1161 from a voltage applying wiring 1163 formed on the peripheral circuit section 1041 outside the pixel array section 20, and a negative bias is applied to the fixed charge film 66 from the transparent conductive film 1103.

[0642] Specifically, in the twenty-fourth embodiment, a voltage applying wiring 1163 is formed in the multilayer wiring layer 811 of the peripheral circuit portion 1041 outside the pixel array portion 20, and a negative bias is supplied to the voltage applying wiring 1163. Furthermore, a through electrode 1161 having an outer periphery covered by an insulating film 1162 is formed on the peripheral circuit portion 1041 of the substrate 61. The through electrode 1161 is connected to the transparent conductive film 1103 on the light incident surface of the substrate 61.

[0643] In the pixel 51 of the twenty-fourth embodiment, a negative bias voltage supplied from the voltage application wiring 1163 of the multilayer wiring layer 811 is applied to the fixed charge film 66 via the through electrode 1161 and the transparent conductive film 1103. This strengthens the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap), thereby achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance to high-speed driving is enhanced.

[0644] Furthermore, if the fixed charge film 66 is not formed on the light incident surface of the substrate 61 in the pixel 51, an insulating film composed of an oxide film or the like may be formed on the light incident surface of the substrate 61, and a negative bias may be applied to the insulating film via the through electrode 1101 and the transparent conductive film 1103. The insulating film is not limited to a single-layer film and may also be a laminated film.

[0645] (Twenty-fifth embodiment)

[0646] (Structural Example of Pixel)

[0647] Figure 63 It is a cross-sectional view of a pixel according to the twenty-fifth embodiment.

[0648] Figure 63 and Figure 60 Likewise, it represents the equivalent of Figure 11 A cross-sectional view of multiple pixels along line BB'.

[0649] exist Figure 63 In, for and Figure 61 and Figure 62 In the cross-sectional views of a plurality of pixels according to the twenty-second and twenty-third embodiments, corresponding portions are denoted by the same reference numerals, and descriptions of such portions are appropriately omitted.

[0650] Will Figure 63 The structure of the pixel 51 of the twenty-fifth embodiment is the same as Figure 61 When comparing the structure of the pixel 51 of the twenty-third embodiment shown, the common point is that the pixel 51 of the twenty-fifth embodiment applies a negative bias to the fixed charge film 66 with the help of the inter-pixel shading film 63, and the difference is that the through electrode 1101 and the insulating film 1102 are not formed on the boundary part with the adjacent pixel 51.

[0651] according to Figure 63 In the twenty-fifth embodiment, since the through-electrode 1101 is not formed in the pixel array section 20, a negative bias cannot be applied from the through-electrode 1101. Therefore, in the twenty-fifth embodiment, a negative bias is supplied to the inter-pixel light shielding film 63 via the through-electrode 1161 from the voltage applying wiring 1163 formed on the peripheral circuit section 1041 outside the pixel array section 20, and a negative bias is applied from the inter-pixel light shielding film 63 to the fixed charge film 66.

[0652] Specifically, in the twenty-fifth embodiment, a voltage application wiring 1163 is formed in the multilayer wiring layer 811 of the peripheral circuit portion 1041 located outside the pixel array portion 20, and a negative bias is supplied to the voltage application wiring 1163. Furthermore, a through electrode 1161 having an outer periphery covered by an insulating film 1162 is formed in the peripheral circuit portion 1041 of the substrate 61, and the through electrode 1161 is connected to the inter-pixel light shielding film 63 on the light incident surface of the substrate 61.

[0653] In the pixel 51 of the twenty-fifth embodiment, a negative bias voltage supplied from the voltage application wiring 1163 of the multilayer wiring layer 811 is applied to the fixed charge film 66 via the through electrode 1161 and the inter-pixel light shielding film 63. This strengthens the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap), thereby achieving improved quantum efficiency (QE) and high-speed driving. Furthermore, the tolerance to high-speed driving is enhanced.

[0654] Furthermore, if the fixed charge film 66 is not formed on the light incident surface of the substrate 61 in the pixel 51, an insulating film composed of an oxide film or the like may be formed on the light incident surface of the substrate 61, and a negative bias may be applied to the insulating film via the through electrode 1101 and the inter-pixel light shielding film 63. The insulating film is not limited to a single-layer film and may also be a laminated film.

[0655] In the above-mentioned twenty-second to twenty-fifth embodiments, a negative bias is applied to the fixed charge film 66 formed on the light incident surface on the side of the on-chip lens 62 of the substrate 61 by the through electrode 1101 or 1161. Here, the negative bias is a voltage lower than the voltage (0V) applied to the P+ semiconductor region 73 of the signal extraction portion 65 serving as a passive tap. In this way, the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap) can be strengthened, and improvement in quantum efficiency (QE) and high-speed driving can be achieved. In addition, the tolerance for high-speed driving is improved. In addition, both the through electrode 1161 of the peripheral circuit portion 1041 and the through electrode 1101 of the pixel boundary portion can be provided, and the two parties can be used to apply a negative bias to the fixed charge film 66.

[0656] (Configuration example of a distance measurement module)

[0657] Figure 64 Is to indicate the use of Figure 1 1 is a block diagram showing a configuration example of a distance measuring module in which the light receiving element 1 outputs distance measurement information.

[0658] The distance measuring module 5000 includes a light emitting unit 5011 , a light emission control unit 5012 , and a light receiving unit 5013 .

[0659] The light-emitting unit 5011 includes a light source that emits light of a predetermined wavelength, and emits illumination light with periodically varying brightness, which is then directed toward an object. For example, the light source includes a light-emitting diode that emits infrared light with a wavelength in the range of 780 nm to 1000 nm. The light-emitting unit 5011 generates the illumination light in synchronization with a rectangular wave illumination control signal CLKp supplied from the illumination control unit 5012.

[0660] Furthermore, the light emission control signal CLKp is not limited to a rectangular wave as long as it is a periodic signal. For example, the light emission control signal CLKp may be a sine wave.

[0661] The light control unit 5012 supplies a light control signal CLKp to the light emitting unit 5011 and the light receiving unit 5013 to control the timing of the light emission. The frequency of the light control signal CLKp is, for example, 20 megahertz (MHz). The frequency of the light control signal CLKp is not limited to 20 MHz and may also be 5 MHz, for example.

[0662] The light receiving unit 5013 receives reflected light from an object, calculates distance information for each pixel based on the light reception result, generates and outputs a depth image that represents the distance to the object using a grayscale value for each pixel.

[0663] The above-mentioned light receiving element 1 is used in the light receiving unit 5013. As the light receiving element 1 of the light receiving unit 5013, for example, based on the light emission control signal CLKp, the distance information is calculated for each pixel according to the signal intensity detected by the respective charge detection units (N+ semiconductor region 71) of the signal extraction units 65-1 and 65-2 of each pixel 51 of the pixel array unit 20.

[0664] As described above, the light receiving unit 5013 of the distance measuring module 5000 that obtains and outputs the distance information to the subject by the indirect ToF method can be assembled Figure 1 By employing the light receiving element 1 of each of the above-described embodiments as the light receiving portion 5013 of the distance measuring module 5000, specifically, employing a back-illuminated light receiving element with improved pixel sensitivity, the distance measuring characteristics of the distance measuring module 5000 can be improved.

[0665] (Application example to mobile objects)

[0666] The technology of the present invention (the present technology) can be applied to a variety of products. For example, the technology of the present invention can be implemented as a device installed in any mobile object, such as an automobile, electric vehicle, hybrid vehicle, motorcycle, bicycle, personal mobility device, aircraft, drone, ship, or robot.

[0667] Figure 65 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present invention can be applied.

[0668] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 65In the example shown, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. The functional configuration of integrated control unit 12050 includes a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface 12053.

[0669] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a braking device that generates the vehicle's braking force.

[0670] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a controller for keyless entry systems, smart key systems, power windows, and various lights such as headlights, taillights, brake lights, indicators, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[0671] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture images outside the vehicle and receive the captured images. The vehicle exterior information detection unit 12030 can also perform object detection processing, such as people, vehicles, obstacles, signs, or text on the road, or distance detection processing based on the received images.

[0672] The imaging unit 12031 is a photosensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as both an image and distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared.

[0673] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver status detection unit 12041 is connected to the in-vehicle information detection unit 12040 to detect the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration level, or determine whether the driver is drowsy.

[0674] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on vehicle interior and exterior information obtained from the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, or vehicle departure warning.

[0675] In addition, the microcomputer 12051 can control the driving force generating device, control mechanism or braking device based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for the purpose of automatic driving, etc., which is independent of the driver's operation.

[0676] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform coordinated control for the purpose of preventing glare, such as switching from high beam to low beam.

[0677] The audio and video output unit 12052 can send an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the passengers of the vehicle or the outside of the vehicle. Figure 65 In the example of FIG, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0678] Figure 66 This is a diagram showing an example of the installation position of the camera unit 12031.

[0679] exist Figure 66 In FIG, the vehicle 12100 includes the imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as the imaging unit 12031 .

[0680] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front bumper, side mirrors, rear bumper, trunk lid, and the upper portion of the front windshield within the vehicle 12100. Camera 12101 on the front bumper and camera 12105 on the upper portion of the front windshield within the vehicle primarily capture images of the front of vehicle 12100. Cameras 12102 and 12103 on the side mirrors primarily capture images of the sides of vehicle 12100. Camera 12104 on the rear bumper or trunk lid primarily captures images of the rear of vehicle 12100. The images of the front captured by cameras 12101 and 12105 are primarily used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0681] In addition, Figure 66 shows an example of the imaging ranges of the cameras 12101 to 12104. Imaging range 12111 represents the imaging range of the camera 12101 installed on the front bumper, imaging ranges 12112 and 12113 represent the imaging ranges of the cameras 12102 and 12103 installed on the side mirrors, respectively, and imaging range 12114 represents the imaging range of the camera 12104 installed on the rear bumper or tailgate. For example, by overlaying the image data captured by the cameras 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

[0682] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[0683] For example, based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 calculates the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change in this distance (relative speed to the vehicle 12100). This allows the microcomputer 12051 to identify the closest three-dimensional object on the path of the vehicle 12100, particularly one traveling in the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to the preceding vehicle and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). This enables coordinated control aimed at autonomous driving, which allows the vehicle to travel independently of the driver's operation.

[0684] For example, based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data related to three-dimensional objects into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, and extract these data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that are visually visible to the driver of the vehicle 12100 and those that are difficult to visually identify. The microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk exceeds a set value, indicating a potential collision, the microcomputer 12051 outputs an alert to the driver via the audio speaker 12061 and display unit 12062, and initiates forced deceleration and evasive steering via the drive system control unit 12010, thereby providing driving assistance to avoid collisions.

[0685] At least one of the imaging units 12101 to 12104 may also be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104, the audio and video output unit 12052 controls the display unit 12062 to display a square outline for emphasis overlaid on the recognized pedestrian. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0686] The above describes an example of a vehicle control system to which the technology of the present invention can be applied. The technology of the present invention can be applied to the camera unit 12031 in the structure described above. Specifically, for example, Figure 1 The light receiving element 1 shown is applied to the imaging unit 12031, and characteristics such as sensitivity can be improved.

[0687] The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present technology.

[0688] For example, it is naturally possible to appropriately combine two or more of the above-described embodiments. Specifically, for example, the number and placement of signal extraction units within a pixel, the shape of the signal extraction units and whether they are shared, the presence or absence of on-chip lenses, the presence or absence of inter-pixel light shielding, the presence or absence of isolation regions, the thickness of on-chip lenses and substrates, the type and film design of the substrate, the presence or absence of a bias voltage toward the light incident surface, the presence or absence of a reflective component, and the like can be appropriately selected based on which characteristic, such as the sensitivity of the pixel, is prioritized.

[0689] Furthermore, while the above embodiments describe an example using electrons as signal carriers, holes generated by photoelectric conversion can also be used as signal carriers. In this case, as long as the charge detection unit for detecting the signal carriers is composed of a P+ semiconductor region and the voltage application unit for generating an electric field within the substrate is composed of an N+ semiconductor region, the charge detection unit provided in the signal extraction unit can detect the holes as signal carriers.

[0690] According to the present technology, by configuring the CAPD sensor as a back-illuminated light-receiving element, it is possible to improve the distance measurement characteristics.

[0691] Furthermore, while the above embodiment describes a driving method in which a voltage is directly applied to the P+ semiconductor region 73 formed on the substrate 61, thereby causing the photoelectrically converted charge to move via the generated electric field, the present technology is not limited to this driving method and may also be applied to other driving methods. For example, a driving method may also be employed in which a predetermined voltage is applied to the gates of the first and second transfer transistors, respectively, formed on the substrate 61, thereby distributing the photoelectrically converted charge to the first floating diffusion region via the first transfer transistor or to the second floating diffusion region via the second transfer transistor for accumulation. In this case, the first and second transfer transistors formed on the substrate 61 function as first and second voltage application units, respectively, for applying the predetermined voltage to the gates, and the first and second floating diffusion regions formed on the substrate 61 function as first and second charge detection units, respectively, for detecting the charge generated by the photoelectric conversion.

[0692] In other words, in a drive method in which a voltage is directly applied to the P+ semiconductor region 73 formed on the substrate 61, and the resulting electric field causes the photoelectrically converted charge to move, the two P+ semiconductor regions 73, serving as the first and second voltage application units, serve as control nodes to which a predetermined voltage is applied, and the two N+ semiconductor regions 71, serving as the first and second charge detection units, serve as detection nodes for detecting the charge. In a drive method in which a predetermined voltage is applied to the gates of the first and second transfer transistors formed on the substrate 61, and the photoelectrically converted charge is distributed to the first floating diffusion region or the second floating diffusion region for accumulation, the gates of the first and second transfer transistors serve as control nodes to which a predetermined voltage is applied, and the first and second floating diffusion regions formed on the substrate 61 serve as detection nodes for detecting the charge.

[0693] Furthermore, the effects described in this specification are merely illustrative and not limiting, and other effects may also be present.

[0694] In addition, the present invention can adopt the following structures.

[0695] (1) A light receiving element comprising:

[0696] On-chip lens;

[0697] wiring layer; and

[0698] a semiconductor layer disposed between the on-chip lens and the wiring layer,

[0699] The semiconductor layer includes:

[0700] a first voltage applying portion to which a first voltage is applied;

[0701] a second voltage applying unit to which a second voltage different from the first voltage is applied;

[0702] a first charge detection unit disposed around the first voltage applying unit;

[0703] a second charge detection unit disposed around the second voltage applying unit; and

[0704] a through electrode penetrating the semiconductor layer,

[0705] A third voltage is applied to a predetermined film formed on the surface of the semiconductor layer on the on-chip lens side through the through electrode.

[0706] (2) Based on the light receiving element described in (1),

[0707] The wiring layer has at least one layer including a reflective component,

[0708] The reflecting member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

[0709] (3) Based on the light receiving element described in (1) or (2),

[0710] The wiring layer has at least one layer including a light shielding member,

[0711] The light shielding member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

[0712] (4) In the light-receiving element described in any one of (1) to (3), the predetermined film is a fixed charge film.

[0713] (5) In the light-receiving element described in any one of (1) to (3), the predetermined film is an insulating film.

[0714] (6) In the light receiving element described in any one of (1) to (5),

[0715] The through-electrode is an inter-pixel through-electrode formed on a pixel boundary portion.

[0716] The third voltage is applied to the predetermined film using the inter-pixel penetration electrode.

[0717] (7) Based on the light receiving element described in (6),

[0718] The upper side of the predetermined film further comprises a transparent conductive film connected to the inter-pixel through-electrode.

[0719] The third voltage is applied to the predetermined film via the transparent conductive film.

[0720] (8) Based on the light receiving element described in (6),

[0721] The semiconductor layer further includes an inter-pixel light shielding film connected to the inter-pixel through-electrode on a surface of the pixel boundary portion on the on-chip lens side.

[0722] The third voltage is applied to the predetermined film via the inter-pixel light shielding film.

[0723] (9) In the light receiving element described in any one of (1) to (8),

[0724] The through electrode is formed on the outer peripheral portion of the pixel array portion.

[0725] The third voltage is applied to the predetermined film from the penetrating electrode in the outer peripheral portion.

[0726] (10) Based on the light receiving element described in (9),

[0727] A transparent conductive film is further provided on the upper side of the predetermined film.

[0728] The transparent conductive film is connected to the through electrode in the peripheral portion.

[0729] The third voltage is applied to the predetermined film via the transparent conductive film.

[0730] (11) Based on the light receiving element described in (9),

[0731] The semiconductor layer further includes an inter-pixel light shielding film on the surface of the pixel boundary portion on the on-chip lens side.

[0732] The through electrode in the peripheral portion is connected to the inter-pixel light shielding film,

[0733] The third voltage is applied to the predetermined film via the inter-pixel light shielding film.

[0734] (12) In the light receiving element described in any one of (1) to (11),

[0735] The through electrodes include an inter-pixel through electrode formed on a pixel boundary portion and a peripheral through electrode formed on an outer peripheral portion outside a pixel array portion.

[0736] The third voltage is applied to the predetermined film using both the inter-pixel through-electrode and the peripheral through-electrode.

[0737] (13) In the light-receiving element described in any one of (1) to (12), the third voltage is a voltage lower than a voltage applied to the passive tap.

[0738] (14) In the light-receiving element described in any one of (1) to (13), the third voltage is a negative voltage.

[0739] (15) In the light-receiving element described in any one of (1) to (14), the through-electrode is formed of polysilicon or a metal material.

[0740] (16) In the light-receiving element described in any one of (1) to (15), the first voltage applying portion and the second voltage applying portion are respectively composed of a first P-type semiconductor region and a second P-type semiconductor region formed on the semiconductor layer.

[0741] (17) In the light receiving element described in any one of (1) to (15), the first voltage applying section and the second voltage applying section are respectively composed of a first transfer transistor and a second transfer transistor formed on the semiconductor layer.

[0742] (18) A distance measurement module, comprising:

[0743] Light receiving element;

[0744] a light source that emits illumination light whose brightness varies periodically; and

[0745] a light emission control unit for controlling the irradiation timing of the irradiation light,

[0746] Wherein, the light receiving element includes:

[0747] On-chip lens;

[0748] wiring layer; and

[0749] a semiconductor layer disposed between the on-chip lens and the wiring layer,

[0750] The semiconductor layer includes:

[0751] a first voltage applying portion to which a first voltage is applied;

[0752] a second voltage applying unit to which a second voltage different from the first voltage is applied;

[0753] a first charge detection unit disposed around the first voltage applying unit;

[0754] a second charge detection unit disposed around the second voltage applying unit; and

[0755] a through electrode penetrating the semiconductor layer,

[0756] A third voltage is applied to a predetermined film formed on the surface of the semiconductor layer on the on-chip lens side through the through electrode.

Claims

1. A light receiving element, characterized in that: The light receiving element includes: On-chip lens; wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer, The semiconductor layer includes: a first voltage applying portion to which a first voltage is applied; a second voltage applying unit to which a second voltage different from the first voltage is applied; a first charge detection unit disposed around the first voltage applying unit; a second charge detection unit disposed around the second voltage applying unit; and a through electrode penetrating the semiconductor layer, A predetermined film is formed on the surface of the semiconductor layer on the on-chip lens side, and a transparent conductive film is further provided on the predetermined film. A third voltage is applied to the predetermined film formed on the surface of the semiconductor layer on the on-chip lens side through the through electrode and the transparent conductive film.

2. The light receiving element according to claim 1, wherein The wiring layer has at least one layer including a reflective component, The reflecting member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

3. The light receiving element according to claim 1, wherein The wiring layer has at least one layer including a light shielding member, The light shielding member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

4. The light receiving element according to claim 1, wherein The prescribed film is a fixed charge film.

5. The light receiving element according to claim 1, wherein The predetermined film is an insulating film.

6. The light receiving element according to claim 1, wherein The through-electrode is an inter-pixel through-electrode formed on a pixel boundary portion. The third voltage is applied to the predetermined film using the inter-pixel penetration electrode.

7. The light receiving element according to claim 6, wherein The semiconductor layer further includes an inter-pixel light shielding film connected to the inter-pixel through-electrode on a surface of the pixel boundary portion on the on-chip lens side. The third voltage is applied to the predetermined film via the inter-pixel light shielding film.

8. The light receiving element according to claim 1, wherein The through electrode is formed on the outer peripheral portion of the pixel array portion. The third voltage is applied to the predetermined film from the penetrating electrode in the outer peripheral portion.

9. The light receiving element according to claim 8, wherein The semiconductor layer further includes an inter-pixel light shielding film on the surface of the pixel boundary portion on the on-chip lens side. The through electrode in the peripheral portion is connected to the inter-pixel light shielding film, The third voltage is applied to the predetermined film via the inter-pixel light shielding film.

10. The light receiving element according to claim 1, wherein The through electrodes include an inter-pixel through electrode formed on a pixel boundary portion and a peripheral through electrode formed on an outer peripheral portion outside a pixel array portion. The third voltage is applied to the predetermined film using both the inter-pixel through-electrode and the peripheral through-electrode.

11. The light receiving element according to claim 1, wherein The third voltage is a voltage lower than a voltage applied to the passive tap.

12. The light receiving element according to claim 1, wherein The third voltage is a negative voltage.

13. The light receiving element according to claim 1, wherein The through-electrode is formed of polysilicon or metal material.

14. The light receiving element according to claim 1, wherein The first voltage applying section and the second voltage applying section are respectively formed of a first P-type semiconductor region and a second P-type semiconductor region formed on the semiconductor layer.

15. The light receiving element according to claim 1, wherein The first voltage applying section and the second voltage applying section are respectively constituted by a first transfer transistor and a second transfer transistor formed on the semiconductor layer.

16. A ranging module, characterized in that: The ranging module includes: Light receiving element; a light source that emits illumination light whose brightness varies periodically; and a light emission control unit for controlling the irradiation timing of the irradiation light, Wherein, the light receiving element includes: On-chip lens; wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer, The semiconductor layer includes: a first voltage applying portion to which a first voltage is applied; a second voltage applying unit to which a second voltage different from the first voltage is applied; a first charge detection unit disposed around the first voltage applying unit; a second charge detection unit disposed around the second voltage applying unit; and a through electrode penetrating the semiconductor layer, A predetermined film is formed on the surface of the semiconductor layer on the on-chip lens side, and a transparent conductive film is further provided on the predetermined film. A third voltage is applied to the predetermined film formed on the surface of the semiconductor layer on the on-chip lens side through the through electrode and the transparent conductive film.

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