Semiconductor device

Abstract

A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode extending in a second direction and crossing the active fin, a gate spacer on both sidewalls of the gate electrode, and a source / drain region in a recessed region of the active fin at least one side of the gate electrode. The source / drain region can include a base layer in contact with the active fin and having inner and outer ends on inner sidewalls of the recessed region opposite each other in the first direction. The source / drain region can include a first layer on the base layer. The first layer can include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer can be in contact with the first layer and can have a shape convex toward an outside of the gate electrode in a plane.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0085563, filed on July 23, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices. Background Technology

[0004] With increasing demands for high performance, high speed, and / or versatility in semiconductor devices, the integration density of semiconductor devices has increased. When manufacturing semiconductor devices corresponding to this trend of high integration, the devices may include patterns with fine widths or fine spacing. Furthermore, to address the operational characteristics resulting from the reduction in size of planar metal-oxide-semiconductor FETs (MOSFETs), semiconductor devices including FinFETs with channels having a three-dimensional structure have been developed. Summary of the Invention

[0005] One aspect of the present invention is to provide a semiconductor device with improved electrical characteristics.

[0006] According to one aspect of the present invention, a semiconductor device includes: a substrate; an active fin on the substrate, the active fin extending along a first direction, the active fin including a recessed region; a gate electrode on the substrate, the gate electrode intersecting the active fin such that the recessed region of the active fin is located on at least one side of the gate electrode, the gate electrode extending along a second direction, the gate electrode including a sidewall; a gate spacer layer on the sidewall of the gate electrode; and a source / drain region located in the recessed region of the active fin. The source / drain region may include a base layer in contact with the active fin and a first layer on the base layer. The base layer may include an inner end and an outer end opposite to each other in the first direction. The base layer may be located on the inner sidewall of the recessed region. The first layer may include germanium (Ge) at a concentration higher than that of germanium (Ge) included in the base layer, and the outer end of the base layer may be in contact with the first layer. The outer end of the base layer may have a shape that protrudes outward in a plane toward the outside of the gate electrode.

[0007] According to one aspect of the present invention, a semiconductor device includes: a substrate; an active fin on the substrate extending in one direction, the active fin including a recessed region; a gate electrode on the substrate extending and intersecting the active fin such that the recessed region of the active fin is located on at least one side of the gate electrode; and a source / drain region located in the recessed region of the active fin. The source / drain region may include a first layer and a second layer of germanium (Ge) with different concentrations. An end of the first layer may have a region protruding outward in a plane toward the gate electrode, and at the end of the first layer, the first layer may contact a second layer located on the inner sidewall of the recessed region.

[0008] According to one aspect of the present invention, a semiconductor device includes: a substrate; an active fin on the substrate extending in one direction, the active fin including a recessed region; a gate electrode on the substrate extending and intersecting the active fin such that the recessed region of the active fin is located on at least one side of the gate electrode; and an epitaxial layer in the recessed region of the active fin. At least one of the end of the active fin and the end of the epitaxial layer may have a region protruding outward in a plane toward the gate electrode. The end of the active fin may be defined by the recessed region in at least one side of the gate electrode. Attached Figure Description

[0009] The above and other aspects, features, and effects of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0011] Figures 2A to 2D This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0012] Figure 3 This is a partially enlarged plan view of a semiconductor device according to an example embodiment;

[0013] Figure 4A and Figure 4B This is a cross-sectional view showing a portion of a semiconductor device according to an example embodiment;

[0014] Figures 5A to 6B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment;

[0015] Figure 7A and Figure 7B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment;

[0016] Figure 8 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0017] Figure 9A and Figure 9B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment;

[0018] Figure 10A and Figure 10B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment;

[0019] Figures 11A to 20B This is a diagram illustrating the process sequence of a method for manufacturing a semiconductor device according to an example embodiment;

[0020] Figures 21A to 23B This is a diagram illustrating the process sequence of a method for manufacturing a semiconductor device according to an example embodiment;

[0021] Figure 24 It is a circuit diagram including an SRAM cell of a semiconductor device according to an example embodiment;

[0022] Figure 25 This is a block diagram illustrating an electronic device including a semiconductor device according to an example embodiment; and

[0023] Figure 26 This is a schematic diagram of a system including a semiconductor device according to an example embodiment. Detailed Implementation

[0024] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0026] Figures 2A to 2D This is a cross-sectional view of a semiconductor device according to an example embodiment. Figures 2A to 2D The diagram shows the sections intercepted along lines IIa-IIa', IIb-IIb', IIc-IIc', and IId-IId'. Figure 1 A cross-section of a semiconductor device. For ease of illustration, in Figures 1 to 2D Only some components of the semiconductor device are shown in the image.

[0027] refer to Figures 1 to 2DSemiconductor device 100 may include a substrate 101, active fins 105, a device isolation layer 110, source / drain regions 150, a gate structure 160, and an interlayer insulating layer 190. Gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, and a gate spacer layer 166. Semiconductor device 100 may include a FinFET element—a transistor in which the active fins 105 have fin structures. The FinFET element may include intersecting transistors arranged based on the positions of the active fins 105 and the gate structure 160. For example, the transistor may be a PMOS transistor.

[0028] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0029] Component isolation layer 110 may define active fins 105 within substrate 101. Component isolation layer 110 may be formed using, for example, a shallow trench isolation (STI) process. According to an example embodiment, component isolation layer 110 may include a region extending deeper into the substrate 101 between the active fins 105. Component isolation layer 110 may have a curved upper surface that becomes higher towards the active fins 105; however, the shape of the upper surface of component isolation layer 110 is not limited thereto. Component isolation layer 110 may be formed of an insulating material. Component isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0030] Active fin 105 may be defined in substrate 101 by device isolation layer 110 and may extend in a first direction (e.g., the X direction). Active fin 105 may have a structure that protrudes from substrate 101. The upper end of active fin 105 may protrude from the upper surface of device isolation layer 110 by a desired (and / or alternatively, predetermined) amount. Active fin 105 may be formed on a portion of substrate 101 and may include an epitaxial layer grown from substrate 101. Simultaneously, a portion of active fin 105 on substrate 101 may be recessed on both sides of gate structure 160, and source / drain regions 150 may be disposed on the recessed active fin 105. Therefore, by comparison... Figure 2C and Figure 2D As can be seen, the active fin 105 can have a relatively high height below the gate structure 160. According to the example embodiment, the active fin 105 may include impurities.

[0031] Source / drain regions 150 may be disposed on recessed regions RC located on both sides of the gate structure 160 and / or adjacent to both sides of the gate structure 160, wherein each has a source fin 105 recessed in the recessed region RC. The recessed regions RC extend in the X direction between the gate structures 160 and may have inner sidewalls located at both ends in the X direction and a bottom surface located between the inner sidewalls. The source / drain regions 150 may be provided as source regions or drain regions of a transistor. The upper surface of the source / drain regions 150 may be located at the same or similar height level as the lower surface of the gate structure 160, such as... Figure 2A As shown. Meanwhile, according to the example embodiment, the relative heights of the source / drain region 150 and the gate structure 160 can be varied. For example, the source / drain region 150 can have an elevated source / drain form, wherein the upper surface is located higher than the lower surface of the gate structure 160 (specifically, the gate electrode 165).

[0032] like Figure 2D As shown, the source / drain region 150 can have a pentagonal or similar cross-section cut in the Y direction. Meanwhile, in the example embodiment, the source / drain region 150 can have various shapes, such as polygons, circles, and rectangles. Furthermore, the source / drain region 150 can have a cross-section cut in the X direction with a flat upper surface, such as... Figure 2A As shown, the upper surface may have a circular, elliptical, or similar shape. Furthermore, in the example embodiment, the shape can be varied depending on factors such as the distance between adjacent gate structures 160 and the height of the active fin 105.

[0033] The source / drain region 150 may include a base layer 151 and first to fifth layers 152, 153, 154, 155, and 156 sequentially stacked in the recessed region RC. The base layer 151 and the first to fifth layers 152, 153, 154, 155, and 156 may include silicon (Si) and may contain germanium (Ge) of different concentrations. Furthermore, in the example embodiment, the number of layers forming the source / drain region 150 may be varied.

[0034] For example, the base layer 151 may be formed solely of silicon (Si), or may also include germanium (Ge). When the base layer 151 includes germanium (Ge), the concentration of germanium (Ge) may be lower than the concentration of germanium (Ge) in each of the first to fifth layers 152, 153, 154, 155, and 156, but higher than the concentration of germanium (Ge) in the active fin 105. For example, the concentration of germanium (Ge) in the base layer 151 may be equal to or less than 20 at.%. In this specification, the concentration of germanium (Ge) refers to atomic concentration (atomic percentage). The base layer 151 may also include dopant elements such as boron (B) or gallium (Ga). In this case, the concentration of the dopant element may be lower than the concentration of the dopant element in each of the first to fifth layers 152, 153, 154, 155, and 156, but higher than the concentration of the dopant element in the active fin 105.

[0035] In the first to fourth layers 152, 153, 154, and 155, the concentration of germanium (Ge) can be increased. The first layer 152 includes germanium (Ge) with a first concentration, the second layer 153 includes germanium (Ge) with a second concentration higher than the first concentration, the third layer 154 includes germanium (Ge) with a third concentration higher than the second concentration, and the fourth layer 155 may include germanium (Ge) with a fourth concentration higher than the third concentration. For example, the first concentration is in the range of 20 at.% to 40 at.%, the second concentration is in the range of 35 at.% to 55 at.%, the third concentration is in the range of 45 at.% to 65 at.%, and the fourth concentration is in the range of 50 at.% to 70 at.%. Furthermore, in the first to fourth layers 152, 153, 154, and 155, the concentration of doping elements such as boron (B) or gallium (Ga) can also be increased. The fifth layer 156 may include germanium (Ge) at a concentration lower than that in the fourth layer 155, or may not include germanium (Ge). For example, according to an exemplary embodiment, the fifth layer 156 may be formed of silicon (Si) and may also include impurities other than silicon (Si).

[0036] The base layer 151 and the first to fifth layers 152, 153, 154, 155 and 156 can have the same thickness or different thicknesses. For example, the base layer 151 and the fifth layer 156 can have relatively thin thicknesses, while the third layer 154 can be formed to be relatively thick. The base layer 151 can have a thickness in the range of, for example, 3 nm to 5 nm.

[0037] At least one region of the base layer 151 is located below the gate electrode 165, and at least one region of the first layer 152 may be located below the gate spacer layer 166. In a plane, the base layer 151 may have a region protruding outward from the gate electrode 165. This will be referred to below. Figures 3 to 4B To describe in more detail.

[0038] The gate structure 160 may be disposed above the active fin 105 and extend in one direction (e.g., the Y direction) while intersecting the active fin 105. The channel region of the transistor may be disposed in the active fin 105 and intersect the gate structure 160. The gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, and a gate spacer layer 166.

[0039] A gate dielectric layer 162 may be disposed between the active fin 105 and the gate electrode 165, and may be configured to cover the lower surface and two side surfaces of the gate electrode 165. Alternatively, in some example embodiments, the gate dielectric layer 162 may be formed only on the lower surface of the gate electrode 165. The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. A high-k material may refer to a dielectric material whose dielectric constant is higher than that of a silicon oxide (SiO2) film. High-k materials may be provided as alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y One of praseodymium oxide (Pr2O3) and praseodymium oxide (Pr2O3).

[0040] The gate electrode 165 may include a conductive material, and may include, for example, a metal nitride (e.g., a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film), and / or a metallic material (e.g., aluminum (Al), tungsten (W), molybdenum (Mo), etc.), or a semiconductor material (e.g., doped polycrystalline silicon). The gate electrode 165 may include a multilayer structure such as two or more layers. According to an example embodiment, a capping layer may also be provided above the gate electrode 165, and the lower surface and side surfaces of the capping layer may be surrounded by the gate electrode 165 and the gate spacer layer 166, respectively.

[0041] A gate spacer layer 166 may be disposed on both side surfaces of the gate electrode 165. The gate spacer layer 166 may allow the source / drain regions 150 to be isolated from the gate electrode 165. According to an example embodiment, the gate spacer layer 166 may have a multilayer structure. The gate spacer layer 166 may be formed of at least one of oxides, nitrides, and oxide oxynitrides, specifically, of a low-k film.

[0042] Interlayer insulating layer 190 may be configured to cover the upper surface of element isolation layer 110, source / drain region 150, and gate structure 160. Interlayer insulating layer 190 may include at least one of, for example, oxide, nitride, and oxynitride, and may include a low-k material. The material of interlayer insulating layer 190 may be different from the material of gate spacer layer 160.

[0043] Figure 3 This is a partially enlarged plan view illustrating a semiconductor device according to an example embodiment. Figure 3 In the middle, it is enlarged and shown Figure 1 The “C” area.

[0044] Figure 4A and Figure 4B This is a cross-sectional view showing a portion of a semiconductor device according to an example embodiment. Figure 4A and Figure 4B The figures taken along lines A-A' and B-B' are shown respectively. Figure 3 The cross-section of a semiconductor device.

[0045] First, refer to Figure 3 The diagram shows an active fin 105, a source / drain region 150 disposed in a recessed region RC of the active fin 105, and a gate structure 160. More specifically, in... Figure 3 The image shows in detail the planar arrangement of the base layer 151 forming the source / drain region 150 and the first to fifth layers 152, 153, 154, 155 and 156.

[0046] The recessed region RC of the active fin 105 is formed to extend downward from the gate structure 160 between the gate structures 160, and the end of the recessed region RC in the X direction may be located below the gate structure 160. The end of the recessed region RC may have a shape that is recessed outward from the gate structure 160. In other words, the end of the recessed region RC may have a shape in which the width increases from the lower part of the gate structure 160 toward the side surface or sidewall of the gate structure 160.

[0047] The base layer 151 is disposed at the lowest part of the recessed region RC and can be configured to contact the inner sidewall and bottom surface of the recessed region RC. Therefore, the inner end 151E1 of the base layer 151 can have a shape that is recessed outward in a manner similar to the end of the recessed region RC. In this specification, in the description of the source / drain region 150, "end" is used as a term referring to a point on the inner sidewall of the recessed region RC that contacts other vertical layers. Furthermore, in the description of the end, based on the center of the gate structure 160 or gate electrode 165 in the X direction, the portion closer to the center is referred to as "inner side," and the portion farther from the center is referred to as "outer side." The outer end 151E2 of the base layer 151 can have a shape that protrudes outward from the gate structure 160 or gate electrode 165. According to an example embodiment, a portion of the outer end 151E2 of the base layer 151 can coincide with the crystal plane of the active fin 105. However, even in this case, the surface grown from the substrate 151 along the X direction may not be formed by a facet formed along a crystal plane, and the facet may at least have a relaxed form. For example, when the upper surface of the substrate 101 or the active fin 105 is <100> In the direction, the base layer 151 can not only be formed by the corresponding X direction. <110> The formation of cross-sections such as {111} in the direction.

[0048] The first layer 152 can be disposed on the base layer 151, and the inner end 152E1 of the first layer 152 can be substantially the same as the outer end 151E2 of the base layer 151. Therefore, the inner end 152E1 of the first layer 152 can have a shape that protrudes outward from the gate structure 160 or the gate electrode 165. The outer end 152E2 of the first layer 152 can also have a shape that protrudes outward from the gate structure 160 or the gate electrode 165, and the surface in the X direction can be not formed by a cross-section. The first layer 152 is formed on the base layer 151 without a cross-section, and therefore can be without a cross-section. Therefore, the uniformity of thickness in the recessed region RC can be improved. At least a portion of the base layer 151 and the first layer 152 can be disposed in a plane below the gate spacer layer 166.

[0049] The second layer 153 can be disposed on the first layer 152 and can have an outer end protruding toward the outer region of the gate electrode 165. However, the position of the outer end is not limited thereto. The width of the second layer 153 in the Y direction can be similar to or greater than the width of the first layer 152. The third to fifth layers 154, 155 and 156 can be disposed sequentially on the second layer 153, and in the example embodiment, the relative positional relationship of the second to fifth layers 153, 154, 155 and 156 can be varied differently.

[0050] refer to Figure 4A and Figure 4B In the inner end 151E1 of the base layer 151, Figure 4A The outermost portion EC closest to the center of the gate electrode 165 in the X direction, as shown, can be located below the gate electrode 165. Furthermore, at least a portion of the first layer 152 can be located below the gate spacer layer 166. On the inner sidewalls of the recessed region RC, the inner ends 151E1 of the base layer 151 and the inner ends 152E1 of the first layer 152 can have regions extending perpendicular to the upper surface of the substrate 101. Alternatively, on the inner sidewalls of the recessed region RC, the inner surfaces of the base layer 151 and the first layer 152 can have regions extending perpendicular to the upper surface of the substrate 101.

[0051] Figure 4A The length L1 of the active fin 105 shown at its center in the Y direction can be shorter than Figure 4B The length L2 of the active fin 105 at the edge is shown. The spacing D1 between the side surface of the gate electrode 165 and the outermost portion EC of the substrate 151 at the center of the active fin 105 in the Y direction, located between the source / drain regions 150, can be greater than the spacing D2 at the edge. Furthermore, Figure 3 and Figure 4A The length L3 at the center of the active fin 105 in the Y direction between the outer ends 151E2 of the two base layers 151 on both sides of the gate electrode 165, as shown, can be greater than Figure 3 and Figure 4B The length L4 at the edge between the outer ends 151E2 is shown.

[0052] At least a portion of the second to fifth layers 153, 154, 155, and 156 may be located below the gate spacer layer 166, but is not limited thereto. The base layer 151 and each of the first layer 152 and the second layer 153 may have a uniform thickness in the recessed region RC, or may have different thicknesses depending on the region. The third layer 154 may have a relatively thick thickness compared to the other layers. The fourth layer 155 and the fifth layer 156 may be disposed in the region adjacent to the upper surface of the source / drain region 150, and may have a relatively thin thickness compared to the other layers.

[0053] The first layer 152 does not have a cross-section. Therefore, the upper layer including the second layer 153 formed above the first layer 152 can have improved thickness uniformity compared to the case where it is formed above a cross-section. When the first layer 152 has a cross-section, the second layer 153 may be formed relatively thick on the bottom surface of the recessed region RC. However, according to the example embodiment, the thickness of the second layer 153 on the sidewall of the active fin 105 may not be significantly different from the thickness on the bottom surface of the recessed region RC, and can be substantially uniform.

[0054] The first to third layers 152, 153, and 154 can be used to apply stress to the channel region of the transistor. Therefore, according to the example embodiment, the layers including the first layer 152 and the second layer 153 are formed to have a uniform thickness, and the inner surfaces of the base layer 151 and the first layer 152 have regions perpendicular to the upper surface of the substrate 101. Therefore, stress is uniformly transmitted to the channel region, thereby improving the electrical characteristics of the semiconductor device, such as the resistance of the channel region, drain-induced barrier reduction (DIBL) characteristics, etc. Furthermore, compared to the case where it is formed above a cross-section, for example, the volume of the third layer 154 can be relatively increased. When the third layer 154 is used as the main layer for applying stress to the channel region, if the volume of the third layer 154 is increased, the stress can be sufficiently applied to the channel region.

[0055] Figures 5A to 6B These are plan views and cross-sectional views illustrating a semiconductor device according to an example embodiment. Figures 5A to 6B In the middle, it is shown that... Figure 3 and Figure 4A The corresponding region in the text.

[0056] refer to Figure 5A and Figure 5B In the source / drain region 150a of the semiconductor device 100a, the outermost portion EC of the base layer 151 may be located below or outside the interface between the gate electrode 165 and the gate dielectric layer 162. For example, the outermost portion EC of the base layer 151 may be located below the gate dielectric layer 162. At least a portion of the first layer 152 may be located below the gate spacer layer 166. At least a portion of the second to fifth layers 153, 154, 155, and 156 may be located below the gate spacer layer 166, but is not limited thereto. In an example embodiment, the third to fifth layers 154, 155, and 156 may not be located below the gate spacer layer 166.

[0057] refer to Figure 6A and Figure 6B In the source / drain region 150b of the semiconductor device 100b, the first layer 152 may include a region located outside the lower portion of the gate spacer layer 166 on the sidewall of the active fin 105. In other words, in the plane, the outer end 152E2 of the first layer 152 may be located externally compared to the gate spacer layer 166. Therefore, the second to fifth layers 153, 154, 155, and 156 may not be located below the gate spacer layer 166 on the sidewall of the active fin 105.

[0058] With reference Figures 5A to 6B In a similar manner to that described above, in the example embodiment, the positions of the inner end 151E1 of the base layer 151, the inner end 152E1 and the outer end 152E2 of the first layer 152 can be changed differently.

[0059] Figure 7A and Figure 7B These are plan views and cross-sectional views illustrating a semiconductor device according to an example embodiment. Figure 7A and Figure 7B In the middle, it is shown that... Figure 3 and Figure 4A The corresponding region in the text.

[0060] refer to Figure 7A and Figure 7B , in order to Figures 1 to 4B In a different manner from the example embodiments, the source / drain region 150c of the semiconductor device 100c may not include the base layer 151. The source / drain region 150c may be formed by the first to fifth layers 152, 153, 154, 155, and 156. Furthermore, the end of the recessed region RCa of the active fin 105 may have a shape that protrudes outward from the gate structure 160 in a plane. In other words, the end of the recessed region RCa may have a shape in which the width decreases toward the sidewalls of the gate structure 160. As described above, when the end of the recessed region RCa has a shape that protrudes outward from the gate structure 160, the electrical characteristics of the semiconductor device 100c can be ensured even if the source / drain region 150c does not include the base layer 151.

[0061] The first layer 152 may be disposed in the recessed region RCa to contact the active fin 105. At least a portion of the first layer 152 may be located below the gate spacer layer 166. However, the location of the first layer 152 is not limited thereto. For example, in an exemplary embodiment, the first layer 152 may be located below the gate electrode 165. The inner end 152E1 and the outer end 152E2 of the first layer 152 may have a shape that protrudes outward from the gate structure 160 or the gate electrode 165. The end of the second layer 153 may have an outwardly protruding shape.

[0062] Figure 8 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 8 In the middle, it is shown that... Figure 3 The region corresponding to the region in the text.

[0063] refer to Figure 8 , in order to Figures 1 to 4BIn a different manner from the example embodiments, the source / drain region 150d of the semiconductor device 100d may not include the base layer 151. The source / drain region 150d may be formed by the first to fifth layers 152, 153, 154, 155, and 156. Furthermore, the end of the recessed region RCb of the active fin 105 may have a shape that is substantially parallel to the sidewall of the gate structure 160 in the plane. As described above, when the end of the recessed region RCb has a shape that extends flat in the Y direction of the gate structure 160, the electrical characteristics of the semiconductor device 100d can be ensured even if the source / drain region 150d does not include the base layer 151.

[0064] The first layer 152 may be disposed in the recessed region RCb to contact the active fin 105. At least a portion of the first layer 152 may be located below the gate spacer layer 166. However, the location of the first layer 152 is not limited thereto. For example, in an exemplary embodiment, the first layer 152 may be located below the gate electrode 165. The inner end 152E1 of the first layer 152 may have a linear shape that is generally parallel to the sidewall of the gate structure 160. The outer end 152E2 of the first layer 152 may have a shape that protrudes outward from the gate structure 160 or the gate electrode 165. However, according to an exemplary embodiment, the outer end 152E2 of the first layer 152 may have a linear shape that is generally parallel to the sidewall of the gate structure 160.

[0065] Figure 9A and Figure 9B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment. Figure 9B The diagram shows the sections taken along lines IId1-IId1' and IId2-IId2'. Figure 9A The cross-section of a semiconductor device.

[0066] refer to Figure 9A and Figure 9B The semiconductor device 100e may include a substrate 101 having a first region I and a second region II, a first active fin 105A and a second active fin 105B, a device isolation layer 110, a first source / drain region 150A and a second source / drain region 150B, a gate structure 160, and an interlayer insulating layer 190. In the semiconductor device 100e, a PMOS transistor may be disposed in the first region I, and an NMOS transistor may be disposed in the second region II.

[0067] The first active fin 105A and the second active fin 105B can be respectively disposed in the first region I and the second region II, and can include impurities with different conductivity types. According to an example embodiment, the gate structure 160 can have different structures in the first region I and the second region II. For example, the material and work function of the gate electrode 165 can be different.

[0068] The first source / drain region 150A and the second source / drain region 150B can be respectively disposed in the first region I and the second region II. The first source / drain region 150A and the second source / drain region 150B can be formed of semiconductor materials with different conductivity types. For example, the first source / drain region 150A may include silicon-germanium (SiGe) doped with p-type impurities, while the second source / drain region 150B may include silicon (Si) doped with n-type impurities. The second source / drain region 150B may not include germanium (Ge). (Refer to Figure 2 to...) Figure 4B The description of the source / drain region 150 is similarly applied to the first source / drain region 150A. The second source / drain region 150B may be formed from a single layer or may include multiple regions comprising doped elements of different concentrations.

[0069] like Figure 9B As shown, the first source / drain region 150A and the second source / drain region 150B can have different cross-sectional shapes. For example, the first source / drain region 150A can have a pentagonal or similar shape, while the second source / drain region 150B can have a hexagonal or similar shape.

[0070] Figure 10A and Figure 10B These are plan views and cross-sectional views of a semiconductor device according to an example embodiment. Figure 10B The cut-off along line IId-IId' is shown. Figure 10A The cross-section of a semiconductor device.

[0071] refer to Figure 10A and Figure 10B In the semiconductor device 100f, the source / drain regions 150f can be connected or merged on two active fins 105 to form a single source / drain region 150f. However, the number of active fins 105 disposed below the single source / drain region 150f connected as described above is not limited to the number shown in the figure, and can be varied differently in the example embodiment.

[0072] For example, in the source / drain region 150f, the base layer 151, the first layer 152, and the second layer 153 can be disposed on each active fin 105, and the third to fifth layers 154, 155, and 156 can be connected to each of the two active fins 105. Therefore, the planar arrangement of the base layer 151, the first layer 152, and the second layer 153 can be consistent with... Figures 1 to 4B The floor plan arrangement is the same as in the example embodiment.

[0073] Figures 11A to 20BThis is a diagram illustrating the process sequence of a method for manufacturing a semiconductor device according to an example embodiment. Figures 11A to 20B The description will be used to manufacture the above reference. Figures 1 to 2D Methods for describing semiconductor devices.

[0074] refer to Figure 11A and Figure 11B The substrate 101 is patterned to form active fins 105 and device isolation layer 110.

[0075] First, a mask layer for patterning the substrate 101 is formed on the substrate 101, and the substrate 101 is anisotropically etched using the mask layer to form trenches TI. The trenches TI can be formed in regions other than the active fins 105. The trenches TI have a high aspect ratio and therefore can have a width that narrows downwards. Therefore, the active fins 105 can have a shape that narrows upwards.

[0076] Then, the trench TI can be filled with insulating material and planarized. The insulating material filling the trench TI is then partially removed, allowing the active fin 105 to protrude from the device isolation layer 110. This operation can be performed using, for example, a wet etching process. Therefore, the active fin 105 can protrude from the upper portion of the device isolation layer 110 to a desired (and / or alternatively, predetermined) height, and the protrusion height can be varied differently in the example embodiment.

[0077] refer to Figure 12A and Figure 12B A sacrificial gate structure 170 can be formed in the active fin 105 and the element isolation layer 110.

[0078] The sacrificial gate structure 170 may be formed by setting it through subsequent operations, such as Figure 1 The sacrificial layer is shown in the region of the gate dielectric layer 162 and the gate electrode 165. The sacrificial gate structure 170 can be patterned to have the shape of a line extending in the Y direction while intersecting with the active fin 105.

[0079] The sacrificial gate structure 170 may include a first sacrificial layer 172 and a second sacrificial layer 174, and a mask patterning layer 176, stacked sequentially. The mask patterning layer 176 may be a hard mask layer remaining after the first sacrificial layer 172 and the second sacrificial layer 174 have been patterned. The first sacrificial layer 172 and the mask patterning layer 176 may be insulating layers, while the second sacrificial layer 174 may be a conductive layer, but the example embodiment is not limited thereto. For example, the first sacrificial layer 172 may include silicon oxide, the second sacrificial layer 174 may include polysilicon, and the mask patterning layer 176 may include silicon nitride. According to the example embodiment, the number of layers forming the sacrificial gate structure 170 and the materials of the layers may be varied.

[0080] refer to Figure 13A and Figure 13B A gate spacer layer 166 can be formed on the side surface of the sacrificial gate structure 170.

[0081] Spacer forming material is deposited to a uniform thickness along the upper and / or side surfaces of the active fin 105, the element isolation layer 110, and the sacrificial gate structure 170, and then the spacer forming material can be anisotropically etched to form the gate spacer layer 166.

[0082] The gate spacer layer 166 may be formed of an insulating material. For example, the gate spacer layer 166 may be formed of a low dielectric constant material and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In an example embodiment, the gate spacer layer 166 may have a structure in which multiple films are stacked. During the formation of the gate spacer layer 166, spacers may also be formed on the side surface of the active fin 105.

[0083] refer to Figure 14A and Figure 14B Active fins 105 are recessed between the sacrificial gate structures 170 to form recessed regions RC.

[0084] The exposed active fins 105 are recessed from their upper surfaces to a desired (and / or alternatively, predetermined) depth between the sacrificial gate structures 170 to form recessed regions RC. For example, the recess process can be performed by sequentially applying dry etching and wet etching processes. Therefore, the active fins 105 can have a lower level between the sacrificial gate structures 170 compared to the level of the active fins 105 below the sacrificial gate structures 170.

[0085] The recessed region RC may extend toward the lower portion of the gate spacer layer 166 and the sacrificial gate structure 170. Therefore, the recessed region RC may be formed above the extended region in the active fin 105, relative to the space between the gate spacers 166. In the recessed region RC, the ends in the X direction may be planar below the gate spacers 166 and the sacrificial gate structure 170, and may have a shape that is recessed outward from the sacrificial gate structure 170. According to an example embodiment, both ends of the upper surface of the recessed region RC are located below the gate spacers 166 or the sacrificial gate structure 170, and therefore may include undercut regions.

[0086] Optionally, after providing the recessed region RC, a separate operation can be performed to solidify the recessed surface of the active fin 105. Furthermore, an operation to implant impurities into the active fin 105 can be performed before or after the recessing operation. The impurity implantation operation can be performed using the sacrificial gate structure 170 and the gate spacer layer 166 as a mask.

[0087] refer to Figure 15A and Figure 15B The base layer 151 of the source / drain region 150 can be set in the recessed region RC.

[0088] For example, a selective epitaxial growth (SEG) process can be used to grow a substrate 151 from the active fin 105. The substrate 151 can be, for example, a silicon (Si) layer. Alternatively, the substrate 151 can be, for example, a silicon-germanium (SiGe) layer. In this case, the substrate 151 may include germanium (Ge) at a concentration lower than the concentration of germanium (Ge) in the first layer 152 to be formed on the substrate 151. The substrate 151 may also include doping elements such as boron (B), and the concentration of doping elements in the substrate 151 may be higher than the concentration of doping elements in the active fin 105. The doping elements can be doped in situ during the growth of the substrate 151 or implanted separately after growth.

[0089] The base layer 151 can be formed on the entire surface of the recessed region RC, and the outermost portion EC can be located below the sacrificial gate structure 170. Depending on the etching conditions, the distance between the sacrificial gate structures 170, the width of the active fins 105, etc., and the planar shape of the inner end 151E1 at the contact point between the base layer 151 and the active fins 105 on the inner sidewall of the recessed region RC can be varied. However, in this case, the inner end 151E1 can have a shape that is typically recessed outward from the sacrificial gate structure 170. The base layer 151 can have an outer end 151E2 located on the inner sidewall of the recessed region RC, such as... Figure 15A As shown by the dashed line, the outer end 151E2 can have a convex curved shape without a cross-section.

[0090] refer to Figure 16A and Figure 16B A first layer 152 can be formed on the base layer 151 of the source / drain region 150.

[0091] The first layer 152 can be formed using, for example, a SEG process. The first layer 152 can be, for example, a silicon-germanium (SiGe) layer. For example, when the substrate 151 is a silicon-germanium (SiGe) layer, the first layer 152 can include germanium (Ge) at a higher concentration than that in the substrate 151. The first layer 152 can also include doping elements such as boron (B).

[0092] The first layer 152 can be formed on the surface of the base layer 151 in the recessed region RC, and the outermost portion that contacts the base layer 151 in the plane can be located below the gate spacer layer 166. The inner end 152E1 of the first layer 152 can have a shape that generally protrudes outward from the sacrificial gate structure 170. The first layer 152 is formed on the base layer 151 without a cross-section, so even the outer end 152E2 that does not contact the base layer 151 can have a convex shape without a cross-section.

[0093] refer to Figure 17A and Figure 17B Layers 153, 154, 155 and 156 are formed on the first layer 152, thus providing source / drain regions 150.

[0094] Layers 153, 154, 155, and 156 can be formed using, for example, a SEG process. Layers 153, 154, and 155 can be, for example, silicon-germanium (SiGe) layers, while layer 156 can be a silicon (Si) layer. The concentration of germanium (Ge) can be increased sequentially in layers 153, 154, and 155. Layers 153, 154, 155, and 156 can also include doping elements such as boron (B). The concentration of doping elements can be increased sequentially in layers 153, 154, and 155.

[0095] The second layer 153 can be formed on the surface of the first layer 152, and the third layer 154 can be formed relatively thickly to primarily fill the recessed region RC. The fourth layer 155 and the fifth layer 156 can be formed relatively thinly on the surface of the recessed region RC.

[0096] The width of the source / drain region 150 in the Y direction on the plane between the sacrificial gate structure 170 can be greater than the width below the sacrificial gate structure 170, and can have a region with increased width.

[0097] refer to Figure 18A and Figure 18B An interlayer insulating layer 190 is formed over the sacrificial gate structure 170, the gate spacer layer 166, the element isolation layer 110, and the source / drain region 150, and the first sacrificial layer 172 and the second sacrificial layer 174 can be removed therefrom.

[0098] After depositing insulating material to cover the sacrificial gate structure 170, gate spacer layer 166, device isolation layer 110, and source / drain region 150, the upper surface of the second sacrificial layer 174 is exposed by a planarization process, thus providing an interlayer insulating layer 190. Therefore, the mask pattern layer 176 of the sacrificial gate structure 170 can be removed in this operation. The interlayer insulating layer 190 may include at least one of, for example, oxides, nitrides, and oxynitrides, and may include a low-k material.

[0099] Then, the first sacrificial layer 172 and the second sacrificial layer 174 of the sacrificial gate structure 170 are selectively removed relative to the device isolation layer 110 and the active fin 105 located below them, thereby providing an opening GR to expose the device isolation layer 110 and the active fin 105. The removal operation of the first sacrificial layer 172 and the second sacrificial layer 174 can be at least one of a dry etching process and a wet etching process.

[0100] refer to Figure 19A and Figure 19B A gate dielectric layer 162 and a gate electrode 165 are formed in the opening GR, thereby ultimately forming a gate structure 160.

[0101] The gate dielectric layer 162 may be formed substantially conformally along the sidewalls and lower surface of the opening GR. The gate dielectric layer 162 may include an oxide, nitride, or high-k material. A gate electrode 165 may be formed to fill the space within the gate dielectric layer 162. The gate electrode 165 may include a metal or a semiconductor material.

[0102] After the gate dielectric layer 162 and the gate electrode 165 are formed, a planarization process such as chemical mechanical polishing (CMP) can be used to remove the material retained on the interlayer insulating layer 190.

[0103] refer to Figure 20A and Figure 20B The interlayer insulating layer 190 is patterned to form a contact hole, and conductive material can be embedded in the contact hole to form a contact plug 180.

[0104] First, an upper insulating layer 195 can be further formed on the interlayer insulating layer 190 and the gate structure 160. Then, a separate mask layer, such as a photoresist pattern, can be formed, and the interlayer insulating layer 190 and the upper insulating layer 195 are removed from both sides of the gate structure 160, thus providing contact holes. The lower surface of the contact holes can allow at least a portion of the source / drain region 150 to be recessed.

[0105] Then, conductive material is deposited in the contact hole, thus providing a contact plug 180 electrically connected to the source / drain region 150. Before depositing the conductive material, impurities can be injected into the lower portion of the contact hole to reduce contact resistance. Therefore, the impurity concentration in the region adjacent to the lower end of the contact plug 180 can be increased compared to the impurity concentration after the source / drain region 150 is formed. In the example embodiment, the shape and arrangement of the contact plug 180 can be varied.

[0106] Figures 21A to 23B This is a diagram illustrating the process sequence of a method for manufacturing a semiconductor device according to an example embodiment. Figures 21A to 23B The description will be used to manufacture the above reference. Figure 7A and Figure 7B Methods for describing semiconductor devices.

[0107] refer to Figure 21A and Figure 21B Active fins 105 are recessed between the sacrificial gate structures 170 to form recessed regions RCa.

[0108] First, execute the above reference in the same way. Figures 11A to 13B The described operation can therefore provide an active fin 105, a sacrificial gate structure 170, and a gate spacer layer 166.

[0109] The exposed active fin 105 is then recessed from its upper surface between the sacrificial gate structures 170 to a desired (and / or alternatively, predetermined) depth to form a recessed region RCa. For example, a dry etching process and / or a wet etching process can be used to perform the recess process. The recessed region RCa may extend in the active fin 105 toward the lower portion of the gate spacer layer 166 and the sacrificial gate structure 170. In the recessed region RCa, the end in the X direction may be located below the gate spacer layer 166 in the plane and may have a shape that protrudes outward from the sacrificial gate structure 170. However, according to an example embodiment, the position of the end in the X direction in the plane can be changed in the recessed region RCa, and this position may be located below the sacrificial gate structure 170.

[0110] refer to Figure 22A and Figure 22B The first layer 152 of the source / drain region 150 can be set in the recessed region RCa.

[0111] For example, a first layer 152 can be grown from the active fin 105 using a SEG process. The first layer 152 can be, for example, a silicon-germanium (SiGe) layer. The first layer 152 may also include doping elements such as boron (B).

[0112] The first layer 152 can be formed over the entire surface of the recessed region RCa, and the outermost portion EC can be located below the gate spacer layer 166. The inner end 152E1 of the first layer 152 that contacts the active fin 105 can have a shape that generally protrudes outward from the sacrificial gate structure 170 in a planar plane, depending on the shape of the recessed region RCa. The first layer 152 can have an outer end 152E2 located on the inner sidewall of the recessed region RCa (in... Figure 22A (shown by alternating long and short dashed lines), and the outer end 152E2 may have a convex curved shape without a cross-section.

[0113] Reference Figure 23A and Figure 23B Layers 153, 154, 155 and 156 are formed on the first layer 152, thus providing the source / drain region 150c.

[0114] The above reference can be used Figure 17A and Figure 17B A similar process is described to provide the second to fifth layers 153, 154, 155, and 156. Therefore, a source / drain region 150c comprising the first to fifth layers 152, 153, 154, 155, and 156 can be provided.

[0115] Figure 24 It is a circuit diagram including an SRAM cell of a semiconductor device according to an example embodiment.

[0116] refer to Figure 24 In an SRAM device, a single SRAM cell can be formed by a first driving transistor TN1 and a second driving transistor TN2, a first load transistor TP1 and a second load transistor TP2, and a first access transistor TN3 and a second access transistor TN4. In this case, the sources of the first driving transistor TN1 and the second driving transistor TN2 can be connected to the ground voltage line Vss, while the sources of the first load transistor TP1 and the second load transistor TP2 can be connected to the power supply voltage line Vdd.

[0117] A first driving transistor TN1 formed by an NMOS transistor and a first load transistor TP1 formed by a PMOS transistor can form a first inverter, while a second driving transistor TN2 formed by an NMOS transistor and a second load transistor TP2 formed by a PMOS transistor can form a second inverter. According to various example embodiments, at least a portion of the first load transistor TP1 and the second load transistor TP2 may include those referenced above. Figures 1 to 10B The aforementioned semiconductor device.

[0118] The output terminals of the first and second inverters can be connected to the sources of the first access transistor TN3 and the second access transistor TN4. Furthermore, the first and second inverters can be connected to each other with their input and output terminals crossed to form a single latch circuit. Additionally, the drains of the first access transistor TN3 and the second access transistor TN4 can be connected to the first bit line BL and the second bit line / BL.

[0119] Figure 25 This is a block diagram illustrating an electronic device including a semiconductor device according to an example embodiment.

[0120] refer to Figure 25 The electronic device 1000 according to the example embodiment may include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.

[0121] The communication unit 1010 may include a wired / wireless communication module, such as a wireless internet module, a local communication module, a global positioning system (GPS) module, or a mobile communication module. The wired / wireless communication module included in the communication unit 1010 can connect to an external communication network based on various communication standards to send and receive data.

[0122] The input unit 1020 may include mechanical switches, touch screens, voice recognition modules, etc., as modules provided to users for controlling the operation of the electronic device 1000. Furthermore, the input unit 1020 may also include a mouse or a finger mouse device based on a trackball or laser pointer, and may also include various sensor modules that enable users to input data.

[0123] Output unit 1030 can output information processed by electronic device 1000 in audio or video format, and memory 1040 can store programs or data for processing or controlling processor 1050. Output unit 1030 may include at least one of a speaker, antenna, connection structure (e.g., terminal, microUSB, etc.) for outputting information to electronic device. Processor 1050 can send instructions to memory 1040 to store data in or retrieve data from memory 1040 as needed.

[0124] The memory 1040 may be embedded in the electronic device 1000 or may communicate with the processor 1050 via an additional interface. When the memory 1040 communicates with the processor 1050 via the additional interface, the processor 1050 may store data in or retrieve data from the memory 1040 via various interface standards such as Secure Digital (SD), Secure Digital High Capacity (SDHC), Secure Digital Extended Capacity (SDXC), micro SD, Universal Serial Bus (USB), etc.

[0125] Processor 1050 controls the operation of each component included in electronic device 1000. Processor 1050 can perform control and processing associated with voice calls, video calls, data communications, etc., or can perform control and processing for multimedia copying and management. Processor 1050 can also process input from a user via input unit 1020 and output the results via output unit 1030. Furthermore, as described above, processor 1050 can store data required to control the operation of electronic device 1000 in memory 1040 or retrieve such data from memory 1040. At least one of processor 1050 and memory 1040 may include, according to various example embodiments as referenced above. Figures 1 to 10B The aforementioned semiconductor device.

[0126] Figure 26 This is a schematic diagram of a system including a semiconductor device according to an example embodiment.

[0127] refer to Figure 26 System 2000 may include controller 2100, input / output (I / O) device 2200, memory 2300, and interface 2400. System 2000 may be a mobile system or a system for sending or receiving information. A mobile system may be a personal digital assistant (PDA), portable computer, tablet computer, cordless phone, mobile phone, digital music player, memory card, etc.

[0128] The controller 2100 can be used to execute programs and control the system 2000. The controller 2100 can be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0129] I / O device 2200 can be used to input or output data to system 2000. System 2000 can use I / O device 2200 to connect to external devices (such as personal computers or networks) to communicate data with external devices. I / O device 2200 can be, for example, buttons, keyboard, or display.

[0130] The memory 2300 may store code and / or data for the operation of the controller 2100, and / or may store data processed by the controller 2100.

[0131] Interface 2400 can serve as a data transmission path between system 2000 and other external devices. Controller 2100, I / O device 2200, memory 2300, and interface 2400 can communicate with each other using bus 2500.

[0132] At least one of the controller 2100 and the memory 2300 may include, according to various example embodiments, as referenced above. Figures 1 to 10B The aforementioned semiconductor device.

[0133] As described above, by controlling the structure and shape of the source / drain regions according to the exemplary embodiments of the present invention, semiconductor devices with improved electrical characteristics can be provided.

[0134] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; An active fin on the substrate, the active fin extending along a first direction, the active fin including a recessed region; A gate electrode on the substrate, the gate electrode intersecting the active fin such that the recessed region of the active fin is adjacent to at least one side of the gate electrode, the gate electrode extending along a second direction, the gate electrode including a sidewall; A gate spacer layer on the sidewall of the gate electrode; as well as In the source / drain region of the recessed region of the active fin, The source / drain region includes a base layer in contact with the active fin and a first layer on the base layer. The base layer includes inner and outer ends that are opposite to each other in the first direction. The base layer is located on the inner wall of the recessed area. The first layer includes germanium (Ge) at a concentration higher than that in the base layer. The outer end of the base layer contacts the first layer, and The outer end of the base layer has a shape that protrudes outward toward the outside of the gate electrode on a plane parallel to the upper surface of the substrate.

2. The semiconductor device according to claim 1, wherein, At least a portion of the inner end of the base layer is located below the gate electrode.

3. The semiconductor device according to claim 1, wherein... The first layer has inner and outer ends opposite to each other in the first direction on the inner sidewall of the recessed region, and The outer end of the first layer has a region that protrudes outward from the gate electrode on the plane.

4. The semiconductor device according to claim 3, wherein, At least a portion of the inner end of the first layer is located below the gate spacer layer.

5. The semiconductor device according to claim 1, wherein, At least a portion of the base layer and the first layer are located below the gate spacer layer on the inner sidewall of the recessed region.

6. The semiconductor device according to claim 1, wherein, The substrate is formed of silicon (Si).

7. The semiconductor device according to claim 1, wherein, The outer end of the base layer is not defined by the crystal plane of the active fin.

8. The semiconductor device according to claim 1, wherein, The first layer is a silicon-germanium (SiGe) layer, which comprises germanium (Ge) in the range of 20 at.% to 40 at.%.

9. The semiconductor device according to claim 1, wherein The source / drain region also includes a second layer on top of the first layer. The second layer fills the recessed area, and The second layer comprises germanium (Ge) at a higher concentration than that in the first layer.

10. The semiconductor device according to claim 1, wherein, The inner end of the base layer includes a region extending perpendicular to the upper surface of the substrate.

11. The semiconductor device according to claim 1, wherein, The base layer includes germanium (Ge) at a concentration higher than that in the active fin.

12. The semiconductor device according to claim 1, wherein The gate electrode includes a first side opposite to the second side. The source / drain region is located on both the first and second sides of the gate electrode. The length along the center of the active fin in the second direction from the outer end of the base layer on one side to the outer end of the base layer on the other side is greater than the length along the edge of the active fin in the second direction from the outer end of the base layer on one side to the outer end of the base layer on the other side.

13. The semiconductor device according to claim 1, further comprising: Contact plugs on the source / drain regions, wherein The contact plug is connected to the source / drain region.

14. A semiconductor device, comprising: Substrate; An active fin on the substrate, the active fin extending in one direction on the substrate, the active fin including a recessed region; A gate electrode on the substrate, the gate electrode extending and intersecting the active fin, such that a recessed region of the active fin is located on at least one side of the gate electrode; as well as The source / drain region in the recessed region of the active fin comprises a first layer and a second layer of germanium (Ge) with different concentrations. The end of the first layer that contacts the second layer located on the inner sidewall of the recessed region has a region that protrudes outward toward the gate electrode in a plane parallel to the upper surface of the substrate.

15. The semiconductor device of claim 14, wherein The end of the active fin, defined by the recessed region, has a region that protrudes outward toward the gate electrode on the plane.

16. The semiconductor device of claim 14, further comprising: In the base layer below the first layer, where The base layer is in contact with the active fin, and The base layer comprises germanium (Ge) at a concentration lower than that of germanium (Ge) included in the first layer.

17. The semiconductor device according to claim 16, wherein, The base layer has an outer recessed region on the plane toward the gate electrode at the end where it contacts the active fin located on the inner sidewall of the recessed region.

18. A semiconductor device, comprising: Substrate; An active fin on the substrate, the active fin extending along a first direction on the substrate, the active fin including a recessed region; A gate electrode on the substrate, the gate electrode extending and intersecting the active fin, such that a recessed region of the active fin is located on at least one side of the gate electrode; as well as In the source / drain region of the recessed area of ​​the active fin, The source / drain region includes a base layer in contact with the active fin and a first layer on the base layer. The base layer and the first layer have different concentrations of germanium (Ge). The base layer includes inner and outer ends that are opposite to each other in the first direction. The outer end of the base layer contacts the first layer, and The outer end of the base layer has a shape that protrudes outward toward the outside of the gate electrode on a plane parallel to the upper surface of the substrate.

19. The semiconductor device of claim 18, wherein The inner end of the base layer has a region that is recessed on the plane toward the outside of the gate electrode.

20. The semiconductor device according to claim 18, wherein, The source / drain region includes silicon (Si).

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