Method and system for calibrating phase nonlinearity of a digital-to-time converter

Abstract

A method for calibrating phase nonlinearity of a digital-to-time converter is provided. The method includes generating a reference signal using a phase-locked loop (PLL) based on a control word. The reference signal has a frequency equal to the frequency of an output signal of the digital-to-time converter. Furthermore, the method includes measuring a temporal sequence of transitions of the output signal from a first signal level to a second signal level and a temporal sequence of transitions of the reference signal from the first signal level to the second signal level. The method also includes adjusting a first entry of a lookup table based on the measured temporal sequence.

Description

Technical Field

[0001] The present disclosure relates to correcting the phase nonlinearity of a digital-to-time converter (DTC). In particular, the present disclosure relates to a method and system for calibrating the phase nonlinearity of a DTC. Background Art

[0002] DTCs are used to generate fractionally offset frequencies or modulated signals from a constant reference frequency. They can be used, for example, for carrier frequency offset and phase modulation in digital polar transmitters (DPTX), for frequency synthesis in receivers (RX), or for digital clock generation in clock-controlled applications.

[0003] Some applications (e.g., digital clock generation) have relaxed specifications, meaning they are tolerant of DTC phase nonlinearity. In particular, DPTX and RX applications require highly linear DTCs. Since no attractive or competitive architectures are known for perfectly linear DTCs, DTC nonlinearities are calibrated on-chip and the digital DTC data is predistorted using information from the DTC calibration.

[0004] Several calibration engines have been proposed and implemented. Their main drawback is the calibration for specific DTC operating conditions (e.g., calibration for quasi-static DTC programming, or calibration for specific code ramps).

[0005] However, DTC nonlinearity varies for different operation types (eg, different code ramps or modulations), so one set of calibration data is not sufficient for all operation types.

[0006] Therefore, there may be a need for improved calibration of DTC nonlinearities. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some examples of apparatus and / or methods will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0008] Figure 1 A flow chart illustrating an example of a method for calibrating phase nonlinearity of a DTC;

[0009] Figure 2 An example of a system for calibrating phase nonlinearity of a DTC is illustrated;

[0010] Figure 3 Another system for calibrating phase nonlinearity of a DTC is illustrated;

[0011] Figure 4 A comparison between ideal and calibrated lookup table entries is illustrated;

[0012] Figure 5 illustrates a comparison of lookup table entry errors for different calibration parameters; and

[0013] Figure 6 An example of a mobile device including a DTC and a system for calibrating phase nonlinearity of the DTC is illustrated. DETAILED DESCRIPTION

[0014] Various examples will now be described more fully with reference to the accompanying drawings, which illustrate some examples.In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0015] Therefore, although the additional examples are capable of various modifications and alternative forms, some specific examples thereof are shown in the drawings and will be described in detail later. However, this detailed description does not limit the additional examples to the specific forms described. The additional examples may cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure. Like reference numerals throughout the description of the drawings refer to similar or analogous elements that, when compared to each other, may be implemented identically or in modified form while providing the same or similar functions.

[0016] It is understood that when an element is said to be "connected" or "coupled" to another element, these elements can be connected or coupled directly or via one or more intervening elements. If two elements A and B are combined using "or", it is understood that all possible combinations are disclosed, namely only A, only B, and A and B. An alternative wording for the same combination is "at least one of A and B". The same applies to combinations of more than two elements.

[0017] The terms used herein to describe specific examples are not intended to limit other examples. Whenever singular forms such as "one" and "the" are used and only a single element is neither explicitly nor implicitly limited to being mandatory, other examples may also use multiple elements to implement the same function. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may utilize a single element or processing entity to implement the same function. It is also to be understood that the terms "comprise" and / or "comprising" when used indicate the presence of the described features, integers, steps, operations, processes, actions, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any groups thereof.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same common meaning as in the art to which the examples belong.

[0019] Figure 1A flow chart of a method 100 for calibrating phase nonlinearity of a DTC is illustrated. Method 100 includes generating 102 a reference signal using a phase-locked loop (PLL) based on a control word. The frequency of the reference signal is (substantially) equal to the frequency of the DTC output signal. Furthermore, method 100 includes measuring 104 a temporal sequence of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level. Method 100 also includes adjusting 106 a first entry of a lookup table (LUT) based on the measured temporal sequence.

[0020] The DTC may generate an output signal based on a first entry of the LUT.The first entry is assigned to a first control code for the DTC, the first control code being based on a control word for controlling a frequency of the output signal.

[0021] Method 100 allows for compensation of DTC phase nonlinearity by adjusting the first entry (assigned to the first codeword) in the LUT based on the temporal sequence of the DTC output signal and the reference signal. Because method 100 does not depend on the specific time difference between the output signal and the reference signal, but only on the temporal sequence, a detector with relatively low resolution can be used to measure 104 the temporal sequence of the output signal and the reference signal. Furthermore, the DTC programming does not need to be changed during calibration. Therefore, background calibration can be performed. That is, the DTC can be operated normally during calibration, thereby avoiding downtime of the device incorporating the DTC. For example, DTC nonlinearity may change after temperature changes. To compensate for temperature-related changes in DTC nonlinearity, background calibration according to method 100 can be performed.

[0022] The DTC may, for example, receive an oscillating input signal. Based on a control word, the frequency and / or phase offset of the output signal relative to the oscillating input signal may be adjusted. For example, if the DTC is used in a receiver, the output signal may be provided to a mixing circuit that uses the output signal to downconvert a radio frequency receive signal. In other words, method 100 may also allow for calibration of specific nonlinearities (including both static and dynamic DTC nonlinearities) for each generated RX carrier.

[0023] The first signal level of a signal is a level associated with a first logical state, while the second signal level of the signal is a level associated with a second, different logical state. That is, if the signal is at the first signal level, it indicates the first logical state, and if the signal is at the second signal level, the signal indicates the second logical state. For example, the first signal level may indicate "1" or "high" and the second signal level may indicate "0" or "low", or vice versa. The signal level may, for example, be a voltage of the signal. In some examples, the transition from the first signal level to the second signal level may be a falling signal edge. In other examples, the transition from the first signal level to the second signal level may be a rising signal edge.

[0024] The temporal sequence indicates which of the output signal and the reference signal switches first from a first signal level to a second signal level. For example, a nonlinear phase detector (BBPD) can be used to measure 104 the temporal sequence. Depending on the DTC nonlinearity for a particular control code, the output signal (i.e., DTC output) switches earlier or later than the reference signal. Because method 100 (which can be understood as a calibration engine) does not rely on measuring a specific time difference between two signals, a BBPD can be used. The use of a time-to-digital converter (TDC) can be avoided because the higher temporal resolution of a TDC is not required. Therefore, the TDC nonlinearity, which is a complication, can be avoided in the calibration engine. However, in some examples, a TDC can also be used to measure 104 the temporal sequence.

[0025] The first control code of the DTC can be part of a continuously increasing or decreasing code sequence (code ramp) generated based on the control word. For example, the first control code and further control codes can be generated by continuously integrating the control word. Thus, several continuously increasing or decreasing control codes of the DTC can be generated.

[0026] The LUT may include an entry for each control code. For example, for N control codes for a DTC, the LUT may include N entries, each of which is assigned to a specific one of the N control codes for the DTC. The LUT may be initially populated with arbitrary data (e.g., zeros, data from a previous calibration, or random data). The entries in the LUT can be understood as the result of pre-distorting the DTC's control code to compensate for DTC nonlinearity. In other words, an entry in the LUT represents an adjusted control code for the DTC, derived from its assigned control code. By adjusting one of the entries in the LUT, the nonlinearity of the DTC for a specific code can be corrected. For example, the entries in the LUT may be incremented or decremented based on the temporal sequence of the output signal and the reference signal.

[0027] Before the first entry in the LUT is calibrated, the reference signal and the output signal can be aligned. Thus, method 100 may also include adjusting the phase of the reference signal to be (substantially) equal to the phase of the output signal generated by the DTC based on the second entry in the LUT. The second entry is assigned to a second control code of the DTC, for which the DTC is phase-linear. The DTC does not exhibit phase nonlinearity for all control codes. For one or more control codes in the code sequence, the DTC is, by definition, phase-linear. These control codes can be used to align the reference signal to the output signal.

[0028] In addition to the control word, generating 102 the reference signal may also be based on a frequency control word. Adjusting the phase of the reference signal may then further include measuring a time offset between a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level for the second entry. Alternatively, adjusting the phase of the reference signal may further include measuring a third time sequence between a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level for the second entry. Furthermore, adjusting the phase of the reference signal may include generating the frequency control word based on the time offset or the third time sequence. Thus, by adjusting the frequency control word, the phase of the reference signal may be adjusted to be equal to the phase of the output signal generated by the DTC based on the second entry in the LUT. In other words, the reference signal is adjusted so that it exhibits no phase offset relative to the output signal of the DTC, where the output signal of the DTC is generated based on a codeword for which the DTC is phase linear.

[0029] For example, adjusting the frequency control word may include calculating a phase error of the reference signal relative to the output signal based on the time offset or the third time sequence. Additionally, adjusting the frequency control word may include adjusting the frequency control word based on the phase error.

[0030] The time offset or third time sequence between the second entry reference signal in the LUT and the output signal and the time sequence between the first entry reference signal in the LUT and the output signal can be measured by the same or different circuits. For example, the time offset between the second entry reference signal in the LUT and the output signal can be measured using a TDC, and the third time sequence between the second entry reference signal in the LUT and the output signal can be measured using a BBPD.

[0031] Alternatively, the DTC output signal can be calibrated to a reference signal. Thus, method 100 may further include measuring a phase error of the reference signal relative to the phase of an output signal generated by the DTC based on the second entry in the LUT. Furthermore, method 100 may include generating a correction code based on the phase deviation, wherein the first control code is further based on the correction code. In other words, the control code of the code sequence may be adjusted based on the correction code. For example, the control code of the code sequence may be incremented or decremented according to the correction code to adjust the phase of the DTC output signal to the phase of the reference signal. Thus, for code words in a code sequence in which the DTC is phase-linear, the phase of the DTC output signal may be equal to the phase of the reference signal.

[0032] The above-described measurement for calibrating the time sequence of the first entry in the LUT can be performed a predetermined number of times in order to measure a predetermined number of time sequences. Thus, adjustment of the first entry can be based on a predetermined number of time sequences. For example, if a BBPD is used to measure the time sequence and a PLL with relatively high jitter is used to generate the reference signal, the measured time sequences can be averaged to achieve high calibration accuracy. For example, the time sequence can be measured 16 times or more, 64 times or more, 256 times or more, 1024 times or more, or 4096 times or more. In some examples, at least a portion of the predetermined number of time sequences can be measured in parallel. Thus, calibration time can be reduced due to multiple simultaneous measurements of the time sequences.

[0033] Adjusting the first entry based on a predetermined number of time sequences may, for example, include deriving an indicator value from the predetermined number of time sequences, the indicator value indicating whether a transition of the output signal from a first signal level to a second signal level or a transition of the reference signal from a first signal level to a second signal level more often precedes the other over the predetermined number of time sequences. For example, a counter may be used to derive the indicator value. If the output signal leads the reference signal, the counter may be incremented, and if the reference signal leads the output signal, the counter may be decremented. Thus, a counter value greater than zero indicates that a transition of the output signal from a first signal level to a second signal level more often precedes a transition of the reference signal from a first signal level to a second signal level, and vice versa, over the predetermined number of time sequences. Adjusting the first entry based on the predetermined number of time sequences may further include adjusting the first entry based on the indicator value.

[0034] In some examples, the first entry may be adjusted only if the absolute value of the indicator value is greater than a threshold. The threshold may allow the first entry in the LUT to be adjusted only if it has not yet been calibrated with sufficient accuracy. In other words, if the first entry has already been calibrated with sufficient accuracy, adjustment of the first entry in the LUT may be omitted. The desired level of accuracy can be adjusted by selecting the threshold.

[0035] In some examples, calibration of the entries in the LUT can be performed iteratively. For example, measuring a predetermined number of time sequences and adjusting the first entry based on the predetermined number of time sequences can be performed iteratively. By iteratively calibrating the entries in the LUT, high calibration accuracy can be achieved.

[0036] As indicated above, the DTC is not limited to generating an output signal based on the first entry in the LUT assigned to the first control code of the code sequence. The DTC can generate output signals based on additional entries in the LUT, where the additional entries are assigned to additional control codes of the DTC (i.e., other control codes of the code sequence). Method 100 can therefore further include measuring, for the additional entries, the corresponding temporal sequence of transitions of the output signal from a first signal level to a second signal level and transitions of the reference signal from the first signal level to the second signal level. Furthermore, method 100 can further include adjusting the additional entries based on the corresponding temporal sequence. Thus, all entries in the LUT can be adjusted to compensate for DTC nonlinearity at the control codes of the code sequence.

[0037] Calibration can be performed iteratively. That is, measuring the corresponding time sequence for the additional entries can be performed a predetermined number of times, so that a corresponding predetermined number of time sequences are measured for each of the additional entries, and the additional entries are adjusted based on the corresponding predetermined number of time sequences. Thus, high calibration accuracy can also be achieved for the additional entries in the LUT.

[0038] In some examples, measuring a predetermined number of time sequences for a first entry and another entry of the LUT and adjusting the first entry and another entry is iteratively performed until a maximum number of iterations is reached or each of the first entry and another entry meets a quality criterion. The maximum number of iterations is a hard stopping criterion. The quality criterion can be any quantity that indicates the desired accuracy of the calibration of the LUT entries. For example, the quality criterion can be that for each LUT entry, the corresponding index value is less than a threshold. Therefore, the number of iterations required to achieve the quality criterion for all entries can be less than the maximum number of iterations.

[0039] In the above example, only the time sequence for one type of signal edge is used to calibrate the entries in the LUT. However, method 100 can use additional signal edges, i.e., falling and rising edges. In some examples, method 100 can therefore further include measuring, for the first entry, a second time sequence of a transition of the output signal from a second signal level to a first signal level and a corresponding transition of the reference signal from the second signal level to the first signal level. Adjusting the first entry can then also be based on the second time sequence. Therefore, a corresponding second time sequence can be measured for the additional entries in the LUT, and the additional LUT entries can be adjusted based on the corresponding second time sequence. As with the first time sequence, the second time sequence can be measured a predetermined number of times (i.e., multiple times) as described above.

[0040] Adjusting the LUT entry can be accomplished in various ways. For example, adjusting 106 the first entry can include incrementing or decrementing the first entry based on the first time sequence. For example, if the output signal of the DTC leads the reference signal, the first entry can be incremented, and vice versa.

[0041] Instead of incrementally filling the LUT, other schemes, such as binary search, may also be used. For example, iteratively adjusting the first entry as described above may include incrementing or decrementing the first entry in the first iteration by a first value based on a predetermined number of chronological sequences for the first iteration. Additionally, iteratively adjusting the first entry may include incrementing or decrementing the first entry in the second iteration by a second value based on a predetermined number of chronological sequences for the second iteration, wherein the second value is (substantially) half the first value. That is, for iteration n (e.g., iteration n out of a total of N iterations), the output signal and the reference signal are incremented by 2 of the first value (i.e., the value of the first iteration) based on the chronological sequences for the nth iteration. -(n-1) The first entry in the LUT may be incremented or decremented by a multiple of the value of 0. This may allow a defined calibration time and may allow a reduction in the required calibration iterations compared to the above-described incremental approach.

[0042] In the following, various examples for implementing the method 100 are discussed. Figure 2 A system 200 for calibrating phase nonlinearity of a DTC 210 is illustrated. System 200 includes a PLL 230 configured to generate a reference signal 231 based on a control word 205. The frequency of reference signal 231 is (substantially) equal to the frequency of output signal 211 of DTC 210. The system also includes a detection circuit 240 configured to measure a temporal sequence of transitions of output signal 211 from a first signal level to a second signal level and a transition of reference signal 231 from the first signal level to the second signal level. Processing circuitry 250 of system 200 is configured to adjust first entry 221 of LUT 220 based on the measured temporal sequence.

[0043] The DTC 210 may generate an output signal 211 based on a first entry 221 of the LUT 220. The first entry 211 is assigned to a first control code for the DTC 210 that is based on a control word 205 for controlling a frequency of the output signal 211.

[0044] As with method 100, system 200 allows calibration of the first entry 221 of the LUT without changing the programming of the DTC 210 during calibration. Thus, background calibration (e.g., after a temperature change) can be performed. Furthermore, because the adjustment of the first entry 221 does not depend on the specific time difference between the output signal 211 and the reference signal 231, but only on the temporal sequence, the detection circuit 240 only needs to provide relatively low temporal resolution. For example, the detection circuit 240 may be a BBPD.

[0045] Before configuring the first entry 221, the system 200 may align the reference signal 231 and the DTC output signal 211. For example, the PLL 230 may be configured to adjust the phase of the reference signal 231 to be (substantially) equal to the phase of the output signal 211 generated by the DTC based on the second entry in the LUT 220. The second entry is assigned to the second control code of the DTC 210 for which the DTC 210 is phase linear.

[0046] PLL 230 may, for example, be configured to also generate reference signal 231 based on the frequency control word. That is, PLL 230 may generate reference signal 231 based on control word 205 and the frequency control word. Furthermore, detection circuit 240 (e.g., implemented as a TDC) may be further configured to measure, for a second LUT entry, a time offset between a transition of output signal 211 from a first signal level to a second signal level and a transition of reference signal 231 from a first signal level to a second signal level. Alternatively, detection circuit 240 (e.g., implemented as a BBPD) may be configured to measure, for a second LUT entry, a third time sequence of a transition of output signal 211 from a first signal level to a second signal level and a transition of reference signal 231 from a first signal level to a second signal level. The system may further include a conversion circuit (not shown) configured to generate the frequency control word based on the time offset or the third time sequence.

[0047] For example, the conversion circuit can be configured to calculate a phase error of the reference signal 231 relative to the output signal 211 based on the time offset or the third time sequence. Additionally, the conversion circuit can be configured to adjust the frequency control word based on the phase error.

[0048] In some examples, system 200 may further include a filter (not shown) coupled between detection circuit 240 and the conversion circuit. The filter may be configured to forward filtered data from detection circuit 240 to the conversion circuit only if a control signal input to the filter indicates that DTC 210 is generating an output signal based on an entry in LUT 220 assigned to a control code for which DTC 210 is phase-linear. In other words, the filter forwards data from detection circuit 240 to the conversion circuit if the DTC is generating an output signal based on the second entry in the LUT, but does not forward data from detection circuit 240 to the conversion circuit if the DTC is generating an output signal based on the first entry in the LUT. Thus, the filter ensures that the frequency control word is adjusted only if the DTC is generating an output signal based on a control word for which DTC 210 is (by definition) phase-linear.

[0049] As noted above, detection circuit 240 may be a BBPD. Additionally, PLL 230 may exhibit relatively high jitter (e.g., PLL 230 may be inductorless). This may affect the accuracy of the measured time sequence. To achieve high calibration accuracy, multiple time sequences may be measured and averaged. Therefore, detection circuit 240 may also be configured to measure the time sequence a predetermined number of times, such that a predetermined number of time sequences are measured. Furthermore, processing circuit 250 may also be configured to adjust first entry 221 based on the predetermined number of time sequences.

[0050] For example, the detection circuit 240 may be configured to measure at least a portion of a predetermined number of time sequences in parallel. The processing circuit 250 may therefore include multiple measurement units. Each measurement unit may be configured to measure the time sequence of the output signal and the reference signal. Thus, the time sequences may be measured simultaneously. For example, the detection circuit 240 may include multiple BBPD units.

[0051] To process multiple time sequences, processing circuit 250 may be further configured to derive an indicator value from a predetermined number of time sequences, the indicator value indicating whether the transition of output signal 211 from a first signal level to a second signal level or the transition of reference signal 231 from a first signal level to a second signal level more often precedes the other in the predetermined number of time sequences. Furthermore, processing circuit 250 may be configured to adjust first entry 221 based on the indicator value. For example, a counter may be executed by processing circuit 250 to derive the indicator value.

[0052] In some examples, processing circuit 250 may also be configured to adjust first entry 221 only if the absolute value of the indicator value is greater than a threshold. The threshold may allow the first entry in the LUT to be adjusted only if it has not been calibrated with sufficient accuracy. The desired level of accuracy may be adjusted by selecting the threshold.

[0053] As with method 100, system 200 can be configured to iteratively calibrate first entry 221 in LUT 220. For example, system 200 can be configured to control detection circuit 240 to iteratively measure a predetermined number of time sequences. System 200 can also be configured to control processing circuit 250 to iteratively adjust first entry 221 based on the predetermined number of time sequences.

[0054] However, system 200 is not limited to calibrating only first entry 221 in the LUT. As described above, DTC 210 may generate output signals based on additional entries in LUT 220. Additional entries may be assigned to additional control codes of DTC 210. Therefore, detection circuit 240 may be further configured to measure, for the additional entries, the corresponding temporal sequence of a transition of output signal 211 from a first signal level to a second signal level and a transition of reference signal 231 from a first signal level to a second signal level. Therefore, processing circuit 250 may be further configured to adjust the additional entries in LUT 220 based on the corresponding temporal sequence.

[0055] Similar to the first entry 221 in the LUT 220, the detection circuit 240 can be further configured to measure the corresponding time sequence for the other entries a predetermined number of times, so that a corresponding predetermined number of time sequences are measured for each of the other entries. Similarly, the processing circuit 250 can be further configured to adjust the other entries in the LUT 220 based on the corresponding predetermined number of time sequences. Therefore, high calibration accuracy can also be achieved for the entries in the LUT 220.

[0056] Calibration can also be performed iteratively for additional entries. That is, the system 200 can be configured to control the detection circuit 240 to iteratively measure a corresponding predetermined number of time sequences for the first entry and the additional entries of the LUT 220. In addition, the system 200 can be configured to control the processing circuit 250 to iteratively adjust the first entry and the additional entries in the LUT 220 until a maximum number of iterations is reached or each of the first entry and the additional entries in the LUT 220 meets a quality standard. The quality standard can be any quantity indicating the desired accuracy of the calibration of the LUT entry. For example, the quality standard can be that the corresponding absolute value of the indicator value is less than a threshold value for each LUT entry. Therefore, the number of iterations required to achieve the quality standard for all entries can be less than the maximum number of iterations.

[0057] In the above example, system 200 is configured to adjust LUT entries based on only one type of signal edge. However, system 200 can also be configured to use more signal edges, namely rising and falling signal edges. Therefore, detection circuit 240 can also be configured in some examples to measure, for first entry 221, a second temporal sequence of a transition of output signal 211 from a second signal level to a first signal level and a corresponding transition of reference signal 231 from a second signal level to a first signal level. Therefore, processing circuit 250 can also be configured to adjust first entry 221 in LUT 220 based on the second temporal sequence. Similarly, for other entries in LUT 220, detection circuit 240 can be configured to measure one or more corresponding second temporal sequences, and processing circuit 250 can be configured to adjust the corresponding entry in LUT 220 based on the measured corresponding (one or more) second temporal sequences.

[0058] As discussed above in connection with method 100, entries in LUT 220 may be adjusted in a variety of ways based on the measured temporal sequence(s). For example, processing circuit 250 may also be configured to adjust first entry 221 by incrementing or decrementing first entry 221 based on the first temporal sequence.

[0059] In addition, the processing circuit 250 may be further configured to iteratively adjust the first entry 211 based on a binary search. That is, for iteration n (e.g., iteration n out of a total of N iterations), the processing circuit 250 may be configured to iteratively adjust the first entry 211 based on a time sequence of the output signal and the reference signal for the nth iteration in the order of two of the values ​​of the first iteration. -(n-1) For example, the processing circuit 250 may be configured to increment or decrement the first entry 221 in the first iteration by a first value based on a predetermined number of chronological orders of the first iteration, and to increment or decrement the first entry 221 in the second iteration by a second value based on a predetermined number of chronological orders of the second iteration. The second value is (substantially) half the first value. This may allow for a defined calibration time and may reduce the number of required calibration iterations compared to the aforementioned incrementing scheme.

[0060] exist Figure 3 , another system 300 for calibrating the phase nonlinearity of the DTC 210 is illustrated. Figure 3 In the example shown in FIG, DTC 210 is part of a receiver. DTC 210 provides its output signal 211 to a mixing circuit (not shown) of the receiver, which uses the output signal 211 to down-convert the RF receive signal.

[0061] The system 300 includes the necessary circuitry for the mixer circuit to generate the RX signal (i.e., output signal 211). The RX generation includes an RX PLL 275 for generating an oscillating input signal 276 (i.e., a reference local oscillator signal) for the DTC 210. In addition, the RX generation includes a RX PLL 275 that is utilized (based on) to generate the desired RX frequency f DTC,out The DTC 210 is programmed with a control code n∈[0,N] (with a maximum DTC control code N). The RX generation also includes a LUT 220 to correct for DTC nonlinearity. The LUT 220 includes an entry for each control code. Each entry in the LUT 220 is based on the assigned control code and is adjusted based on the DTC nonlinearity of the corresponding control code (i.e., the entries in the LUT 220 can be understood as pre-distorted control codes of the DTC 210 to take DTC nonlinearity into account). In addition, the RX generation includes a control circuit 260 (e.g., implemented as a digital part) for correcting the DTC nonlinearity by adjusting the frequency f used to control the output signal 211. DTC,out The RX control word (FCW) 205 is integrated to generate the RX control code sequence (control code ramp) 290.

[0062] The calibration engine adds (calibrates) the PLL 230 for generating a reference signal 231 having the same frequency as the output signal 211 of the DTC 210, ie, f RX,ideal =f DTC,out The calibration PLL 230 uses the same FCW 205 used to derive the DTC programming. That is, the reference signal 231 is based on the control word 205. DTC,out The ideal output frequency desired at the output of the DTC 210 may be exhibited, but distorted by the DTC nonlinearity. In addition, the RX PLL 275 and the calibration PLL 230 receive the same reference frequency f ref , for a reference frequency f ref The oscillating input signal 276 and the reference signal 231 are generated for the DTC 210 , respectively.

[0063] The DTC output signal 211 and the reference signal 231 have the same frequency, but their phases are initially misaligned. To lock their phases, the BBPD 240, which acts as a detection circuit, compares f RX,ideal and f DTC,out In the closed calibration DTC-PLL control loop consisting of the BBPD 240, the (loop) filter (LF) 270 and the differentiator 280 (which acts as a conversion circuit for converting the phase error into a frequency for programming the calibration PLL 230), the phase error between the output signal 211 and the reference signal 231 is reduced to zero.

[0064] However, only DTC edges (i.e., signal edges of the output signal 211) of control codes with zero integral nonlinearity (INL), i.e., control codes for which the DTC 210 is phase linear (e.g., control code n=0 by definition, which is a 0° phase reference for the output signal 211), are used to lock the phase of the calibration PLL 230 to the DTC 210.

[0065] Calibration PLL 230 may exhibit poor signal quality.For example, PLL 230 may be inductorless or ring oscillator based.

[0066] The goal of the first step is to calibrate out any phase deviation between PLL 230 and DTC 210, that is, any phase deviation between reference signal 231 and output signal 211. DTC 210 generates output signal 211 (RX signal) based on the RX code ramp (sequence). LUT 220 can be filled with arbitrary data (zeros, data from a previous calibration, random data). Calibration can be initialized according to the following algorithm.

[0067] First, the DTC-PLL control loop is opened. Then the calibration PLL 230 is locked to f RX,ideal =f DTC,out That is, the frequency of reference signal 231 is adjusted to the frequency of output signal 211. The DTC-PLL control loop is now closed. The DTC-PLL's LF 270 is fed only with data related to DTC control codes with inherently zero INL (e.g., code n=0 has zero INL by definition). Processing circuit 250 (i.e., the calibration engine) instructs LF 270 which inputs to process. That is, filter 270 is configured to process data from BBPD 240 and forward the filtered data to differentiator 280 only when the control signal 251 input to filter 270 indicates that the (current) measured edge of DTC output signal 211 is based on an entry in LUT 220 assigned to DTC 210 for a control code for which DTC 210 is phase linear. Differentiator 280 converts the phase error into a frequency used to program calibration PLL 230. Specifically, differentiator 280 generates a frequency control word for calibration PLL 230. This frequency control word is combined with FCW 205 to generate the control word for calibrating PLL 230. The above process may be iteratively repeated throughout the calibration procedure.

[0068] Since the DTC-PLL loop only operates on DTC codes that have (by definition) perfect linearity, it is not affected by the LUT programming. Now, the calibration algorithm can begin.

[0069] Each rising and / or falling DTC output is compared by the BBPD 240 to the ideal RX signal, which allows the DTC,out Phase detection is performed at a rate of 0.1°. For each measured edge, the programmed DTC control code is known to the calibration engine (e.g., processing circuit 250 can read it from LUT 220). For example, if a measured DTC edge (i.e., output signal 211) has a positive time deviation compared to an edge of reference signal 231, then DTC 210 has positive nonlinearity for that particular code. If this is the case, the LUT entry at that location is decremented by processing circuit 250. Conversely, for a negative time deviation, the LUT entry is incremented by the processing circuit.

[0070] For example, calibration can be achieved by:

[0071] 1) Measure whether the rising DTC output 211 or the rising ideal RX signal 231 is leading. A leading DTC signal 211 results in a "-1" at the output of the BBPD 240, while a leading RX signal 231 results in a "1." The DTC output signal 211 is generated for the first DTC control code n (i.e., based on the first entry in the LUT 220 assigned to the first control code).

[0072] 2) Program the LUT accordingly:

[0073] a. If BBPD 240 output is "-1": Increment the LUT entry at code n.

[0074] b. If BBPD 240 output is "1": decrement the LUT entry at code n.

[0075] 3) Move to 1) and measure the next DTC output edge.

[0076] Due to the required high calibration accuracy and the potentially high jitter of the calibration PLL 230, measurements can be averaged. For example, this can be accomplished by measuring several values ​​for each control code and storing them by accumulating the BBPD 240 outputs in a counter within the digital portion of the calibration engine (i.e., processing circuitry 250 performs computational operations). After the desired averaging, the counter values ​​can be evaluated and the LUT 220 programmed accordingly. As noted above, the thresholds of the counters can be used to define stopping criteria for calibration. For example, if (substantially) equal numbers of measurement points for the same code have positive and negative time deviations from a reference (i.e., the counter is at or near zero), calibration for this code can be stopped, as it is ideally calibrated. If random chatter is added to the DTC RX sequence 290, it can be averaged in the same manner.

[0077] For example, several A measurements are made for each DTC control code (i.e., for each entry in LUT 220), and the output of BBPD 240 is summed in counter c[n] (i.e., one counter is used for each of the N+1 DTC control codes to speed up calibration). If the majority of the measured edges indicate "-1" at the output of BBPD 240, the corresponding LUT value is incremented, otherwise it is decremented by processing circuit 250. Counter threshold c thres It is possible to indicate whether the calibration has been completed with sufficient accuracy. It also defines the maximum number of iterations I max To have a hard stopping criterion. The complete algorithm (method) can be as follows:

[0078] 1) Define the averaging factor A, which determines how many measurements are averaged (i.e. A defines the accuracy). In addition, define the maximum number of iterations I max .

[0079] 2) Set the iteration counter to i=0.

[0080] 3) Set the average counter to a=0.

[0081] 4) Measure whether the rising DTC output 211 or the rising ideal RX signal 231 is leading. A leading DTC output 211 results in a "-1" at the output of the BBPD 240, while a leading RX signal 231 results in a "1." Record the active DTC control code n.

[0082] 5) Program the internal calibration counter c[n].

[0083] a. If BBPD output is "-1": increment counter c[n]

[0084] b. If BBPD output is "1": decrement counter c[n]

[0085] 6) Increment the average counter a.

[0086] 7) If a=A·N then move to 8), otherwise move to 4) and measure the subsequent rising DTC output 211.

[0087] 8) If c[n]>c thres Then increment the corresponding LUT entry if c[n]<-c thres decrements the corresponding LUT entry, or if -c thres ≤c[n]≤c thres Then the control code n is marked as calibrated.

[0088] 9) Increase the iteration counter i.

[0089] 10) If control code n is marked as calibrated, Or i=I max , then move to 11), otherwise move to 3).

[0090] 11) Stop calibration.

[0091] As noted above, the rising edge calibration described above can be changed to a falling edge or double edge calibration. Instead of incremental LUT filling, other algorithms, such as binary search, can also be used. Binary search can enable a defined calibration time and allow the number of required calibration iterations to be further reduced. For binary search, the algorithm stopping criteria (quality criteria) can be adapted accordingly.

[0092] The implementation of BBPD 240 can be of arbitrary complexity.As noted above, multiple parallel BBPD units can be used to reduce mismatch effects, increase accuracy, and reduce calibration time through multiple simultaneous measurements.

[0093] In other words, Figure 3 The calibration engine can be illustrated as being focused on RX DTC operation. For example, an inductorless calibration PLL 230 generates an ideal RX signal 231, and the DTC output 211 is compared to it using a BBPD 240. The LUT 220 of the DTC 210 is then incrementally populated with calibration data, for example, until an accuracy threshold is achieved between the ideal RX and DTC-generated RX signals. The architecture of the calibration engine allows it to be recalibrated as needed during DTC operation.

[0094] As noted above, the inductorless calibration PLL 230 may be used to generate the reference signal f for RX DTC calibration. RX,ideal , where the reference signal is locked to the DTC output phase. Two signals 1)f DTC,out The DTC output signal at (generated by the RX control code ramp) and 2)f RX,ideal The calibration PLL signal at 276 can be compared using BBPD 240 to extract the direction of DTC nonlinearity compared to the ideal RX signal. Compared to other detection circuits such as TDCs, the BBPD can operate at rates up to the oscillating input signal 276 for DTC, thereby reducing calibration time. LUT 220 can be incrementally populated based on the extracted information. Averaging the measurements can be used to increase resolution and reduce the effects of DTC and calibration PLL jitter.

[0095] The accuracy of the proposed calibration scheme is verified by the following Figure 4 and Figure 5 This becomes apparent in the discussion of Figure 4A comparison between ideal and calibrated lookup table entries is shown. The abscissa represents the control code for the DTC, and the ordinate represents the entry in the LUT for each control code.

[0096] Dots 410 indicate ideal entries for the control codes, ie, entries assigned to each control code to obtain optimal compensation for DTC nonlinearity at the corresponding control code.

[0097] The diamond-shaped data points 420 indicate the entries of the LUT after a defined number of calibration iterations according to the proposed concept.For the diamond-shaped data points 420, a first number A1 of time sequences are measured for each iteration and averaged.

[0098] The square data points 430 indicate the entries of the LUT after a defined number of calibration iterations according to the proposed concept. For the square data points 420, a second number A2 of time sequences are measured for each iteration and averaged. A2 is greater than A1.

[0099] from Figure 4 It is clear that the accuracy of the calibration is better for a larger number of averaged measurements.

[0100] Figure 5 A comparison of LUT entry errors for different calibration parameters is further illustrated. The horizontal axis represents the number of time sequences measured and averaged. The vertical axis represents the average (e.g., root mean square (RMS)) error of the LUT entry compared to the ideal LUT entry. Data point 510 represents the error of the LUT entry for the first jitter y of the PLL used to generate the reference signal. Data point 520 represents the error of the LUT entry for the second jitter 3·y of the PLL (i.e., the second jitter is three times the first jitter). Data point 530 represents the error of the LUT entry for the third jitter 5·y of the PLL. Data point 540 represents the error of the LUT entry for the fourth jitter 7·y of the PLL. Data point 550 represents the error of the LUT entry for the fifth jitter 9·y of the PLL.

[0101] from Figure 5 It is again clear that the accuracy of the calibration is better for a larger number of averaged measurements. Figure 5 It is clear that for lower jitter of the calibration PLL used to generate the reference signal, the accuracy of the calibration is better.To calibrate the LUT with a desired accuracy, a trade-off can be made between the jitter of the calibration PLL and the number of time sequences to be averaged (ie the runtime of the calibration).

[0102] In summary, some examples presented herein relate to an apparatus for calibrating phase nonlinearity of a DTC. The apparatus includes means for generating a reference signal using a phase-locked loop (PLL) based on a control word, wherein the frequency of the reference signal is equal to the frequency of an output signal of the DTC. The apparatus also includes means for measuring a temporal sequence of transitions of the output signal from a first signal level to a second signal level and transitions of the reference signal from the first signal level to the second signal level. Furthermore, the apparatus includes means for adjusting a first entry of a LUT based on the measured temporal sequence.

[0103] The DTC may generate an output signal based on a first entry of the LUT, wherein the first entry is assigned to a first control code for the DTC, the first control code being based on a control word for controlling a frequency of the output signal.

[0104] In some examples, the apparatus for generating a reference signal may be further configured to adjust a phase of the reference signal to be equal to a phase of an output signal generated by the DTC based on a second entry in the LUT, wherein the second entry is assigned to a second control code for the DTC for which the DTC (by definition) is phase linear.

[0105] The apparatus for calibrating the phase nonlinearity of the DTC may be provided by the above or the following (eg Figure 2 ) is implemented by the system for calibrating the phase nonlinearity of the DTC described above. The device for generating the reference signal can be provided by the above or below (e.g. Figure 2 ) is implemented by the PLL described above. The device for measuring the time sequence can be provided by the above or below (e.g. Figure 2 ) is implemented by the detection circuit described above. The device for adjusting the first item can be provided by the above or below (e.g. Figure 2 ) is implemented by the processing circuit described in .

[0106] An example of an implementation for calibrating phase nonlinearity of a DTC using one or more aspects of the proposed architecture or one or more examples described above is provided in Figure 6 Middle picture. Figure 6 Schematically illustrated is an example of a mobile device 600 (e.g., a mobile phone, smartphone, tablet, or laptop computer) that includes a DTC 610 that generates a radio frequency output signal based on entries in a LUT 620. The mobile device 600 also includes a system 630 for calibrating phase nonlinearity of the DTC according to examples described herein.

[0107] For example, receiver 670 may include DTC 610 , LUT 620 , and system 630 .

[0108] To this end, a mobile device 600 may be provided to enable fully digital receive carrier generation. Thus, the number of on-chip inductors may be reduced, thereby reducing chip area and alleviating crosstalk issues.

[0109] Receiver 670 may include one or more additional components. For example, receiver 670 may include control circuitry 640 configured to generate a continuous rising or falling code sequence based on a control word, wherein the first control code for DTC 610 is part of the code sequence. Receiver 670 may also include PLL 650 configured to generate an oscillating input signal for DTC 610. Furthermore, receiver 670 may include mixing circuitry 660 configured to down-convert a radio frequency receive signal using an output signal from DTC 610.

[0110] For example, the receiver 670 may be configured to operate in accordance with one of the 3GPP standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, Long Term Evolution (LTE), LTE-Advanced (LTE-A), High Speed ​​Packet Access (HSPA), Universal Mobile Telecommunication System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), evolved-UTRAN (e-UTRAN), Global System for Mobile communications (GSM) or Enhanced Data rates for GSM Evolution (EDGE) network, GSM / EDGE Radio Access Network (GERAN), or a mobile communication network of a different standard, such as Worldwide Interoperability for Microwave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, generally Orthogonal Frequency Division Multiple Access (OFDMA) network. Division Multiple Access (OFDMA) network, Time Division Multiple Access (TDMA) network, Code Division Multiple Access (CDMA) network, Wideband-CDMA (WCDMA) network, Frequency Division Multiple Access (FDMA) network, Spatial Division Multiple Access (SDMA) network, and so on.

[0111] At least one antenna element 680 of the mobile device 600 may be coupled to the receiver 670 .

[0112] The examples described in this article can be summarized as follows:

[0113] Example 1 is a method for calibrating the phase nonlinearity of a digital-to-time converter, comprising: generating a reference signal using a phase-locked loop based on a control word, wherein the frequency of the reference signal is substantially equal to the frequency of the output signal of the digital-to-time converter; measuring a time sequence of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and adjusting a first entry of a lookup table based on the measured time sequence.

[0114] In Example 2, the digital-to-time converter in the method as described in Example 1 generates the output signal based on a first entry of the lookup table, wherein the first entry is assigned to a first control code for the digital-to-time converter, which is based on a control word for controlling the frequency of the output signal.

[0115] In Example 3, the method as described in Example 1 or Example 2 also includes: adjusting the phase of the reference signal to be substantially equal to the phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code for the digital-to-time converter, and for the second control code, the digital-to-time converter is phase linear.

[0116] In Example 4, generating the reference signal in the method as described in Example 3 is also based on a frequency control word, and wherein adjusting the phase of the reference signal includes: measuring, for the second entry, a time offset between a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and generating the frequency control word based on the time offset.

[0117] In Example 5, adjusting the frequency control word in the method of Example 4 includes: calculating a phase error of the reference signal relative to the output signal based on the time offset; and adjusting the frequency control word based on the phase error.

[0118] In Example 6, generating the reference signal in the method as described in Example 3 is also based on a frequency control word, and wherein adjusting the phase of the reference signal includes: measuring a third time sequence of a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level for the second entry; and generating the frequency control word based on the third time sequence.

[0119] In Example 7, adjusting the frequency control word in the method of Example 6 includes: calculating a phase error of the reference signal relative to the output signal based on the third time sequence; and adjusting the frequency control word based on the phase error.

[0120] In Example 8, the method described in Example 2 also includes: measuring a phase error of the reference signal relative to the phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code for the digital-to-time converter, for which the digital-to-time converter is phase-linear; and generating a correction code based on the phase deviation, wherein the first control code is also based on the correction code.

[0121] In Example 9, as in the method of any preceding example, measuring the time sequence comprises measuring a predetermined number of time sequences, wherein adjusting the first entry is based on the predetermined number of time sequences.

[0122] In Example 10, at least a portion of the predetermined number of time sequences in the method of Example 9 are measured in parallel.

[0123] In Example 11, adjusting the first entry based on the predetermined number of time sequences in the method as described in Example 9 or Example 10 includes: deriving an indicator value from the predetermined number of time sequences, the indicator value indicating whether the transition of the output signal from the first signal level to the second signal level or the transition of the reference signal from the first signal level to the second signal level more often leads the other among the predetermined number of time sequences; and adjusting the first entry based on the indicator value.

[0124] In Example 12, in the method of Example 11, the first entry is adjusted only if an absolute value of the indicator value is greater than a threshold.

[0125] In Example 13, measuring the predetermined number of temporal sequences and adjusting the first entry based on the predetermined number of temporal sequences in the method of any one of Examples 9 to 12 is performed iteratively.

[0126] In Example 14, the digital-to-time converter in the method as described in Example 13 generates the output signal based on an additional entry in the lookup table, the additional entry being assigned to an additional control code for the digital-to-time converter, wherein the method further includes: measuring, for the additional entry, a corresponding time sequence of a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and adjusting the additional entry based on the corresponding time sequence.

[0127] In Example 15, measuring the corresponding time sequences for the further entries in the method of Example 14 is performed a predetermined number of times, so that a corresponding predetermined number of time sequences are measured for each of the further entries, and adjusting the further entries is based on the corresponding predetermined number of time sequences.

[0128] In Example 16, measuring a corresponding predetermined number of time sequences for the first entry and the further entry of the lookup table and adjusting the first entry and the further entry in the method of Example 15 is iteratively performed until a maximum number of iterations is reached or each of the first entry and the further entry meets a quality criterion.

[0129] In Example 17, the method as described in any of the preceding examples further includes: measuring a second time sequence of a transition of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level for the first entry, wherein adjusting the first entry is also based on the second time sequence.

[0130] In Example 18, adjusting the first entry in the method as described in any preceding example includes incrementing or decrementing the first entry based on the first time sequence.

[0131] In Example 19, iteratively adjusting the first entry as described in Example 13 includes: increasing or decreasing the first entry in the first iteration by a first value based on a predetermined number of time sequences of the first iteration; and increasing or decreasing the first entry in the second iteration by a second value based on a predetermined number of time sequences of the second iteration, wherein the second value is substantially half of the first value.

[0132] In Example 20, a nonlinear phase detector is used to measure the time sequence in a method as described in any preceding example.

[0133] In Example 21, the first control code for the digital-to-time converter in the method of Example 2 is part of a continuous rising or falling code sequence generated based on the control word.

[0134] Example 22 is a system for calibrating the phase nonlinearity of a digital-to-time converter, comprising: a phase-locked loop configured to generate a reference signal based on a control word, wherein the frequency of the reference signal is substantially equal to the frequency of the output signal of the digital-to-time converter; a detection circuit configured to measure a time sequence of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and a processing circuit configured to adjust a first entry of a lookup table based on the measured time sequence.

[0135] In Example 23, the digital-to-time converter in the system of Example 22 generates the output signal based on a first entry of the lookup table, wherein the first entry is assigned to a first control code for the digital-to-time converter, which is based on a control word for controlling the frequency of the output signal.

[0136] In Example 24, the phase-locked loop in the system of Example 22 or Example 23 is configured to adjust the phase of the reference signal to be substantially equal to the phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code for the digital-to-time converter, for which the digital-to-time converter is phase-linear.

[0137] In Example 25, the phase-locked loop in the system of Example 24 is further configured to generate the reference signal based on a frequency control word, wherein the detection circuit is further configured to measure, for the second entry, a time offset between a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and wherein the system further comprises a conversion circuit configured to generate the frequency control word based on the time offset.

[0138] In Example 26, the conversion circuit in the system of Example 25 is configured to: calculate a phase error of the reference signal relative to the output signal based on the time offset; and adjust the frequency control word based on the phase error.

[0139] In Example 27, the phase-locked loop in the system as described in Example 24 is further configured to generate the reference signal based on a frequency control word, wherein the detection circuit is further configured to measure a third time sequence of a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level for the second entry; and wherein the system further includes a conversion circuit configured to generate the frequency control word based on the third time sequence.

[0140] In Example 28, the conversion circuit in the system of Example 27 is configured to: calculate a phase error of the reference signal relative to the output signal based on the third time sequence; and adjust the frequency control word based on the phase error.

[0141] In Example 29, the system as described in any one of Examples 25 to 28 also includes a filter coupled between the detection circuit and the conversion circuit, wherein the filter is configured to forward filtered data from the detection circuit to the conversion circuit only if a control signal input to the filter indicates that the digital-to-time converter generates the output signal based on the following entry in the lookup table: the entry is assigned to the following control code for the digital-to-time converter: for this control code, the digital-to-time converter is phase linear.

[0142] In Example 30, the detection circuitry of the system of any preceding example is further configured to measure a predetermined number of time sequences, wherein the processing circuitry is further configured to adjust the first entry based on the predetermined number of time sequences.

[0143] In Example 31, the detection circuit in the system of Example 30 is further configured to measure at least a portion of the predetermined number of time sequences in parallel.

[0144] In Example 32, the processing circuit in the system as described in Example 30 or Example 31 is further configured to: derive an indicator value from the predetermined number of time sequences, the indicator value indicating whether the transition of the output signal from the first signal level to the second signal level or the transition of the reference signal from the first signal level to the second signal level more often leads the other among the predetermined number of time sequences; and adjust the first entry based on the indicator value.

[0145] In Example 33, the processing circuit in the system of Example 32 is further configured to adjust the first entry only if an absolute value of the indicator value is greater than a threshold value.

[0146] In Example 34, the system of any one of Examples 30 to 33 is configured to control the detection circuit to iteratively measure the predetermined number of time sequences, and control the processing circuit to iteratively adjust the first entry based on the predetermined number of time sequences.

[0147] In Example 35, the digital-to-time converter in the system described in Example 34 also generates the output signal based on an additional entry in the lookup table, the additional entry being assigned to an additional control code for the digital-to-time converter; wherein the detection circuit is also configured to measure, for the additional entry, a corresponding time sequence of a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and wherein the processing circuit is further configured to adjust the additional entry based on the corresponding time sequence.

[0148] In Example 36, the detection circuit in the system as described in Example 35 is further configured to measure the corresponding time sequence a predetermined number of times for the additional entries, so that a corresponding predetermined number of time sequences are measured for each of the additional entries, and the processing circuit is further configured to adjust the additional entries based on the corresponding predetermined number of time sequences.

[0149] In Example 37, the system as described in Example 36 is configured to control the detection circuit to iteratively measure a corresponding predetermined number of time sequences for the first entry and the additional entry of the lookup table, and control the processing circuit to iteratively adjust the first entry and the additional entry until a maximum number of iterations is reached or each of the first entry and the additional entry meets a quality standard.

[0150] In Example 38, the detection circuit in the system as described in any of the preceding examples is further configured to measure, for the first entry, a second time sequence of a transition of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level; and the processing circuit is further configured to adjust the first entry based on the second time sequence.

[0151] In Example 39, the processing circuitry in the system of any preceding example is further configured to adjust the first entry by incrementing or decrementing the first entry based on the first time sequence.

[0152] In Example 40, the processing circuit in the system as described in Example 34 is further configured to iteratively adjust the first entry by: incrementing or decrementing the first entry in the first iteration by a first value based on a predetermined number of time sequences of the first iteration; and incrementing or decrementing the first entry in the second iteration by a second value based on a predetermined number of time sequences of the second iteration, wherein the second value is substantially half of the first value.

[0153] In Example 41, the detection circuit in the system as in any preceding example is a nonlinear phase detector.

[0154] Example 42 is a receiver comprising a digital-to-time converter and a system for calibrating phase nonlinearity of the digital-to-time converter according to any one of Examples 22 to 41.

[0155] In Example 43, the receiver of Example 42 further includes a control circuit configured to generate a continuous rising or falling code sequence based on the control word, wherein the first control code is part of the code sequence.

[0156] In Example 44, the receiver of Example 42 or Example 43 further comprises: another phase-locked loop configured to generate an oscillating input signal for the digital-to-time converter.

[0157] In Example 45, the receiver of any one of Examples 42 to 44 further comprises a mixing circuit configured to down-convert the RF receive signal using the output signal.

[0158] Example 46 is a mobile device comprising the receiver according to any one of Examples 42 to 45.

[0159] In Example 47, the mobile device of Example 46 further comprises at least one antenna element coupled to the receiver.

[0160] Example 48 is a device for calibrating the phase nonlinearity of a digital-to-time converter, comprising: a device for generating a reference signal using a phase-locked loop based on a control word, wherein the frequency of the reference signal is equal to the frequency of the output signal of the digital-to-time converter; a device for measuring the time sequence of the transition of the output signal from a first signal level to a second signal level and the transition of the reference signal from the first signal level to the second signal level; and a device for adjusting the first entry of a lookup table based on the measured time sequence.

[0161] In Example 49, the digital-to-time converter in the apparatus of Example 48 generates the output signal based on a first entry of the lookup table, wherein the first entry is assigned to a first control code for the digital-to-time converter that is based on a control word for controlling the frequency of the output signal.

[0162] In Example 50, the device for generating the reference signal in the device as described in Example 48 or Example 49 is further configured to adjust the phase of the reference signal to be substantially equal to the phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code for the digital-to-time converter, and for the second control code, the digital-to-time converter is phase linear.

[0163] Aspects and features mentioned and described in conjunction with one or more of the previously detailed examples and figures may also be combined with one or more other examples in order to replace similar features of the other examples or to introduce the features additionally to the other examples.

[0164] Examples may also be or may relate to a computer program with a program code, which, when executed on a computer or processor, is used to perform one or more of the above methods. The steps, operations, or processes of various methods described above may be performed by a programmed computer or processor. Examples may also cover program storage devices, such as digital data storage media, which are readable by a machine, processor, or computer and have encoded a machine-executable, processor-executable, or computer-executable instruction program. The instructions execute or cause some or all of the actions of the above methods to be performed. Program storage devices may include or may be, for example, digital memories, magnetic storage media such as disks and tapes, hard drives, or optically readable digital data storage media. Additional examples may also cover computers, processors, or control units programmed to perform the actions of the above methods, or (field) programmable logic arrays ((field) programmable logic arrays, (F) PLAs) or (field) programmable gate arrays ((field) programmable gate arrays, (F) PGAs) programmed to perform the actions of the above methods.

[0165] The description and drawings are merely illustrative of the principles of the present disclosure. In addition, all examples described herein are expressly intended for most purposes only to help the reader understand the principles of the present disclosure and the concepts contributed by the inventors to advance the art. All statements herein describing principles, aspects, and examples of the present disclosure, as well as specific examples thereof, are intended to encompass their equivalents.

[0166] A functional block that performs a specific function and is expressed as a “means for…” may refer to a circuit configured to perform the specific function. Therefore, “means for something” can be realized as “means configured or adapted for something,” such as a device or circuit configured or adapted for a corresponding task.

[0167] The functions of the various elements shown in the accompanying drawings, including any functional blocks labeled as "means," "means for providing a sensor signal," "means for generating a transmit signal," and the like, may be implemented in the form of dedicated hardware, such as a "signal provider," "signal processing unit," "processor," "controller," and the like, as well as hardware capable of executing software in conjunction with appropriate software. When provided by a processor, these functions may be provided by a single dedicated processor, by a single shared processor, or by multiple individual processors, some or all of which may be shared. However, the terms "processor" or "controller" are by no means limited to hardware capable of executing software alone, but may include digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read-only memory (ROM), random access memory (RAM), and non-volatile storage devices for storing software. Other hardware, conventional and / or custom, may also be included.

[0168] Block diagrams, for example, may illustrate high-level circuit diagrams that implement the principles of the present disclosure. Similarly, flow charts, job diagrams, state transition diagrams, pseudocode, and the like may represent various processes, operations, or steps that, for example, may be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or claims may be implemented by an apparatus having means for performing each of the individual actions of these methods.

[0169] It is to be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a particular order, unless otherwise expressly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a particular order, unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Such sub-actions may be included in a portion of the disclosure of this single action, unless expressly excluded.

[0170] In addition, the following claims are hereby incorporated into the detailed description, where each claim can stand on its own as a separate example. Although each claim can stand on its own as a separate example, it should be noted that although a dependent claim may refer to a specific combination with one or more other claims in the claims, other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly proposed herein unless a specific combination is stated to be undesirable. In addition, it is intended that features of a claim be included in any other independent claim, even if the claim is not directly dependent on the independent claim.

Claims

1. A method (100) for calibrating phase nonlinearity of a digital-to-time converter, comprising: generating (102) a reference signal using a phase-locked loop based on a control word, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-to-time converter; measuring (104) a temporal sequence of transitions of: a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level, wherein the temporal sequence indicates which of the output signal and the reference signal switches first from the first signal level to the second signal level; and The first entry of the lookup table is adjusted (106) based on the measured temporal sequence.

2. The method according to claim 1, wherein The digital-to-time converter generates the output signal based on a first entry of the lookup table, and wherein the first entry is assigned to a first control code of the digital-to-time converter, the first control code being based on a control word for controlling a frequency of the output signal.

3. The method according to claim 1 or 2, further comprising: The phase of the reference signal is adjusted to be substantially equal to the phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code of the digital-to-time converter for which the digital-to-time converter is phase-linear.

4. The method according to claim 3, wherein: Generating the reference signal is further based on a frequency control word, and wherein adjusting the phase of the reference signal comprises: measuring, for the second entry, a third temporal sequence of transitions of: a transition of the output signal from the first signal level to the second signal level, and a transition of the reference signal from the first signal level to the second signal level; and The frequency control word is generated based on the third time sequence.

5. The method according to claim 4, wherein: Adjusting the frequency control word includes: calculating a phase error of the reference signal relative to the output signal based on the third time sequence; and The frequency control word is adjusted based on the phase error.

6. The method of claim 2, further comprising: measuring a phase error of the reference signal relative to a phase of the output signal generated by the digital-to-time converter based on a second entry in the lookup table, wherein the second entry is assigned to a second control code of the digital-to-time converter for which the digital-to-time converter is phase-linear; and A correction code is generated based on the phase error, wherein the first control code is also based on the correction code.

7. The method according to claim 1 or 2, wherein: Measuring (104) the time sequence includes measuring a predetermined number of time sequences, and wherein adjusting (106) the first entry is based on the predetermined number of time sequences.

8. The method of claim 7, wherein: At least a portion of the predetermined number of time sequences are measured in parallel.

9. The method of claim 7, wherein: Adjusting (106) the first entry based on the predetermined number of chronological sequences includes: deriving an indicator value from the predetermined number of time sequences, the indicator value indicating whether a transition of the output signal from the first signal level to the second signal level or a transition of the reference signal from the first signal level to the second signal level more often leads the other among the predetermined number of time sequences; and The first entry is adjusted based on the indicator value.

10. The method of claim 9, wherein: The first entry is adjusted only when the absolute value of the indicator value is greater than a threshold.

11. The method according to claim 7, wherein: Measuring (104) the predetermined number of time sequences and adjusting (106) the first entry based on the predetermined number of time sequences are performed iteratively.

12. The method of claim 11, wherein: The digital-to-time converter generates the output signal based on further entries in the look-up table, the further entries being assigned to further control codes of the digital-to-time converter, and wherein the method further comprises: measuring for the further entries a respective temporal sequence of transitions of: a transition of the output signal from the first signal level to the second signal level, and a transition of the reference signal from the first signal level to the second signal level; and The further entries are adjusted based on the respective chronological order.

13. The method of claim 12, wherein: Measuring the respective time sequences for the further entries is performed a predetermined number of times such that a respective predetermined number of time sequences is measured for each of the further entries, and wherein adjusting the further entries is based on the respective predetermined number of time sequences.

14. The method of claim 13, wherein: A respective predetermined number of temporal sequences are measured for a first entry and a further entry of the lookup table, and adjusting the first entry and the further entry is iteratively performed until a maximum number of iterations is reached or each of the first entry and the further entry meets a quality criterion.

15. The method of claim 1 or 2, further comprising: measuring for the first entry a second temporal sequence of transitions of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level, Wherein, adjusting the first entry is also based on the second time sequence.

16. The method according to claim 1 or 2, wherein: Adjusting the first item includes: The first entry is incremented or decremented based on the chronological order.

17. The method of claim 11, wherein: Iteratively adjusting the first entry includes: incrementing or decrementing the first entry in the first iteration by a first value based on a chronological order of a predetermined number of first iterations; and The first entry in the second iteration is incremented or decremented by a second value based on the chronological order of the predetermined number of second iterations, wherein the second value is substantially half of the first value.

18. A system (200) for calibrating phase nonlinearity of a digital-to-time converter (210), comprising: a phase-locked loop (230) configured to generate a reference signal (231) based on a control word (205), wherein a frequency of the reference signal (231) is substantially equal to a frequency of an output signal (211) of the digital-to-time converter (210); a detection circuit (240) configured to measure a temporal sequence of transitions of: a transition of the output signal (211) from a first signal level to a second signal level, and a transition of the reference signal (231) from the first signal level to the second signal level, wherein the temporal sequence indicates which of the output signal and the reference signal switches first from the first signal level to the second signal level; and A processing circuit (250) is configured to adjust a first entry (221) of a lookup table (220) based on the measured temporal sequence.

19. The system of claim 18, wherein: The digital-to-time converter (210) generates the output signal (211) based on a first entry (221) of the lookup table (220), wherein the first entry (221) is assigned to a first control code of the digital-to-time converter (210), the first control code being based on a control word (205) for controlling the frequency of the output signal (211).

20. The system of claim 18 or 19, wherein: The phase-locked loop (230) is configured to adjust the phase of the reference signal (231) to be substantially equal to the phase of the output signal (211) generated by the digital-to-time converter (210) based on a second entry in the lookup table (220), wherein the second entry is assigned to a second control code of the digital-to-time converter (210) for which the digital-to-time converter (210) is phase-linear.

21. The system of claim 20, wherein: The phase locked loop (230) is further configured to generate the reference signal (231) based on a frequency control word, The detection circuit (240) is further configured to measure, for the second entry, a third temporal sequence of the following transitions: a transition of the output signal (211) from the first signal level to the second signal level, and a transition of the reference signal (231) from the first signal level to the second signal level; and The system also includes a conversion circuit (280) configured to generate the frequency control word based on the third time sequence.

22. The system of claim 18 or 19, wherein: The detection circuit (240) is further configured to measure a predetermined number of time sequences, and wherein the processing circuit (250) is further configured to adjust the first entry (221) based on the predetermined number of time sequences.

23. The system of claim 22, wherein: The processing circuit (250) is further configured to: deriving an indicator value from the predetermined number of time sequences, the indicator value indicating whether a transition of the output signal (211) from the first signal level to the second signal level or a transition of the reference signal (231) from the first signal level to the second signal level more often precedes the other among the predetermined number of time sequences; and The first entry is adjusted based on the indicator value (221).

24. The system of claim 23, wherein: The processing circuit (250) is further configured to adjust the first entry (221) only if the absolute value of the indicator value is greater than a threshold value.

25. A receiver (670) comprising a digital-to-time converter (610) and a system (630) for calibrating phase nonlinearity of the digital-to-time converter (610) according to any one of claims 18 to 24.

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