Apparatus and Method for Quasi-Resonant Mode Voltage Control of a Switching Converter

Abstract

The present application relates to an apparatus and method for quasi-resonant mode voltage control of a switching converter. A control device for controlling a switching converter includes a switch controller that generates a control signal having a switching period for controlling the switching of a switching element of the switching converter, and for setting a first interval during which current flows in the switch, a second interval during which energy is transferred to a storage element of the switching converter, and a third interval, i.e., a waiting interval, at the end of the second interval. The duration of the first interval is determined based on a control voltage indicative of an output voltage. A predistortion stage receives the control voltage and generates a predistorted control voltage based on the control voltage and a relationship between one of the first time interval and the third time interval and the switching period, wherein the switch controller is configured to control the duration of the first interval based on the predistorted control voltage.

Description

[0001] This application is a divisional application of the patent application with the application date of December 27, 2016, the application number of 201611228258.2, and the invention title of "Device and Method for Quasi-Resonant Mode Voltage Control of a Switching Converter". Technical Field

[0002] The present disclosure relates to a device and a method for quasi-resonant mode voltage control of a switching converter, which is particularly (but without implying any loss of generality) a power factor correction converter (hereinafter referred to as a PFC converter). Background Art

[0003] As is well known, voltage converters used in switch mode power supplies (SMPS) or solid state lighting (SSL) systems are typically used to meet strict specifications regarding the corresponding electrical performance. In particular, the converters are used to ensure a high quality factor (in terms of the basic unit power factor - PF, e.g., greater than 0.9) and high efficiency / low power consumption in the absence of a load (e.g., dissipated power less than 300 mW).

[0004] Typically, these power converters are designed to convert the quantity received at the input, such as an AC voltage from a mains power supply, into a regulated output quantity, such as a DC voltage, to power an electrical load such as an LED cluster.

[0005] For example, a high power factor meets the limits on harmonic current emissions envisaged by standards (e.g., the IEC 61000-3-2 standard in Europe and the JEITA-MITI standard in Japan); while high efficiency / low power consumption meets energy efficiency specifications, such as ENERGY STAR 2.0 for external power supplies or ENERGY STAR 5.0 for computers, etc.

[0006] In particular, when a high output power is desired (e.g., higher than 50 W - 75 W), it is known to use a power converter with a two-stage architecture, where the first stage typically defines a PFC converter, such as a boost type. In this case, the PFC converter performs a boost operation on the AC mains voltage, generating a regulated DC voltage with a value of, for example, 400 V at the output. The PFC converter is controlled by a suitable control device for regulating the power factor in the absorption from the power grid.

[0007] By way of example, Figure 1 a circuit diagram of a power converter is shown, such as a boost type PFC converter indicated as a whole by 1, which is controlled by a corresponding control device indicated by 2 (however, it should be emphasized that the following content can be applied to different converter topologies, such as flyback or buck-boost types).

[0008] The control device 2 is made as an integrated circuit and has a package and corresponding input and output pins. The integrated circuit can be mounted on the same printed circuit board (PCB) together with the circuit components that define the power converter 1.

[0009] In particular, in this configuration, the power converter 1 has: an input terminal IN on which there is an input voltage V in (rectified sine wave), starting from an AC mains voltage V provided, for example, by a mains power supply, the input voltage V AC is generated by a rectifier stage 3 (schematically shown); and an output terminal OUT on which there is an output voltage V in ; and the output voltage V out is, for example, a DC voltage, and the value of the output voltage V out is higher than the value of the input voltage V regulated at a desired value (e.g., 400 V) out IN

[0010] A filter capacitor 4a having a high-frequency filtering function is connected to the input terminal IN, while a storage capacitor 4b having a charge storage function is connected to the output terminal OUT. Both the filter capacitor 4a and the storage capacitor 4b are further connected to a reference terminal or a ground terminal (GND).

[0011] The power converter 1 includes: an inductor 5, which is connected between the input terminal IN and a first internal node N1; a switching element 6, in particular a power MOSFET, which is connected between the first internal node N1 and the reference terminal; and a diode element 7, whose anode is connected to the first internal node N1 and whose cathode is connected to the output terminal OUT.

[0012] The switching element 6 has: a first current-conducting terminal connected to the first internal node N1, in particular the drain terminal of the corresponding MOSFET; a second current-conducting terminal connected to the reference terminal and the control terminal, in particular the source terminal of the corresponding MOSFET; and a control terminal that coincides with the gate terminal of the corresponding MOSFET.

[0013] A voltage divider 8 is connected between the output terminal OUT and the reference terminal and is formed by a first voltage-divider resistor 8a and a second voltage-divider resistor 8b connected in series, which defines an internal node N2, and a feedback voltage V FB is taken from the internal node N2.

[0014] The power converter 1 further includes an auxiliary winding 9, which is magnetically coupled to the inductor 5 and on which there is a monitoring voltage V ZCD

[0015] ​​​The control device 2 has: a first input terminal 2a, which is connected to the second internal node N2 and is designed to receive a feedback voltage V FB ; a second input terminal 2b, which is connected to the auxiliary winding 9 through a first coupling resistor 10 and is designed to receive a monitoring voltage V ZCD , the monitoring voltage V ZCD being based on the voltage across the auxiliary winding 9; and an output terminal 2c, which is connected to the control terminal of the switching element 6 through a second coupling resistor 11 and is designed to provide a control signal GD at an appropriate timing, the control signal GD being used to control the switching of the same switching element 6 in pulse width modulation (PWM).

[0016] The control device 2 has additional terminals 2d, 2e that are respectively connected to the power supply voltage V CC and the reference terminal.

[0017] In particular, the control device 2 can be configured to control the operation of the power converter 1 in a so-called quasi-resonant mode, which is also defined as a "transition mode", "critical mode" or "boundary mode".

[0018] In each switching cycle, the control device 2 controls the closing of the switching element 6 for an interval T ON (the "on" interval of the duty cycle), during which the current from the power supply flows through the inductor 5 and through the switching element 6 to ground, determining the storage of energy in the same inductor 5.

[0019] In voltage control mode, based on the value indicating the output voltage V out , the control device 2 sets the duration of the on interval T ON through an appropriate feedback control loop, in which case the value of the output voltage V out is obtained from the feedback voltage V FB and compared with an appropriate reference voltage (described in detail below).

[0020] In a manner not shown herein, the control loop can alternatively be based on peak current control.

[0021] Then, the control device 2 controls the opening of the switching element 6 for an interval T OFF (the "off" interval of the duty cycle), during which the energy previously stored in the inductor 5 is transferred to the load and the charge storage element 4b via the diode element 7.

[0022] In particular, at the end of the energy transfer, the current in the inductor 5 is zero. Due to the capacitance present at the first internal node N1, mainly due to the parasitic capacitance of the drain terminal of the MOSFET of the switching element 6 and the parasitic capacitance of the diode element 7 (in the off state), the input voltage Vin The resonance condition around the value occurs on the voltage at the same first internal node N1.

[0023] According to the quasi-resonant control mode, the switching element 6 is closed (and the corresponding MOSFET is turned on) when the harmonic oscillation present on the drain voltage of the corresponding MOSFET is minimized, which is with a certain delay relative to the instant when the current in the inductor 5 returns to zero. Thus, the converter operates in a state where switching occurs at zero current and zero voltage, thereby achieving high efficiency and minimum conduction loss. This control is also referred to as "valley switching" as long as the closing of the switching element 6 occurs at the oscillation valley of the MOSFET drain voltage.

[0024] The control device 2 detects the valley condition based on the monitoring voltage V ZCD and thus determines the duration of the cut-off interval T OFF , and the monitoring voltage V ZCD is again based on the voltage across the auxiliary winding 9.

[0025] Figure 2 Shows the current I in the inductor 5 L and the control signal GD (with the conduction interval T ON during which energy is stored in the inductor 5, and the cut-off interval T OFF is shown) corresponding to the graph of the shown control mode. Also shown is the so-called free-wheeling time interval T FW and the delay time interval T R , during the free-wheeling time interval T L the inductor current I FW flows through the diode element 7 (transmitting energy to the storage element 4b), and the delay time interval T R corresponds to the waiting interval for valley switching, that is, the interval between the moment when the inductor current I L becomes zero and the moment when the switching element 6 closes again.

[0026] Refer to Figure 3 , for an example embodiment of a known type of control device 2 implementing the control method discussed above, a more detailed description is now presented. For example, the control device 2 corresponds to the device coded STCMB1 produced and sold by the present applicant.

[0027] The control device 2 includes an error amplifier stage 12 having an inverting input terminal connected to the first input terminal 2a and receiving the feedback voltage V FB , and a non-inverting input terminal receiving a reference voltage V REF with an appropriate value (for example, generated by a bandgap generator within the control device 2, from the supply voltage V CCthe non-inverting input terminal of (starting); the error amplifier stage 12 generates a control voltage V FB based on the difference between the feedback voltage V REF and the reference voltage V C , and the control voltage V C indicates the value of the output voltage V out of the power converter 1.

[0028] In a manner not described in detail, an RC-type compensation network is coupled to the output of the error amplifier stage 12, which is designed to define the DC gain and the corresponding operating frequency bandwidth of the error amplifier stage 12 to ensure the stability of the control loop.

[0029] The control device 2 further includes a comparator stage 15 having a first comparison terminal, a second comparison terminal, and an output. The first comparison terminal is coupled to the output of the error amplifier stage 12 and receives the control voltage V C , the second comparison terminal receives a ramp voltage V R , and the output generates a comparison signal S C .

[0030] In particular, the ramp voltage V C is generated by charging a capacitor 16 having a capacitance C with an appropriate constant charging current I R generated by a current generator 17. A switch 18 controlled by a control signal SW is further connected in parallel with the capacitor element 16 to determine the start of charging and subsequent discharging (and thus determine the alternating rising and falling pattern of the ramp voltage V R ).

[0031] The control device 2 further includes an S / R flip-flop 19 having: a reset input R, which is connected to the output of the comparator stage 15 and receives the comparison signal S C ; a set input S, which is connected to the timing stage 20; an inverted output Q, which defines the above control signal SW for the switch 18; and an output Q, which provides a control signal GD for controlling the switching of the switching element 6 of the power converter 1 via a driver unit 21.

[0032] The timing stage 20 includes a detection unit 26, and the detection unit 26 is coupled to the second input 2b of the control device 2 and receives a monitoring voltage V ZCD . The detection unit 26 generates a detection signal ZCD indicating the start of a zero-current condition in the inductor 5.

[0033] The timing stage 20 further includes: a delay unit 22, which is connected to the output of the detection unit 26 and is configured to apply an appropriate time delay to the detection signal ZCD; an OR logic gate 24, which has a first input connected to the output of the delay unit 22, a second input connected to the starter unit 25, and an output that provides a set signal S to the S / R flip-flop 19.

[0034] During operation, considering that the bandwidth of the error amplifier stage 12 is narrow enough, for example, less than 20 Hz, the control voltage V C can be considered substantially constant (i.e., DC value) during the power grid cycle.

[0035] The ramp voltage V R peaks at V R_pk and can be expressed as:

[0036]

[0037] Assuming that the switching element 6 is initially conducting, the ramp voltage V R increases until it reaches the value of the control voltage V C , thereby switching the output of the comparator stage 15, which resets the S / R flip-flop 19 and causes the disconnection of the same switching element 6.

[0038] Therefore, the output of the comparator stage 15 determines the conduction interval T ON of the switching element 6 according to the following expression:

[0039]

[0040] which is obtained by setting V R_pk = V C starting from the above equation (1).

[0041] It should be noted that under the above assumption that the control voltage V C is constant, the duration of the conduction interval T ON is substantially constant during each power grid cycle.

[0042] After the switching element 6 is disconnected, the inductor 5 transfers the energy accumulated on the storage capacitor 4b and transfers it to the load until it is completely demagnetized. At this time, the diode element 7 stops conducting, and the voltage on the first internal node N1 and thus the drain voltage of the MOSFET float.

[0043] Due to the resonant coupling between the corresponding parasitic capacitance and the inductance of the inductor 5, this voltage will tend to reach the instantaneous power grid voltage via oscillation.

[0044] However, the voltage dip occurring at the above-described first internal node N1 after the inductor 5 is demagnetized is detected by the detection unit 26 of the timing stage 20, and the detection unit 26 generates a pulse when detecting the falling edge of the monitoring voltage V ZCD .

[0045] This pulse in the detection signal ZCD appropriately delayed by the delay unit 22 according to the delay time interval T R thus sets the S / R flip-flop 19 and closes the switching element 6 again, thereby determining a new operation cycle of the power converter 1.

[0046] In this way, the control method contemplates that after the current in the inductor 5 reaches the zero level, after an appropriate delay, the start of each new switching cycle occurs.

[0047] It should be noted that when the monitoring voltage V ZCD is not yet present at the second input 2b of the control device 2, the presence of the OR logic gate 24 in the timing stage 20 enables, for example, the start of a new operation cycle during the startup phase (or when returning from a deactivated condition). This feature also enables the power converter 1 not to stop in the case where the same monitoring voltage V ZCD is not present at the second input 2b for any reason.

[0048] More specifically, and also referring to the figure of Figure 4 (which shows the main electrical quantities in the control device 2), the input voltage V IN can be considered to be substantially a rectified sine wave, i.e., V IN (θ) = V IN，pk |sinθ|, where θ ∈ (0, π).

[0049] Therefore, the peak value I L of the inductor current I L pk is given by:[[]]

[0050]

[0051] Substituting equation (2) into:

[0052]

[0053] From the schematic diagram of Figure 2 it can be noted that the switching cycle T(θ) of the power converter 1 can be expressed as:

[0054] T(θ) = T ON + T FW (θ) + T R (5)

[0055] where, and TFW (θ) + T R constitutes the dead time interval T OFF .

[0056] In addition, the input current I of the power converter 1 IN can be determined by averaging the inductor current I L (t, θ) over one switching period. Referring again to Figure 2 , it can be immediately verified that the following equation holds:

[0057]

[0058] Substituting the previous equations (4) and (5) into equation (6):

[0059]

[0060] In particular, it is found from equation (7) that the input current is purely sinusoidal only when the dead time interval T R is zero or substantially negligible (thus ensuring an ideal unity power factor and an ideal zero distortion).

[0061] However, it is known that there are several cases and applications where, in order to maximize the efficiency of the power converter, the dead time interval T R can be extended, and the dead time interval T R can thus be non - zero.

[0062] For example, the so - called valley - skipping control techniques of known types contemplate skipping one or more valleys of the monitored voltage V ZCD for control purposes in medium or low load conditions in order to limit the switching frequency.

[0063] However, based on the foregoing discussion, an increase in the dead time interval T R results in an increase in the distortion characteristics (the so - called THD - total harmonic distortion - factor) of the power converter, and in particular an increase in the harmonic current emission, which may not allow the achievement of the desired performance (e.g., a THD of less than 10% may be desired).

[0064] In other words, especially in medium or low load operating conditions, existing control solutions involve a trade - off between distortion characteristics and achievable efficiency characteristics. Summary of the Invention

[0065] One or more embodiments of the present disclosure solve the above-mentioned prominent problems and, in particular, provide a control solution that enables the combination of the advantageous effects of the control techniques discussed above, which in turn contemplates maximizing efficiency (by appropriately extending the delay time interval T R ), or alternatively contemplates minimizing harmonic current emissions. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] To better understand the present disclosure, its preferred embodiments are now described by way of non-limiting examples and with reference to the accompanying drawings, in which:

[0067] - Figure 1 shows a general circuit diagram of a power converter of a known type and a corresponding control device;

[0068] - Figure 2 shows a schematic diagram of electrical quantities associated with the Figure 1 power converter;

[0069] - Figure 3 shows a more detailed block diagram of the control device of the Figure 1 power converter;

[0070] - Figure 4 shows a schematic diagram of electrical quantities in the control device of the Figure 3 power converter;

[0071] - Figure 5 shows a block diagram of the control device of a switching converter of the type shown, for example, in Figure 1 according to an embodiment of the present solution;

[0072] - Figure 6 shows a schematic diagram of electrical quantities in the control device of the Figure 5 power converter;

[0073] - Figure 7 is a circuit diagram of a current generator in the control device of the Figure 5 power converter;

[0074] - Figure 8 and Figure 9 respectively show graphs of electrical quantities of the control devices of Figure 3 and Figure 5 ;

[0075] - Figure 10 is a general block diagram of an electronic device using a power converter;

[0076] - Figure 11 shows a circuit diagram of a power converter and a corresponding control device according to another embodiment of the present solution;

[0077] - Figure 12 shows theFigure 11 Graph of the electrical quantity in the power converter;

[0078] - Figure 13 Schematic diagram showing the electrical quantity corresponding to another embodiment of the present solution;

[0079] - Figure 14 Circuit diagram of the control device of the power converter showing the above-mentioned another embodiment according to the present solution; and

[0080] - Figure 15 Shows Figure 14 Graph of the electrical quantity in the control device of. Detailed implementation mode

[0081] Considering that the switching period can be expressed as T(θ) = T ON (θ) + T FW (θ) + T R , and the conduction time interval T ON (θ) depends on the instantaneous grid phase angle θ (where 0 ≤ θ = 2πf L t ≤ π, f L is the grid frequency), the conduction time interval T ON (θ) does not actually have to be constant as in the traditional solution, the above equation (7) can be rewritten as follows:

[0082]

[0083] As will be discussed in detail, one aspect of the present solution stems from the realization of the applicant that a distortion factor can be recognized in the above equation (8), which is associated with the operation of taking the average in the switching period and causes distortion of the value of the input current I IN (θ).

[0084] The distortion factor is given by the following formula:

[0085]

[0086] The distortion factor is thus associated with the switching operation and depends on the time intervals T ON , T FW and T R values. Depending on the phase angle θ, the distortion factor intervenes as a multiplicative factor in the above equation (8), thus distorting the graph of the input current I IN which would otherwise be sinusoidal.

[0087] Therefore, one aspect of the present solution contemplates by applying a control voltage V CThe value is pre-distorted to appropriately compensate for the above distortion. The above pre-distortion is performed by a pre-distortion factor given by the reciprocal of the above distortion factor, and this pre-distortion factor is given by the following formula:

[0088]

[0089] Therefore, assuming that the control voltage V C intervenes as a multiplication factor of the input current I IN in the above equation (8), then this term corresponding to the reciprocal of the distortion term introduced by the above averaging operation cancels out the influence of its distortion substantially.

[0090] Therefore, the control method contemplates the generation of a pre-distorted control voltage V C starting from the control voltage V CT (θ), which is given by the following formula:

[0091]

[0092] where K is an appropriate constant, and V C is the control voltage initially provided in the control device 2 (in the previously described case, it is the voltage present at the output of the error amplifier stage 12) to determine the duration of the conduction interval T ON .

[0093] Once the distortion factor has been eliminated using the above pre-distortion factor, by considering equation (8) and substituting the expression of the pre-distorted control voltage V CT (θ) into it, the following formula is obtained,

[0094]

[0095] which is a perfect sine wave, particularly independent of the duration of the delay time interval T R (and, equivalently, independent of the duration of the conduction interval T ON and the duration of the freewheeling interval T FW ).

[0096] Reference Figure 5 , now a possible embodiment of the control device 30A according to the present solution will be described. It should be noted that, generally, the control device 30A is implemented in the same manner as the previously described control device 2, and can also be used, for example, in the power converter 1, such as a boost-type PFC converter, whose configuration is equivalent to the configuration discussed in reference Figure 1 . However, it should be emphasized that, as shown below and also highlighted on the other hand below, the content described herein can also find advantageous applications in other topologies of power converters and in different configurations of the corresponding control devices.

[0097] As described above Figure 5 As shown, due to the presence of the predistortion stage 32 provided between the output of the error amplifier stage 12 and the inverting input of the comparator stage 15, the control device 30A is different from the above-described control device 2.

[0098] Specifically, the predistortion stage 32 has an input 32a and an output 32b. The input 32a is connected to the output of the error amplifier stage 12 and receives the control voltage V C , and the output 32b provides the predistorted control voltage V CT (θ) to the inverting input terminal of the comparator stage 15.

[0099] The predistortion stage 32 includes a controlled current generator 34 having a control input, which is coupled to the input 32a of the predistortion stage 32 and receives the control voltage V C . The controlled current generator 34 generates a charging current I i at the output at the charging node N CH , and the value of the charging current I CH is based on the control voltage V C according to the following formula:

[0100] I CH (θ) = G M V C (13)

[0101] where G M is the voltage / current gain of the controlled current generator 34.

[0102] As shown, the controlled current generator 34 also has a power supply input, which receives the power supply voltage V CC of, for example, the power converter 1.

[0103] The predistortion stage 32 further includes a charging capacitor 36 connected between the node N i and the reference terminal.

[0104] It should be noted that, depending on the application, the charging capacitor 36 can be integrated with other circuit elements of the control device 30A (i.e., obtained on the same die and / or in the same package); alternatively, the charging capacitor 36 can be a discrete component electrically connected to the input terminal of the control device 30A. In the latter case, the charging node N i constitutes another input terminal of the control device 30A.

[0105] The control device 30A further includes:

[0106] a discharge resistor 38, which is connected to the charging node N i and is also connected to the reference terminal via a discharge switch 39.

[0107] The discharge switch 39 receives an inverted signal As a control signal, the inverted signal constitutes an inverted version of the detection signal ZCD generated by the detection unit 26, indicating the start of a zero-current condition in the inductor 5.

[0108] In use, when the inverted signal is high, i.e., during the time interval T(θ)-T when the inductor 5 is magnetized (see also the subsequent R ), that is, when the inductor current I Figure 6 is non-zero, the discharge resistor 38 is connected in parallel with the charging capacitor 36. L

[0109] When the inverted signal is low, i.e., when the inductor 5 is demagnetized and the inductor current I L is zero, the same discharge resistor 38 is disconnected and decoupled from the charging capacitor 36.

[0110] Thus, the charging capacitor 36 is charged during the delay time interval T when the inductor 5 is demagnetized, and discharges during the remaining time interval of the switching period (T R (θ)+T ON (θ)), during which the inductor 5 is magnetized by the inductor current I FW (θ). L

[0111] In other words, the discharge of the charging capacitor 36 occurs during the time interval in the switching period T when the inductor current I L is non-zero.

[0112] The voltage across the charging capacitor 36 is the pre-distortion control voltage V CT (θ) provided to the inverting input terminal of the comparator stage 15 (it should be noted that no modification is made to the circuit components connected to the non-inverting terminal of the same comparator stage 15).

[0113] Under the assumption that the control voltage V C is substantially constant during a half-cycle of the power grid (as described above), the charging current I CH (θ) is also substantially constant.

[0114] In particular, for the following considerations, it is assumed that the following expression applies:

[0115] T(θ) << R T C T << 1 / f L (14)

[0116] where f L ​​is the grid frequency; that is, assuming that the switching period ratio is much lower than the time constant R T C T defined by the discharge resistor 38 and the charging capacitor 36, and that the same time constant R T C T is much lower than the grid period. If this assumption is valid, the ripple of the switching frequency on the charging capacitor 36 is negligible. Furthermore, the charging current I CH (θ) is substantially constant during each grid half-cycle.

[0117] Applying the charge balance relationship on the charging capacitor 36 (considering that the charging current I CH flows towards the charging capacitor 36 during the entire period T(θ) and discharges towards the reference terminal during the interval T(θ)-T R ), the following expression can be obtained:

[0118]

[0119] Substituting equation (13) for the charging current I CH (θ) into equation (15) and solving for the pre-distorted control voltage V CT (θ), the following expression is obtained:

[0120]

[0121] which has the same form as equation (11) and thus meets the control objective with a constant K given by:

[0122] K = G M R T (17)

[0123] Therefore, it can be concluded that the proposed solution makes it possible to obtain an input current I IN that is always sinusoidal, especially even in the case where the delay time interval T R is non-zero.

[0124] As previously mentioned, in the proposed solution, the conduction interval T ON is not constant as in the traditional solution, but depends on the instantaneous grid phase θ according to the following expression:

[0125]

[0126] In a way similar to that shown previously in Figure 4 (), Figure 6 the main electrical quantities in the control device 30A are shown, the curves of which reflect what has been shown previously.

[0127] Reference Figure 7 , now discuss possible circuit embodiments of the controlled current generator 34, which in this case includes an operational amplifier 40, whose non-inverting terminal is connected to the control input of the controlled current generator 34 and receives the control voltage V C , and whose output terminal is connected to the base terminal of the transistor 41, while its inverting terminal is connected to the emitter terminal of the same transistor 41.

[0128] The controlled current generator 34 further includes: a resistor 43, which is connected between the above-mentioned emitter terminal of the transistor 41 and the reference terminal; and a current mirror 44, which is constituted by a pair of transistors 44a, 44b in a manner known per se (not described in detail herein).

[0129] In particular, the first branch of the current mirror 44 is connected to the collector terminal of the transistor 41, while the second branch of the current mirror 44 is connected to the output of the controlled current generator 34 to provide the charging current I CH .

[0130] It can be immediately verified that in this solution, the charging current I CH is given by the following expression:

[0131]

[0132] where, R M is the resistance of the resistor 43, and s is the mirror factor of the current mirror 44.

[0133] Therefore, the above voltage / current gain G M is given in this case by the following formula

[0134]

[0135] The Applicant has tested and verified the solution proposed by a number of simulation and experimental tests.

[0136] As an example, Figure 8 and Figure 9 provide a comparison between the performance of a control device according to the known art (in particular Figure 8 the control device 2) as shown and the performance of the control device 30 according to the present solution as shown in Figure 3 . Figure 9 In both cases, the power converter operates at half load and the valley skipping mode is enabled to improve efficiency.

[0137] In both cases, the power converter operates at half load and the valley skipping mode is enabled to improve efficiency.

[0138] It can be immediately verified that the proposed solution can greatly reduce the waveform distortion, thus obtaining a significant reduction in the distortion factor THD, from approximately 29% (in the traditional solution) to approximately 10% (in the proposed solution).

[0139] As previously mentioned, the power converter 1 and the corresponding control device 30A can be advantageously used in a switching power supply 50, as Figure 10 shown.

[0140] Specifically, the switching power supply 50 includes, in this example, a rectifier stage 3 (e.g., of the diode bridge type) connected to the power grid 52 via an EMI filter 53 and an input capacitor element 4a connected to the output of the rectifier stage 3, with the input voltage V IN present on the rectifier stage 3.

[0141] As previously defined, the switching power supply 50 also includes a power converter 1, whose input terminals IN are connected to the input capacitor element 4a and whose output terminals OUT are connected to a charge storage element 4b.

[0142] The control device 30A controls the operation of the power converter 1 to ensure a desired power factor in the absorption from the power grid 52.

[0143] The switching power supply 50 also includes an output power converter 56, which, in the example of the DC / DC type, has its input connected to the output capacitor element 4b and is designed to provide an expected value of the output voltage to a load or end user (not shown), which value is, for example, appropriately reduced with respect to the value of the output voltage V OUT value.

[0144] The advantages of the proposed solution clearly emerge from the previous description.

[0145] In any case, it is again emphasized that the present solution allows overcoming the limitations of known types of control solutions, such that, among other features, an ideal sinusoidal input current I IN can be obtained, and in any case a distortion factor of less than 10% can be obtained.

[0146] At the same time, the proposed control solution enables the use, without any impact, of control techniques (such as valley skipping techniques, or techniques generally envisaging an appropriate, even extended duration of the delay time interval T R ) aimed at maximizing the efficiency under any load conditions.

[0147] Finally, it is clear that modifications and variations can be made to what has been described and shown herein, and thus do not depart from the scope of the present disclosure.

[0148] In particular, it is again emphasized that although a boost converter was explicitly mentioned in the previous description, the present solution can also be advantageously applied to other topologies of converters not only for power factor - control applications.

[0149] In this regard, Figure 11 the proposed solution is shown applied to a flyback - type power converter indicated by 1'.

[0150] To avoid burdening the discussion, the circuit configuration of the known - type power converter 1' is not described in detail, but it is only emphasized that the previously described solution also finds a similar application in this power converter 1', with some differences due to its different circuit topology.

[0151] In particular, in this case, the primary winding of the transformer of the flyback converter corresponds to the inductor 5 of the boost converter (and is thus indicated by the same reference numeral). In this case, the inductor current I L flows through the inductor element formed by this primary winding.

[0152] In this case, the control voltage V C is obtained starting from the feedback current I FB which is drawn from the isolated secondary winding 60 of the transformer of the power converter 1'. This feedback current I FB generates the control voltage V FB in the control resistor 51 which is connected between the power supply terminal and the first input terminal 2a of the control device 30B. C In a generally similar manner to that previously described, the control voltage V

[0153] is pre - distorted by the pre - distortion stage 32 to generate the pre - distorted control voltage V C (θ). The pre - distortion stage 32 is obtained in a generally similar manner to that discussed previously, with the only difference being that the discharge switch 39 is controlled by the signal Q of the S / R flip - flop 19 in this case. CT In fact, in this case, it is obvious to those skilled in the art that the distortion factor associated with the averaging operation of the inductor current I

[0154] during the switching period is given by the following formula: L

[0155]

[0156] It should be noted that in this case, this distortion factor is related to the first time interval T ONassociated with the duration. In fact, a negligible delay time interval TR is also assumed, and the distortion factor is non-zero (T ON / T).

[0157] When the signal Q is high (and the control signal GD is also high), that is, during the conduction interval T ON the discharge switch 39 is closed, and when the signal Q is low (and the control signal GD is also low), that is, during the cut-off interval T OFF of the switching period T(θ), the discharge switch 39 is opened.

[0158] Also in this case, the discharge of the charging capacitor 36 occurs during the time interval in the switching period T, during which the current I L is non-zero (in this case, the current I L flows through the inductor element 5 constituted by the primary winding of the transformer).

[0159] Therefore, in this embodiment, the predistortion factor multiplied by the control voltage V C in the predistortion stage 32 is given by the following formula:

[0160]

[0161] For completeness, all meaningful equations related to this other embodiment are provided below in any case. In addition, in a similar manner to the previous discussion, Figure 12 the main electrical quantities in the power converter 1' are shown.

[0162] As described above, the consideration of the charge balance of the charging capacitor 36 with respect to the predistortion stage 32 is applied:

[0163]

[0164] Considering that Equation (13) is also valid in this case, the following formula is obtained:

[0165]

[0166] In addition, considering V R_pk = V CT (θ) for the comparator stage 15 and Equation (2) discussed previously, the following expression is obtained:

[0167]

[0168] Substituting the above Equation (25) into Equation (3), the peak value of the inductor current is given by the following formula:

[0169]

[0170] The input current of the power converter obtained by averaging the inductor current I L (t, θ) over the switching period is given in this case by:

[0171]

[0172] Substituting this into equation (26) and considering the expression V IN (θ) = V IN，pk |sinθ| is valid again:

[0173]

[0174] As required, in particular, independent of the duration of the delay time interval T R , this current is sinusoidal under all conditions.

[0175] Even if not discussed in detail, it will be obvious at this point how the solution under discussion can find advantageous applications in several further topologies of power converters, such as buck - boost, SEPIC, zeta (inverted SEPIC) type and corresponding variants, for example in all converters having a conversion or gain factor between the input and output of this type:

[0176]

[0177] where D is the duty cycle of the switching period, i.e., the ratio between the on - time T ON and the switching period T.

[0178] Now, by way of example, another possible variant of the solution is described with reference again to the application for a boost - type power converter.

[0179] As shown in the graph of Figure 13 and on the other hand will be known to those skilled in the art, due to the parasitic capacitance at the drain terminal of the MOSFET of the switching element of the power converter, the inductor current I L may become negative. Thus, it is possible that the peak value I L of the inductor current I L_pk is lower than the expected value.

[0180] To compensate for this effect, known control solutions envisage, for example, appropriately increasing the duration of the on - time T R by appropriately delaying the start of the ramp of the ramp voltage V ON , the ramp of the ramp voltage V R as long as the inductor current I LIt starts when it becomes positive (instead of being synchronized with the control signal GD for this reason).

[0181] As an alternative to this known technique, as shown in Figure 14 , by appropriately driving the discharge switch 39 of the predistortion stage 32 via a modified version of the inverted signal , this solution can achieve the desired effect of extending the conduction interval T ON 's duration.

[0182] In particular, the discharge switch 39 is driven in this case by a modified drive signal which has a duration appropriately extended relative to the inverted signal .

[0183] As shown in the graphs of Figure 13 and Figure 15 above, the duration of the modified drive signal is appropriately extended relative to the inverted signal , and in this way an increase in the predistortion control voltage V CT can be obtained, and thus the desired increase in the conduction interval T ON .

[0184] In this example, the modified drive signal can be obtained by comparing the inductor current with a positive threshold TH. In particular, the modified drive signal L switches when the inductor current I

[0185] crosses the threshold TH.

[0186] Finally, it should be emphasized that the power converter can also be supplied by a power source different from the mains supply. In addition, the converter according to this solution can advantageously provide a voltage regulator or converter, the above processing has been explicitly referred to a voltage regulator or converter by way of non-limiting example, or provide a current regulator or converter (for example, for an LED driver device or a battery charger).

[0186] The different embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in accordance with the description detailed above. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents given by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A control device for controlling a switching converter, comprising: a switch controller configured to generate a control signal having a switching period for controlling the switching of a switching element of the switching converter, the switching period including a first time interval, a second time interval, and a third time interval, in the first time interval, the control signal causes the switching element to cause an inductor current to flow in an inductor element of the switching converter, in the second time interval, the control signal causes the switching element to cause energy to be transferred from the inductor element, and the third time interval is a waiting interval that extends from a zero level of the inductor current to the next turn-on of the switching element; and a predistortion stage configured to receive a control voltage indicative of an output voltage of the switching converter and generate a predistortion control voltage that is positively correlated with both the control voltage and the third time interval and negatively correlated with the first time interval, wherein the switch controller is configured to control a duration of the first time interval to be positively correlated with the predistortion control voltage.

2. The device according to claim 1, wherein The predistortion stage includes a charging capacitor and a discharge switch configured to be controlled by a timing signal, the discharge switch being configured to control the discharge of the charging capacitor during a time interval in the switching period when the inductor current is not zero.

3. The device according to claim 2, wherein, The predistortion stage is configured to control the charging of the charging capacitor according to the control voltage and provide the predistortion control voltage as a voltage across the charging capacitor.

4. The apparatus according to claim 2, wherein, The predistortion stage includes a current generator configured to receive the control voltage and generate a charging current as a function of the control voltage at a charging node coupled to the charging capacitor.

5. The device according to claim 4, wherein, The predistortion stage further includes a discharge resistor connected to the charging node and the discharge switch and defining a time constant together with the charging capacitor.

6. The device according to claim 2, wherein, The switch controller includes: a comparator stage having a first comparison terminal, a second comparison terminal, and an output, the first comparison terminal being configured to receive the predistortion control voltage, the second comparison terminal being configured to receive a ramp voltage, and the output being configured to provide a comparison signal based on the ramp voltage and the predistortion control voltage; and an S / R flip-flop having a reset input connected to the output of the comparator stage and an output configured to provide the control signal based on the comparison signal.

7. The device according to claim 6, further comprising: an input terminal configured to receive a monitoring voltage from an auxiliary winding magnetically coupled to the inductor element; a detection unit coupled to the input terminal and configured to generate a detection signal indicative of the start of a zero-current condition in the inductor element; and A delay unit electrically coupled to an output of the detection unit and configured to impose a time delay having a duration equal to the third time interval; wherein the S / R flip-flop has a set input coupled to the output of the delay unit.

8. The device according to claim 7, wherein The detection unit is configured to control the discharge switch by using an inverted version of the detection signal as the timing signal.

9. The device according to claim 7, wherein, The S / R flip-flop is configured to generate the timing signal at an output of the S / R flip-flop for controlling the discharge switch.

10. The apparatus according to claim 1, further comprising: An input terminal configured to receive a feedback voltage generated based on the output voltage, and An error amplifier stage having a first input connected to the input terminal and configured to receive the feedback voltage, a second input configured to receive a reference voltage, and an output configured to provide the control voltage based on a difference between the feedback voltage and the reference voltage.

11. A switching converter, comprising: An inductor element; A switching element electrically coupled to the inductor element; A control device, the control device comprising: A switch controller configured to generate a control signal having a switching period for controlling switching of the switching element, the switching period including a first time interval, a second time interval, and a third time interval, wherein in the first time interval, the control signal causes the switching element to cause inductor current to flow in the inductor element, in the second time interval, the control signal causes the switching element to cause energy to be transferred from the inductor element, and the third time interval is a waiting interval that extends from a zero level of the inductor current to a next turn-on of the switching element; And A predistortion stage configured to receive a control voltage indicative of an output voltage of the switching converter and generate a predistortion control voltage that is positively correlated with both the control voltage and the third time interval, and the predistortion control voltage is negatively correlated with the first time interval, wherein the switch controller is configured to control a duration of the first time interval to be positively correlated with the predistortion control voltage.

12. The switching converter according to claim 11, wherein the predistortion stage includes a charging capacitor and a discharge switch configured to be controlled by a timing signal, the discharge switch being configured to control discharge of the charging capacitor during a time interval in the switching period when the inductor current is non-zero.

13. An electronic device, comprising: A switching converter including an inductor element, a switching element electrically coupled to the inductor element, and an output electrically coupled to the inductor element; An output stage having an input electrically coupled to the output of the switching converter and configured to provide a regulated amount to a load; And A control device configured to control the switching converter, the control device comprising: A switch controller configured to generate a control signal having a switching period for controlling the switching of the switching element, the switching period including a first time interval, a second time interval, and a third time interval. During the first time interval, the control signal causes the switching element to cause an inductor current to flow in the inductor element. During the second time interval, the control signal causes the switching element to cause energy to be transferred from the inductor element. The third time interval is a waiting interval that extends from the zero level of the inductor current to the next turn-on of the switching element; And A predistortion stage configured to receive a control voltage indicating the output voltage of the switching converter and generate a predistorted control voltage that is positively correlated with both the control voltage and the third time interval, and the predistorted control voltage is negatively correlated with the first time interval, wherein the switch controller is configured to control the duration of the first time interval to be positively correlated with the predistorted control voltage.

14. The apparatus according to claim 13, comprising an input stage including the converter configured to be coupled to a power supply and provide an input quantity; wherein the control device is configured to control a power correction factor in power absorption from the power supply.

15. A control method comprising: Generating a control signal having a switching period for controlling the switching of a switching element of a switching converter, the switching period including a first time interval, a second time interval, and a third time interval. During the first time interval, an inductor current flows in an inductor element of the switching converter for energy storage. During the second time interval, energy is transferred to a storage element through a diode element. The third time interval is a waiting interval that extends from the zero level of the inductor current to the next turn-on of the switching element; Receiving a control voltage indicating the output voltage of the switching converter; Applying predistortion to the control voltage by a predistortion factor to produce a predistorted control voltage that is positively correlated with both the control voltage and the third time interval, and the predistorted control voltage is negatively correlated with the first time interval; And Controlling the duration of the first time interval to be positively correlated with the predistorted control voltage.

16. The method according to claim 15, wherein, The predistortion factor is given by the ratio between the switching period and the switching period minus the third time interval.

17. The method according to claim 15, wherein, The predistortion factor is given by the ratio between the switching period and the first time interval.

18. The method according to claim 15, wherein Applying the predistortion to the control voltage includes: during a time interval when the inductor current in the inductor element in the switching period is non-zero, discharging a charging capacitor using a discharge current that is a function of the control voltage; the voltage across the charging capacitor is the predistorted control voltage.

19. The method according to claim 15, wherein, Controlling the duration of the first time interval includes: comparing the predistortion control voltage with a ramp voltage and generating a comparison signal based on the comparison; and setting a first boundary of the first time interval when the comparison signal switches.

20. The method according to claim 19, wherein The converter includes an auxiliary winding magnetically coupled to the inductor element, and controlling the duration of the first time interval includes: generating a detection signal indicating the start of a zero current condition in the inductor element according to a monitored voltage on the auxiliary winding; and setting a second boundary of the first time interval by applying a time delay equal to the duration of the third time interval to the detection signal.

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