A wireless repeater with adaptive multi-carrier, multi-frequency and multi-band selection

Abstract

The present invention provides an adaptive multi-carrier, multi-frequency, and multi-band wireless repeater, comprising a signal receiver / transmitter, a low noise amplifier, a modem, a clock chip, a second processor, a power amplifier, a first processor, and at least one digital signal processor. The signal receiver / transmitter receives a signal, amplifies the signal through a low noise amplifier, and then down-converts the signal through the digital signal processor. Then, the analog-to-digital signal is converted into a digital signal, which is input into the first processor for digital down-conversion, extraction, and filtering. Channels of various bandwidths are output, and the frequency point, bandwidth, and number of carriers of the working signal are calculated for use by the system. Then, the signal is interpolated, filtered, and digitally up-converted by an NCO, and then output to the digital signal processor for digital-to-analog conversion. At the same time, the radio frequency end is up-converted, and then sent to the power amplifier. After amplification and output, the signal is covered, thereby realizing the functions of multi-carrier, multi-frequency, and multi-bandwidth.

Description

[Technical field]

[0001] The present invention relates to the field of mobile communication technology, in particular to an adaptive multi-carrier, multi-frequency and multi-band wireless repeater. [Background technology]

[0002] With the rapid development of mobile communications, operators have continuously increased their requirements for mobile network coverage. Wireless repeaters play an important role in indoor and outdoor mobile communication signal coverage. Due to the limited coverage area of ​​base stations, it is difficult to add new base stations to the network after the base station coverage reaches a certain level. At the same time, the cost of building base stations is too high and the infrastructure is relatively complex. Especially in some remote areas with less business volume, only wireless repeaters, such as wireless remote devices, are needed. They are low-cost and easy to install. Wireless repeaters are used in areas where base station signals are too weak. As a relay, they amplify the base station signal and then extend it to more distant areas to expand the coverage of the network, improve and optimize the quality of network signal coverage, and have been widely used in communication networks.

[0003] The existing repeater is generally composed of antennas, RF duplexers, low noise amplifiers, mixers, electrically adjustable attenuators, filters, power amplifiers and other components or modules. These fixed modules can only replace the hardware when re-planning the frequency band and bandwidth. At present, the communication standards have developed from 2G, 3G, 4G to the current 5G, the existing walkie-talkie communication standards, and some civilian communication standards. The entire communication network has the coexistence of different communication standards, and different communication standards have multiple carriers, multiple bandwidths, and multiple frequencies. Various communication equipment of different standards will inevitably be used. This will cause a problem. Due to the increase in business volume, some areas need to increase the number of carriers, expand the bandwidth, or move the frequency. In particular, the emergence of 5G will re-plan the original frequency band and bandwidth. This will cause the originally installed equipment to be unusable, and the equipment needs to be redeveloped to replace it, or it needs to be manually upgraded, which greatly increases the labor cost, equipment replacement cost, and maintenance cost. [Summary of the invention]

[0004] In order to overcome the defects of the existing equipment, the present invention provides an adaptive multi-carrier, multi-frequency, and multi-band wireless repeater, which can adaptively complete the setting of multi-carrier, multi-center frequency, and multi-band without manual intervention.

[0005] The present invention is implemented as follows: an adaptive multi-carrier, multi-frequency, multi-band wireless repeater, comprising

[0006] Signal receiver / transmitter;

[0007] A low noise amplifier, the low noise amplifier is connected to the signal receiver / transmitter;

[0008] At least one digital signal processor integrating radio frequency, analog-to-digital and digital-to-analog conversion, each of the digital signal processors being connected to the low noise amplifier;

[0009] A power amplifier connected to each of the digital signal processors;

[0010] a first processor connected to each of the digital signal processors;

[0011] a second processor, the second processor being connected to the first processor and each of the digital signal processors respectively;

[0012] A clock chip, wherein the clock chip is respectively connected to the first processor, the second processor and each of the digital signal processors;

[0013] Modem, the Modem is connected to the second processor.

[0014] Furthermore, the digital signal processor is an AD80438 chip.

[0015] Furthermore, there are four digital signal processors.

[0016] Furthermore, the first processor is an FPGA.

[0017] Furthermore, the second processor is an ARM processor.

[0018] Furthermore, the signal receiver / transmitter is an antenna.

[0019] Furthermore, the narrowband mode in the first processor is: the first processor first performs NCO frequency selection, then uses CIC for extraction, then performs FIR single-rate filtering, then performs CIC interpolation, and finally performs NCO digital up-conversion back to the original frequency.

[0020] Furthermore, the broadband mode in the first processor is: the first processor first performs digital down-conversion to perform NCO frequency selection; then performs decimation and interpolation, or direct FIR single-rate filtering; and finally performs NCO digital up-conversion to return to the original frequency.

[0021] Further, the adaptive mode in the first processor is: firstly, a narrowband signal with a frequency F is generated in the first processor, and frequency sweep is performed at intervals of the frequency F;

[0022] At each frequency point of frequency F, the average power of each point is calculated by the formula of I2+Q2, where I and Q are complex numbers. The real signal can generate one I signal and one Q signal through modulation, and the phase difference between the I signal and the Q signal is 90 degrees;

[0023] When all the frequency sweeps are completed, the continuous bandwidth and the number of discontinuous carriers are calculated;

[0024] Calculate the center frequency of the carrier bandwidth;

[0025] Calculate the number of carriers, the bandwidth of the carriers, and the frequency of the carriers; finally, transfer the number of carriers, the bandwidth of the carriers, and the frequency of the carriers to the second processor, and the second processor calculates according to the transmitted parameters and sets the calculated filter coefficients to the broadband and narrowband filter channels of the first processor accordingly.

[0026] The advantages of the present invention are as follows: the present invention provides an adaptive multi-carrier, multi-frequency, and multi-band wireless repeater, comprising a signal receiver / transmitter, a low noise amplifier, a modem, a clock chip, a second processor, a power amplifier, a first processor, and at least one digital signal processor integrating radio frequency, analog-to-digital, and digital-to-analog conversion. The signal receiver / transmitter receives a signal, and then sends it to the low noise amplifier for signal amplification, and then sends it to the digital signal processor for down-conversion, and then converts the analog-to-digital signal into a digital signal, and inputs it into the first processor. The first processor performs digital down-conversion, extraction, and filtering, and outputs channels of various bandwidths, calculates the frequency point, bandwidth, and number of carriers of the working signal for use by the system, and then performs interpolation, filtering, and NCO digital up-conversion, and outputs it to the digital signal processor for digital-to-analog conversion. At the same time, the radio frequency end of the digital signal processor performs up-conversion, and then sends it to the power amplifier, and after amplification and output, the signal is covered, thereby realizing the functions of multi-carrier, multi-frequency, and multi-bandwidth.

Brief Description of the Drawings

[0027] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0028] Figure 1 It is the hardware principle diagram of the present invention.

[0029] Figure 2 Design block diagram for narrowband mode.

[0030] Figure 3 Design block diagram for broadband mode.

[0031] Figure 4 Design block diagram of adaptive mode. [Specific implementation method]

[0032] See also Figures 1 to 4 shown.

[0033] The present invention provides an adaptive multi-carrier, multi-frequency, and multi-band wireless repeater, comprising

[0034] A signal receiver / transmitter, used for receiving and transmitting signals, and in a specific implementation, an antenna may be used;

[0035] A low noise amplifier, which is connected to the signal receiver / transmitter; the low noise amplifier is used to amplify the useful signal, suppress the noise signal in the signal, and improve the signal-to-noise ratio; Figure 1 The LAN in the figure is the low noise amplifier.

[0036] At least one digital signal processor integrating radio frequency, analog-to-digital and digital-to-analog conversion, each of which is connected to the low noise amplifier; the digital signal processor is a chip integrating radio frequency and analog-to-digital and digital-to-analog conversion, so that the signal input from the low noise amplifier can be down-converted, and then the analog-to-digital signal is converted into a digital signal and sent to the first processor; or the signal fed back by the first processor is digital-to-analog converted, and the radio frequency end of the digital signal processor is up-converted, and then sent to the power amplifier for amplification and output.

[0037] A power amplifier, the power amplifier is connected to each of the digital signal processors; the power amplifier is named power amplifier in English, abbreviated as PA, which is referred to as "power amplifier", and refers to an amplifier that can generate maximum power output to drive a certain load under given distortion conditions. Figure 1 The PA in the figure is the power amplifier.

[0038] The first processor is connected to each of the digital signal processors; the first processor is mainly used for filtering and frequency shifting of signals, and in specific implementation, FPGA can be used. FPGA is a field programmable device with high flexibility for signal processing.

[0039] The second processor is connected to the first processor and each of the digital signal processors respectively; the second processor is mainly used to configure the digital signal processor, the first processor, and the clock chip, so as to realize remote parameter setting without having to go to the repeater site for setting. At the same time, information is transmitted through the modem to communicate remotely with the computer room, for example, remote alarm reminders and remote parameter settings are performed with the computer room. In a specific implementation, the second processor can adopt an ARM processor.

[0040] A clock chip, the clock chip is connected to the first processor, the second processor and each of the digital signal processors respectively; the clock chip is mainly used to provide multiple synchronous clocks for each chip of the digital module. In a specific embodiment, the clock chip is AD04805, which can output multiple synchronous clocks for use by multiple processors and modules.

[0041] Modem, the Modem is connected to the second processor. The Modem is used to realize remote communication between the second processor and the computer room to realize information transmission. Modem is also called a modem, commonly known as a "cat".

[0042] In a specific implementation, a preferred embodiment is: the digital signal processor is an AD80438 chip. The AD80438 chip is a single-channel integrated RF, analog-to-digital and digital-to-analog conversion chip, with a frequency range of 300M to 6000M, which can realize the design of both uplink and downlink links.

[0043] There are four digital signal processors. The design of four digital signal processors is mainly to meet the needs of full network signal coverage. One channel of the AD80438 chip is a carrier, so four AD80438 chips can also form four carriers. By setting parameters to the ARM processor through the remote modem, the ARM processor will configure the AD80438 chip accordingly, modify its filtering parameters and frequency, and realize the change of bandwidth and frequency.

[0044] The first processor is an FPGA. In a specific embodiment, the FPGA is an A7 chip of Xilinx. Since FPGA is a field programmable device, it has high flexibility for signal processing, and various functional requirements can be achieved by simply modifying the software. Based on the hardware of the present invention, without innovating the software program, the number of multi-carriers achieved is limited, that is, one carrier corresponds to one AD80438 chip. If the narrowband mode, broadband mode, and adaptive mode are designed based on the hardware of the present invention (that is, only 4 AD80438 chips are needed), the functions of multi-carrier, multi-frequency selection, and multi-band selection can also be achieved, thereby adapting to the use requirements of different scenarios without adding AD80438 chip hardware equipment, reducing hardware costs. The design of narrowband mode, broadband mode, and adaptive mode is mainly implemented inside the PFGA.

[0045] The second processor is an ARM processor.

[0046] The signal receiver / transmitter is an antenna.

[0047] The narrowband mode in the first processor is: the first processor first performs NCO frequency selection, then uses CIC for extraction, then performs FIR single-rate filtering, then performs CIC interpolation, and finally performs NCO digital up-conversion back to the original frequency.

[0048] The broadband mode in the first processor is: the first processor first performs digital down-conversion to perform NCO frequency selection; then performs decimation and interpolation, or direct FIR single-rate filtering; and finally performs NCO digital up-conversion to return to the original frequency point.

[0049] The adaptive mode in the first processor is: firstly, a narrowband signal with a frequency F is generated in the first processor, and a frequency sweep is performed at intervals of a frequency F;

[0050] At each frequency point of frequency F, the average power of each point is calculated by the formula of I2+Q2, where I and Q are complex numbers. The real signal can generate one I signal and one Q signal through modulation, and the phase difference between the I signal and the Q signal is 90 degrees;

[0051] When all the frequency sweeps are completed, the continuous bandwidth and the number of discontinuous carriers are calculated;

[0052] Calculate the center frequency of the carrier bandwidth;

[0053] Calculate the number of carriers, the bandwidth of the carriers, and the frequency of the carriers; finally, transfer the number of carriers, the bandwidth of the carriers, and the frequency of the carriers to the second processor, and the second processor calculates according to the transmitted parameters and sets the calculated filter coefficients to the broadband and narrowband filter channels of the first processor accordingly.

[0054] Downlink: The base station signal is received via the antenna, sent to the low noise amplifier, input by the low noise amplifier, and then down-converted by the AD80438 chip. The AD80438 chip then converts the analog-to-digital signal into a digital signal and inputs it into the main processor FPGA. The FPGA performs NCO digital down-conversion, extraction, filtering, and outputs channels of various bandwidths. The FPGA then undergoes interpolation, filtering, and NCO digital up-conversion, and outputs it to the AD80438 chip for digital-to-analog conversion. At the same time, the RF end of the AD80438 chip performs up-conversion, and then sends it to the power amplifier for amplification and output, and then transmits it through the antenna to cover the signal.

[0055] Uplink: The signal of the mobile phone user is received by the antenna, sent to the low noise amplifier, input by the low noise amplifier, and then down-converted by the AD80438 chip. The AD80438 chip converts the analog-to-digital signal into a digital signal and inputs it into the main processor FPGA. The FPGA performs NCO digital down-conversion, extraction, filtering, and outputs channels of various bandwidths. The FPGA then undergoes interpolation, filtering, and NCO digital up-conversion, and outputs it to the AD80438 chip for digital-to-analog conversion. At the same time, the RF end of the AD80438 chip performs up-conversion, and then sends it to the power amplifier for amplification and output, and then transmits it through the antenna to the base station, forming a loop of the signal link.

[0056] Example:

[0057] The antenna receives the signal, sends it to the low noise amplifier, passes through the low noise amplifier input, and then passes through the AD80438 chip to downconvert to 0 frequency, and its 0 frequency bandwidth is 100M. The frequency used is determined by the actual project usage requirements. For example, the sampling rate used is 122.88M, so it is designed according to the signal with 100M bandwidth, because the bandwidth of one carrier of 5G is 100M at present. Then the AD80438 chip converts the analog-to-digital signal into a digital signal, inputs it into the main processor FPGA, and the FPGA performs NCO digital downconversion, extraction, filtering, and outputs channels of various bandwidths. At this time, if the FPGA is not innovatively designed in the software program, only a limited number of multi-carriers, multi-center frequencies (i.e., multi-selective frequencies), and multi-bandwidths (i.e., multi-selective bands) can be selected. On the hardware basis of the present invention, to realize the functions of multi-carrier, multi-selective frequency, and multi-bandwidth, it is necessary to process broadband mode, narrowband mode, and adaptive mode. The difference between broadband and narrowband modes is mainly to save FPGA resources. The broadband mode is defined as 1M to 100M, and the narrowband mode is defined as 6.25K to 1M. The filtering processing mechanisms of the two modes are different. The adaptive mode mainly scans the frequency through a narrowband signal of 3.125K, and makes power judgments at each interval point to calculate the frequency, bandwidth, and number of carriers of the working signal for the system to use. Then the FPGA undergoes interpolation, filtering, and NCO digital up-conversion, and outputs to the AD80438 chip for digital-to-analog conversion. At the same time, the RF end of the AD80438 chip performs up-conversion, and then sends it to the power amplifier for amplification and output to cover the signal.

[0058] Figure 1The hardware schematic diagram of the present invention. Among them, the AD80438 chip is a single-channel integrated RF, analog-to-digital and digital-to-analog conversion chip, and its frequency range is: 300M to 6000M, which can realize the design of two uplink and downlink links. The design of 4 AD80438 chips is mainly to meet the needs of full network signal coverage. The main processing chip FPGA adopts Xilinx's A7 chip. Since FPGA is a field programmable device with high flexibility for signal processing, various functional requirements can be achieved by simply modifying the software. The clock chip is mainly used to provide multiple synchronous clocks for each chip of the digital module board, that is, to provide multiple synchronous clocks for the AD80438 chip and FPGA. The ARM processor is mainly used to configure and start the AD80438 chip, FPGA, and clock chip, and to transmit information through the Modem to remotely warn and remind the computer room, as well as remote parameter settings.

[0059] Figure 2 The design of narrowband mode is mainly implemented inside FPGA. The baseband sampling rate of AD80438 chip is 122.88M. The narrowband of this design is defined as 6.25K to 1M. Since the number of carriers of narrowband signals is relatively large and the bandwidth of narrowband is relatively small, such as 25K bandwidth signal, the sampling rate needs to be extracted from 122.8M to a sampling rate close to 25K, so as to reduce the filter order. For example, the processing for 25K bandwidth is to extract 96 from 122.88M to get a sampling rate of 1.28M, and then use 1.28M to perform single-rate filtering for 6.25K bandwidth, and its order is 58th order.

[0060] In order to save FPGA resources, the NCO frequency selection of the corresponding frequency point is first performed, and then CIC is used for decimation. After the sampling rate is reduced, FIR single-rate filtering is performed, and then CIC corresponding interpolation is performed to insert the rate to 122.88M, and finally NCO digital up-conversion is performed. The specific decimation rate, filter coefficient, and number of carriers need to be set through ARM.

[0061] Figure 3The design for broadband mode is mainly implemented inside FPGA. The baseband sampling rate of AD80438 chip is 122.88M. For example, the definition of narrowband is 1M to 100M. Two filtering channels are designed in broadband. The first one is the bandwidth of 1M to 20M, which needs to be reduced from 122.88M to 30.72M. The second one is the bandwidth of 20M to 100M, which is directly filtered at a single rate of 122.88M. The signal processing process: the signal input of AD80438 chip, and then digital down-conversion is performed in FPGA for NCO frequency selection. The first method is to extract and interpolate to 4, and the second method is to directly filter at a single rate of FIR. Finally, NCO digital up-conversion is performed and the output is output to AD80438 chip.

[0062] Figure 4 Designed for adaptive mode, this module is mainly used to determine the number of carriers, carrier frequency, and carrier bandwidth of the system. Of course, the premise is that the maximum number of carriers should be designed in FPGA to meet the needs of actual applications. Since the AD80438 chip is an integrated AD, DA, and RF chip, it can meet our needs for different frequencies. First of all, the adaptive frequency range is within 100M. If the equipment on site needs to be changed to a frequency range beyond the 100M range, the machine room needs to set the RF frequency of the AD80438 chip through the Modem. For example: the original frequency band is 1.9G, and now it needs to be changed to 2.6G. There, only need to send a signal to the wireless repeater equipment through the Modem in the machine room, and the 100M bandwidth signal can be moved to 2.6G. The baseband sampling rate of the AD80438 chip is 122.88M. In order to realize the recognition of 6.15K to 100M bandwidth, first generate a 3.125K narrowband signal in the FPGA and perform frequency sweeping at intervals of 3.125K. Each 3.125K frequency point, through I 2 +Q 2 The formula is used to calculate the average power of each point, where I and Q are complex expressions. Real signals can be modulated to generate one I signal and one Q signal. The I signal and the Q signal are 90 degrees out of phase. When the frequency sweep from 0M to 100M is completed, it can be concluded that the continuous bandwidth is how many M, and how many discontinuous carriers there are. Knowing the size of the bandwidth, the center frequency of this carrier bandwidth can be calculated. Then it can be obtained how many carriers there are, how much the bandwidth of the carrier is, and how much the frequency of the carrier is. Finally, these parameter settings are transferred to the ARM processor, and the ARM processor calculates according to the parameters transmitted, and calculates the filter coefficient of the filter. A specific calculation implementation example is:

[0063] The ARM processor runs a Linux system, and the remezord function in matlab is run through the ARM processor. The remezord function uses the best approximation maximum and minimum criterion algorithm to design the filter.

[0064] The .m file it runs is:

[0065]

[0066]

[0067] b is the obtained filter coefficient:

[0068]

[0069] Finally, b is converted into a hexadecimal number and set to the FPGA broadband and narrowband filter channels for corresponding broadband and narrowband filtering. Finally, the center frequency, bandwidth, and number of carriers can be set adaptively without manual intervention. This realizes an intelligent adaptive multi-frequency and multi-bandwidth digital wireless station device.

[0070] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. An adaptive multi-carrier, multi-frequency, and multi-band wireless repeater, characterized by: include Signal receiver / transmitter; A low noise amplifier, the low noise amplifier is connected to the signal receiver / transmitter; At least one digital signal processor integrating radio frequency, analog-to-digital and digital-to-analog conversion, each of the digital signal processors being connected to the low noise amplifier; A power amplifier connected to each of the digital signal processors; a first processor connected to each of the digital signal processors; a second processor, the second processor being connected to the first processor and each of the digital signal processors respectively; A clock chip, wherein the clock chip is respectively connected to the first processor, the second processor and each of the digital signal processors; Modem, the Modem is connected to the second processor; The narrowband mode in the first processor is: the first processor first performs NCO frequency selection of the frequency point, then uses CIC for extraction, then performs FIR single rate filtering, then performs CIC interpolation, and finally performs NCO digital up-conversion to return to the original frequency point; The broadband mode in the first processor is: the first processor first performs digital down-conversion to perform NCO frequency selection; then performs decimation and interpolation, or direct FIR single-rate filtering; and finally performs NCO digital up-conversion to return to the original frequency point; The adaptive mode in the first processor is: firstly, a narrowband signal with a frequency F is generated in the first processor, and an interval frequency sweep with a frequency F is performed; Each frequency point is F, through I 2 +Q 2 The average power of each point is calculated by the formula, where I and Q are complex expressions. The real signal can generate one I signal and one Q signal through modulation. The phase difference between the I signal and the Q signal is 90 degrees. When all frequency sweeps are completed, the size of the continuous bandwidth and the number of discontinuous carriers are calculated; Calculate the center frequency of the carrier bandwidth; The number of carriers, the bandwidth of the carriers, and the frequency of the carriers are calculated; finally, the number of carriers, the bandwidth of the carriers, and the frequency of the carriers are transferred to the second processor, and the second processor calculates the filter coefficients of the filter according to the parameters transmitted, and transmits the settings corresponding to the filter coefficients of the filter to the broadband and narrowband filtering channels of the first processor to perform corresponding broadband mode and narrowband mode filtering processing.

2. The adaptive multi-carrier, multi-frequency, and multi-band wireless repeater according to claim 1, characterized in that: The digital signal processor is an AD80438 chip.

3. The adaptive multi-carrier, multi-frequency, and multi-band wireless repeater according to claim 1 or 2, characterized in that: There are four digital signal processors.

4. The adaptive multi-carrier, multi-frequency, and multi-band wireless repeater according to claim 1, characterized in that: The first processor is an FPGA.

5. The adaptive multi-carrier, multi-frequency, and multi-band wireless repeater according to claim 1, characterized in that: The second processor is an ARM processor.

6. The adaptive multi-carrier, multi-frequency, and multi-band wireless repeater according to claim 1, characterized in that: The signal receiver / transmitter is an antenna.

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