Array substrate, light control panel, and display device

Abstract

An array substrate, a light control panel, and a display device. The array substrate includes a data line layer, and a substrate, a first electrode layer, an insulating layer, and a second electrode layer sequentially arranged. The first electrode layer includes a plurality of gate lines, each of the plurality of gate lines extends integrally along the first direction and includes a plurality of first folded line structures directly connected in sequence in the first direction; the data line layer includes a plurality of data lines, each of the plurality of data lines extends integrally along a second direction intersecting the first direction; the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of light control pixel units; the second electrode layer includes a plurality of common electrodes arranged in an array, and each of the plurality of common electrodes is disposed in at least one of the plurality of light control pixel units; at least one of the plurality of gate lines and at least one of the common electrodes overlap at least partially in the orthographic projection on the first electrode layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a light control panel, and a display device. Background Art

[0002] A liquid crystal display device includes a backlight module (backlight unit) and a liquid crystal panel. The backlight module is disposed on the non-display side of the liquid crystal panel to provide a light source for the display operation of the display panel. The liquid crystal panel includes a polarizer, an array substrate, a counter substrate, and a liquid crystal molecule layer filled between the two substrates. The liquid crystal display device deflects the liquid crystal molecules in the liquid crystal molecule layer by forming an electric field between the array substrate and the counter substrate. The deflected liquid crystal molecules cooperate with the polarizer to form a liquid crystal light valve. Since the liquid crystal molecule layer itself does not emit light, the backlight module is required to implement the display function. With the continuous development of display technology, users have put forward higher and higher requirements for the contrast, brightness uniformity, etc. of the display device. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an array substrate, which includes a data line layer, and a substrate, a first electrode layer, an insulating layer, and a second electrode layer sequentially disposed. The first electrode layer includes a plurality of gate lines, and each of the plurality of gate lines extends integrally along the first direction and includes a plurality of first folded line structures directly connected in sequence in the first direction; the data line layer includes a plurality of data lines, and each of the plurality of data lines extends integrally along a second direction intersecting the first direction; the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of light control pixel units; the second electrode layer includes a plurality of common electrodes arranged in an array, and each of the plurality of common electrodes is disposed in at least one of the plurality of light control pixel units; and at least one of the plurality of gate lines and at least one of the common electrodes overlap at least partially in the orthographic projection on the first electrode layer.

[0004] For example, in at least one example of the array substrate, the orthographic projections on the first electrode layer of the two opposite sides of each of the plurality of common electrodes in the second direction respectively overlap with one side of the corresponding two gate lines close to each of the plurality of common electrodes.

[0005] For example, in at least one example of the array substrate, a gap is provided between two adjacent common electrodes in the second direction, and the gate line that overlaps the orthographic projections on the first electrode layer of the two adjacent common electrodes in the second direction overlaps with the orthographic projection of the gap on the first electrode layer.

[0006] For example, in at least one example of the array substrate, each of the plurality of common electrodes includes: a plurality of strip electrodes arranged side by side in the first direction, and a first connection sub-electrode and a second connection sub-electrode that are opposite sides of each of the plurality of common electrodes in the second direction; the first connection sub-electrode is connected to the first ends of the plurality of strip electrodes, the second connection sub-electrode is connected to the second ends of the plurality of strip electrodes; and the orthographic projections of the first connection sub-electrode and the second connection sub-electrode on the first electrode layer respectively partially overlap with one side portions of corresponding two gate lines close to each of the plurality of common electrodes.

[0007] For example, in at least one example of the array substrate, each of the first connection sub-electrode and the second connection sub-electrode has the same extension trend as a corresponding region of the plurality of gate lines, the corresponding region of the plurality of gate lines being the region of the plurality of gate lines that overlaps with each of the first connection sub-electrode and the second connection sub-electrode in the second direction; and each of the plurality of strip electrodes has the same extension trend as a corresponding region of the plurality of data lines, the corresponding region of the plurality of data lines being the region of the plurality of data lines that overlaps with the plurality of strip electrodes in the first direction.

[0008] For example, in at least one example of the array substrate, each of the plurality of data lines includes a plurality of second broken line structures directly connected in sequence in the second direction; the plurality of first broken line structures included in the plurality of gate lines correspond one-to-one with the plurality of light control pixel units, and the plurality of second broken line structures included in the plurality of data lines correspond one-to-one with the plurality of light control pixel units.

[0009] For example, in at least one example of the array substrate, the first electrode layer further includes a plurality of pixel electrodes; each of the plurality of pixel electrodes is disposed in a corresponding light control pixel unit; and the plurality of pixel electrodes are spaced apart from the plurality of gate lines.

[0010] For example, in at least one example of the array substrate, the pixel electrode is a plate-shaped electrode, and the orthographic projection of the plate-shaped electrode on the second electrode layer is a continuous plane.

[0011] For example, in at least one example of the array substrate, each of the plurality of common electrodes includes: a plurality of strip electrodes arranged side by side in the first direction, and a first connection sub-electrode and a second connection sub-electrode that are opposite sides of each of the plurality of common electrodes in the second direction; the first connection sub-electrode is connected to the first ends of the plurality of strip electrodes, and the second connection sub-electrode is connected to the second ends of the plurality of strip electrodes; the positive projections of the first connection sub-electrode and the second connection sub-electrode on the first electrode layer respectively partially overlap with one side portions of the corresponding two gate lines close to each of the plurality of common electrodes; and the positive projections of the plurality of pixel electrodes on the second electrode layer are exposed from the gaps between adjacent strip electrodes included in the corresponding common electrode.

[0012] For example, in at least one example of the array substrate, each of the plurality of common electrodes and the pixel electrodes includes a transparent conductive oxide, and each of the plurality of gate lines includes a metal.

[0013] For example, in at least one example of the array substrate, the surface of each of the plurality of gate lines on the side close to the second electrode layer has a concavo-convex structure.

[0014] At least one embodiment of the present disclosure further provides a light control panel, which includes: a counter substrate, a liquid crystal layer, and the array substrate provided by at least one embodiment of the present disclosure. The array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the array substrate and the counter substrate.

[0015] For example, in at least one example of the light control panel, the counter substrate includes a black matrix layer; the black matrix layer includes a plurality of black matrix units, and each of the plurality of black matrix units extends integrally in the first direction; and the positive projections of the plurality of gate lines on the black matrix layer are respectively located within the corresponding black matrix units.

[0016] For example, in at least one example of the light control panel, each of the plurality of black matrix units includes a plurality of black matrix structures that are directly connected in sequence in the first direction, and the positive projections of the plurality of first folded line structures included in the plurality of gate lines on the black matrix layer are respectively located in the corresponding black matrix structures.

[0017] For example, in at least one example of the light control panel, the ratio of the width of each of the plurality of black matrix units to the width of the corresponding gate line is between 1 and 2.5.

[0018] At least one embodiment of the present disclosure further provides a display device, which includes: a display panel, a backlight unit, and a light control panel provided by at least one embodiment of the present disclosure. The display panel, the light control panel, and the backlight unit are stacked, the display panel is located on the light-emitting side of the light control panel, and the backlight unit is located on the side of the light control panel away from the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0020] Figure 1A Shows a cross-sectional schematic diagram of a liquid crystal display device;

[0021] Figure 1B Shows Figure 1A A plan view of the light control panel and the display panel of the liquid crystal display device shown;

[0022] Figure 1C Shows Figure 1A A plan view of the light control panel of the liquid crystal display device shown;

[0023] Figure 1D Shows Figure 1A The light control pixel unit of the light control panel shown;

[0024] Figure 2A Shows the Figure 1A Schematic diagram of the gate line occlusion of the liquid crystal display device shown from the first perspective;

[0025] Figure 2B Shows the Figure 1A Schematic diagram of the gate line occlusion of the liquid crystal display device shown from the second perspective;

[0026] Figure 3A Is Figure 1C Another plan view of the light control panel shown;

[0027] Figure 3B Is Figure 1C And Figure 3A A cross-sectional schematic diagram of the light control panel shown;

[0028] Figure 3C Is Figure 3B Another cross-sectional schematic diagram of the light control panel shown;

[0029] Figure 4A Is Figure 3A An enlarged plan view of the first region of the light control panel shown;

[0030] Figure 4B is Figure 4A A cross-sectional schematic view of the first region of the light control panel shown;

[0031] Figure 4C is Figure 3A An enlarged plan view of the second region of the light control panel shown;

[0032] Figure 5 A cross-sectional schematic view of the light control panel provided by at least one embodiment of the present disclosure;

[0033] Figure 6A is Figure 5 A plan view of the array substrate of the light control panel shown;

[0034] Figure 6B is Figure 6A Another plan view of the array substrate shown;

[0035] Figure 7A is Figure 5 Another cross-sectional schematic view of the light control panel shown;

[0036] Figure 7B The surface of each of the multiple gate lines of the array substrate provided by at least one embodiment of the present disclosure, on the side close to the second electrode layer;

[0037] Figure 8A A plan view of the common electrode provided by at least one embodiment of the present disclosure;

[0038] Figure 8B is Figure 6B An enlarged view of the first region of the array substrate shown;

[0039] Figure 9A is Figure 6B An enlarged view of the second region of the array substrate shown;

[0040] Figure 9B is Figure 9A A cross-sectional schematic view of the second region of the array substrate shown;

[0041] Figure 10A is Figure 6B Another schematic view of the array substrate shown;

[0042] Figure 10B A plan view of another first fold line structure and a first connecting sub-electrode (or a second connecting sub-electrode) provided by at least one embodiment of the present disclosure;

[0043] Figure 11 A cross-sectional schematic view of the display device provided by at least one embodiment of the present disclosure;

[0044] Figure 12A is Figure 11 a schematic plan view of a display panel of the display device shown; and

[0045] Figure 12B is Figure 11 a schematic plan view of the display device shown. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "Connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0048] The inventors of the present disclosure noticed in their research that ordinary liquid crystal display devices (for example, liquid crystal display devices based on advanced super-dimensional field conversion technology with a single liquid crystal cell) usually have the problem of light leakage in the dark state, which results in a low contrast of the display screen of the liquid crystal display device. The inventors of the present disclosure noticed in their research that a liquid crystal display device with a double liquid crystal cell can be used to improve the contrast of the display screen. The following will be described by way of Figure 1A exemplary illustration.

[0049] Figure 1A shows a cross-sectional schematic view of a liquid crystal display device 500. As Figure 1A shown, the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502, and a display panel 501 arranged in sequence. Figure 1B shows Figure 1AA plan view of the light control panel 502 and the display panel 501 of the liquid crystal display device 500 shown. Figure 1C Shows Figure 1A A plan view of the light control panel 502 (array substrate 551 of the light control panel 502) of the liquid crystal display device 500 shown. For example, the light control panel 502 is configured to adjust the intensity of the light emitted by the backlight unit 503 and incident on the display panel 501. For example, the light emitted from the light control panel 502 is white light, that is, the light control panel 502 does not have a color adjustment function.

[0050] As Figure 1B Shown, the display panel 501 includes a plurality of first signal lines 541 extending along a first direction D1 and a plurality of second signal lines 542 extending along a second direction D2; the plurality of first signal lines 541 and the plurality of second signal lines 542 intersect to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 530 arranged in an array; each display pixel unit 530 includes a first display sub-pixel unit 531, a second display sub-pixel unit 532, and a third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 are, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit respectively. For example, the first direction D1 is perpendicular to the second direction D2. For example, the first signal line 541 is a gate line of the display panel 501, and the second signal line 542 is a data line of the display panel 501.

[0051] As Figure 1B And Figure 1C Shown, the light control panel 502 (array substrate 551 of the light control panel 502) includes a plurality of gate lines 510 extending along the first direction D1 and a plurality of data lines 521 extending along a second direction D2 intersecting the first direction D1; the plurality of gate lines 510 and the plurality of data lines 521 intersect to define a plurality of light control pixel units 523. For example, the light control panel 502 further includes a plurality of common electrode lines 522 extending along the second direction D2. For example, the light control panel 502 includes a plurality of light control units arranged in an array, and the plurality of light control pixel units 523 of the array substrate 551 are respectively disposed in corresponding light control units.

[0052] For example, the light control panel 502 can adjust the transmittance of each light control unit of the light control panel based on the data signal received by the data line 521. Therefore, the light control units of the light control panel 502 can be used to control the intensity of the light incident on the display sub-pixel units of the display panel 501 corresponding to the light control unit. Thus, the light control panel 502 can be used to provide the adjusted backlight to the display panel 501. For example, by providing the light control panel 502 in the display device 500, the transmittance of the light control units in the area where the brightness of the display screen corresponding to the liquid crystal display device is relatively low (for example, the brightness is zero) can be made relatively low (for example, the transmittance is equal to or close to zero). In this case, the adverse effect of the possible light leakage problem in the dark state of the display panel 501 on the contrast of the display screen is relatively small. Therefore, by using a liquid crystal display device with a dual liquid crystal cell (that is, a display device with a light control panel), the contrast of the display screen can be improved.

[0053] For example, the width of the first signal line 541 is greater than the width of the gate line 510. For example, the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the first direction D1 are the same as each other. For example, the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the second direction D2 are the same as each other.

[0054] As Figure 1B and Figure 1C shown, each gate line 510 of the light control panel 502 is implemented as a folded trace; each gate line 510 includes a plurality of first trace portions 511 and a plurality of second trace portions 512. The plurality of first trace portions 511 and the plurality of second trace portions 512 are alternately arranged, and the adjacent first trace portion 511 and the second trace portion 512 are connected to each other. As Figure 1B shown, the angle α (acute angle) between the first trace portion 511 (or / and the second trace portion 512) and the first direction D1 is about 50 - 70 degrees to reduce the moiré problem of the liquid crystal display device 500. For example, both the first trace portion 511 and the second trace portion 512 are straight trace portions.

[0055] Figure 1D shows Figure 1A the light control pixel unit 523 of the light control panel 502 shown in Figure 1D shown. As Figures 1B - 1DAs shown, the size S1 of the light control pixel unit 523 in the first direction D1 is twice the size of the display pixel unit 530 in the first direction D1, and the size S2 of the light control pixel unit 523 in the second direction D2 is four times the size of the display pixel unit 530 in the second direction D2.

[0056] The inventors of the present disclosure noticed in the research that by making the gate line 510 implemented as a zigzag line, the problem of uneven brightness of the liquid crystal display device 500 can be suppressed. For example, the problem of uneven brightness is the problem of black and white stripes or horizontal stripes (e.g., black and white stripes under a side viewing angle). The specific analysis is as follows. When the gate line 510 (and the black matrix unit that blocks the gate line) is implemented as a straight line, if there is a misalignment error when bonding the light control panel 502 and the display panel 501, the positive projection of the gate line 510 (straight line) on the display panel 501 will overlap with a row of display pixels of the display panel 501. This gate line 510 will block the light provided by the backlight unit 503, and make the brightness of the area of the liquid crystal display device 500 corresponding to the gate line 510 close to zero (i.e., corresponding to black stripes), and the area of the liquid crystal display device 500 corresponding to the area outside the gate line 510 corresponds to white stripes. In this case, there are alternately arranged black and white stripes in the second direction D2 of the liquid crystal display device 500, that is, the problem of black and white stripes that the liquid crystal display device 500 may have. When the gate line 510 is implemented as a zigzag line, the problem of black and white stripes or horizontal stripes of the liquid crystal display device 500 can be suppressed.

[0057] The inventors of the present disclosure also noticed in the research that Figure 1A and Figure 1B the liquid crystal display device 500 shown may have a problem of color unevenness (rainbow pattern). The rainbow pattern problem is a problem of uneven color mixing in different areas of the display device. Specifically, when the predetermined display screen of the display device is a white screen, the user observes a colored stripe in the actual screen. The rainbow pattern problem is related to the difference in the light blocking of the light emitted by the backlight unit by the areas of the gate line 510 (and the black matrix unit that blocks the gate line) corresponding to different color display sub-pixel units at different viewing angles. The following will give an exemplary description of the rainbow pattern problem in combination with Figure 2A and Figure 2B Figure 2A shows the schematic diagram of the light blocking situation of the gate line 510 of the liquid crystal display device 500 shown in Figure 1A at the first viewing angle (e.g., the front viewing angle), Figure 2B shows the schematic diagram of the light blocking situation of the gate line 510 of the liquid crystal display device 500 shown in Figure 1A ​Schematic diagram of the shielding situation of the gate line 510 of the liquid crystal display device 500 shown. For the convenience of explanation, it is assumed here that the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the first direction D1 are the same as each other; both the first trace portion 511 and the second trace portion 512 are straight trace portions. As Figure 2A and Figure 2B shown, since the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the first direction D1 are the same as each other, therefore, the length of the portion of the trace portion (for example, the first trace portion 511) corresponding to the first display sub-pixel unit 531, the length of the portion of the trace portion (for example, the first trace portion 511) corresponding to the second display sub-pixel unit 532, and the length of the portion of the trace portion (for example, the first trace portion 511) corresponding to the third display sub-pixel unit 533 are the same as each other. As Figure 2A shown, in the first viewing angle, since the portion of the trace portion (for example, the first trace portion 511) corresponding to the second display sub-pixel unit 532 also overlaps with the first signal line 541, therefore, in the first viewing angle, the overlapping area between the trace portion (for example, the first trace portion 511) and the first display sub-pixel unit 531 and the overlapping area between the trace portion (for example, the first trace portion 511) and the third display sub-pixel unit 533 are both larger than the overlapping area between the trace portion (for example, the first trace portion 511) and the second display sub-pixel unit 532, that is, the light emitted by the backlight unit is blocked least by the trace portion (for example, the first trace portion 511) corresponding to the second display sub-pixel unit 532, and the intensity of the light incident on the second display sub-pixel unit 532 is the strongest; in this case, the display screen in the first viewing angle tends to the color of the second display sub-pixel unit 532. For similar reasons, as Figure 2B shown, the display screen in the second viewing angle tends to the color of the first display sub-pixel unit 532 (that is, the display sub-pixel unit in the column where the overlapping area between the trace portion and the first signal line 541 is located). Since the user observes the liquid crystal display device 500 within a certain viewing angle range, therefore, the actual screen observed by the user has color stripes. It should be noted that the portion of the trace portion corresponding to the display sub-pixel unit refers to the portion between the two intersection points of the trace portion and the boundary of the display sub-pixel unit (for example, the column of display sub-pixel units where the display sub-pixel unit is located) in the first direction.

[0058] The inventors of the present disclosure also noticed in the research that, in order to avoid Figure 1C the possible problem of dark state light leakage around the gate line 510 of the light control panel shown, the width of the black matrix unit for shielding the gate line 510 is increased, which makes the included Figure 1CThe problem of rainbow patterns in the display device with the light control panel shown is relatively serious. The following will make an exemplary description in combination with Figures 3A - 3C and Figure 4A and Figure 4B for illustration.

[0059] Figure 3A is Figure 1C Another schematic plan view of the light control panel 502 (array substrate 551 of the light control panel 502) shown. Compared with Figure 1C , Figure 3A shows the pixel electrodes included in the light control pixel unit. Figure 3B is Figure 1C and Figure 3A The schematic cross-sectional view of the light control panel 502 shown, Figure 3B The shown cross-sectional view corresponds to the AA' line shown in Figure 3A .

[0060] As shown in Figure 3A and Figure 3B , the light control panel 502 includes an array substrate 551 and a counter substrate 552 disposed opposite to each other and a liquid crystal layer 553 sandwiched between the array substrate 551 and the counter substrate 552. The light incident on the light control panel 502 can enter the light control panel 502 from the array substrate 551 and can leave the light control panel 502 from the counter substrate 552. As shown in Figure 3B , the counter substrate 552 includes a black matrix unit 564 and a second substrate 565.

[0061] As shown in Figure 3A and Figure 3B , the array substrate 551 includes a data line layer and a first substrate 561, a first electrode layer, an insulating layer (for example, including a first insulating layer 562 or a second insulating layer 563), and a second electrode layer sequentially arranged. The first electrode layer includes a plurality of gate lines 510, and each of the plurality of gate lines 510 extends integrally along a first direction D1; the data line layer includes a plurality of data lines 521, and each of the plurality of data lines 521 extends integrally along a second direction D2 intersecting with the first direction D1; the plurality of gate lines 510 and the plurality of data lines 521 intersect with each other to define a plurality of light control pixel units 523; the second electrode layer includes a plurality of pixel electrodes 524 arranged in an array, and each of the plurality of pixel electrodes 524 is disposed in the plurality of light control pixel units 523.

[0062] As shown in Figure 3A and Figure 3BAs shown, the orthographic projection of the pixel electrode 524 on the first electrode layer does not overlap with the gate line 510, and the electric field formed by the pixel electrode 524 and the gate line 510 enters the liquid crystal layer 553 located away from the gate line 510 of the pixel electrode 524. Since in the dark state (i.e., the light control pixel unit 523 driven by the gate line 510 is theoretically in a light-blocking state), there is still a voltage difference between the pixel electrode 524 and the gate line 510. Therefore, the electric field formed by the pixel electrode 524 and the gate line 510 causes the liquid crystal molecules near the gate line 510 to deviate from the predetermined orientation in the dark state, and allows part of the light incident on the light control panel 502 to pass through the corresponding area of the liquid crystal layer 553 corresponding to the gate line 510 and enter the counter substrate 552. If the width of the black matrix unit 564 included in the counter substrate 552 is equal to the width of the corresponding gate line 510, the above-mentioned light passes through the corresponding area of the liquid crystal layer 553 corresponding to the gate line 510 and enters the counter substrate 552, and then passes through the counter substrate 552 and leaves the light control panel 502. In this case, there will be a problem of light leakage in the dark state in the area of the light control panel 502 near the gate line 510. In order to avoid the above-mentioned problem of light leakage in the dark state of the light control panel 502, the width of the black matrix unit 564 is greater than the width of the corresponding gate line 510.

[0063] Figure 3C is Figure 3B Another cross-sectional schematic diagram of the light control panel 502 shown in the figure. As Figure 3C shown, the distance L3 between the orthographic projection of the gate line 510 and the corresponding pixel electrode 524 on the first electrode layer in the fourth direction DA (i.e., the direction perpendicular to the extension direction of the routing part of the gate line 510) can be equal to 6 - 10 microns (for example, 8 microns), and the distance L1 between the side of the gate line 510 facing in the fourth direction DA and the side of the orthographic projection of the black matrix unit 564 on the first electrode layer facing in the fourth direction DA can be equal to 18 - 22 microns (for example, 20 microns); the difference between the width of the black matrix unit 564 in the fourth direction DA and the width of the corresponding gate line 510 in the fourth direction DA is equal to 2×L1. For example, the width of the black matrix unit 564 in the fourth direction DA is equal to 52 - 60 microns (for example, 56 microns), and the width of the gate line 510 in the fourth direction DA is equal to 12 - 20 microns (for example, 16 microns).

[0064] For example, due to the large width of the black matrix unit 564, the difference in the overlapping area between the gate line 510 (or the black matrix unit 564) of the light control panel 502 and the display sub-pixels of different colors on the display panel 501 is relatively large. The areas of the gate line 510 (or the black matrix unit 564) corresponding to the display sub-pixels of different colors have a relatively large difference in blocking the light emitted by the backlight unit. As a result, the difference in the intensity of the light emitted by the backlight unit 503 and incident on the display sub-pixels of different colors on the display panel 503 is relatively large, and the problem of rainbow pattern in the display device including the light control panel 501502 is relatively serious.

[0065] Figure 4A Yes Figure 3A It is an enlarged plan schematic diagram of the first region RE1 of the light control panel 502 shown. Figure 4B Yes Figure 4A It is a cross-sectional schematic diagram of the light control panel 502 shown. Figure 4B The cross-sectional schematic diagram shown corresponds to Figure 4A the dashed line with an arrow shown. It should be noted that for convenience of description, Figure 4B the common electrode 525 included in the light control pixel unit 523 is also shown.

[0066] As Figure 4A and Figure 4B shown, the pixel electrode 524 may include a plurality of strip electrodes 5243 arranged in parallel in the first direction D1 and the first connection sub-electrode 5241 and the second connection sub-electrode 5242 which are opposite sides of the pixel electrode 524 in the second direction D2. That is, the pixel electrode 524 can be implemented as a slit electrode. It should be noted that Figure 4A and Figure 4B shown, the first connection sub-electrode 5241 and the second connection sub-electrode 5242 respectively belong to two adjacent pixel electrodes 524 in the second direction D2. As Figure 4B shown, the common electrode 525 is a plate-shaped electrode, and the distance L2 between the common electrode 525 and the corresponding gate line 510 in the fourth direction DA can be equal to 6 - 10 microns (for example, 7.5 microns). For example, the distance L3 between the positive projection of the gate line 510 and the corresponding pixel electrode 524 (the first connection sub-electrode 5241 or the second connection sub-electrode 5242) on the first electrode layer in the fourth direction DA is greater than the distance L2 between the common electrode 525 and the corresponding gate line 510 in the fourth direction DA. As a result, part of the common electrode 525 is exposed from the interval between the positive projections of the first connection sub-electrode 5241 and the second connection sub-electrode 5242 on the first electrode layer.

[0067] As Figure 4AAs shown, the gate line 510 is located within the gap formed by two sides 5641 and 5642 of the orthographic projection of the black matrix unit 564 on the first electrode layer in the fourth direction (perpendicular to the extending direction of the black matrix unit 564), that is, the gate line 510 is located within the orthographic projection of the black matrix unit 564 on the first electrode layer.

[0068] Figure 4C is an enlarged plan view of a partial area of another light control panel. As Figure 4C shown, the plurality of common electrode lines 522 are not limited to being implemented as straight lines parallel to the second direction D2, and may also include a broken line structure.

[0069] At least one embodiment of the present disclosure provides an array substrate, a light control panel, and a display device. The array substrate includes a data line layer, and a substrate substrate, a first electrode layer, an insulating layer, and a second electrode layer sequentially arranged. The first electrode layer includes a plurality of gate lines, each of the plurality of gate lines extends integrally along the first direction and includes a plurality of first broken line structures directly connected in sequence in the first direction; the data line layer includes a plurality of data lines, each of the plurality of data lines extends integrally along a second direction intersecting the first direction; the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of light control pixel units; the second electrode layer includes a plurality of common electrodes arranged in an array, and each of the plurality of common electrodes is disposed in at least one of the plurality of light control pixel units; at least one of the plurality of gate lines and at least one common electrode at least partially overlap in the orthographic projection on the first electrode layer. By making at least one of the plurality of gate lines and at least one common electrode at least partially overlap in the orthographic projection on the first electrode layer, the array substrate can prevent the electric field formed by the gate line and the common electrode from entering the side of the second electrode layer far from the first electrode layer.

[0070] At least one embodiment of the present disclosure further provides a light control panel, which includes: a counter substrate, a liquid crystal layer, and the array substrate provided by at least one embodiment of the present disclosure. The array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the array substrate and the counter substrate.

[0071] For example, by making at least one of the plurality of gate lines of the array substrate of the light control panel and at least one common electrode at least partially overlap in the orthographic projection on the first electrode layer, the light control panel has the ability to suppress (for example, completely suppress) the problem of dark state light leakage of the light control panel without providing a black matrix layer or reducing the size of the black matrix unit of the black matrix layer, and the ability to suppress the rainbow pattern problem of the display device including the light control panel.

[0072] The array substrate and the light control panel provided according to the embodiments of the present disclosure will be described below by way of several examples and embodiments in a non-limiting manner. As described below, different features in these specific examples and embodiments can be combined with each other without conflict, so as to obtain new examples and embodiments, and these new examples and embodiments also fall within the scope of protection of the present disclosure.

[0073] Figure 5 is a schematic cross-sectional view of the light control panel 10 provided by at least one embodiment of the present disclosure. As Figure 5 shown, the light control panel 10 includes: an array substrate 100 and a counter substrate 200 opposed to each other in the third direction D3, and a liquid crystal layer 300 sandwiched between the array substrate 100 and the counter substrate 200.

[0074] As Figure 5 shown, the array substrate 100 includes a data line layer ( Figure 5 not shown in the figure), and a first substrate 101, a first electrode layer, an insulating layer (for example, the insulating layer can be one of the first insulating layer 102 and the second insulating layer 103), and a second electrode layer that are sequentially arranged (sequentially arranged in the third direction D3). Relative to the first substrate 101, the second electrode layer is closer to the liquid crystal layer 300.

[0075] As Figure 5 shown, the counter substrate 200 includes a second substrate 210 and a black matrix layer 220. For example, relative to the second substrate 210, the black matrix layer 220 is closer to the liquid crystal layer 300; the black matrix layer 220 includes a plurality of black matrix units 221 extending integrally along the first direction D1.

[0076] Figure 6A is Figure 5 a schematic plan view of the array substrate 100 of the light control panel 10 shown in the figure. As Figure 5 and Figure 6A shown, the first electrode layer includes a plurality of gate lines 110. Each of the plurality of gate lines 110 extends integrally along the first direction D1 and includes a plurality of first folded line structures 111 directly connected in sequence in the first direction D1; the data line layer ( Figure 6A not marked in the figure) includes a plurality of data lines 120. Each of the plurality of data lines 120 extends integrally along the second direction D2; the plurality of gate lines 110 and the plurality of data lines 120 intersect each other to define a plurality of light control pixel units 130. For example, the first direction D1, the second direction D2, and the third direction D3 intersect each other (for example, are perpendicular to each other).

[0077] For example, the light control panel 10 may include a plurality of light control units arranged in an array, and a plurality of light control pixel units 130 of the array substrate 100 are respectively disposed in corresponding light control units. For example, the light control unit further includes a portion of the liquid crystal layer stacked with the light control pixel unit 130 in the third direction D3 and a portion of the counter substrate. For example, the light control panel can adjust the transmittance of each light control unit of the light control panel based on the data signal received thereby. Therefore, the light control units of the light control panel can be used to control the intensity of the light incident on the display sub-pixel units of the display panel corresponding to the light control units, and thus the light control panel can be used to provide the adjusted backlight to the display panel of the display device including the light control panel.

[0078] For example, as Figure 5 and Figure 6A shown, each of the plurality of data lines 120 includes a plurality of second folded line structures 121 directly connected in sequence in the second direction D2. It should be noted that the overall extension of each of the plurality of gate lines 110 along the first direction D1 only defines the extension direction of the gate line 110, and does not mean that the traces included in the gate line 110 are everywhere parallel to the first direction D1. For example, the gate line 110 includes a first number (greater than or equal to 2) of line segments, and some line segments may intersect the first direction D1. Correspondingly, the overall extension of each of the plurality of data lines 120 along the second direction D2 only defines the extension direction of the data line 120, and does not mean that the traces included in the data line 120 are everywhere parallel to the second direction D2.

[0079] For example, the plurality of first folded line structures 111 included in the plurality of gate lines 110 correspond one-to-one with the plurality of light control pixel units 130, and the plurality of second folded line structures 121 included in the plurality of data lines 120 correspond one-to-one with the plurality of light control pixel units 130. For example, each of the plurality of light control pixel units 130 partially overlaps with the corresponding gate line 110. For example, each of the plurality of light control pixel units 130 partially overlaps with the corresponding data line 120.

[0080] Figure 6B is Figure 6A Another plan view of the array substrate 100 shown in. Compared with Figure 6A , Figure 6B shows the common electrode 131 included in the light control pixel unit 130, Figure 5 The cross-sectional view shown corresponds to Figure 6B the AA' line shown in. As Figure 5 , Figure 6A and Figure 6BAs shown, the second electrode layer includes a plurality of common electrodes 131 arranged in an array, and each of the plurality of common electrodes 131 is disposed in at least one of the plurality of light control pixel units 130. For example, the plurality of common electrodes 131 and the plurality of light control pixel units 130 are in one-to-one correspondence, and each of the plurality of common electrodes 131 is disposed in (e.g., completely located in) the corresponding light control pixel unit 130.

[0081] As Figure 5 and Figure 6B shown, at least one of the plurality of gate lines 110 and at least one common electrode 131 have at least partial overlap in the positive projection on the first electrode layer. For example, each of the plurality of gate lines 110 and each common electrode 131 in one or two rows of common electrodes 131 adjacent to the gate line 110 in the second direction D2 have at least partial overlap in the positive projection on the first electrode layer.

[0082] For example, the overlapping size of the gate line 110 and the corresponding common electrode 131 in the positive projection on the first electrode layer can be set according to actual application requirements (e.g., according to the requirements of the light control panel and the display device for capacitance), and the embodiments of the present disclosure do not make specific limitations in this regard. For example, for a 65-inch display device, the overall overlapping size of the gate line 110 and the corresponding common electrode 131 in the positive projection on the first electrode layer can be greater than 0 and less than or equal to G_WL, where G_WL is the width of the gate line 110. For example, in the case where the positive projections of two common electrodes 131 on the first electrode layer overlap with the gate line 110, the overall size refers to the sum of the overlapping sizes of the positive projections of the two common electrodes 131 on the first electrode layer and the gate line 110.

[0083] Figure 7A is Figure 5 Another cross-sectional schematic diagram of the light control panel 10 shown. For example, slightly overlapping the positive projection of the gate line 110 and the corresponding common electrode 131 on the first electrode layer can prevent the electric field formed by the gate line 110 and the common electrode 131 overlapping with the gate line 110 from entering the side of the second electrode layer far from the first electrode layer. For example, as Figure 5 and Figure 7A shown, the above-mentioned slight overlap means that the width OV1 of the region where the gate line 110 overlaps with the positive projection of the corresponding common electrode 131 on the first electrode layer in the fourth direction DA is greater than 0 and less than 1 micron. It should be noted that the fourth direction DA refers to the direction perpendicular to the extension direction of a certain line segment of the gate line 110. Since the extension directions of the plurality of line segments included in the gate line 110 are not completely the same, the fourth direction DA corresponding to different line segments of the gate line 110 can be different.

[0084] For example, the width OV1 in the fourth direction DA (i.e., the direction perpendicular to the extending direction of the gate line 110) of the overlapping region of the gate line 110 and the corresponding common electrode 131 in the positive projection on the first electrode layer may be between 3 μm and 7 μm (4 μm, 5 μm, or 6 μm). For example, by making the width OV1 in the fourth direction DA of the overlapping region of the gate line 110 and the corresponding common electrode 131 in the positive projection on the first electrode layer be between 3 μm and 7 μm (4 μm, 5 μm, or 6 μm), it is possible to avoid the problem that the positive projections of the gate line 110 and the corresponding common electrode 131 on the first electrode layer may not overlap in the actual product due to potential alignment errors between the gate line 110 and the corresponding common electrode 131, and it is also possible to avoid the problem that the charging time required for the gate line 110 and the common electrode 131 is relatively long due to an excessive capacitance between the gate line 110 and the corresponding common electrode 131.

[0085] For example, by making at least one of the multiple gate lines 110 and at least one common electrode 131 at least partially overlap in the positive projection on the first electrode layer, the array substrate 100 can prevent the electric field formed by the gate line 110 and the common electrode 131 overlapping with the gate line 110 from entering the side of the second electrode layer far from the first electrode layer (for example, entering the liquid crystal layer 300 located on the side of the second electrode layer far from the first electrode layer). Therefore, although there is still a voltage difference between the common electrode 131 and the gate line 110 in the dark state (i.e., the light control unit where the light control pixel unit 130 driven by the gate line 110 is theoretically in an opaque state), the electric field formed by the common electrode 131 and the gate line 110 cannot cause the liquid crystal molecules near the gate line 110 to deviate from the predetermined orientation in the dark state. Thus, the light control panel 10 including the array substrate 100 has the ability to suppress the light leakage problem in the dark state of the light control panel 10 without providing the black matrix layer 220 or reducing the size of the black matrix unit 221 of the black matrix layer 220.

[0086] For example, the gate line 110 can be formed of a metal material (such as copper, aluminum, or aluminum alloy). For example, as Figure 7A shown, the positive projections of the multiple gate lines 110 on the black matrix layer 220 are respectively located within the corresponding black matrix units 221. For example, each of the multiple black matrix units 221 includes multiple first black matrix structures (not marked in the figure) that are directly connected in sequence in the first direction D1, and the positive projections of the multiple first broken line structures 111 included in the multiple gate lines 110 on the black matrix layer 220 are respectively located in the corresponding first black matrix structures.

[0087] For example, the extending trend of each of the plurality of first black matrix structures is the same as that of the corresponding first broken line structure 11. It should be noted that the extending trend of each of the plurality of first black matrix structures being the same as that of the corresponding first broken line structure 11 means that each of the first black matrix structures has a first number of black matrix sub-structures, and the extending direction of each black matrix sub-structure of each first black matrix structure is the same as that of the corresponding line segment of the corresponding first broken line structure 111.

[0088] For example, by making the positive projections of the plurality of gate lines 110 on the black matrix layer 220 be respectively located within the corresponding black matrix units 221, the black matrix units 221 can be used to suppress the reflection of the gate lines 110. For example, the width of the black matrix unit 221 in the fourth direction DA can be equal to the width of the corresponding gate line 110 in the fourth direction DA. For another example, the width of the black matrix unit 221 in the fourth direction DA can be greater than the width of the corresponding gate line 110 in the fourth direction DA. Thus, even when there is a misalignment error between the black matrix unit 221 and the gate line 110, the positive projections of the plurality of gate lines 110 on the black matrix layer 220 can still be respectively located within the corresponding black matrix units 221, thereby improving the suppression effect of the black matrix unit 221 on the reflection of the gate lines 110.

[0089] For example, the width of the black matrix unit 221 in the fourth direction DA can be set according to actual application requirements, and the embodiments of the present disclosure do not make specific limitations thereto. For example, the ratio of the width of each of the plurality of black matrix units 221 to the width of the corresponding gate line 110 is between 1 and 2.5 (for example, 2). For example, as Figure 7A shown, the difference between the width of the black matrix unit 221 in the fourth direction DA and the width of the corresponding gate line 110 in the fourth direction DA is equal to 2×L1. The spacing L1 between the opposite side edges of the gate line 110 in the fourth direction DA and the opposite side edges of the positive projection of the corresponding black matrix unit 221 on the first electrode layer in the fourth direction DA can be equal to 6 - 10 micrometers (for example, 8 micrometers). For example, the width of the black matrix unit 221 in the fourth direction DA is equal to 28 - 36 micrometers (for example, 32 micrometers), and the width of the gate line 110 in the fourth direction DA is equal to 12 - 20 micrometers (for example, 16 micrometers).

[0090] For example, compared with Figure 3B and Figure 4B the light control panel shown, Figure 5The light control panel 10 shown can reduce the difference in the overlapping area between the black matrix cells 221 of the black matrix layer 220 and the display sub-pixels of different colors on the display panel (the display panel of the display device including this light control panel 10) by reducing the size of the black matrix cells 221 of the black matrix layer 220, and reduce the difference in the light blocking of the regions of the black matrix cells 221 corresponding to the display sub-pixels of different colors on the light emitted by the backlight unit. Thus, the difference in the intensity of the light emitted by the backlight unit (the backlight unit of the display device including this light control panel 10) and incident on the display sub-pixels of different colors on the display panel (the display panel of the display device including this light control panel 10) can be reduced, and further, the rainbow pattern problem of the display device including this light control panel 10 can be suppressed.

[0091] For example, the black matrix layer 220 further includes a plurality of second black matrix cells 221, and each of the plurality of second black matrix cells 221 extends integrally along the second direction D2; the orthographic projections of the plurality of data lines 120 on the black matrix layer 220 are respectively located within the corresponding second black matrix cells 221. For example, each of the plurality of second black matrix cells 221 includes a plurality of second black matrix structures that are directly connected in sequence in the second direction D2, and the orthographic projections of the plurality of second broken line structures 121 included in the plurality of gate lines 110 on the black matrix layer 220 are respectively located in the corresponding second black matrix structures.

[0092] It should be noted that, in some examples, the counter substrate 200 may not be provided with a black matrix layer. Figure 7B is the surface of one side of each of the plurality of gate lines of the array substrate provided by at least one embodiment of the present disclosure, which is close to the second electrode layer. For example, as Figure 7B shown, the surface of one side of each of the plurality of gate lines 110, which is close to the second electrode layer, is a diffuse reflection surface and has an uneven structure 191 (that is, a concave structure and a convex structure). For example, the distance RU_L between two adjacent convex structures on the surface of one side of each of the plurality of gate lines 110, which is close to the second electrode layer, is less than 1 mm, and the distance between two adjacent concave structures on the surface of one side of each of the plurality of gate lines 110, which is close to the second electrode layer, is less than 1 mm.

[0093] For example, compared with Figure 7AThe light control panel shown, by making the surface of each of the plurality of gate lines 110 on the side close to the second electrode layer a diffuse reflection surface and having a concavo-convex structure 191, the reflectivity of the gate lines 110 to the light incident on the surface of each of the plurality of gate lines 110 on the side close to the second electrode layer is small. In this case, the counter substrate 200 may not be provided with a black matrix layer, thereby further reducing the difference in the intensity of the light emitted by the backlight unit (the backlight unit of the display device including this light control panel 10) and incident on the display sub-pixels of different colors of the display panel (the display panel of the display device including this light control panel 10), and further suppressing the rainbow pattern problem of the display device including this light control panel 10.

[0094] For example, the width of the black matrix unit 221 may be greater than or equal to zero microns and less than or equal to 32 microns.

[0095] For example, as Figure 5 and Figure 6B shown, the two sides of each of the plurality of common electrodes 131 opposed in the second direction D2 are respectively overlapped (for example, partially overlapped) with the corresponding two gate lines 110 on the side close to each of the plurality of common electrodes 131 on the first electrode layer. Thus, the array substrate 100 can better prevent the electric field formed by the plurality of gate lines 110 and the common electrodes 131 overlapping with the plurality of gate lines 110 from entering the side of the second electrode layer far from the first electrode layer (for example, entering the liquid crystal layer 300 located on the side of the second electrode layer far from the first electrode layer).

[0096] For example, as Figure 5 and Figure 6B shown, a gap is provided between two adjacent common electrodes 131 in the second direction D2, and the projection of the gate line 110 overlapping with the projections of both of the two adjacent common electrodes 131 in the first electrode layer in the second direction D2 overlaps with the projection of the above gap in the first electrode layer. For example, the projection of the above gap in the first electrode layer is located (for example, completely located) within the gate line 110 overlapping with the projections of both of the two adjacent common electrodes 131 in the first electrode layer in the second direction D2.

[0097] For example, by providing a gap between two adjacent common electrodes 131 in the second direction D2, it is possible to avoid an excessive capacitance between the gate line 110 and the corresponding common electrode 131, thereby avoiding a potential problem of a relatively long charging time required for the gate line 110 and the common electrode 131. In some other examples, a gap may not be provided between two adjacent common electrodes 131 in the second direction D2, that is, two adjacent common electrodes 131 in the second direction D2 may be in direct contact or the gate line 110 may be completely covered by two adjacent common electrodes 131 in the second direction D2, thereby further improving the ability of the light control panel 10 to suppress light leakage in the dark state.

[0098] For example, the specific shape of the common electrode 131 can be set according to actual application requirements, and the embodiments of the present disclosure do not make specific limitations thereto. For example, the common electrode 131 can be a plate-shaped electrode or a slit electrode. Figure 8A is a schematic plan view of a common electrode 131 provided by at least one embodiment of the present disclosure. As Figure 8A shown, the common electrode 131 includes a plurality of strip-shaped electrodes 132 arranged in parallel in the first direction D1, and a first connecting sub-electrode 133 and a second connecting sub-electrode 134 that are opposite sides of each of the plurality of common electrodes 131 in the second direction D2; the first connecting sub-electrode 133 is connected to the first ends of the plurality of strip-shaped electrodes 132, and the second connecting sub-electrode 134 is connected to the second ends of the plurality of strip-shaped electrodes 132.

[0099] Figure 8B is Figure 6B an enlarged view of the first region RE1 of the array substrate 100 shown in Figure 9A is Figure 6B an enlarged view of the second region RE2 of the array substrate 100 shown in Figure 9B is Figure 9A a cross-sectional schematic view of the second region RE2 of the array substrate 100 shown in Figure 9B The cross-sectional schematic view shown corresponds to Figure 9A the dashed line with an arrow shown in Figure 10A is Figure 6B another schematic view of the array substrate 100 shown in Figure 9B For convenience of description,

[0100] As Figure 8B 、 Figures 9A - 9B and Figure 10AAs shown, the common electrode 131 includes a plurality of strip electrodes 132 arranged side by side in the first direction D1, and a first connection sub-electrode 133 and a second connection sub-electrode 134 which are opposite two sides of each of the plurality of common electrodes 131 in the second direction D2; the first connection sub-electrode 133 is connected to the first ends of the plurality of strip electrodes 132, and the second connection sub-electrode 134 is connected to the second ends of the plurality of strip electrodes 132; the orthographic projection of the first connection sub-electrode 133 on the first electrode layer overlaps (e.g., partially overlaps or completely overlaps) with the side of the corresponding gate line 110 close to the first connection sub-electrode 133, and the orthographic projection of the second connection sub-electrode 134 on the first electrode layer overlaps (e.g., partially overlaps or completely overlaps) with the side of the corresponding gate line 110 close to the second connection sub-electrode 134. For example, the orthographic projection of the first connection sub-electrode 133 (or the second connection sub-electrode 134) on the first electrode layer completely overlapping with the side of the corresponding gate line 110 close to the first connection sub-electrode 133 (or the second connection sub-electrode 134) means that the orthographic projection of the first connection sub-electrode 133 (or the second connection sub-electrode 134) on the first electrode layer is located within the gate line 110.

[0101] It should be noted that Figure 9A and Figure 9B the first connection sub-electrode 133 and the second connection sub-electrode 134 shown respectively belong to two adjacent common electrodes 131 in the second direction D2. For example, Figure 9A and Figure 9B there is a gap between the first connection sub-electrode 133 and the second connection sub-electrode 134 shown, and the gate line 110 that overlaps with the orthographic projections of both the first connection sub-electrode 133 and the second connection sub-electrode 134 on the first electrode layer overlaps (e.g., partially overlaps) with the orthographic projection of the above gap on the first electrode layer.

[0102] For example, as Figure 6B , Figure 8A , Figure 8B and Figure 9A shown, each of the first connection sub-electrode 133 and the second connection sub-electrode 134 has the same or similar shape as the corresponding first folded line structure 111 (the first folded line structure 111 of multiple gate lines 110 that overlaps with each of the first connection sub-electrode 133 and the second connection sub-electrode 134 in the second direction D2); each of the plurality of strip electrodes 132 has the same or similar shape as the corresponding second folded line structure 121 (the second folded line structure 121 of multiple data lines 120 that overlaps with each of the plurality of strip electrodes 132 in the first direction D1).

[0103] For example, each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 has the same extension trend in the first direction D1 as the corresponding regions of the plurality of gate lines 110. The corresponding regions of the plurality of gate lines 110 are the regions of the plurality of gate lines 110 that overlap with each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 in the second direction D2 (that is, the first folded - line structure 111 of the plurality of gate lines 110 that overlaps with each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 in the second direction D2); each of the plurality of strip - shaped electrodes 132 has the same extension trend in the second direction D2 as the corresponding regions of the plurality of data lines 120. The corresponding regions of the plurality of data lines 120 are the regions of the plurality of data lines 120 that overlap with the plurality of strip - shaped electrodes 132 in the first direction D1 (that is, the second folded - line structure 121 of the plurality of data lines 120 that overlaps with each of the plurality of strip - shaped electrodes 132 in the first direction D1).

[0104] It should be noted that each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 having the same extension trend in the first direction D1 as the corresponding regions of the plurality of gate lines 110 means that each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 has a first number of electrode segments, and the extension direction of each electrode segment of each of the first connection sub - electrodes 133 and the second connection sub - electrodes 134 is the same as the extension direction of the corresponding line segment of the corresponding first folded - line structure 111; each of the plurality of strip - shaped electrodes 132 having the same extension trend in the second direction D2 as the corresponding regions of the plurality of data lines 120 means that the plurality of strip - shaped electrodes 132 have a second number of electrode segments (the second folded - line structure 121 includes line segments of second data), and the extension direction of each electrode segment of each strip - shaped electrode 132 is the same as the extension direction of the corresponding line segment of the corresponding second folded - line structure 121.

[0105] For example, such as Figure 6B 、 Figure 8A 、 Figure 8B 、 Figure 9A and Figure 10AAs shown, each of the multiple first folded line structures 111 includes a first wiring portion (i.e., a line segment) 122 and a second wiring portion 113 that are directly connected in sequence. Each of the first wiring portion 112 and the second wiring portion 113 intersects with the first direction D1 and the second direction D2. Each of the first connecting sub-electrode 133 and the second connecting sub-electrode 134 includes a first electrode portion 1131 and a second electrode portion 1132 that are directly connected in sequence. Each of the first electrode portion (electrode segment) 1131 and the second electrode portion 1132 intersects with the first direction D1 and the second direction D2. For example, the extending directions of the first wiring portion 112 and the second wiring portion 113 are respectively equal to the extending directions of the first electrode portion 1131 and the second electrode portion 1132. For example, the first electrode portion 1131 and the second electrode portion 1132 respectively overlap with the first wiring portion 112 and the second wiring portion 113 in the second direction D2.

[0106] For example, as Figure 6B , Figure 8A , Figure 8B , Figure 9A and Figure 10A shown, each of the multiple second folded line structures 121 includes a third wiring portion 122 and a fourth wiring portion 123 that are directly connected in sequence. Each of the third wiring portion 122 and the fourth wiring portion 123 intersects with the first direction D1 and the second direction D2. Each of the multiple strip electrodes 132 includes a third electrode portion 1321 and a fourth electrode portion 1322 that are directly connected in sequence. Each of the third electrode portion 1321 and the fourth electrode portion 1322 intersects with the first direction D1 and the second direction D2. For example, the extending directions of the third wiring portion 122 and the fourth wiring portion 123 are respectively the same as the extending directions of the third electrode portion 1321 and the fourth electrode portion 1322. For example, the third electrode portion 1321 and the fourth electrode portion 1322 respectively overlap with the third wiring portion 122 and the fourth wiring portion 123 in the first direction D1.

[0107] It should be noted that the first folded line structure 111 and the first connecting sub-electrode 133 (or the second connecting sub-electrode 134) of the array substrate 100 provided by at least one embodiment of the present disclosure are not limited to Figure 6B and Figure 8A the structures shown. According to actual application requirements, the first folded line structure 111 and the first connecting sub-electrode 133 (or the second connecting sub-electrode 134) of the array substrate 100 provided by at least one embodiment of the present disclosure can also adopt Figure 10B the structures shown.

[0108] Figure 10BIt is a schematic plan view of another first broken line structure 111 and a first connecting sub-electrode 133 (or a second connecting sub-electrode 134) provided by at least one embodiment of the present disclosure. As Figure 10B shown, the first broken line structure 111 further includes a fifth wiring portion 114, a sixth wiring portion 115, and a seventh wiring portion 116. Each of the first connecting sub-electrode 133 and the second connecting sub-electrode 134 further includes a fifth electrode portion 1133, a sixth electrode portion 1134, and a seventh electrode portion 1135.

[0109] For example, the extending direction of the fifth wiring portion 114, the extending direction of the sixth wiring portion 115, and the extending direction of the seventh wiring portion 116 are respectively equal to the extending direction of the fifth electrode portion 1133, the extending direction of the sixth electrode portion 1134, and the extending direction of the seventh electrode portion 1135. For example, each of the fifth wiring portion 114, the sixth wiring portion 115, the seventh wiring portion 116, the fifth electrode portion 1133, the sixth electrode portion 1134, and the seventh electrode portion 1135 is parallel to the first direction D1.

[0110] For example, as Figure 10B shown, the fifth wiring portion 114, the first wiring portion 112, the sixth wiring portion 115, the second wiring portion 113, and the seventh wiring portion 116 are connected in sequence in the first direction D1; the fifth electrode portion 1133, the first electrode portion 1131, the sixth electrode portion 1134, the second electrode portion 1132, and the seventh electrode portion 1135 are connected in sequence in the first direction D1. For example, the seventh wiring portion 116 of each first broken line structure 111 is directly connected to the fifth wiring portion 114 of the first broken line structure 111 located on its right side, and the seventh electrode portion 1135 of each first connecting sub-electrode 133 (or second connecting sub-electrode 134) is directly connected to the fifth electrode portion 1133 of the first connecting sub-electrode 133 (or second connecting sub-electrode 134) located on its right side.

[0111] For example, the positive projection of each of the plurality of data lines 120 on the first electrode layer overlaps at least one of the fifth wiring portion 114 and the seventh wiring portion 116 of the corresponding first broken line structure 111.

[0112] For example, as Figure 9A shown, the gate line 110 is located within the gap formed by two sides 2211 and 2212 of the positive projection of the black matrix unit 221 on the first electrode layer in the fourth direction DA (perpendicular to the extending direction of the black matrix unit 221), that is, the gate line 110 is located within the positive projection of the black matrix unit 221 on the first electrode layer.

[0113] For example, as Figure 9BAs shown, the first electrode layer further includes a plurality of pixel electrodes 135; each of the plurality of pixel electrodes 135 is disposed (e.g., entirely located) in a corresponding light control pixel unit 130. For example, the plurality of pixel electrodes 135 and the plurality of light control pixel units 130 are in one-to-one correspondence. For example, the plurality of pixel electrodes 135 are spaced apart from each other, and the plurality of pixel electrodes 135 are not electrically connected to each other; as Figure 9B As shown, the plurality of pixel electrodes 135 and the plurality of gate lines 110 are spaced apart. For example, the width L2 of the spacing between each gate line 110 and the corresponding pixel electrode 135 in the fourth direction DA can be set according to actual application requirements, and the embodiments of the present disclosure do not make specific limitations thereto. For example, the width L2 of the spacing between each gate line 110 and the corresponding pixel electrode 135 in the fourth direction DA can be equal to 6-10 micrometers (e.g., 7.5 micrometers).

[0114] For example, as Figure 9B As shown, each of the plurality of pixel electrodes 135 is a plate-shaped electrode, and the orthographic projection of the plate-shaped electrode on the second electrode layer is a continuous plane. For example, as Figure 9B As shown, there are slits between the plurality of strip electrodes 132, and the orthographic projection of the pixel electrode 135 on the second electrode layer exposes from the above slits, so that the electric field formed by the pixel electrode 135 and the common electrode 131 can enter the side of the second electrode layer away from the first electrode layer (enter the liquid crystal layer 300), and drive the rotation of the liquid crystal molecules in the liquid crystal layer 300 as needed.

[0115] For example, the pixel electrode 135 and the gate line 110 are formed in different patterning processes. For example, the pixel electrode 135 can be formed of a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO). For example, by making the first electrode layer include both the plurality of gate lines 110 and the plurality of pixel electrodes 135 at the same time, the number of insulating layers provided in the direction perpendicular to the first substrate 101 can be reduced, and thus the thickness of the array substrate 100 can be reduced.

[0116] For example, as Figure 10AAs shown, each light control pixel unit 130 further includes a switching element 151, which is, for example, a thin film transistor; the thin film transistor includes a gate, a source, and a drain. For example, the gate of the thin film transistor is on the same layer as and electrically connected to the gate line 110, one of the source and the drain of the thin film transistor is on the same layer as and electrically connected to the data line 120, and the other of the source and the drain of the thin film transistor is electrically connected to the pixel electrode 135 (for example, via a via). For example, the pixel electrode 135 is configured to receive a data signal provided by the data line 120. For example, the data signals received by the pixel electrodes 135 included in different light control pixel units 130 may not be exactly the same and may vary according to display requirements. For example, the number of switching elements 151 is equal to the number of a plurality of first broken line structures 111.

[0117] For example, the gate line 110 is configured to receive a gate scan signal. For example, the gate line 110, the data line 120, and the common electrode line 140 are configured to be connected to different signal sources.

[0118] For example, as Figure 6A , Figure 6B and Figure 10A shown, the array substrate 100 further includes a plurality of common electrode lines 140. Each of the plurality of common electrode lines 140 extends integrally along the second direction D2 and includes a plurality of third broken line structures 141 directly connected in sequence in the second direction D2. For example, the common electrode 131 is configured to receive a common voltage signal. For example, the common voltage signal is a constant voltage signal. For example, a plurality of common electrodes 131 are configured to be electrically connected to each other via the plurality of common electrode lines 140 so that the common voltage signals on the plurality of common electrodes 131 are the same as each other. For example, the common electrode line 140 and the data line 120 are alternately arranged in the first direction D1.

[0119] For example, as Figure 6A , Figure 6B and Figure 10A shown, each of the plurality of third broken line structures 141 includes an eighth trace portion 142 and a ninth trace portion 143 directly connected in sequence. Each of the eighth trace portion 142 and the ninth trace portion 143 intersects with both the first direction D1 and the second direction D2. For example, the extending directions of the eighth trace portion 142 and the ninth trace portion 143 are the same as the extending directions of the third electrode portion 1321 and the fourth electrode portion 1322, respectively. For example, the eighth trace portion 142 and the ninth trace portion 143 overlap with the third electrode portion 1321 and the fourth electrode portion 1322, respectively, in the first direction D1.

[0120] For example, the positive projection of each of the multiple common electrode lines 140 on the first electrode layer overlaps with the intersection points of the first routing portion 112 and the second routing portion 113 of the corresponding first folded line structure 111. Another example is that the positive projection of each of the multiple common electrode lines 140 on the first electrode layer overlaps with the sixth routing portion 115 of the corresponding first folded line structure 111.

[0121] For example, the common electrode 131 can be formed of a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO). Another example is that the common electrode 131 can be formed of a metal material. For example, the first substrate 101 and the second substrate 210 can be transparent substrates. For example, the transparent substrate can be a glass substrate, a quartz substrate, a plastic substrate (such as a polyethylene terephthalate (PET) substrate), or a substrate made of other suitable materials. For example, the first insulating layer 102 and the second insulating layer 103 can be formed of inorganic or organic materials. For example, the first insulating layer 102 and the second insulating layer 103 can be formed of an organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride (SiNx). For example, the data line 120 can be formed of a metal material (such as copper, aluminum, or aluminum alloy). For example, the data line layer can be disposed between the first insulating layer 102 and the second insulating layer 103.

[0122] At least one embodiment of the present disclosure further provides a display device 01. For example, the display device 01 can be implemented as a display device based on ADS (Advanced Super Dimension Field Switching technology) or a display device based on IPS-ADS (i.e., i-ADS, In-Plane Switching - Advanced Super Dimension Field Switching technology).

[0123] Figure 11 is a cross-sectional schematic diagram of the display device 01 provided by at least one embodiment of the present disclosure. As Figure 11 shown, the display device 01 includes a display panel 30, a backlight unit 20, and any light control panel 10 provided by at least one embodiment of the present disclosure, which are stacked on each other in the third direction D3. The display panel 30 is located on the light-emitting side of the light control panel 10, and the backlight unit 20 is located on the side of the light control panel 10 away from the display panel 30. For example, as Figure 11 shown, the display panel 30, the light control panel 10, and the backlight unit 20 are sequentially arranged in the third direction D3. For example, compared with the counter substrate 201 of the light control panel 10, the array substrate 100 of the light control panel 10 is closer to the backlight unit 20.

[0124] Figure 12A is Figure 11 a plan view of the display panel 30 of the display device 01 shown in. As Figure 12AAs shown, the display panel 30 includes a plurality of first signal lines 305 extending along a first direction D1 and a plurality of second signal lines 306 extending along a second direction D2; the plurality of first signal lines 305 and the plurality of second signal lines 306 intersect to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 304 arranged in an array. For example, the first signal line 305 is a gate line of the display panel 20, and the second signal line 306 is a data line of the display panel 30. For example, the plurality of first signal lines 305 and the plurality of second signal lines 306 are connected to different signal sources.

[0125] As Figure 12A shown, each display pixel unit 304 includes a first display sub-pixel unit 3041, a second display sub-pixel unit 3042, and a third display sub-pixel unit 3043; the first display sub-pixel unit 3041, the second display sub-pixel unit 3042, and the third display sub-pixel unit 3043 are respectively, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit.

[0126] Figure 12B is Figure 11 a schematic plan view of the display device 01 shown. For example, as Figure 12B shown, the size of each light control pixel unit 130 in the first direction D1 is equal to twice the size of each display pixel unit 304 in the first direction D1, and the size of each light control pixel unit 130 in the second direction D2 is equal to or slightly smaller than four times the size of each display pixel unit 304 in the second direction D1.

[0127] For example, the display device 01 further includes an isotropic diffusion film (not shown in the figure) disposed between the display panel 30 and the light control panel 10. The isotropic diffusion film can diffuse the light emitted from the light control panel 10 within a small angular range, thereby blurring the pattern of the data line to further eliminate moiré, and at the same time, will not have a great impact on the direction of the light emitted from the light control panel 10.

[0128] For example, the display device 01 can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. It should be noted that for other components of the display device 01 (such as a control device, an image data encoding / decoding device, a line scan driver, a column scan driver, a clock circuit, etc.), applicable components can be used, which are all understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present disclosure.

[0129] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it on the basis of the embodiments of the present disclosure, which will be apparent to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present disclosure all fall within the scope of protection required by the present disclosure.

[0130] The above are only exemplary embodiments of the present disclosure and are not used to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising a data line layer, and a substrate substrate, a first electrode layer, an insulating layer, and a second electrode layer sequentially arranged, wherein, the first electrode layer includes a plurality of gate lines, each of the plurality of gate lines extends integrally along a first direction and includes a plurality of first broken line structures directly connected in sequence in the first direction; the data line layer includes a plurality of data lines, each of the plurality of data lines extends integrally along a second direction intersecting the first direction; the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of light control pixel units; the second electrode layer includes a plurality of common electrodes arranged in an array, and each of the plurality of common electrodes is disposed in at least one of the plurality of light control pixel units; and at least one of the plurality of gate lines and at least one of the common electrodes overlap at least partially in the orthographic projection on the first electrode layer.

2. The array substrate according to claim 1, wherein, for each of the plurality of common electrodes, the two opposite sides in the second direction overlap, in the orthographic projection on the first electrode layer, with one side of the corresponding two gate lines close to each of the plurality of common electrodes respectively.

3. The array substrate according to claim 2, wherein, a gap is provided between two adjacent common electrodes in the second direction, and the gate line that overlaps the orthographic projections of the two adjacent common electrodes in the second direction on the first electrode layer overlaps with the orthographic projection of the gap on the first electrode layer.

4. The array substrate according to any one of claims 1-3, wherein, each of the plurality of common electrodes includes: a plurality of strip electrodes arranged side by side in the first direction, and a first connecting sub-electrode and a second connecting sub-electrode serving as the two opposite sides of each of the plurality of common electrodes in the second direction; the first connecting sub-electrode is connected to the first ends of the plurality of strip electrodes, the second connecting sub-electrode is connected to the second ends of the plurality of strip electrodes; and the orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer overlap partially with one side of the corresponding two gate lines close to each of the plurality of common electrodes respectively.

5. The array substrate according to claim 4, wherein, each of the first connecting sub-electrode and the second connecting sub-electrode has the same extension trend as the corresponding region of the plurality of gate lines, and the corresponding region of the plurality of gate lines is the region of the plurality of gate lines that overlaps with each of the first connecting sub-electrode and the second connecting sub-electrode in the second direction; and each of the plurality of strip electrodes has the same extension trend as the corresponding region of the plurality of data lines, and the corresponding region of the plurality of data lines is the region of the plurality of data lines that overlaps with the plurality of strip electrodes in the first direction.

6. The array substrate according to claim 4, wherein, each of the plurality of data lines includes a plurality of second broken line structures directly connected in sequence in the second direction; and the plurality of first broken line structures included in the plurality of gate lines correspond one-to-one to the plurality of light control pixel units, and the plurality of second broken line structures included in the plurality of data lines correspond one-to-one to the plurality of light control pixel units.

7. The array substrate according to any one of claims 1-3, wherein, the first electrode layer further includes a plurality of pixel electrodes; each of the plurality of pixel electrodes is disposed in a corresponding light control pixel unit; and the plurality of pixel electrodes are arranged at intervals with the plurality of gate lines.

8. The array substrate according to claim 7, wherein, the pixel electrode is a plate-shaped electrode, and the orthographic projection of the plate-shaped electrode on the second electrode layer is a continuous plane.

9. The array substrate according to claim 8, wherein, each of the plurality of common electrodes includes: a plurality of strip-shaped electrodes arranged side by side in the first direction, and a first connecting sub-electrode and a second connecting sub-electrode that are opposite sides of each of the plurality of common electrodes in the second direction; the first connecting sub-electrode is connected to the first ends of the plurality of strip-shaped electrodes, and the second connecting sub-electrode is connected to the second ends of the plurality of strip-shaped electrodes; the orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer respectively partially overlap with one side of the corresponding two gate lines close to each of the plurality of common electrodes; and the orthographic projections of the plurality of pixel electrodes on the second electrode layer are exposed from the gaps between adjacent strip-shaped electrodes included in the corresponding common electrodes.

10. The array substrate according to claim 7, wherein, each of the plurality of common electrodes and the pixel electrodes includes a transparent conductive oxide, and each of the plurality of gate lines includes a metal.

11. The array substrate according to any one of claims 1-3, wherein, the surface of each of the plurality of gate lines on the side close to the second electrode layer has an uneven structure.

12. A light control panel, comprising: the array substrate, a counter substrate and a liquid crystal layer according to any one of claims 1-11, wherein, the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the array substrate and the counter substrate.

13. The light control panel according to claim 12, wherein, the counter substrate includes a black matrix layer; the black matrix layer includes a plurality of black matrix units, and each of the plurality of black matrix units extends integrally in the first direction; and the orthographic projections of the plurality of gate lines on the black matrix layer are respectively located within the corresponding black matrix units.

14. The light control panel according to claim 13, wherein, each of the plurality of black matrix units includes a plurality of black matrix structures that are directly connected in sequence in the first direction, and the orthographic projections of the plurality of first broken line structures included in the plurality of gate lines on the black matrix layer are respectively located in the corresponding black matrix structures.

15. The light control panel according to claim 13 or 14, wherein, the ratio of the width of each of the plurality of black matrix units to the width of the corresponding gate line is between 1 and 2.

5.

16. A display device, comprising: a display panel, a backlight unit, and the light control panel according to any one of claims 12-15, Among them, the display panel, the light control panel, and the backlight unit are stacked, the display panel is located on the light-emitting side of the light control panel, and the backlight unit is located on the side of the light control panel away from the display panel.

Images