A JTAG link automatic identification and expansion device

Abstract

The present invention provides a JTAG link automatic identification and expansion device, comprising at least two PCBs, each of which is provided with a first JTAG connector, a second JTAG connector, a two-choice chip, and a JTAG sub-link formed by at least one JTAG device connected in series. The present invention changes the control signal input of the two-choice chip by disconnecting and connecting the second JTAG connector on the first PCB of two adjacent PCBs with the first JTAG connector on the second PCB, thereby automatically adjusting the length of the JTAG link, without the need for software control, and can selectively select the range of test objects according to needs, providing users with more selectivity.

Description

Technical Field

[0001] The invention relates to the technical field of cascading JTAG links between PCB boards, in particular to a JTAG link automatic identification and expansion device. Background Art

[0002] JTAG (Joint Test Action Group) is an international standard test protocol, mainly used for internal chip testing. At present, many complex devices support the JTAG protocol, such as DSP, FPGA and other devices. Generally, such devices that support the JTAG protocol are called JTAG devices. JTAG devices can be easily downloaded and debugged through the JTAG connector.

[0003] When there are multiple JTAG devices in the circuit, if a separate JTAG connector is set for each JTAG device, the space occupied by the circuit will be greatly increased. One solution is to connect multiple JTAG devices in the circuit in series into a JTAG link (i.e., TDI connects TDO connects TDI to form a non-closed JTAG link, wherein the JTAG device that is not connected in series with the TDO pin of other JTAG devices in the JTAG link can be called the first JTAG device of the JTAG link, and the JTAG device that is not connected in series with the TDI pin of other JTAG devices in the JTAG link can be called the last JTAG device of the JTAG link), then the download and debugging of each JTAG device can be completed through a JTAG connector, and the connectivity between each JTAG device can also be tested through the JTAG link.

[0004] At present, the industry has derived a variety of application scenarios based on JTAG links, but the existing cascading and adjustment solutions of JTAG links between PCB boards need to be controlled by software, and cannot automatically identify and adjust the length of the JTAG link. It can only achieve a fixed JTAG maximum link, which has certain constraints. Moreover, during use, it is more inclined to achieve cascading from the overall to the local stages of the circuit, but the existing solutions cannot meet the needs of local circuit debugging. Summary of the invention

[0005] The purpose of the present invention is to provide a JTAG link automatic identification and expansion device, which can realize the cascading of JTAG links between PCB boards without the help of software, and automatically identify and adjust the length of the JTAG link.

[0006] The technical solution of the present invention is:

[0007] A JTAG link automatic identification and expansion device includes at least two PCBs, each of which is provided with a first JTAG connector, a second JTAG connector, a two-choice chip, and a JTAG sub-link formed by at least one JTAG device connected in series;

[0008] When the second JTAG connector on the first PCB of the two adjacent PCBs is disconnected from the first JTAG connector on the second PCB, the first signal transmission channel of the two-choose-one chip is turned on, and the JTAG sub-link on the first PCB is disconnected from the JTAG sub-link on the second PCB;

[0009] When the second JTAG connector on the first PCB of two adjacent PCBs is connected to the first JTAG connector on the second PCB, the second signal transmission channel of the two-to-one chip is turned on, and the JTAG sub-link on the first PCB is connected to the JTAG sub-link on the second PCB.

[0010] The JTAG link automatic identification and expansion device, the TDI pin of the first JTAG device of the JTAG sub-link on each PCB is connected to the TDI pin of the first JTAG connector, the TDO pin of the last JTAG device is respectively connected to the TDO pin of the second JTAG connector and the first input pin of the two-choice chip, the second input pin of the two-choice chip is connected to the TDI pin of the second JTAG connector, and the output pin of the two-choice chip is connected to the TDO pin of the first JTAG connector;

[0011] The port input pin of the first JTAG connector is connected to GND, the port input pin of the second JTAG connector is connected to the control signal input pin of the two-choice chip, and the node between the port input pin of the second JTAG connector and the control signal input pin of the two-choice chip is connected to VCC through a pull-up resistor;

[0012] When the second JTAG connector on the first PCB of the two adjacent PCBs is disconnected from the first JTAG connector on the second PCB, the control signal input of the two-choice chip on the first PCB is at a high level, and the signal on the first input pin of the two-choice chip reaches the output pin through the first signal transmission channel;

[0013] When the second JTAG connector on the first of two adjacent PCBs is connected to the first JTAG connector on the second PCB, the control signal input of the two-to-one chip on the first PCB is at a low level, and the signal on the second input pin of the two-to-one chip reaches the output pin through the second signal transmission channel.

[0014] The JTAG link automatic identification and expansion device, the JTAG device is an FPGA chip.

[0015] It can be seen from the above technical solution that the present invention realizes automatic length adjustment of the JTAG link by connecting and disconnecting the JTAG connectors between PCB boards, without the need for software control, and can selectively select the range of test objects according to needs, providing users with more options. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of the present invention;

[0017] Figure 2 It is a schematic diagram of the working principle of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described below with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 1 , Figure 2 As shown, a JTAG link automatic identification and expansion device includes at least two PCB0s, each of which is provided with a first JTAG connector 1, a second JTAG connector 2, a two-choice chip 3 and a JTAG sub-link 4 formed by at least one JTAG device connected in series (the JTAG sub-link mentioned here has the same definition as the well-known JTAG link, but different names are used for convenience of expression, the same below).

[0020] The TDI pin of the first JTAG device of the JTAG sub-link 4 on each PCB0 is connected to the TDI pin of the first JTAG connector 1, the TDO pin of the last JTAG device of the JTAG sub-link 4 is respectively connected to the TDO pin of the second JTAG connector 2 and the first input pin IN1 of the two-to-one chip 3, the second input pin IN2 of the two-to-one chip 3 is connected to the TDI pin of the second JTAG connector 2, and the output pin OUT of the two-to-one chip 3 is connected to the TDO pin of the first JTAG connector 1.

[0021] The PINx pin (port input pin) of the first JTAG connector 1 is connected to GND, the PINx pin (port input pin) of the second JTAG connector 2 is connected to the control signal input pin S of the two-to-one chip 3, and the node between the PINx pin of the second JTAG connector 2 and the control signal input pin S of the two-to-one chip 3 is connected to VCC through a pull-up resistor 5.

[0022] When the second JTAG connector 2 on the first PCB0 of two adjacent PCB0 is disconnected from the first JTAG connector 1 on the second PCB0 (at this time, the PINx pin of the second JTAG connector 2 on the first PCB0 is disconnected from the PINx pin of the first JTAG connector 1 on the second PCB0), the control signal SEL input of the two-select-one chip 3 on the first PCB0 is high level, the first signal transmission channel of the two-select-one chip 3 is turned on, and the signal on the first input pin IN1 of the two-select-one chip 3 reaches the output pin OUT through the first signal transmission channel of the two-select-one chip 3.

[0023] When the second JTAG connector 2 on the first PCB0 of two adjacent PCB0 is connected to the first JTAG connector 1 on the second PCB0 (at this time, the PINx pin of the second JTAG connector 2 on the first PCB0 is connected to the PINx pin of the first JTAG connector 1 on the second PCB0), the control signal SEL input of the two-select-one chip 3 on the first PCB0 is at a low level, the second signal transmission channel of the two-select-one chip 3 is turned on, and the signal on the second input pin IN2 of the two-select-one chip 3 reaches the output pin OUT through the second signal transmission channel of the two-select-one chip 3.

[0024] In this embodiment, the JTAG device constituting the JTAG sub-link 4 is an FPGA chip.

[0025] Working principle of the present invention:

[0026] like Figure 2 As shown in the figure, assuming that the number of PCB0 is 2, this example is used for explanation:

[0027] When the second JTAG connector 2 on the first PCB0 is suspended, the value of the control signal SEL of the two-select-one chip 3 on the first PCB0 is VCC. At this time, the first signal transmission channel between the first input pin IN1 and the output pin OUT of the two-select-one chip 3 on the first PCB0 is turned on.

[0028] The JTAG path is: the first JTAG connector 1 on the first PCB0 → the JTAG sub-link 4 on the first PCB0 → the first JTAG connector 1 on the first PCB0, that is, only the intra-board JTAG link of the first PCB0 can be realized. In this JTAG path, the first JTAG connector 1 on the first PCB0 is used as the system debugging interface connector.

[0029] When the second JTAG connector 2 on the first PCB0 is plugged and interconnected with the first JTAG connector 1 on the second PCB0, the value of the control signal SEL of the two-to-one chip 3 on the first PCB0 is GND. At this time, the second signal transmission channel between the second input pin IN2 and the output pin OUT of the two-to-one chip 3 on the first PCB0 is turned on.

[0030] The JTAG path is: the first JTAG connector 1 on the first PCB0 → the JTAG sub-link 4 on the first PCB0 → the JTAG sub-link 4 on the second PCB0 → the first JTAG connector 1 on the first PCB0, which means that the JTAG link cascade between the two PCB0 boards is realized. In this JTAG path, the first JTAG connector 1 on the first PCB0 is used as the system debugging interface connector.

[0031] In summary, the present invention can change the level of the control signal SEL by plugging and unplugging the JTAG connector on the adjacent PCB according to the needs, and the control signal SEL adjusts the number of connections of the JTAG sub-link by controlling the signal transmission channel of the two-choice chip, thereby realizing automatic length adjustment of the JTAG link.

[0032] The above-described embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A JTAG link automatic identification and expansion device, comprising at least two PCBs, characterized in that: Each PCB is provided with a first JTAG connector, a second JTAG connector, a two-choice chip, and a JTAG sub-link formed by at least one JTAG device connected in series; When the second JTAG connector on the first PCB of the two adjacent PCBs is disconnected from the first JTAG connector on the second PCB, the first signal transmission channel of the two-choose-one chip is turned on, and the JTAG sub-link on the first PCB is disconnected from the JTAG sub-link on the second PCB; When the second JTAG connector on the first PCB of the two adjacent PCBs is connected to the first JTAG connector on the second PCB, the second signal transmission channel of the two-choose-one chip is turned on, and the JTAG sub-link on the first PCB is connected to the JTAG sub-link on the second PCB; The TDI pin of the first JTAG device of the JTAG sub-link on each PCB is connected to the TDI pin of the first JTAG connector, the TDO pin of the last JTAG device is respectively connected to the TDO pin of the second JTAG connector and the first input pin of the two-choice chip, the second input pin of the two-choice chip is connected to the TDI pin of the second JTAG connector, and the output pin of the two-choice chip is connected to the TDO pin of the first JTAG connector; The port input pin of the first JTAG connector is connected to GND, the port input pin of the second JTAG connector is connected to the control signal input pin of the two-choice chip, and the node between the port input pin of the second JTAG connector and the control signal input pin of the two-choice chip is connected to VCC through a pull-up resistor; When the second JTAG connector on the first PCB of the two adjacent PCBs is disconnected from the first JTAG connector on the second PCB, the control signal input of the two-choice chip on the first PCB is at a high level, and the signal on the first input pin of the two-choice chip reaches the output pin through the first signal transmission channel; When the second JTAG connector on the first of two adjacent PCBs is connected to the first JTAG connector on the second PCB, the control signal input of the two-to-one chip on the first PCB is at a low level, and the signal on the second input pin of the two-to-one chip reaches the output pin through the second signal transmission channel.

2. The JTAG link automatic identification and expansion device according to claim 1, characterized in that: The JTAG device is an FPGA chip.

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