Power metallization structures for semiconductor devices

Abstract

A power metallization structure for a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a power metallization structure formed on the semiconductor substrate, and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent metal atoms from diffusing from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or a conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer inserted between the barrier layer and the power metallization structure in a second region. A corresponding method for manufacturing the semiconductor device is also described.

Description

Background Art

[0001] Copper is widely used as power metallization in semiconductor devices. However, when copper thin films are subjected to temperature cycles, they undergo elastic and plastic deformations, which induce stresses on surrounding components such as barriers, ILDs (interlayer dielectrics), passivation, etc. The stress induced by the copper thin film may lead to one or more failure modes, such as cracks in the passivation and / or in the device substrate, delamination between the copper thin film metal and the barrier, etc. The induced stress strongly depends on the morphology of the power metal after structuring. Therefore, improved measures are needed for mitigating the stress induced by copper thin films used in semiconductor devices.

[0002] In addition, thick copper has low wiring density due to low spacing. The increase in wiring density can be achieved by adding additional wiring layers, which include metal deposition and patterning, ILD deposition for insulation, and through-hole etching to connect metal layers. This adds to the overall cost of the semiconductor device. For power technologies with thick copper metallization and bonding on active areas, additional softer (e.g., aluminum) layers increase layout complexity. Copper damascene processes circumvent such problems, but have extremely high additional costs. Therefore, improved measures are needed to increase wiring density when using copper metallization in semiconductor devices. Summary of the invention

[0003] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor substrate; a power metallization structure formed on the semiconductor substrate; a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer being configured to prevent metal atoms from diffusing from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or a conductive layer formed on the barrier layer in a first region; and a passivation layer inserted between the barrier layer and the power metallization structure in a second region.

[0004] In an embodiment, the barrier layer may be structured into a signal wiring structure in the second region.

[0005] Separately or in combination, the power metallization structure may be disposed over the signal wiring structure in the second region, and the signal wiring structure may be insulated from the power metallization structure by a passivation layer in the second region.

[0006] Separately or in combination, the power metallization structure may be structured independently from the signal wiring structure in the second region.

[0007] Separately or in combination, the first region and the second region may directly adjoin, the power metallization structure and the barrier layer may be unpatterned in the first region and the second region, and the passivation layer may cover the periphery of the barrier layer in the second region.

[0008] Separately or in combination, the barrier layer can extend laterally beyond side faces of the power metallization structure in the second region.

[0009] Separately or in combination, the barrier layer may extend laterally between 500 nm and 5 micrometers beyond the side faces of the power metallization structure in the second region.

[0010] Separately or in combination, a passivation layer may be inserted between the barrier layer and the power metallization structure in a section of the second region separated from the first region.

[0011] Separately or in combination, the barrier layer may be structured as a signal wiring structure in a section of the second region separated from the first region.

[0012] Separately or in combination, the power metallization structure may be disposed over the signal wiring structure in a section of the second region separated from the first region, and the signal wiring structure may be insulated from the power metallization structure by a passivation layer.

[0013] Separately or in combination, the power metallization structure may be structured independently of the signal wiring structure in a section of the second region separated from the first region.

[0014] Separately or in combination, the semiconductor device may further include an intermediate layer interposed between the barrier layer and the passivation layer in the second region, and the intermediate layer may be structured identically to the barrier layer in the second region.

[0015] Separately or in combination, the barrier layer may include TiW, the intermediate layer may include AlCu and the power metallization structure may include Cu.

[0016] Separately or in combination, the semiconductor device may further include an intermediate layer interposed between the passivation layer and the power metallization structure in the second region.

[0017] Separately or in combination, the barrier layer may include TiW, the intermediate layer may include TiW and the power metallization structure may include Cu.

[0018] Separately or in combination, a power metallization structure above the barrier layer can be omitted in the second region.

[0019] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming a barrier layer on a semiconductor substrate, wherein the barrier layer is configured to prevent metal atoms from diffusing from the barrier layer in a direction toward the semiconductor substrate; structuring the barrier layer; and after structuring the barrier layer, forming a power metallization structure on the structured barrier layer without forming an additional barrier layer for the power metallization structure, the power metallization structure being in direct contact with the barrier layer or a conductive layer formed on the barrier layer in a first region.

[0020] In an embodiment, forming a power metallization structure may include: after structuring the barrier layer, forming an adhesion promoting layer on the barrier layer and forming a Cu layer on the adhesion promoting layer, the adhesion promoting layer being configured to increase adhesion of the power metallization structure to the barrier layer in a first region; forming a mask on the Cu layer, the mask having openings aligned with features previously structured into the barrier layer; and isotropically etching the Cu layer and the adhesion promoting layer through the openings in the mask to structure the power metallization structure and thereby the barrier layer laterally extends beyond the sides of the power metallization structure in regions aligned with the openings in the mask. In the case of Cu metallization, the adhesion promoting layer may not be combined with the (thick) Cu layer after sputtering and etching, but may instead be formed as part of an electrochemical deposition (ECD) process for forming the Cu layer.

[0021] Separately or in combination, the method may further include: before structuring the barrier layer, forming a protection layer on the barrier layer, the protection layer being configured to prevent oxidation of the barrier layer during structuring.

[0022] Separately or in combination, forming a power metallization structure may include: forming a Cu seed layer on the protective layer after structuring the protective layer and the barrier layer; forming a mask on the Cu seed layer in the second region; forming a Cu layer on the Cu seed layer in the first region but not in the second region where the mask is present; and after forming the Cu layer, removing the mask and the Cu seed layer from the protective layer in the second region.

[0023] Separately or in combination, forming a power metallization structure may include: forming a passivation layer on the protective layer after structuring the protective layer and the barrier layer; removing the passivation layer in the first region but not in the second region; forming a Cu seed layer on the protective layer in the first region and on the passivation layer in the second region; and forming a Cu layer on the Cu seed layer in at least the first region.

[0024] Separately or in combination, the method may further include: before forming the Cu layer, forming a mask on the Cu seed layer in the second region, thereby forming the Cu layer on the Cu seed layer in the first region instead of in the second region where the mask exists; and after forming the Cu layer, removing the mask.

[0025] Separately or in combination, the method may further include removing the Cu seed layer from the passivation layer in the second region after removing the mask.

[0026] Separately or in combination, a Cu layer may be formed in the first region and in the second region, and a passivation layer may be interposed between the barrier layer and the Cu layer in the second region.

[0027] Separately or in combination, the barrier layer may be structured as a signal wiring structure in the second region, and the method may further include structuring the Cu layer in the second region independently of the signal wiring structure.

[0028] Separately or in combination, forming the power metallization structure may include: forming a passivation layer on the protective layer after structuring the protective layer and the barrier layer; removing the passivation layer in the first region but not in the second region; and forming a Cu layer on the protective layer in the first region and on the passivation layer in the second region by physical vapor deposition.

[0029] Separately or in combination, the method may further include removing the Cu layer from the passivation layer in the second region.

[0030] Separately or in combination, the barrier layer may be structured as a signal wiring structure in the second region and the method may further include: structuring the Cu layer in the second region independently of the signal wiring structure.

[0031] Separately or in combination, the protective layer may be deposited in situ together with the barrier layer, and the protective layer and the barrier layer may be structured simultaneously.

[0032] Separately or in combination, the protective layer may include AlCu and the barrier layer may include TiW.

[0033] Separately or in combination, forming the protective layer may include depositing an oxide layer on the barrier layer using atomic layer deposition.

[0034] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are detailed in the subsequent description.

[0036] Figure 1 A partial cross-sectional view of an embodiment of a semiconductor device is illustrated.

[0037] FIG. 2A to FIG. 2E Graphic Manufacturing Figure 1 An embodiment of a method for a semiconductor device is shown in FIG.

[0038] Figure 3 A partial cross-sectional view of another embodiment of a semiconductor device is illustrated.

[0039] Figure 4 A partial cross-sectional view of another embodiment of a semiconductor device is illustrated.

[0040] FIG. 5A to FIG. 5F An embodiment of a method of manufacturing a semiconductor device is illustrated.

[0041] 6A to 6H Another embodiment of a method of manufacturing a semiconductor device is shown.

[0042] Figure 7A to Figure 7G Another embodiment of a method of manufacturing a semiconductor device is shown.

[0043] FIG. 8A to FIG. 8E Another embodiment of a method of manufacturing a semiconductor device is shown. DETAILED DESCRIPTION

[0044] Embodiments described herein provide a semiconductor device comprising: a semiconductor substrate; a power metallization structure formed on the semiconductor substrate; and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer prevents metal atoms from diffusing from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or a conductive layer formed on the barrier layer in the first region, and a passivation layer is inserted between the barrier layer and the power metallization structure in the second region. In one embodiment, the barrier layer is structured as a signal wiring structure in the second region. According to this embodiment, the signal wiring structure is implemented by the barrier layer rather than by the overlying power metallization structure, and the power metallization structure can have a lower wiring density due to its relatively thick construction compared to the barrier layer. In another embodiment, the first region and the second region are directly adjacent, the power metallization structure and the barrier layer are unpatterned in the first region and the second region, and the passivation layer covers the periphery of the barrier layer in the second region. According to this embodiment, a pad-like structure is formed in the second region and includes a passivation layer separating the barrier layer from the power metallization structure. The pad-like structure surrounds a first region where the power metallization structure and the barrier layer are not separated from each other by the passivation layer. In another embodiment, the semiconductor device comprises both the signal wiring structure and the pad-like structure. A corresponding manufacturing method is also described.

[0045] Figure 1 The semiconductor device includes a semiconductor substrate 100, a power metallization structure 102 formed on the semiconductor substrate 100, and a barrier layer 104 formed between the power metallization structure 102 and the semiconductor substrate 100. The barrier layer 104 may be formed as shown in FIG. Figure 1, or the barrier layer 104 may be separated from the semiconductor substrate 100 by one or more insulating layers. In either case, the semiconductor substrate 100 may be any type of semiconductor substrate typically used to implement logic and / or power semiconductor devices. For example, the semiconductor substrate 100 may be a Si substrate, a Si-on-insulator (SOI) substrate, a GaN substrate, a SiC substrate, a GaAs substrate, another type of III-V or II-VI substrate, etc.

[0046] Various power metallization / barrier combinations are contemplated. For example, the power metallization 102 may include Cu and the barrier 104 may include at least one of Ti, TiW, W, and Ta. In another embodiment, the power metallization 102 includes Al or an Al alloy, and the barrier 104 includes at least one of Ti, TiN, and W. In yet another embodiment, the power metallization 102 includes Au, and the barrier 104 is compatible with Au. A common barrier for at least Cu and Al metal systems is TiW. Still other power metallization / barrier combinations are possible.

[0047] The barrier layer 104 is configured to prevent metal atoms from diffusing from the power metallization structure 102 in a direction toward the semiconductor substrate 100. For example, in the case of Cu metallization, the barrier layer 104 may include TiW or any other suitable metal layer or stack of metal sub-layers configured to prevent Cu atoms from diffusing from the power metallization structure 102 in a direction toward the semiconductor substrate 100.

[0048] In the first region 106 of the semiconductor device, the power metallization structure 102 is in direct contact with the barrier layer 104 or an intermediate conductive layer 108 formed on the barrier layer 104. That is, there is direct electrical contact between the power metallization structure 102 and the barrier layer 104 or an intermediate conductive layer 108 formed on the barrier layer 104 in the first region 106 of the semiconductor device.

[0049] In one embodiment, the intermediate layer 108 is a conductive adhesion promoting layer configured to increase the adhesion of the power metallization structure 102 to the underlying barrier layer 104 in the first region 106. For Cu metallization, the barrier layer 104 may include a relatively thick TiW layer, while the intermediate layer 108 may include a relatively thin TiW layer or Ti layer. If relatively thin, the TiW or Ti intermediate layer 108 may be an ineffective barrier against the migration of Cu atoms, but if formed as part of the power metallization structure process, increases the adhesion of the power metallization structure 102 to the barrier layer 104. In the case of Cu metallization, the adhesion promoting layer 108 may not be bonded to the underlying (thick) Cu layer after sputtering and etching, but may instead be formed as part of the electrochemical deposition (ECD) process used to form the Cu layer.

[0050] A thin oxide layer may inevitably form on the barrier layer 104 during structuring. To achieve proper adhesion, a TiW or Ti intermediate layer 108 and a thicker Cu metallization may be formed via the same process. Alternatively, oxidation may be prevented, which is described in the next embodiment.

[0051] In another embodiment, the intermediate layer 108 is an anti-oxidation layer formed on the barrier layer 104 before the structuring of the barrier layer 104. As will be described in more detail later herein, the barrier layer 104 is structured / patterned before the power metallization structure 102 is formed. Depending on the composition of the barrier layer 104, the barrier layer 104 may oxidize when exposed during the structuring / patterning process. For example, when exposed, TiW oxidizes, which may reduce the adhesion of the barrier layer 104 to the power metallization structure 102. During the structuring of the barrier layer 104, the anti-oxidation layer 108 protects the barrier layer 104 from oxidation. For Cu metallization, the barrier layer 104 may include TiW and the intermediate layer 108 may include AlCu. The AlCu intermediate layer 108 is effective in preventing oxidation of TiW and other types of barrier layer materials. There are also other types of materials that can be used for the intermediate layer 108. Depending on the composition of the intermediate layer 108 and the processing parameters involved, the intermediate layer 108 may or may not exist in the first area 106 of the final semiconductor device.

[0052] The semiconductor device further includes an electrically insulating passivation layer 110 interposed between the barrier layer 104 and the power metallization structure 102 in a second region 112 of the semiconductor device that is different from the first region 106. In the second region 112, an intermediate layer 108 is interposed between the barrier layer 104 and the passivation layer 110. In the case where the intermediate layer 108 is an anti-oxidation layer for the barrier layer 104 as previously described herein, the intermediate layer 108 is structured identically to the barrier layer 104 in the second region 112 because the intermediate layer 108 is formed on the barrier layer 104 prior to structuring of the barrier layer 104.

[0053] In the first section 112a of the second region 112, the barrier layer 104 may be structured as a signal wiring structure 114. Because the barrier layer 104 is significantly thinner than the power metallization structure 102, for example, one-half, one-fifth, one-tenth, one-twentieth, one-fiftieth or thinner than the power metallization structure 102, the barrier layer 104 has a higher wiring density than the power metallization structure 102. Figure 1 As shown in FIG. 1 , the power metallization structure 102 may be disposed above the signal wiring structure 114 in the first section 112a of the second region 112 of the semiconductor device. In this case, the signal wiring structure 114 is insulated from the overlying power metallization structure 102 by the passivation layer 110 in the first section 112a of the second region 112. The power metallization structure 102 may be structured independently of the signal wiring structure 114 in the first section 112a of the second region 112. That is, because the signal wiring structure 114 is formed before the power metallization structure 102, the power metallization structure 102 and the signal wiring structure 114 may have different or independent wiring configurations.

[0054] In the second section 112b of the second region 112 of the semiconductor device, the first region 106 and the second region 112 are directly adjacent. The power metallization structure 102 and the barrier layer 104 may be unpatterned in the first region 106 and in the second section 112b of the second region 112, and the passivation layer 110 may cover the periphery of the barrier layer 104 in the second section 112b of the second region 112 to form a shim-like structure 116 in the second region 112, the shim-like structure 116 including the passivation layer 110 separating the barrier layer 104 from the power metallization structure 102. The shim-like structure 116 surrounds the first region 106 in which the power metallization structure 102 and the barrier layer 104 are not separated from each other by the passivation layer 110.

[0055] The barrier layer 104 may extend laterally beyond the side 118 of the power metallization structure 102 in the second section 112b of the second region 112 to form a shim-like structure 116. For example, the barrier layer 104 may extend laterally beyond the side 118 of the power metallization structure 102 by an amount x between 500 nm and 5 micrometers in the second section 112b of the second region 112 to form the shim-like structure 116. The shim-like structure 116 acts as a compressive barrier to prevent cracks.

[0056] For example, as in Figure 1 , the semiconductor device may include both a barrier layer signal wiring structure 114 in a first section 112a of a second region 112 of the device and a pad-like structure 116 in a second section 112b of the second region 112 of the device. In this embodiment, in the first section 112a of the second region 112 of the semiconductor device, the barrier layer 104 is structured as the signal wiring structure 114 and the passivation layer 110 is inserted between the signal wiring structure 114 and the power metallization structure 102. The power metallization structure 102 may be disposed above the barrier layer signal wiring structure 114. In this case, the barrier layer signal wiring structure 114 is insulated from the power metallization structure 102 by the passivation layer 110 in the first section 112a of the second region 112 of the device. As previously described herein, the power metallization structure 102 may be structured independently of the barrier layer signal wiring structure 114 in the first section 112a of the second region 112 of the device.

[0057] FIG. 2A to FIG. 2E Picture made in Figure 1 An embodiment of a method for a semiconductor device is shown in FIG.

[0058] Figure 2A The semiconductor device is shown after forming an intermediate layer 108 on the barrier layer 104, after structuring the intermediate / barrier layer stack 104 / 108 in the first section 112a of the second region 112 of the device to form a signal wiring structure 114, and after forming a passivation layer 110 on the structured intermediate / barrier layer stack 104 / 108. According to this embodiment, the intermediate layer 108 is an anti-oxidation layer formed on the barrier layer 104 before structuring of the barrier layer 104. For example, the barrier layer 104 may include TiW and the intermediate layer 108 may include AlCu. In a more specific example, the intermediate layer 104 may be a 30nm to 70nm thick AlCu layer deposited in situ on the TiW barrier layer 104. The subsequent alloying of such an AlCu intermediate layer 108 with the thick Cu power metallization structure 102 improves fatigue robustness.

[0059] In one embodiment, the barrier layer 104 is covered in situ by the intermediate layer 108 to protect the barrier layer 104 from oxidation during the subsequent structuring / patterning process. The intermediate layer 108 may alternatively be formed ex situ. Examples of the intermediate layer 108 include, but are not limited to, a thin metal film such as 30nm to 70nm of AlCu or Ti, an ultra-thin metal film such as 2nm of Au, an ALD (atomic layer deposition) Ultra-thin interlayer dielectric layer, etc.

[0060] according to Figure 2A In the embodiment shown in , the intermediate layer 108 may include one or more material sub-layers and is structured / patterned together with the barrier layer 104. The intermediate layer 108 may remain on the barrier layer 104 until the end of manufacturing, or may be removed or diffused in a later stage. For example, the intermediate layer 108 may be removed by a dedicated removal step before starting to form the power metallization structure 102, by diffusion of the intermediate layer 108 into the barrier layer 104 and / or the power metallization structure 102 during a subsequent anneal, etc. In the case of an Al-based intermediate layer 108 and a TiW barrier layer 104, the intermediate layer 108 not only protects the barrier layer 104 from oxidation during the subsequent structuring / patterning process, but also remains on the barrier layer wiring structure 114, where the intermediate layer 108 improves the conductivity of the barrier layer 104, which typically has a higher impedance.

[0061] The intermediate / barrier layer stack 104 / 108 can be structured / patterned simultaneously, for example, by a lithography-assisted plasma etching process such as a Cl-based and / or F-based plasma etching process. The resulting structured intermediate / barrier layer stack 104 / 108 can be passivated by a passivation layer 110. Any typical passivation material can be used for the passivation layer 110, the passivation material being, for example, silicon nitride and / or silicon oxide. In the case of silicon nitride and / or silicon oxide, the passivation layer 110 can be formed by chemical vapor deposition (CVD). The barrier layer wiring structure 114 and the pad-like structure 116 are defined by the structuring / patterning process for the intermediate / barrier layer stack 104 / 108.

[0062] Figure 2B The semiconductor device is shown after a mask 200, such as a photoresist, is formed on the passivation layer 110 and after unprotected portions of the passivation layer 110 are removed to expose the barrier layer wiring structure 114 and the pad-like structure 116. For example, the passivation layer 110 may be lithographically processed and plasma structured to define via or pad openings 202 to the underlying barrier layer wiring structure 114 and the pad-like structure 116. The mask 200 is then removed.

[0063] Figure 2C The semiconductor device is shown after physical vapor deposition (PVD) of a Cu seed layer 204 over the exposed portions of the remaining passivation layer 110 and the intermediate layer 108. The Cu seed layer 204 may be used in the case of a Cu power metallization structure 102. The Cu seed layer 204 may be omitted for other types of power metallization materials such as Al, Au, etc. If the Cu seed layer 204 is used, a thin Al layer (not shown) may be formed on the passivation layer 110 to improve adhesion between the passivation layer 110 and the subsequently formed power metallization structure 102.

[0064] Figure 2D The semiconductor device is shown after electrochemical deposition (ECD) of a thick Cu power metal 206 on the Cu seed layer 204. A mask 208, such as a photoresist, may be used to prevent ECD of the thick Cu power metal 206 in certain regions of the device, for example to allow the thick Cu power metal 206 to be structured independently over the wiring structure 114 formed by the barrier layer 104, which is still covered by the passivation layer 110 in this region 112a of the device. Figure 2C and Figure 2D As shown in FIG. 1 , the power metallization 102 is formed above the structured barrier layer 104 without forming an additional barrier layer for the power metallization 102 .

[0065] Figure 2E The semiconductor device is shown after removing the mask 208. The thick Cu power metal 206 can then be used as a hard mask for removing the exposed Cu seed layer 204, for example, by blanket wet etching. If a passivation layer 110 is present above the wiring structure 114, the passivation layer 110 ensures that the underlying barrier wiring structure 114 is electrically isolated from the overlying power metallization structure 102. The semiconductor device is then annealed to complete the power metallization structure 102. Figure 1 The resulting device is shown in .

[0066] As explained above, as a result of the annealing process, some or all of the intermediate layer 108 may diffuse. However, in other cases, there may be little or no diffusion of the intermediate layer 108. In these cases, the intermediate layer 108 may be formed as in Figure 1 remains substantially intact as shown in FIG.

[0067] Figure 3An embodiment is shown in which the intermediate layer 108 remains substantially intact in the barrier wiring structure 114 and the pad-like structure 116 but does not remain intact in the region 106 (where the passivation layer 110 is removed). According to this embodiment, in this region 106, the intermediate layer 108 diffuses into the power metallization structure 102 and the barrier layer 104 is in direct contact with the power metallization structure 102.

[0068] Figure 4 An embodiment is illustrated in which the intermediate layer 108 does not exist as a defining layer in the final device. In one embodiment, the intermediate layer 108 is formed by ALD and the intermediate layer 108 is inherently removed by the subsequent ECD process for forming the power metallization structure 102, and thus the intermediate layer 108 does not diffuse into the barrier layer 104 or the power metallization structure 102. In another embodiment, the intermediate layer 108 diffuses into the barrier layer 104 and / or the power metallization structure 102. For example, in the case of AlCu as the intermediate layer 108, during the annealing process, a component of Al may diffuse into the barrier layer 104 and / or the power metallization structure 102.

[0069] FIG. 5A to FIG. 5F Another embodiment of a method of manufacturing a semiconductor device having a barrier wiring structure 114 is illustrated.

[0070] Figure 5A The semiconductor device is shown after forming a barrier layer 104 above the substrate 100 and forming an intermediate layer 108 such as an anti-oxidation layer on the barrier layer 104, wherein the barrier layer 104 is configured to prevent metal atoms from diffusing from above the barrier layer 104 in a direction toward the semiconductor substrate 100. Figure 5A As shown in FIG. 1 , the barrier layer 104 may be in contact with the semiconductor substrate 100, or the barrier layer 104 may be separated from the semiconductor substrate 100 by one or more insulating layers. In either case, the semiconductor substrate 100 may be any type of semiconductor substrate typically used to implement logic and / or power semiconductor devices. For example, as previously described with reference to FIG. Figure 2A As relatedly described herein, the barrier layer 104 may be covered by the intermediate layer 108 in-situ or ex-situ to protect the barrier layer 104 from oxidation during subsequent structuring / patterning of the barrier layer 104 .

[0071] Figure 5B The semiconductor device is shown after simultaneously structuring / patterning the intermediate layer 108 and the barrier layer 104 using the mask 300, for example by a lithography-assisted plasma etching process such as a Cl-based and / or F-based plasma etching process, to define a barrier layer wiring structure 114. The mask 300 is then removed.

[0072] Figure 5C The semiconductor device is shown after PVD of a Cu seed layer 302 over the structure. In the case of Cu power metallization, Cu is typically used as the seed layer 302. For other types of power metallization materials such as Al, Au, etc., the Cu seed layer 302 may be omitted.

[0073] Figure 5D 1 shows a semiconductor device after ECD of thick Cu power metal 304 on Cu seed layer 302. According to this embodiment, a mask 306 such as a photoresist is used to prevent ECD of thick Cu power metal 304 above barrier wiring structure 114. Therefore, power metallization structure 102 is omitted above barrier wiring structure 114. FIG. 2A to FIG. 2E Unlike the embodiment illustrated in FIG. 1 , the passivation layer 110 between the intermediate layer 108 and the power metallization structure 102 may be omitted because the power metallization structure 102 does not extend over the barrier wiring structure 114 .

[0074] Figure 5E The semiconductor device is shown after removing the mask 306 and after using the thick Cu power metal 304 as a hard mask to remove the exposed Cu seed layer 302 , for example, by a blanket wet etch.

[0075] Fig. 5F FIG. 4 shows the semiconductor device after annealing, which is performed to complete the power metallization structure 102. Figure 1 , Figure 3 and Figure 4 The semiconductor devices shown in Fig. 5F The semiconductor device shown in FIG. 1 does not have a passivation layer between the intermediate layer 108 and the power metallization structure 102, and the power metallization structure 102 does not extend over the barrier layer wiring structure 114. As previously explained herein, some or all of the intermediate layer 108 may diffuse into the barrier layer 104 and / or the power metallization structure 102 as a result of the annealing process, may be inherently removed by the ECD process used to form the power metallization structure 102 and therefore not diffuse into the barrier layer 104 or the power metallization structure 102, or may remain substantially intact.

[0076] 6A to 6H Another embodiment of a method of manufacturing a semiconductor device having a barrier wiring structure 114 is illustrated.

[0077] Fig. 6AThe semiconductor device is shown after forming a barrier layer 104 above the substrate 100 and forming an intermediate layer 108 such as an anti-oxidation layer on the barrier layer 104, wherein the barrier layer 104 is configured to prevent metal atoms from diffusing from above the barrier layer 104 in a direction toward the semiconductor substrate 100. Fig. 6A As shown in FIG. 1 , the barrier layer 104 may be in contact with the semiconductor substrate 100, or the barrier layer 104 may be separated from the semiconductor substrate 100 by one or more insulating layers. In either case, the semiconductor substrate 100 may be any type of semiconductor substrate typically used to implement logic and / or power semiconductor devices. For example, as previously described with reference to FIG. Figure 2A As relatedly described herein, the barrier layer 104 may be covered by the intermediate layer 108 in-situ or ex-situ to protect the barrier layer 104 from oxidation during subsequent structuring / patterning of the barrier layer 104 .

[0078] Figure 6B As shown in example previously here with Figure 2A The semiconductor device after simultaneously structuring / patterning the intermediate layer 108 and the barrier layer 104 using the mask 400 to define the barrier layer wiring structure 114 is described in relation thereto.

[0079] Figure 6C As shown in example previously here with Figure 2A Semiconductor device after forming the passivation layer 110 on the structured intermediate / barrier layer stack 104 / 108 as described in relation. The mask 400 is then removed.

[0080] Fig.6D After forming another mask 402 such as a photoresist on the passivation layer 110 and, for example, as previously described herein with reference to Figure 2B The semiconductor device after removing the unprotected portion of the passivation layer 110 to expose the underlying intermediate layer 108 as described above.

[0081] Fig. 6E As shown previously here with Figure 2C The semiconductor device after PVD of the Cu seed layer 404 over the passivation layer 110 and the exposed portions of the intermediate layer 108 as described above.

[0082] Fig. 6F The semiconductor device is shown after ECD of thick Cu power metal 406 on Cu seed layer 404. According to this embodiment, for example, as previously described herein Figure 5D As described above, a mask 408, such as a photoresist, is used to prevent ECD of the thick Cu power metal 406 over the barrier wiring structure 114. Thus, the power metallization structure 102 does not extend over the barrier wiring structure 114.

[0083] Figure 6G After removing the mask 408 and, for example, as previously described herein with Figure 5E The semiconductor device after using the thick Cu power metal 406 as a hard mask to remove the exposed Cu seed layer 404 is described in relation.

[0084] Figure 6H FIG. 4 shows the semiconductor device after annealing, which is performed to complete the power metallization structure 102. Figure 1 , Figure 3 and Figure 4 Similar to the semiconductor device shown in Figure 6H The semiconductor device shown in FIG. 1 has a passivation layer 110 between the intermediate layer 108 and the power metallization structure 102 in one region of the device. Fig. 5F Similar to the semiconductor device shown in FIG. 1 , the power metallization structure 102 is not in another area of ​​the device. Figure 6H 104 and / or the power metallization structure 102 as a result of the annealing process, may be inherently removed by the ECD process used to form the power metallization structure 102 and therefore not diffuse into the barrier layer 104 or the power metallization structure 102, or may remain substantially intact.

[0085] FIG. 7A to FIG. 7G Another embodiment of a method of manufacturing a semiconductor device having a barrier wiring structure is illustrated.

[0086] Fig. 7A The semiconductor device is shown after forming a barrier layer 104 above the substrate 100 and forming an intermediate layer 108 such as an anti-oxidation layer on the barrier layer 104, wherein the barrier layer 104 is configured to prevent metal atoms from diffusing from above the barrier layer 104 in a direction toward the semiconductor substrate 100. Fig. 7A As shown in FIG. 1 , the barrier layer 104 may be in contact with the semiconductor substrate 100, or the barrier layer 104 may be separated from the semiconductor substrate 100 by one or more insulating layers. In either case, the semiconductor substrate 100 may be any type of semiconductor substrate typically used to implement logic and / or power semiconductor devices. For example, as previously described herein with reference to FIG. Figure 2A As described in relation, the barrier layer 104 may be covered by an intermediate layer 108 in-situ or ex-situ in order to protect the barrier layer 104 from oxidation during subsequent structuring / patterning of the barrier layer 104 .

[0087] Figure 7B As shown in example previously here with Figure 2A The semiconductor device after simultaneously structuring / patterning the intermediate layer 108 and the barrier layer 104 using the mask 500 to define the barrier layer wiring structure 114 is described in relation thereto.

[0088] Figure 7C As shown in example previously here with Figure 2A The semiconductor device after forming the passivation layer 110 on the structured intermediate / barrier layer stack 104 / 108 as described above.

[0089] Fig.7D After forming a mask 502 such as a photoresist on the passivation layer 110 and, for example, as previously described herein with reference to Figure 2B The semiconductor device after removing the unprotected portion of the passivation layer 110 to expose the barrier wiring structure 114 as described above.

[0090] Fig. 7E FIG. 1 shows the semiconductor device after PVD of thick Cu power metallization 504 over the exposed portions of the passivation layer 110 and the intermediate layer 108. Figure 2D , Figure 5D as well as Fig. 6F Unlike the embodiment illustrated in , the thick Cu power metallization 504 is blanket deposited and then subsequently patterned.

[0091] Figure 7F After forming a mask 506 such as a photoresist over the blanket deposited thick Cu power metallization 504 and after, for example, The etchant solution is used to etch the exposed portions of the thick Cu power metallization 504 of the semiconductor device.

[0092] Figure 7G The semiconductor device is shown after an anneal, which is performed in order to complete the power metallization structure 102 .

[0093] FIG. 8A to FIG. 8E An embodiment of a method of manufacturing a semiconductor device is illustrated, wherein the intermediate layer 108 is an adhesion promoting layer configured to increase adhesion of the power metallization structure 102 to the barrier layer 104 in a region of the device.

[0094] Fig. 8A FIG. 1 shows a semiconductor device after forming a barrier layer 104 above the substrate 100, wherein the barrier layer 104 is configured to prevent metal atoms from diffusing from above the barrier layer 104 in a direction toward the semiconductor substrate 100. The barrier layer 104 may be formed as shown in FIG. Fig. 8A104, or the barrier layer 104 may be separated from the semiconductor substrate 100 by one or more insulating layers. In either case, the semiconductor substrate 100 may be any type of semiconductor substrate typically used to implement logic and / or power semiconductor devices. The barrier layer 104 may be annealed with nitrogen to increase its durability.

[0095] Figure 8B The semiconductor device is shown after structuring the barrier layer 104, for example by a plasma etching process using a lithographic mask (not shown) such as a photoresist. The reticle design of the lithographic mask and the size of the opening 600 formed in the barrier layer 104 define a range of positive edge lengths (x) for the barrier layer 104. The mask is then removed and the structure is cleaned to remove mask residues.

[0096] Figure 8C 1 shows a semiconductor device after a power metallization process. An adhesion promoting intermediate layer 108 such as TiW or Ti is deposited in situ above the barrier layer 104 together with the thick Cu power metal layer 602, for example, via a sputtering process. In this embodiment, the intermediate layer 108 acts as an adhesion promoter between the barrier layer 104 below and the overlying thick Cu power metal layer 602. In another embodiment, the adhesion promoting intermediate layer 108 is a TiW / Cu seed layer deposited above the barrier layer 104, and the thick Cu power metal layer 602 is electrochemically deposited on the TiW / Cu seed layer using a resist. In either case, the adhesion promoting intermediate layer 108 is substantially thinner than the Cu power metal layer 602, for example, about 50 nm in the case of the TiW adhesion promoting intermediate layer.

[0097] Fig.8D The semiconductor device is shown after forming a mask 604, such as a photoresist, on the Cu power metal layer 602. The mask 604 has openings 606 that are aligned with features previously structured into the barrier layer 104.

[0098] Fig. 8E The semiconductor device is shown after isotropically etching the Cu power metal layer 602 and the adhesion promoting interlayer 108 through the openings 606 in the mask 604 to structure / pattern the power metallization structure 102. The isotropic etching provides a well-defined positive edge / step 608 in the barrier layer 104 with respect to the power metallization structure 102. That is, the edge 608 etched into the barrier layer 104 extends laterally further than the edge 610 etched into the power metallization structure 102.

[0099] The positive edge / step 608 in the barrier layer 104 increases the distance for metal electromigration between the power terminals of the semiconductor device and the control terminals of the device and also more evenly distributes stress in the ILD induced during thermal cycling of the power metallization structure 102. The positive edge / step 608 in the barrier layer 104 thus reduces stress at the etched edge 608 of the barrier layer 104 that might otherwise cause cracks or delamination. Fig. 8E A decomposed region is included showing that the barrier layer 104 extends laterally beyond the etched side 610 of the power metallization structure 102 in the region aligned with the opening 606 in the mask 604 by an amount x, which may be in a range of, for example, between 500 nm and 5 microns.

[0100] Terms such as "first" and "second" are used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0101] As used herein, the terms "having," "comprising," "including," and "containing" and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the quantifiers "a," "an," and the pronoun "the" are intended to include the plural as well as the singular.

[0102] It will be understood that the features of the various embodiments described herein may be combined with each other unless explicitly stated otherwise.

[0103] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. It is intended that the present application cover any adaptation or variation of the specific embodiments discussed herein. It is therefore intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a power metallization structure formed on the semiconductor substrate; a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer being configured to prevent metal atoms from diffusing from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or a conductive layer formed on the barrier layer in a first region; as well as a passivation layer, which is interposed between the barrier layer and the power metallization structure in the second region, wherein the barrier layer is structured into a signal wiring structure in the second region, wherein the power metallization structure is disposed above the signal wiring structure in the second region, The signal wiring structure is insulated from the power metallization structure by a passivation layer in the second region. 2 . The semiconductor device of claim 1 , wherein the power metallization structure is structured independently of the signal wiring structure in the second region. 3 . The semiconductor device of claim 1 , wherein a first region and a second region directly adjoin, wherein in the first region the power metallization structure and the barrier layer are unpatterned, and wherein in the second region a passivation layer covers a periphery of the barrier layer. 4 . The semiconductor device of claim 3 , wherein in the second region the barrier layer extends laterally beyond sides of the power metallization structure. 5 . The semiconductor device of claim 4 , wherein the barrier layer in the second region extends laterally beyond the side surfaces of the power metallization structure by between 500 nm and 5 microns. 6 . The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the barrier layer and the passivation layer in the second region, wherein the intermediate layer is structured identically to the barrier layer in the second region. 7 . The semiconductor device of claim 6 , wherein the barrier layer comprises TiW, the intermediate layer comprises AlCu and the power metallization structure comprises Cu. 8 . The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the passivation layer and the power metallization structure in the second region. 9 . The semiconductor device of claim 8 , wherein the barrier layer comprises TiW, the intermediate layer comprises TiW and the power metallization structure comprises Cu.

10. The semiconductor device of claim 1, wherein the power metallization structure above the barrier layer is omitted in the second region.

11. A semiconductor device comprising: Semiconductor substrate; a power metallization structure formed on the semiconductor substrate; a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer being configured to prevent metal atoms from diffusing from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or a conductive layer formed on the barrier layer in a first region; as well as a passivation layer, which is inserted between the barrier layer and the power metallization structure in the second section of the second region, wherein the barrier layer is structured into a signal wiring structure in a first section of the second region, wherein the first section of the second zone is separated from the first zone by the second section of the second zone, There is no metallization structure above the signal wiring structure.

12. The semiconductor device of claim 11, wherein the first region and the second region directly adjoin, wherein in the first region the power metallization structure and the barrier layer are unpatterned, and wherein in the second section of the second region a passivation layer covers a periphery of the barrier layer. 13 . The semiconductor device of claim 12 , wherein the barrier layer in the second section of the second region extends laterally beyond the side surfaces of the power metallization structure.

14. The semiconductor device of claim 13, wherein the barrier layer in the second section of the second region extends laterally beyond the side surfaces of the power metallization structure by between 500 nm and 5 micrometers. 15 . The semiconductor device of claim 11 , further comprising an intermediate layer interposed between the barrier layer and the passivation layer in the first section of the second region, wherein in the second section of the second region the intermediate layer is structured identically to the barrier layer. 16 . The semiconductor device of claim 15 , wherein the barrier layer comprises TiW, the intermediate layer comprises AlCu and the power metallization structure comprises Cu. 17 . The semiconductor device of claim 11 , further comprising an intermediate layer interposed between the passivation layer and the power metallization structure in the second section of the second region.

18. The semiconductor device of claim 17, wherein the barrier layer comprises TiW, the intermediate layer comprises TiW and the power metallization structure comprises Cu.

Images