Voltage controlled oscillator, PLL circuit and CDR device

Abstract

A voltage controlled oscillator, a PLL circuit and a CDR device are provided, which can suppress the performance degradation caused by the leakage current of a variable capacitance element. The voltage controlled oscillator (40A) has a first capacitance circuit (41A), a second capacitance circuit (42A), a third capacitance circuit (43), an inductor (44, 45) and an NMOS transistor (46, 47). The first capacitance circuit (41A) and the second capacitance circuit (42A) respectively include a variable capacitance element (C1), a capacitance element (C2), a detection circuit (48) and a compensation circuit (49). The variable capacitance element (C1) is arranged between a node (N1) and a node (N2). The capacitance value of the variable capacitance element (C1) depends on the voltage value between the node (N1) and the node (N2). The detection circuit (48) applies a bias voltage value (Vbias) to the node (N2) and detects the amount of leakage current flowing through the variable capacitance element (C1). A compensation circuit (49) causes a current for compensating for a leakage current of a variable capacitance element (C1) to flow through a node (N1) based on a detection result of a detection circuit (48).

Description

Technical Field

[0001] The present invention relates to a voltage controlled oscillator, a PLL circuit and a CDR device. Background Art

[0002] A voltage controlled oscillator (VCO) is capable of outputting an oscillation signal having a frequency corresponding to an input control voltage value. Voltage controlled oscillators are used as an important structural element in PLL (Phase Locked Loop) circuits and CDR (Clock Data Recovery) devices, etc. There are various types of voltage controlled oscillators. Among them, LC-VCO also includes an inductor and a capacitor whose capacitance value changes by voltage control, and outputs an oscillation signal having a frequency corresponding to an input control voltage value according to the resonance phenomenon generated by these inductors and capacitors. When compared with other types of voltage controlled oscillators, LC-VCO has less jitter. Therefore, in the case of frequencies above 10Gbps, the use of LC-VCO is also indispensable among various types of voltage controlled oscillators.

[0003] The LC-VCO includes a capacitance element whose capacitance value changes according to the voltage value applied between two terminals, as a capacitor participating in the resonance phenomenon. Such a capacitance element is called a varicap diode, a variactor diode, or a variable capacitance diode. In this specification, such a capacitance element is referred to as a "variable capacitance element". For example, a variable capacitance element is a P-type diode having a high concentration of P-type impurities injected into an N-well into which a low concentration of N-type impurities is injected by a CMOS process. + In addition, for example, the variable capacitance element is composed of two N wells having high-concentration N-type impurities injected into a P well having low-concentration P-type impurities injected. + The MOS transistors in the region are configured.

[0004] In general, a variable capacitance element not only has a capacitance value corresponding to an applied voltage value, but also generates a leakage current corresponding to the voltage value. Due to the leakage current of the variable capacitance element, jitter is generated in the oscillation signal output from the LC-VCO, and the performance of the LC-VCO may deteriorate. When the performance of the LC-VCO deteriorates, the performance of the PLL circuit or CDR device using the LC-VCO also deteriorates.

[0005] Patent document 1 discloses an invention that aims to solve such a problem. The invention disclosed in the document has a replica circuit that is different from the LC-VCO. The replica circuit includes a variable capacitance element that is the same as the variable capacitance element of the LC-VCO, and further includes a differential amplifier and a current mirror circuit. Furthermore, the purpose of the invention is to suppress the performance degradation of the LC-VCO by compensating the leakage current of the variable capacitance element of the LC-VCO using the leakage current of the variable capacitance element of the replica circuit.

[0006] Patent Document 1: European Patent No. 1237283 Summary of the invention

[0007] However, in the invention disclosed in Patent Document 1, when the characteristics of the variable capacitance element of the LC-VCO and the variable capacitance element of the replica circuit are different, the leakage current flowing through each variable capacitance element is different and cannot be fully compensated. Therefore, the performance degradation of the LC-VCO cannot be fully suppressed, and the performance degradation of the PLL circuit or CDR device using the LC-VCO cannot be fully suppressed. In addition, in the invention disclosed in Patent Document 1, when integrated on a semiconductor substrate, the layout area of ​​the variable capacitance element of the replica circuit is large.

[0008] The present invention is made to solve the above-mentioned problems, and its purpose is to provide a voltage controlled oscillator capable of suppressing performance degradation caused by leakage current of a variable capacitance element and suppressing increase in layout area. In addition, the present invention aims to provide a PLL circuit and a CDR device capable of suppressing performance degradation caused by leakage current of a variable capacitance element of an LC-VCO.

[0009] The voltage controlled oscillator of the present invention comprises an inductor, a first capacitor circuit and a second capacitor circuit, and outputs an oscillation signal having a frequency corresponding to an input control voltage value through a resonance phenomenon caused by the inductor, the first capacitor circuit and the second capacitor circuit, wherein the first capacitor circuit and the second capacitor circuit respectively comprise: a variable capacitor element, which is arranged between a node (N1) and a node (N2) and has a capacitance value corresponding to a voltage value between the two nodes; a capacitor element, which is arranged between a node (N2) and a node (N3); a detection circuit, which applies a bias voltage value to the node (N2) and detects the amount of leakage current flowing through the variable capacitor element; and a compensation circuit, which allows a current that compensates for the leakage current to flow through the node (N1) according to the detection result of the detection circuit. In addition, in the voltage controlled oscillator of the present invention, an inductor is arranged between the nodes (N3) of the first capacitor circuit and the second capacitor circuit, and the nodes (N1) of the first capacitor circuit and the second capacitor circuit are electrically connected to each other and the control voltage value is input.

[0010] Preferably, the voltage controlled oscillator of the present invention further includes a third capacitor circuit connected to each node (N3) of the first capacitor circuit and the second capacitor circuit and having a capacitance value set by a control signal.

[0011] In the voltage controlled oscillator of the present invention, preferably, the first capacitor circuit and the second capacitor circuit each have a common detection circuit, and further preferably, the first capacitor circuit and the second capacitor circuit each have a common compensation circuit.

[0012] In the voltage controlled oscillator of the present invention, it is preferred that the detection circuit includes: (1) a MOS transistor M1 having a source connected to a first potential supply terminal; (2) a resistor provided between a drain of the MOS transistor M1 and a node N2; and (3) a differential amplifier having a first input terminal connected to the drain of the MOS transistor M1, a second input terminal to which a bias voltage value is input, and an output terminal connected to a gate of the MOS transistor M1. In addition, it is preferred that the compensation circuit includes: (1) a MOS transistor M2 having a source connected to the first potential supply terminal and a gate connected to an output terminal of the differential amplifier; (2) a MOS transistor M3 provided between a second potential supply terminal and a drain of the MOS transistor M2; and (3) a MOS transistor M4 provided between the second potential supply terminal and the node N1 and forming a current mirror circuit together with the MOS transistor M3 so as to flow a current of the same amount as a current flowing through the MOS transistor M3.

[0013] In addition, one of the first potential supply terminal and the second potential supply terminal is a high potential supply terminal, and the other is a low potential supply terminal. When the first potential supply terminal is a high potential supply terminal and the second potential supply terminal is a low potential supply terminal, the MOS transistors M1 and M2 whose sources are connected to the high potential supply terminal are PMOS transistors, and the MOS transistors M3 and M4 whose sources are connected to the low potential supply terminal are NMOS transistors. On the contrary, when the first potential supply terminal is a low potential supply terminal and the second potential supply terminal is a high potential supply terminal, the MOS transistors M1 and M2 whose sources are connected to the low potential supply terminal are NMOS transistors, and the MOS transistors M3 and M4 whose sources are connected to the high potential supply terminal are PMOS transistors.

[0014] In the voltage controlled oscillator of the present invention, preferably, the detection circuit further includes a first current source, which is arranged between the second potential supply terminal and the drain of the MOS transistor M1. In addition, it is also preferred that the detection circuit further includes a second current source, which is arranged between the second potential supply terminal and the node N2.

[0015] In the voltage controlled oscillator of the present invention, preferably, the compensation circuit further includes a third current source, which is provided between the first potential supply terminal and the node N1. In addition, it is also preferred that the compensation circuit further includes a fourth current source, which is provided between the second potential supply terminal and the gates of the MOS transistor M3 and the MOS transistor M4.

[0016] In the voltage-controlled oscillator of the present invention, preferably, the detection circuit includes: (1) a MOS transistor M11, the source of which is connected to a first potential supply terminal; (2) a MOS transistor M21, the source of which is connected to a second potential supply terminal; (3) a resistor portion, which is provided between the drains of the MOS transistor M11 and the MOS transistor M21 and a node N2; and (4) a differential amplifier, which has a first input terminal connected to the drains of the MOS transistor M11 and the MOS transistor M21, a second input terminal to which a bias voltage value is input, and an output terminal connected to the gates of the MOS transistor M11 and the MOS transistor M21. In addition, it is preferred that the compensation circuit includes: (1) a MOS transistor M12, the source of which is connected to the first potential supply terminal and the gate of which is connected to the output terminal of the differential amplifier; (2) a MOS transistor M13, which is provided between the second potential supply terminal and the drain of the MOS transistor M12; (3) a MOS transistor M14, which is provided between the second potential supply terminal and the node N1, and together with the MOS transistor M13, forms a current mirror circuit, and flows a current of the same amount as the current flowing through the MOS transistor M13; (4) a MOS transistor M22, the source of which is connected to the second potential supply terminal and the gate of which is connected to the output terminal of the differential amplifier; (5) a MOS transistor M23, which is provided between the first potential supply terminal and the drain of the MOS transistor M22; and (6) a MOS transistor M24, which is provided between the first potential supply terminal and the node N1, and together with the MOS transistor M23, forms a current mirror circuit, and flows a current of the same amount as the current flowing through the MOS transistor M23.

[0017] In addition, one of the first potential supply terminal and the second potential supply terminal is a high potential supply terminal, and the other is a low potential supply terminal. When the first potential supply terminal is a high potential supply terminal and the second potential supply terminal is a low potential supply terminal, the MOS transistors M11, M12, M23, and M24 whose sources are connected to the high potential supply terminal are PMOS transistors, and the MOS transistors M21, M22, M13, and M14 whose sources are connected to the low potential supply terminal are NMOS transistors. On the contrary, when the first potential supply terminal is a low potential supply terminal and the second potential supply terminal is a high potential supply terminal, the MOS transistors M11, M12, M23, and M24 whose sources are connected to the low potential supply terminal are NMOS transistors, and the MOS transistors M21, M22, M13, and M14 whose sources are connected to the high potential supply terminal are PMOS transistors. In addition, one of the first input terminal and the second input terminal of the differential amplifier is an inverting input terminal, and the other is a non-inverting input terminal.

[0018] In the voltage-controlled oscillator of the present invention, it is preferable that the detection circuit includes a MOS transistor M5 having a resistance value corresponding to the gate voltage as a resistance section.

[0019] The PLL circuit of the present invention comprises: (1) the voltage-controlled oscillator of the present invention described above, which outputs an oscillation signal having a frequency corresponding to an input control voltage value; (2) a phase comparator, which inputs an oscillation signal output from the voltage-controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal, and also inputs an input signal, detects the phase difference between the feedback oscillation signal and the input signal, and outputs a phase difference signal indicating the phase difference; (3) a charge pump, which inputs the phase difference signal output from the phase comparator, and outputs a charge-discharge current corresponding to the phase difference indicated by the phase difference signal; and (4) a loop filter, which inputs the charge-discharge current output from the charge pump, and outputs a control voltage value that increases or decreases according to the charge-discharge amount to the voltage-controlled oscillator.

[0020] Preferably, the PLL circuit of the present invention includes a plurality of voltage controlled oscillators as the voltage controlled oscillator, and further includes a selection unit that selects and outputs an oscillation signal output from any one of the plurality of voltage controlled oscillators.

[0021] In the PLL circuit of the present invention, preferably, the control voltage value is input to the voltage controlled oscillators other than the voltage controlled oscillator selected by the selection unit among the plurality of voltage controlled oscillators instead of the bias voltage value.

[0022] The CDR device of the present invention inputs a digital signal embedded with a clock, restores data and clock based on the digital signal, and outputs the restored data and restored clock. The CDR device of the present invention comprises: (1) a sampler that samples the data of the digital signal at a timing indicated by the restored clock, outputs the sampled data as restored data in synchronization with the restored clock; and (2) the above-mentioned PLL circuit of the present invention that inputs the restored data as an input signal to the phase comparator, outputs the restored clock from the voltage-controlled oscillator as an oscillation signal, and applies the restored clock to the sampler.

[0023] The capacitor circuit of the present invention comprises: a variable capacitor element, which is arranged between node N1 and node N2 and has a capacitance value corresponding to the voltage value between the two nodes; a capacitor element, which is arranged between node N2 and node N3; a detection circuit, which applies a bias voltage value to node N2 and detects the amount of leakage current flowing through the variable capacitor element; and a compensation circuit, which allows a current that compensates for the leakage current according to the detection result of the detection circuit to flow through node N1.

[0024] The LC-VCO of the present invention can suppress performance degradation due to leakage current of the variable capacitance element and can suppress increase in layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a diagram showing the configuration of the PLL circuit 1 .

[0026] Figure 2 2 is a diagram showing a circuit example of the voltage controlled oscillator 40 .

[0027] Figure 3 It is a diagram for explaining the characteristics of the voltage controlled oscillator 40 .

[0028] Figure 4 It is a diagram for explaining the characteristics of a variable capacitance element.

[0029] Figure 5 is a diagram showing the structure of a voltage controlled oscillator 40A.

[0030] Figure 6 is a diagram showing the structure of the voltage controlled oscillator 40B.

[0031] Figure 7 1 is a diagram showing a first circuit example of the detection circuit 48 and the compensation circuit 49 .

[0032] Figure 8 4 is a diagram showing a second circuit example of the detection circuit 48 and the compensation circuit 49 .

[0033] Fig. 9 4 is a diagram showing a third circuit example of the detection circuit 48 and the compensation circuit 49 .

[0034] Fig.10 4 is a diagram showing a fourth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0035] Fig.11 4 is a diagram showing a fifth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0036] Fig.12 4 is a diagram showing a sixth circuit example of the detection circuit 48 and the compensation circuit 49.

[0037] Fig.13 48 and 49. FIG. 48 is a diagram showing a seventh circuit example of the detection circuit 48 and the compensation circuit 49. FIG.

[0038] Fig.14 1 is a diagram showing an eighth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0039] Fig.15 4 is a diagram showing a ninth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0040] Fig.16 1 is a diagram showing a tenth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0041] Fig.17 1 is a diagram showing an eleventh circuit example of the detection circuit 48 and the compensation circuit 49 .

[0042] Fig.18 1 is a diagram showing a twelfth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0043] Fig.19 13 is a diagram showing a thirteenth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0044] Fig. 20 14 is a diagram showing a fourteenth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0045] Fig.21 15 is a diagram showing a fifteenth circuit example of the detection circuit 48 and the compensation circuit 49 .

[0046] Fig. 22 This is a diagram showing the use of the first circuit example ( Figure 7 ) of the voltage controlled oscillator 40B ( Figure 6 ) structure diagram.

[0047] Fig.23 : is a graph showing the relationship between the applied voltage value between two terminals and the leakage current amount in a variable capacitance element.

[0048] Fig.242 is a diagram showing time changes of the control voltage value VC and the frequency of the oscillation signal CLKout in the PLL circuit.

[0049] Fig.25 1A is a diagram showing a configuration of a PLL circuit 1A.

[0050] Fig.26 4 is a graph showing the relationship between the capacitance value of the capacitance element 33 of the loop filter 30 to which the capacitance value of the variable capacitance element C1 of each of the voltage controlled oscillators 401 and 402 is applied and the control voltage value VC.

[0051] Fig. 27 It is a diagram showing the structure of the CDR device 2.

[0052] Description of symbols

[0053] 1, 1A: PLL circuit; 2: CDR device; 10: phase comparator; 20: charge pump; 30: loop filter; 31: resistor; 32: capacitor element; 33: capacitor element; 40, 40A, 40B: voltage controlled oscillator; 41, 41A, 41B: first capacitor circuit; 42, 42A, 42B: second capacitor circuit; 43: third capacitor circuit; 44, 45: inductor; 46, 47: NMOS transistor; 48: detection circuit; 49: compensation circuit; 50, 51: frequency divider; 60, 61: selection unit; 70: sampler; 80: frequency synchronization detection unit; C1: variable capacitor element; C2: capacitor element. DETAILED DESCRIPTION

[0054] Hereinafter, the mode for implementing the present invention will be described in detail with reference to the accompanying drawings. In addition, in the description of the accompanying drawings, the same reference numerals are used to mark the same elements, and repeated descriptions are omitted. The present invention is not limited to these examples, but is represented by the claims, which are intended to include all changes within the meaning and scope equivalent to the claims.

[0055] Figure 1 2 is a diagram showing a configuration of a PLL circuit 1. The PLL circuit 1 includes a phase comparator 10, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, and a frequency divider 50. The loop filter 30 includes a resistor 31, a capacitor 32, and a capacitor 33.

[0056] The phase comparator 10 inputs the feedback oscillation signal output from the frequency divider 50, and also inputs the input signal. The input signal may be a reference oscillation signal with a constant frequency, or a digital signal with a constant period of each bit. The phase comparator 10 detects the phase difference between the feedback oscillation signal and the input signal, and outputs a phase difference signal indicating the phase difference to the charge pump 20. The phase difference signal indicates which signal, the feedback oscillation signal or the input signal, has a phase advance.

[0057] The charge pump 20 inputs the phase difference signal output from the phase comparator 10, and outputs a charge and discharge current corresponding to the phase difference indicated by the phase difference signal to the loop filter 30. The polarity of the charge and discharge current output from the charge pump 20 to the loop filter 30 differs depending on which signal, the reference oscillation signal or the input signal, has a phase that is advanced. The loop filter 30 inputs the charge and discharge current output from the charge pump 20, and outputs a control voltage value VC that increases or decreases in accordance with the charge and discharge amount to the voltage controlled oscillator 40.

[0058] The loop filter 30 includes a resistor 31 that inputs the charge and discharge current output from the charge pump 20 to a first end, a capacitor 32 that is provided between a second end of the resistor 31 and a ground potential end, and a capacitor 33 that is provided between a first end of the resistor 31 and the ground potential end. The output end of the charge pump 20 and the input end of the voltage controlled oscillator 40 are connected to the first end of the resistor 31 of the loop filter 30.

[0059] The voltage controlled oscillator 40 receives the control voltage value VC output from the loop filter 30, and outputs an oscillation signal CLKout having a frequency corresponding to the control voltage value VC. The frequency divider 50 receives the oscillation signal output from the voltage controlled oscillator 40, divides the oscillation signal by N to generate a feedback oscillation signal, and outputs the feedback oscillation signal to the phase comparator 10.

[0060] The phase comparator 10, the charge pump 20, the loop filter 30, the voltage controlled oscillator 40 and the frequency divider 50 constitute a loop. In the loop, the charge and discharge current is input from the charge pump 20 to the loop filter 30 to reduce the phase difference between the feedback oscillation signal input to the phase comparator 10 and the input signal. Moreover, when the operation of the loop is stable, the oscillation signal output from the voltage controlled oscillator 40 has a frequency obtained by amplifying the frequency of the input signal by N times. In addition, the frequency divider 50 may not be provided. In this case, the oscillation signal output from the voltage controlled oscillator 40 has the same frequency as the reference oscillation signal, and the frequency division ratio N=1 is set.

[0061] Figure 21 is a diagram showing a circuit example of a voltage controlled oscillator 40. The voltage controlled oscillator 40 shown in the figure is an LC-VCO. The voltage controlled oscillator 40 includes a first capacitor circuit 41, a second capacitor circuit 42, a third capacitor circuit 43, an inductor 44, an inductor 45, an NMOS transistor 46, and an NMOS transistor 47.

[0062] The first capacitor circuit 41 and the second capacitor circuit 42 have the same structure. The first capacitor circuit 41 and the second capacitor circuit 42 respectively include a variable capacitor element C1, a capacitor element C2 and a resistor R. The variable capacitor element C1 is arranged between a node N1 and a node N2. The capacitance value of the variable capacitor element C1 depends on the voltage value between the node N1 and the node N2. The capacitor element C2 is arranged between the node N2 and the node N3. The capacitance value of the capacitor element C2 can also be constant, regardless of the voltage value between the node N2 and the node N3. One end of the resistor R is connected to the node N2, and an arbitrary bias voltage value Vbias is input to the other end of the resistor R. The resistance value of the resistor R is high, and an arbitrary bias voltage value Vbias is applied to the node N2 of each of the first capacitor circuit 41 and the second capacitor circuit 42.

[0063] The third capacitor circuit 43 is connected to the node N3 of each of the first capacitor circuit 41 and the second capacitor circuit 42. The third capacitor circuit 43 includes: a plurality of capacitor elements connected to the node N3 of the first capacitor circuit 41; and switches, which are connected in series with these multiple capacitor elements respectively. In addition, the third capacitor circuit 43 includes: a plurality of capacitor elements connected to the node N3 of the second capacitor circuit 42; and switches, which are connected in series with these multiple capacitor elements respectively. The third capacitor circuit 43 uses a control signal applied from the outside to set the on / off state of each switch, and has a capacitance value corresponding to these settings.

[0064] The inductor 44 and the inductor 45 have the same characteristics. The inductor 44 is provided between the power supply potential supply terminal and the node N3 of the first capacitor circuit 41. The inductor 45 is provided between the power supply potential supply terminal and the node N3 of the second capacitor circuit 42.

[0065] The NMOS transistor 46 and the NMOS transistor 47 have the same characteristics. The drain of the NMOS transistor 46 is connected to the node N3 of the first capacitor circuit 41. The source of the NMOS transistor 46 is connected to the ground potential supply terminal. The gate of the NMOS transistor 46 is connected to the drain of the NMOS transistor 47. The drain of the NMOS transistor 47 is connected to the node N3 of the second capacitor circuit 42. The source of the NMOS transistor 47 is connected to the ground potential supply terminal. The gate of the NMOS transistor 47 is connected to the drain of the NMOS transistor 46.

[0066] The first capacitor circuit 41 and the second capacitor circuit 42 have a common node N1 to which a control voltage value VC is inputted. The first capacitor circuit 41 and the second capacitor circuit 42 output an oscillation signal CLKout from a node N3 (or a node connected to the node N3) thereof.

[0067] Figure 3 4 is a diagram for explaining the characteristics of the voltage controlled oscillator 40. In this diagram, the horizontal axis is the control voltage value VC input to the voltage controlled oscillator 40. The vertical axis is the frequency f of the oscillation signal CLKout output from the voltage controlled oscillator 40. OSC . In this figure, 9 lines representing the relationship (FV characteristics) between the control voltage value VC and the frequency of the oscillation signal CLKout are shown. By setting the capacitance value of the third capacitor circuit 43 according to the control signal, any one of the 9 FV characteristics can be selected. Moreover, the oscillation signal CLKout of the frequency corresponding to the control voltage value VC in the selected FV characteristic is output from the voltage controlled oscillator 40. In addition, there is no need to select one from a plurality of FV characteristics. If the FV characteristic can also be fixed, the third capacitor circuit 43 may not be provided.

[0068] However, variable capacitance elements C1 included in first capacitance circuit 41 and second capacitance circuit 42 of voltage controlled oscillator 40 generate leakage currents corresponding to the voltage value applied between node N1 and node N2. The performance of PLL circuit 1 deteriorates depending on the leakage current.

[0069] For example, the variable capacitance element is formed by having two N capacitors in a P well through a CMOS fine process. + The MOS transistor of the region is constituted. When the source and drain of the MOS transistor are electrically connected to each other to form one terminal and the gate is made into another terminal, the junction capacitance value of the MOS transistor corresponds to the voltage value applied between these two terminals. In addition, a leakage current corresponding to the applied voltage value is generated between these two terminals. The leakage current in the MOS transistor is called gate leakage. In recent years, the process has been miniaturized and the gate oxide film has become thinner, thereby making the gate leakage more significant.

[0070] Figure 4 Graph showing the characteristics of a variable capacitance element. The horizontal axis of the graph represents the applied voltage value V between the two terminals. APPLY , the vertical axis represents the capacitance value C / leakage current I LEAK The graph shows the applied voltage value V between the two terminals. APPLY The relationship between the capacitance value C and the applied voltage value V between the two terminals APPLY and leakage current I LEAK As shown in the figure, when the applied voltage value V APPLYWhen it exceeds 0 and becomes larger, the leakage current I LEAK In addition, the leakage current I LEAK It also changes greatly with temperature. Generally, the higher the temperature, the greater the leakage current I LEAK The leakage current is, for example, several nA to several tens of μA.

[0071] When leakage current is generated in the variable capacitance element C1 included in the first capacitance circuit 41 and the second capacitance circuit 42 of the voltage controlled oscillator 40, the current flows in a direction from the input end of the bias voltage value Vbias through the resistor R and the variable capacitance element C1 toward the input end of the control voltage value VC or in a direction opposite to the direction. The direction in which the current flows differs depending on the direction of the variable capacitance element C1 and the bias voltage value Vbias.

[0072] Regardless of the direction in which the current flows, the amount of stored charge in the capacitor elements 32 and 33 of the loop filter 30 changes according to the current, and the control voltage value VC output from the loop filter 30 changes. When the control voltage value VC input to the voltage controlled oscillator 40 changes, the frequency of the oscillation signal CLKout output from the voltage controlled oscillator 40 also changes, and the frequency of the feedback oscillation signal input to the phase comparator 10 also changes.

[0073] In the phase comparator 10, the phase difference between the input signal and the feedback oscillation signal is detected. A charge-discharge current is input from the charge pump 20 to the loop filter 30 to reduce the phase difference. The charge-discharge current is, for example, about 10 μA or more. The control voltage value VC is restored to its original value, thereby restoring the frequency of the oscillation signal CLKout output from the voltage-controlled oscillator 40.

[0074] However, since feedback is performed in the PLL circuit 1 for each cycle of the input signal, when the cycle of the input signal (or the time per 1 bit) is long, the frequency fluctuation range of the oscillation signal CLKout between 1 cycle becomes larger, and the jitter of the oscillation signal CLKout becomes larger. In addition, when the leakage current of the variable capacitance element C1 is larger than the charge and discharge current applied from the charge pump 20 to the loop filter 30, the control voltage value VC cannot be restored to its original value by feedback, and does not operate as a PLL circuit.

[0075] As variable capacitance elements, for example, there are the following two elements. One of them is that the gate oxide film is thin, and it operates at a low voltage (1.0V), the capacitance change is large, and the leakage current is relatively large. The other is that the gate oxide film is thick, and it operates at a high voltage (3.3V), the capacitance change is small, and the leakage current is relatively small. In the case of using the latter high-voltage variable capacitance element, there is a method of increasing the range of the control voltage to increase the variable capacitance range, but it is necessary to use a variable capacitance element that allows peripheral circuits such as charge pumps and loop filters to also operate at a high voltage. When integrated on a semiconductor substrate, the layout area becomes larger. In addition, as a countermeasure, it is also considered to increase the size of the variable capacitance element without increasing the range of the control voltage. In this case, the layout area also becomes larger.

[0076] The invention disclosed in Patent Document 1 achieves the purpose of suppressing the performance degradation of the LC-VCO by providing a replica circuit including a variable capacitance element identical to the variable capacitance element of the LC-VCO, and compensating the leakage current of the variable capacitance element of the LC-VCO by using the leakage current of the variable capacitance element of the replica circuit. However, in this case, the layout area also becomes larger. In addition, when the characteristics of the variable capacitance element of the LC-VCO and the variable capacitance element of the replica circuit are different, the leakage current flowing through each variable capacitance element is different and cannot be fully compensated. Therefore, the performance degradation of the LC-VCO cannot be fully suppressed, and the performance degradation of the PLL circuit or CDR device using the LC-VCO cannot be fully suppressed.

[0077] The embodiment described below can overcome such problems.

[0078] Figure 5 4 is a diagram showing the structure of a voltage controlled oscillator 40A. The voltage controlled oscillator 40A shown in the figure has a first capacitor circuit 41A, a second capacitor circuit 42A, a third capacitor circuit 43, an inductor 44, an inductor 45, an NMOS transistor 46, and an NMOS transistor 47. Figure 2 When compared with the structure of the voltage controlled oscillator 40 shown in FIG. Figure 5 The voltage-controlled oscillator 40A shown is different in that it includes a first capacitor circuit 41A instead of the first capacitor circuit 41 , and includes a second capacitor circuit 42A instead of the second capacitor circuit 42 .

[0079] The first capacitor circuit 41A and the second capacitor circuit 42A have the same structure. The first capacitor circuit 41 and the second capacitor circuit 42A respectively include a variable capacitor element C1, a capacitor element C2, a detection circuit 48 and a compensation circuit 49. The variable capacitor element C1 is arranged between a node N1 and a node N2. The capacitance value of the variable capacitor element C1 depends on the voltage value between the node N1 and the node N2. The capacitor element C2 is arranged between the node N2 and the node N3. The capacitance value of the capacitor element C2 can also be constant, regardless of the voltage value between the node N2 and the node N3. The detection circuit 48 applies a bias voltage value Vbias to the node N2, and detects the amount of leakage current flowing through the variable capacitor element C1. The compensation circuit 49 allows a current that compensates for the leakage current of the variable capacitor element C1 according to the detection result of the detection circuit 48 to flow through the node N1.

[0080] Figure 6 4B is a diagram showing the structure of a voltage controlled oscillator 40B. The voltage controlled oscillator 40B shown in the figure has a first capacitor circuit 41B, a second capacitor circuit 42B, a third capacitor circuit 43, an inductor 44, an inductor 45, an NMOS transistor 46, and an NMOS transistor 47. Figure 5 When compared with the structure of the voltage controlled oscillator 40A shown in FIG. Figure 6 The voltage-controlled oscillator 40B shown is different in that it includes a first capacitor circuit 41B instead of the first capacitor circuit 41A, and includes a second capacitor circuit 42B instead of the second capacitor circuit 42A.

[0081] The first capacitor circuit 41B and the second capacitor circuit 42B have the same structure. The first capacitor circuit 41B and the second capacitor circuit 42B respectively include a variable capacitance element C1, a capacitance element C2, a detection circuit 48 and a compensation circuit 49. In this structure, the detection circuit 48 of the first capacitor circuit 41B and the second capacitor circuit 42B is common. In addition, the compensation circuit 49 of the first capacitor circuit 41B and the second capacitor circuit 42B is common.

[0082] In addition, in the voltage controlled oscillator 40A ( Figure 5 ) and voltage controlled oscillator 40B ( Figure 6 ) in each of the above-mentioned embodiments, there is no need to select one FV characteristic from a plurality of FV characteristics, and if the FV characteristic can be fixed, the third capacitor circuit 43 may not be provided.

[0083] Figure 7 is a diagram showing a first circuit example of the detection circuit 48 and the compensation circuit 49. In the first circuit example, the detection circuit 48 includes a PMOS transistor M1, a resistor R, and a differential amplifier A. The compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, and an NMOS transistor M4.

[0084] In the detection circuit 48, the source of the PMOS transistor M1 is connected to the power supply potential supply terminal. The resistor R is provided between the drain of the PMOS transistor M1 and the node N2. The non-inverting input terminal of the differential amplifier A is connected to the drain of the PMOS transistor M1. The bias voltage value Vbias is input to the inverting input terminal of the differential amplifier A. The output terminal of the differential amplifier A is connected to the gate of the PMOS transistor M1.

[0085] In the compensation circuit 49, the source of the PMOS transistor M2 is connected to the power supply potential supply terminal. The gate of the PMOS transistor M2 is connected to the output terminal of the differential amplifier A. The source of the NMOS transistor M3 is connected to the ground potential supply terminal. The drain of the NMOS transistor M3 is connected to the drain of the PMOS transistor M2. The source of the NMOS transistor M4 is connected to the ground potential supply terminal. The drain of the NMOS transistor M4 is connected to the node N1. The gate of the NMOS transistor M4 is connected to the gate and drain of the NMOS transistor M3. The NMOS transistor M4 and the NMOS transistor M3 together form a current mirror circuit, and the same amount of current as the current flowing through the NMOS transistor M3 flows.

[0086] In the detection circuit 48, the inverting input terminal and the non-inverting input terminal of the differential amplifier A have a virtual short circuit (Imaginary Short) relationship, so the inverting input terminal of the differential amplifier A becomes the same bias voltage value Vbias as the non-inverting input terminal, and the bias voltage value Vbias is applied to the node N2 via the resistor R. The leakage current of the variable capacitance element C1 flows from the power supply potential supply end through the PMOS transistor M1, the resistor R and the variable capacitance element C1 to the node N1. That is, the amount of current flowing through the PMOS transistor M1 is the same as the leakage current of the variable capacitance element C1. The voltage value applied to the gate of the PMOS transistor M1 from the output terminal of the differential amplifier A becomes a value that causes the same amount of current as the leakage current of the variable capacitance element C1 to flow through the PMOS transistor M1.

[0087] In the compensation circuit 49, the voltage value applied to the gate of the PMOS transistor M2 from the output terminal of the differential amplifier A is the same as the voltage value applied to the gate of the PMOS transistor M1 from the output terminal of the differential amplifier A. Therefore, the amount of current flowing through the PMOS transistor M2 is the same as the amount of current flowing through the PMOS transistor M1. The current flowing through the PMOS transistor M2 also flows through the NMOS transistor M3. The NMOS transistor M4 and the NMOS transistor M3 constitute a current mirror circuit, so the amount of current flowing through the NMOS transistor M4 is the same as the amount of current flowing through the PMOS transistor M3. That is, the amount of current flowing through the NMOS transistor M4 is the same as the amount of leakage current of the variable capacitance element C1. Therefore, the current flowing through the NMOS transistor M4 can compensate for the leakage current of the variable capacitance element C1.

[0088] Figure 8 is a diagram showing a second circuit example of the detection circuit 48 and the compensation circuit 49. In the second circuit example, the detection circuit 48 includes an NMOS transistor M1, a resistor R, and a differential amplifier A. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4.

[0089] In the detection circuit 48, the source of the NMOS transistor M1 is connected to the ground potential supply terminal. The resistor R is provided between the drain of the NMOS transistor M1 and the node N2. The non-inverting input terminal of the differential amplifier A is connected to the drain of the NMOS transistor M1. The bias voltage value Vbias is input to the inverting input terminal of the differential amplifier A. The output terminal of the differential amplifier A is connected to the gate of the NMOS transistor M1.

[0090] In the compensation circuit 49, the source of the NMOS transistor M2 is connected to the ground potential supply terminal. The gate of the NMOS transistor M2 is connected to the output terminal of the differential amplifier A. The source of the PMOS transistor M3 is connected to the power supply potential supply terminal. The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M2. The source of the PMOS transistor M4 is connected to the power supply potential supply terminal. The drain of the PMOS transistor M4 is connected to the node N1. The gate of the PMOS transistor M4 is connected to the gate and drain of the PMOS transistor M3. The PMOS transistor M4 and the PMOS transistor M3 together form a current mirror circuit, and the same amount of current as the current flowing through the PMOS transistor M3 flows.

[0091] In the detection circuit 48, the inverting input terminal and the non-inverting input terminal of the differential amplifier A have a virtual short-circuit relationship, so the inverting input terminal of the differential amplifier A becomes the same bias voltage value Vbias as the non-inverting input terminal, and the bias voltage value Vbias is applied to the node N2 via the resistor R. The leakage current of the variable capacitance element C1 flows from the node N1 to the ground potential supply terminal through the variable capacitance element C1, the resistor R, and the NMOS transistor M1. That is, the amount of current flowing through the NMOS transistor M1 is the same as the leakage current of the variable capacitance element C1. The voltage value applied to the gate of the NMOS transistor M1 from the output terminal of the differential amplifier A becomes a value that causes the same amount of current as the leakage current of the variable capacitance element C1 to flow through the NMOS transistor M1.

[0092] In the compensation circuit 49, the voltage value applied to the gate of the NMOS transistor M2 from the output terminal of the differential amplifier A is the same as the voltage value applied to the gate of the NMOS transistor M1 from the output terminal of the differential amplifier A. Therefore, the amount of current flowing through the NMOS transistor M2 is the same as the amount of current flowing through the NMOS transistor M1. The current flowing through the NMOS transistor M2 also flows through the PMOS transistor M3. The PMOS transistor M4 and the PMOS transistor M3 constitute a current mirror circuit, so the amount of current flowing through the PMOS transistor M4 is the same as the amount of current flowing through the NMOS transistor M3. That is, the amount of current flowing through the PMOS transistor M4 is the same as the amount of leakage current of the variable capacitance element C1. Therefore, the current flowing through the PMOS transistor M4 can compensate for the leakage current of the variable capacitance element C1.

[0093] Fig. 9 is a diagram showing a third circuit example of the detection circuit 48 and the compensation circuit 49. In the third circuit example, the detection circuit 48 includes a PMOS transistor M1, a PMOS transistor M5, and a differential amplifier A. In addition, the compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, and an NMOS transistor M4.

[0094] When compared with the first circuit example ( Figure 7 ) is compared with the third circuit example ( Fig. 9 ), the difference is that the detection circuit 48 includes a PMOS transistor M5 instead of the resistor R. The PMOS transistor M5 is provided between the drain of the PMOS transistor M1 and the node N2. The PMOS transistor M5 is used as a resistor portion in the same manner as the resistor R, and has a resistance value corresponding to the reference voltage value Vref applied to the gate. By using the PMOS transistor M5 as a resistor portion, a resistor portion with high resistance can be realized with a small layout area.

[0095] Fig.10is a diagram showing a fourth circuit example of the detection circuit 48 and the compensation circuit 49. In the fourth circuit example, the detection circuit 48 includes an NMOS transistor M1, an NMOS transistor M5, and a differential amplifier A. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4.

[0096] When compared with the second circuit example ( Figure 8 ) is compared with the fourth circuit example ( Fig.10 ), the difference is that the detection circuit 48 includes an NMOS transistor M5 instead of the resistor R. The NMOS transistor M5 is provided between the drain of the NMOS transistor M1 and the node N2. The NMOS transistor M5 is used as a resistor section in the same manner as the resistor R, and has a resistance value corresponding to the reference voltage value Vref applied to the gate. By using the NMOS transistor M5 as a resistor section, a high-resistance resistor section can be implemented with a small layout area.

[0097] In the first circuit example ( Figure 7 )、Second Circuit Example ( Figure 8 )、CIRCUIT EXAMPLE 3( Fig. 9 ) and the fourth circuit example ( Fig.10 ), depending on the magnitude of the control voltage value VC, the leakage current may become smaller, and the leakage current amount cannot be detected by the detection circuit 48, and the leakage current cannot be compensated by the compensation circuit 49. As a countermeasure, as shown in the fifth circuit example ( Fig.11 )、CIRCUIT EXAMPLE 6( Fig.12 )、CIRCUIT EXAMPLE 7( Fig.13 ) and Circuit Example 8 ( Fig.14 ), it is preferable to provide a first current source I1 or a second current source I2 through which a virtual leakage current flows. The amount of the virtual leakage current flowing through the first current source I1 or the second current source I2 is appropriately about several tens of nA. The flow of such a virtual leakage current becomes a leakage current caused by the circuit. However, the amount of the virtual leakage current is about 1 / 100 of the amount of the current from the charge pump, which is small enough, and can therefore be handled as an error.

[0098] Fig.11 4 is a diagram showing a fifth circuit example of the detection circuit 48 and the compensation circuit 49. In the fifth circuit example, the detection circuit 48 includes a PMOS transistor M1, a resistor R, a differential amplifier A, and a first current source I1. In addition, the compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, and an NMOS transistor M4. When compared with the first circuit example ( Figure 7 ) is compared with the 5th circuit example ( Fig.11), the difference is that the detection circuit 48 further includes a first current source I1. The first current source I1 is provided between the ground potential supply terminal and the drain of the PMOS transistor M1.

[0099] Fig.12 4 is a diagram showing a sixth circuit example of the detection circuit 48 and the compensation circuit 49. In the sixth circuit example, the detection circuit 48 includes an NMOS transistor M1, a resistor R, a differential amplifier A, and a first current source I1. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4. When compared with the second circuit example ( Figure 8 ) are compared, the difference is that in the sixth circuit example ( Fig.12 ), the detection circuit 48 further includes a first current source I1. The first current source I1 is provided between the power supply potential supply terminal and the drain of the NMOS transistor M1.

[0100] Fig.13 : is a diagram showing a seventh circuit example of the detection circuit 48 and the compensation circuit 49. In the seventh circuit example, the detection circuit 48 includes a PMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, and an NMOS transistor M4. When compared with the first circuit example ( Figure 7 ) are compared, the difference is that in the seventh circuit example ( Fig.11 ), the detection circuit 48 further includes a second current source I2. The second current source I2 is provided between the ground potential supply terminal and the node N2.

[0101] Fig.14 : is a diagram showing an eighth circuit example of the detection circuit 48 and the compensation circuit 49. In the eighth circuit example, the detection circuit 48 includes an NMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M4. When compared with the second circuit example ( Figure 8 ) are compared, the difference is that in the 8th circuit example ( Fig.12 ), the detection circuit 48 further includes a second current source I2. The second current source I2 is provided between the power supply potential supply terminal and the node N2.

[0102] Alternatively, in the fifth circuit example ( Fig.11 )、CIRCUIT EXAMPLE 6( Fig.12 )、CIRCUIT EXAMPLE 7( Fig.13 ) and Circuit Example 8 ( Fig.14 ), compared with the third circuit example ( Fig. 9 ) and the fourth circuit example ( Fig.10 ) Similarly, a MOS transistor M5 is provided instead of the resistor R.

[0103] In the fifth circuit example ( Fig.11 )、CIRCUIT EXAMPLE 6( Fig.12 )、CIRCUIT EXAMPLE 7( Fig.13 ) and Circuit Example 8 ( Fig.14 ), an error occurs due to a virtual leakage current flowing through the first current source I1 or the second current source I2. Fig.15 )、CIRCUIT EXAMPLE 10( Fig.16 )、11th Circuit Example ( Fig.17 ) and the 12th circuit example ( Fig.18 ) is provided with a third current source I3 or a fourth current source I4 for suppressing the error.

[0104] Fig.15 : is a diagram showing a ninth circuit example of the detection circuit 48 and the compensation circuit 49. In the ninth circuit example, the detection circuit 48 includes a PMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, and a third current source I3. When compared with the seventh circuit example ( Fig.13 ) are compared, the difference is that in the 9th circuit example ( Fig.15 ), the compensation circuit 49 further includes a third current source I3. The third current source I3 is provided between the power supply potential supply terminal and the node N1. The amount of current flowing through the third current source I3 is the same as the amount of current flowing through the second current source I2.

[0105] Fig.16 10 is a diagram showing a 10th circuit example of a detection circuit 48 and a compensation circuit 49. In the 10th circuit example, the detection circuit 48 includes an NMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, and a third current source I3. When compared with the 8th circuit example ( Fig.14 ) are compared, the difference is that in the 10th circuit example ( Fig.16 ), the compensation circuit 49 further includes a third current source I3. The third current source I3 is provided between the ground potential supply terminal and the node N1. The amount of current flowing through the third current source I3 is the same as the amount of current flowing through the second current source I2.

[0106] Fig.1711 is a diagram showing an 11th circuit example of a detection circuit 48 and a compensation circuit 49. In the 11th circuit example, the detection circuit 48 includes a PMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, and a fourth current source I4. When compared with the 7th circuit example ( Fig.13 ) are compared, the difference is that in the 11th circuit example ( Fig.17 ), the compensation circuit 49 further includes a fourth current source I4. The fourth current source I4 is provided between the ground potential supply terminal and the gates of the NMOS transistor M3 and the NMOS transistor M4. The amount of current flowing through the fourth current source I4 is the same as the amount of current flowing through the second current source I2.

[0107] Fig.18 1 is a diagram showing a twelfth circuit example of a detection circuit 48 and a compensation circuit 49. In the twelfth circuit example, the detection circuit 48 includes an NMOS transistor M1, a resistor R, a differential amplifier A, and a second current source I2. In addition, the compensation circuit 49 includes an NMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, and a fourth current source I4. When compared with the eighth circuit example ( Fig.14 ) are compared, the difference is that in the 12th circuit example ( Fig.18 ), the compensation circuit 49 further includes a fourth current source I4. The fourth current source I4 is provided between the power supply potential supply terminal and the gates of the PMOS transistor M3 and the PMOS transistor M4. The amount of current flowing through the fourth current source I4 is the same as the amount of current flowing through the second current source I2.

[0108] Alternatively, in the ninth circuit example ( Fig.15 )、CIRCUIT EXAMPLE 10( Fig.16 )、11th Circuit Example ( Fig.17 ) and the 12th circuit example ( Fig.18 ), compared with the third circuit example ( Fig. 9 ) and the fourth circuit example ( Fig.10 ) Similarly, a MOS transistor M5 is provided instead of the resistor R. In addition, the fifth circuit example ( Fig.11 ) and Circuit Example 6 ( Fig.12 )Set the third current source I3 or the fourth current source I4.

[0109] The 5th to 12th circuit examples described above allow a virtual leakage current to flow through the first current source I1 or the second current source I2. In addition, the 9th to 12th circuit examples use the third current source I3 or the fourth current source I4 to suppress the error caused by the virtual leakage current flowing through the first current source I1 or the second current source I2. The 13th circuit example described below ( Fig.19)、CIRCUIT EXAMPLE 14 ( Fig. 20 ) and Circuit Example 15 ( Fig.21 ) can form the detection circuit 48 and the compensation circuit 49 without adding a current source.

[0110] Fig.19 is a diagram showing a thirteenth circuit example of the detection circuit 48 and the compensation circuit 49. In the thirteenth circuit example, the detection circuit 48 includes a PMOS transistor M11, an NMOS transistor M21, a resistor R, and a differential amplifier A. The compensation circuit 49 includes a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M22, a PMOS transistor M23, and a PMOS transistor M24.

[0111] In the detection circuit 48, the source of the PMOS transistor M11 is connected to the power supply potential supply terminal. The source of the NMOS transistor M21 is connected to the ground potential supply terminal. The drains of the PMOS transistor M11 and the NMOS transistor M21 are connected to each other. The resistor R is provided between the drains of the PMOS transistor M11 and the NMOS transistor M21 and the node N2. The non-inverting input terminal of the differential amplifier A is connected to the drains of the PMOS transistor M11 and the NMOS transistor M21. The bias voltage value Vbias is input to the inverting input terminal of the differential amplifier A. The output terminal of the differential amplifier A is connected to the gates of the PMOS transistor M11 and the NMOS transistor M21.

[0112] In the compensation circuit 49, the source of the PMOS transistor M12 is connected to the power supply potential supply terminal. The gate of the PMOS transistor M12 is connected to the output terminal of the differential amplifier A. The source of the NMOS transistor M13 is connected to the ground potential supply terminal. The drain of the NMOS transistor M13 is connected to the drain of the PMOS transistor M12. The source of the NMOS transistor M14 is connected to the ground potential supply terminal. The drain of the NMOS transistor M14 is connected to the node N1. The gate of the NMOS transistor M14 is connected to the gate and drain of the NMOS transistor M13. The NMOS transistor M14 and the NMOS transistor M13 together form a current mirror circuit, and the same amount of current as the current flowing through the NMOS transistor M13 flows.

[0113] In addition, in the compensation circuit 49, the source of the NMOS transistor M22 is connected to the ground potential supply terminal. The gate of the NMOS transistor M22 is connected to the output terminal of the differential amplifier A. The source of the PMOS transistor M23 is connected to the power supply potential supply terminal. The drain of the PMOS transistor M23 is connected to the drain of the NMOS transistor M22. The source of the PMOS transistor M24 is connected to the power supply potential supply terminal. The drain of the PMOS transistor M24 is connected to the node N1. The gate of the PMOS transistor M24 is connected to the gate and drain of the PMOS transistor M23. The PMOS transistor M24 and the PMOS transistor M23 together form a current mirror circuit, and the same amount of current as the current flowing through the PMOS transistor M23 flows.

[0114] Thirteenth circuit example of the detection circuit 48 and the compensation circuit 49 ( Fig.19 ) is configured to include the first circuit example ( Figure 7 ) and the second circuit example ( Figure 8 ) based on the structures of both parties, the first circuit example ( Figure 7 ) and the second circuit example ( Figure 8 ) are respectively included in the resistor R and the differential amplifier A. The PMOS transistor M11 and the NMOS transistor M21 in the detection circuit 48 constitute a push-pull buffer.

[0115] Fig. 20 14 is a diagram showing a fourteenth circuit example of the detection circuit 48 and the compensation circuit 49 . Fig.21 48 and the compensation circuit 49. Fig. 20 ) and Circuit Example 15 ( Fig.21 ), the detection circuit 48 includes a PMOS transistor M11, an NMOS transistor M21, a MOS transistor M5, and a differential amplifier A. The compensation circuit 49 includes a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M22, a PMOS transistor M23, and a PMOS transistor M24.

[0116] When compared with the 13th circuit example ( Fig.19 ) are compared, the difference is that in the 14th circuit example ( Fig. 20 ) and Circuit Example 15 ( Fig.21) in each of the above, the detection circuit 48 includes a MOS transistor M5 instead of the resistor R. The MOS transistor M5 is provided between the drain of each of the PMOS transistor M11 and the NMOS transistor M21 and the node N2. The MOS transistor M5 is used as a resistor section in the same manner as the resistor R, and has a resistance value corresponding to the reference voltage value Vref applied to the gate. By using the MOS transistor M5 as a resistor section, a resistor section with high resistance can be realized with a small layout area.

[0117] Circuit Example 14 ( Fig. 20 ) and Circuit Example 15 ( Fig.21 ) is different in the direction of the leakage current flowing through the variable capacitance element C1. Fig. 20 ), the leakage current of the variable capacitance element C1 flows from the node N1 through the variable capacitance element C1, the MOS transistor M5 and the NMOS transistor M21 to the ground potential supply terminal. Fig.21 ), the leakage current of the variable capacitance element C1 flows from the power supply potential supply terminal through the PMOS transistor M11, the MOS transistor M5 and the variable capacitance element C1 to the node N1.

[0118] Fig. 22 This is a diagram showing the first circuit example ( Figure 7 ) of the voltage controlled oscillator 40B ( Figure 6 ) structure. The detection circuit 48 has an LDO (Low Dropout) structure, and a voltage value that is the same as the bias voltage value Vbias input to the inverting input terminal of the differential amplifier A is applied to the node N2 from the non-inverting input terminal of the differential amplifier A via the resistor R. A current of the same amount as the leakage current of the two variable capacitance elements C1 flows through the PMOS transistor M1. The amount of current flowing through the PMOS transistor M2 is the same as the amount of current flowing through the PMOS transistor M1. The current flowing through the PMOS transistor M2 also flows through the NMOS transistor M3. The NMOS transistor M4 and the NMOS transistor M3 constitute a current mirror circuit, so the amount of current flowing through the NMOS transistor M4 is the same as the amount of current flowing through the PMOS transistor M3. That is, the amount of current flowing through the NMOS transistor M4 is the same as the leakage current of the two variable capacitance elements C1. Therefore, the current flowing through the NMOS transistor M4 can compensate for the leakage current of the two variable capacitance elements C1.

[0119] Fig.23 is the voltage value V applied between the two terminals of the variable capacitance element. APPLY and leakage current I LEAK. The leakage current here represents the current flowing from the voltage controlled oscillator to the charge pump (or the current flowing in the opposite direction to the leakage current of the variable capacitance element C1). The figure shows a comparative example in which the detection circuit 48 and the compensation circuit 49 are not provided and an embodiment in which the detection circuit 48 and the compensation circuit 49 are provided. By providing the detection circuit 48 and the compensation circuit 49, the amount of the current flowing from the voltage controlled oscillator to the charge pump in the leakage current of the variable capacitance element C1 is greatly reduced.

[0120] Fig.24 4 is a diagram showing the time variation of the control voltage value VC and the frequency of the oscillation signal CLKout in the PLL circuit. The figure also shows a comparative example in which the detection circuit 48 and the compensation circuit 49 are not provided and an embodiment in which the detection circuit 48 and the compensation circuit 49 are provided. By providing the detection circuit 48 and the compensation circuit 49, the variation range of the control voltage value VC becomes smaller, and the variation range of the frequency of the oscillation signal CLKout is also smaller.

[0121] In this embodiment, since there is no need to replicate the variable capacitance element, there is no problem of different characteristics between the variable capacitance element of the LC-VCO and the replicated variable capacitance element. In this embodiment, the performance degradation caused by the leakage current of the variable capacitance element can be suppressed, and the increase in the layout area can be suppressed. In addition, the control voltage value VC changes according to the leakage current. In the comparative example, as shown in the region P COM As shown in FIG. 1 , when the control voltage value VC increases from the initial value, feedback for suppressing the increase is applied, and the control voltage VC is restored to the original initial value. In addition, in the embodiment, the change amount of the control voltage value VC is small, especially, as in the region P EMB As shown, the amount by which the control voltage value VC is restored to the initial value through feedback is also small.

[0122] Next, an embodiment of the PLL circuit is described. The PLL circuit of this embodiment is a PLL circuit 1 ( Figure 1 ) uses a voltage controlled oscillator 40A ( Figure 5 ) or voltage controlled oscillator 40B ( Figure 6 ), as the voltage controlled oscillator 40. In addition, in the voltage controlled oscillator 40A ( Figure 5 ) or voltage controlled oscillator 40B ( Figure 6 ), any one of the first to fifteenth circuit examples (or a combination or a modified example thereof) can be used as the detection circuit 48 and the compensation circuit 49. The PLL circuit of this embodiment preferably has Fig.25 The structure shown.

[0123] Fig.251 is a diagram showing the structure of a PLL circuit 1A. The PLL circuit 1A includes a phase comparator 10, a charge pump 20, a loop filter 30, voltage controlled oscillators 401 and 402, a frequency divider 50, and a selection unit 60. Figure 1 When compared with the structure of the PLL circuit 1 shown in FIG. Fig.25 The PLL circuit 1A shown in the figure has a plurality of voltage controlled oscillators (two voltage controlled oscillators 401 and 402 in the figure) instead of one voltage controlled oscillator 40, and further has a selection unit 60. The voltage controlled oscillators 401 and 402 have the same voltage controlled oscillators as the voltage controlled oscillator 40A ( Figure 5 ) or voltage controlled oscillator 40B ( Figure 6 )Same structure.

[0124] The voltage controlled oscillators 401 and 402 have different relationships (FV characteristics) between the control voltage value VC and the frequency of the oscillation signal CLKout. The selection unit 60 selects the oscillation signal output from any one of the voltage controlled oscillators 401 and 402 and outputs it to the frequency divider 50. As a result, the frequency range in which the PLL circuit 1A can operate can be expanded compared to the case where one voltage controlled oscillator is provided.

[0125] Furthermore, the control voltage values ​​VC input to the voltage controlled oscillators 401 and 402 are the same. Thus, since only one charge pump 20 and one loop filter 30 are required, it is possible to suppress an increase in the circuit scale.

[0126] Any one of the voltage controlled oscillators 401 and 402 is in use, and the other is in an unused state. The capacitance value of the variable capacitance element C1 of each of the voltage controlled oscillators 401 and 402 is added to the capacitance value of the capacitance element 33 of the loop filter 30. In the voltage controlled oscillator in the unused state, when the bias voltage value Vbias applied to the node N2 is less than the control voltage value VC applied to the node N1, the leakage current of the variable capacitance element C1 becomes smaller, and the influence on the loop filter 30 is small. However, the capacitance value of the variable capacitance element C1 changes due to the change of the control voltage value VC, and the change of the capacitance value of the variable capacitance element C1 affects the capacitance value of the capacitance element 33 of the loop filter 30.

[0127] Therefore, in the voltage controlled oscillator in the unused state, it is preferred that the voltage value applied to the node N2 is replaced with a constant bias voltage value Vbias to make it a control voltage value VC, thereby suppressing the change in the capacitance value of the variable capacitance element C1. That is, it is preferred that the voltage controlled oscillators 401 and 402 each have a switch, and the switch selects any one of the constant bias voltage value Vbias and the control voltage value VC as the voltage value applied to the node N2. The voltage controlled oscillator in the used state selects the constant bias voltage value Vbias through the switch and applies it to the node N2. The voltage controlled oscillator in the unused state selects the control voltage value VC through the switch and applies it to the node N2. Thus, in the voltage controlled oscillator in the unused state, the change in the capacitance value of the variable capacitance element C1 can be suppressed, and the leakage current of the variable capacitance element C1 can be suppressed.

[0128] Fig.26 1 and 2 are diagrams showing the capacitance value C of the capacitance element 33 of the loop filter 30 to which the capacitance value of the variable capacitance element C1 of each of the voltage controlled oscillators 401 and 402 is applied. L The graph is a graph showing the relationship between the voltage control oscillator and the control voltage value VC. The graph shows the case where a constant bias voltage value (0V) is applied to the node N2 in the voltage control oscillator not in use (Bias 0V) and the case where the control voltage value VC is applied to the node N2 in the voltage control oscillator not in use (Bias Following VC). In the latter case, the capacitance value of the capacitive element 33 of the loop filter 30 changes less.

[0129] When the capacitance value of the capacitor 33 of the loop filter 30 changes little, the deviation of the design parameters is smaller, and the design becomes easier. According to such a structure, the leakage current of the variable capacitance element C1 in the voltage controlled oscillator in the use state can be suppressed, and the variation of the capacitance value of the variable capacitance element C1 in the voltage controlled oscillator in the non-use state can be suppressed, and the variation of the capacitance value of the capacitor 33 of the loop filter 30 can be suppressed. In addition, even if there is a leakage current of the variable capacitance element C1 in the voltage controlled oscillator in the non-use state, the leakage current can be compensated.

[0130] Next, an implementation of the CDR device is described. The CDR device inputs a digital signal (e.g., 8B10B or 128B130B encoded data) embedded with a clock, restores the data and clock based on the digital signal, and outputs the restored data and the restored clock. The CDR device is configured to include a PLL circuit and a sampler. In the CDR device, the sampler samples the data of the digital signal at the timing indicated by the restored clock, and outputs the sampled data as restored data in synchronization with the restored clock. The PLL circuit inputs the restored data as an input signal to the phase comparator, outputs the restored clock from the voltage-controlled oscillator as an oscillation signal, and applies the restored clock to the sampler. The CDR device of this implementation has the above-mentioned PLL circuit of this implementation. The CDR device of this implementation preferably has Fig. 27 The structure shown.

[0131] Fig. 27 1 is a diagram showing the structure of a CDR device 2. The CDR device 2 includes phase comparators 101, 102, a charge pump 20, a loop filter 30, voltage controlled oscillators 401, 402, frequency dividers 50, 51, selection units 60, 61, a sampler 70, and a frequency synchronization detection unit 80. A loop including the phase comparator 101, the charge pump 20, the loop filter 30, the voltage controlled oscillator 401, and the frequency divider 50 constitutes a first PLL circuit. A loop including the phase comparator 102, the charge pump 20, the loop filter 30, and the voltage controlled oscillator 402 constitutes a second PLL circuit. In these first and second PLL circuits, the charge pump 20 and the loop filter 30 are commonly provided. The second PLL circuit does not include a frequency divider.

[0132] The sampler 70 receives the digital signal with the clock embedded therein and receives the oscillation signal (restored clock) selected and output by the selector 60. The sampler 70 samples the data of the digital signal at the timing indicated by the restored clock and outputs the sampled data as restored data to the phase comparator 102 in synchronization with the restored clock.

[0133] The phase comparator 102 receives the restored data from the sampler 70 and receives the oscillation signal (restored clock) selected and output by the selector 60. The phase comparator 102 detects the phase difference between the restored clock and the restored data, and outputs a phase difference signal indicating the phase difference to the selector 61. The phase comparator 102 is preferably a Bang-Bang type phase comparator.

[0134] When the input signal is data of a repetitive pattern with a constant period such as 101010 . . . , the frequency divider 51 divides the frequency of the input signal to generate a reference clock, and outputs the reference clock to the phase comparator 101 .

[0135] Phase comparator 101 receives a reference clock generated by frequency divider 51 dividing an input signal and receives a feedback oscillation signal output from frequency divider 50. Phase comparator 101 detects a phase difference between the feedback oscillation signal and the reference clock and outputs a phase difference signal indicating the phase difference to selector 61.

[0136] The frequency synchronization detection unit 80 detects whether the feedback oscillation signal input to the phase comparator 101 is frequency synchronized with the reference clock.

[0137] During the first period in which the frequency synchronization detection unit 80 does not detect frequency synchronization, the selection unit 61 selects the phase difference signal output from the phase comparator 101 to which the reference oscillation signal is input as an input signal, and outputs it to the charge pump 20. In addition, during the first period, the selection unit 60 selects and outputs the oscillation signal output from the voltage controlled oscillator 401 of the voltage controlled oscillators 401 and 402.

[0138] During the second period in which the frequency synchronization is detected by the frequency synchronization detection unit 80, the selection unit 61 selects the phase difference signal output from the phase comparator 102 to which the restored data is input as an input signal, and outputs it to the charge pump 20. In addition, during the second period, the selection unit 60 selects and outputs the oscillation signal output from the voltage controlled oscillator 402 of the voltage controlled oscillators 401 and 402.

[0139] In the CDR device 2, during the first period when frequency synchronization is not achieved, the first PLL circuit including the phase comparator 101 and the voltage controlled oscillator 401 to which the reference clock output from the frequency divider 51 is input operates. On the other hand, during the second period when frequency synchronization is achieved, the second PLL circuit including the phase comparator 102 and the voltage controlled oscillator 402 to which the restored data output from the sampler 70 is input operates. Therefore, the operation of the first PLL circuit using the reference clock can be stabilized in a short time, and restoration of data and clock based on the input digital signal can be started as early as possible.

[0140] In the PLL circuit and the CDR device of the present embodiment, the voltage controlled oscillators 401 and 402 have the above-described configurations, thereby being able to suppress performance degradation due to the leakage current of the variable capacitance element C1 .

[0141] As described above, for example, when referring to Figure 5The LC-VCO is a voltage controlled oscillator having: a control voltage input terminal (node ​​N1) to which a control voltage value (VC) is input; first and second output terminals (terminals for outputting CLKout); and a power supply potential supply terminal (a node between an inductor 44 and an inductor 45), wherein the voltage controlled oscillator has: a first inductor (44) having one end connected to the power supply potential supply terminal and the other end connected to the first output terminal (one of the terminals of CLKout) (node ​​N3); a second inductor (45) having one end connected to the power supply potential supply terminal and the other end connected to the second output terminal (the other of the terminals of CLKout); a first variable capacitor (C1: belonging to 41A) and a first capacitor (C2: belonging to 41A) ), which are connected in series between a control voltage input terminal (node ​​N1) and the other end (node ​​N3) of the first inductor (44); a second variable capacitor (C1: belonging to 42A) and a second capacitor (C2: belonging to 42A), which are connected in series between the control voltage input terminal (node ​​N1) and the other end (node ​​N3) of the second inductor (45); a first current detector (detection circuit 48: belonging to 41A), which is connected between a node (N2) between the first variable capacitor (C1: belonging to 41A) and the first capacitor (C2: belonging to 41A) and a bias input terminal (Vbias); and a first feedback compensator (compensation circuit 49: belonging to 41A), which is connected between an output terminal of the first current detector (detection circuit 48: belonging to 41A) and the control voltage input terminal (node ​​N1).

[0142] exist Figure 5 In the structure, the voltage controlled oscillator has: a second current detector (detection circuit 48: belongs to 42A), which is connected between the node (N2) between the second variable capacitor (C1: belongs to 42A) and the second capacitor (C2: belongs to 42A) and the bias input terminal (Vbias); and a second feedback compensator (compensation circuit 49: belongs to 42A), which is connected between the output terminal of the second current detector (detection circuit 48: belongs to 42A) and the control voltage input terminal (node ​​N1).

[0143] In addition, Figure 6 In the structure, a common current detector and feedback compensator are used. In this case, in the voltage controlled oscillator, the first current detector (detection circuit 48: common) is also connected between the node (N2) between the second variable capacitor (C1: belonging to 42B) and the second capacitor (C2: belonging to 42BA) and the bias input terminal (Vbias).

Claims

1. A voltage controlled oscillator comprising an inductor, a first capacitor circuit and a second capacitor circuit, which outputs an oscillation signal having a frequency corresponding to an input control voltage value through a resonance phenomenon caused by the inductor, the first capacitor circuit and the second capacitor circuit, wherein: The first capacitor circuit and the second capacitor circuit respectively have: a variable capacitance element disposed between the node N1 and the node N2 and having a capacitance value corresponding to a voltage value between the two nodes; A capacitor element, which is arranged between the node N2 and the node N3; a detection circuit that applies a bias voltage value to the node N2 and detects an amount of leakage current flowing through the variable capacitance element; as well as a compensation circuit that allows a current that compensates for the leakage current according to a detection result of the detection circuit to flow through the node N1, The inductor is provided between the node N3 of each of the first capacitor circuit and the second capacitor circuit. The nodes N1 of the first capacitor circuit and the second capacitor circuit are electrically connected to each other and the control voltage value is inputted thereto. The detection circuit comprises: A MOS transistor M1, wherein a source of the MOS transistor M1 is connected to a first potential supply terminal; a resistor portion disposed between the drain of the MOS transistor M1 and the node N2; as well as a differential amplifier having a first input terminal connected to the drain of the MOS transistor M1, a second input terminal to which a bias voltage value is input, and an output terminal connected to the gate of the MOS transistor M1, The compensation circuit comprises: a MOS transistor M2, wherein a source of the MOS transistor M2 is connected to the first potential supply terminal, and a gate of the MOS transistor M2 is connected to the output terminal of the differential amplifier; A MOS transistor M3, which is arranged between the second potential supply terminal and the drain of the MOS transistor M2; as well as The MOS transistor M4 is provided between the second potential supply terminal and the node N1, and constitutes a current mirror circuit together with the MOS transistor M3, and flows a current having the same amount as the current flowing through the MOS transistor M3.

2. The voltage controlled oscillator according to claim 1, wherein: The voltage controlled oscillator further includes a third capacitor circuit connected to each of the first capacitor circuit and the second capacitor circuit and having a capacitance value set by a control signal.

3. The voltage controlled oscillator according to claim 1 or 2, wherein: The detection circuits of the first capacitor circuit and the second capacitor circuit are common. The first capacitor circuit and the second capacitor circuit each have a common compensation circuit.

4. The voltage controlled oscillator according to claim 1, wherein: The detection circuit further includes a first current source provided between the second potential supply terminal and the drain of the MOS transistor M1 .

5. The voltage controlled oscillator according to claim 1, wherein: The detection circuit further includes a second current source provided between the second potential supply terminal and the node N2.

6. The voltage controlled oscillator according to claim 4 or 5, wherein: The compensation circuit further includes a third current source, which is provided between the first potential supply terminal and the node N1.

7. The voltage controlled oscillator according to claim 4 or 5, wherein: The compensation circuit further includes a fourth current source, which is provided between the second potential supply terminal and the gates of the MOS transistor M3 and the MOS transistor M4 .

8. A voltage controlled oscillator comprising an inductor, a first capacitor circuit and a second capacitor circuit, which outputs an oscillation signal having a frequency corresponding to an input control voltage value through a resonance phenomenon caused by the inductor, the first capacitor circuit and the second capacitor circuit, wherein: The first capacitor circuit and the second capacitor circuit respectively have: a variable capacitance element disposed between the node N1 and the node N2 and having a capacitance value corresponding to a voltage value between the two nodes; A capacitor element, which is arranged between the node N2 and the node N3; a detection circuit that applies a bias voltage value to the node N2 and detects an amount of leakage current flowing through the variable capacitance element; as well as a compensation circuit that allows a current that compensates for the leakage current according to a detection result of the detection circuit to flow through the node N1, The inductor is provided between the node N3 of each of the first capacitor circuit and the second capacitor circuit. The nodes N1 of the first capacitor circuit and the second capacitor circuit are electrically connected to each other and the control voltage value is inputted thereto. The detection circuit comprises: a MOS transistor M11, wherein a source of the MOS transistor M11 is connected to the first potential supply terminal; a MOS transistor M21, wherein a source of the MOS transistor M21 is connected to the second potential supply terminal; a resistor portion disposed between the drain of each of the MOS transistor M11 and the MOS transistor M21 and the node N2; a differential amplifier having a first input terminal connected to the drains of the MOS transistor M11 and the MOS transistor M21, a second input terminal to which a bias voltage value is input, and an output terminal connected to the gates of the MOS transistor M11 and the MOS transistor M21, The compensation circuit comprises: a MOS transistor M12, wherein a source of the MOS transistor M12 is connected to the first potential supply terminal, and a gate of the MOS transistor M12 is connected to the output terminal of the differential amplifier; a MOS transistor M13 disposed between the second potential supply terminal and the drain of the MOS transistor M12; and a MOS transistor M14, which is provided between the second potential supply terminal and the node N1, and forms a current mirror circuit together with the MOS transistor M13, and flows a current of the same amount as the current flowing through the MOS transistor M13; a MOS transistor M22, wherein a source of the MOS transistor M22 is connected to the second potential supply terminal, and a gate of the MOS transistor M22 is connected to the output terminal of the differential amplifier; a MOS transistor M23 disposed between the first potential supply terminal and the drain of the MOS transistor M22; and The MOS transistor M24 is provided between the first potential supply terminal and the node N1, and forms a current mirror circuit together with the MOS transistor M23, and flows a current having the same amount as the current flowing through the MOS transistor M23.

9. The voltage controlled oscillator according to any one of claims 4, 5 and 8, wherein: The detection circuit includes a MOS transistor M5 having a resistance value corresponding to a gate voltage as the resistance section.

10. A PLL circuit, comprising: The voltage controlled oscillator according to any one of claims 1 to 9, which outputs an oscillation signal having a frequency corresponding to an input control voltage value; a phase comparator which inputs the oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal and also inputs the input signal, detects the phase difference between the feedback oscillation signal and the input signal, and outputs a phase difference signal indicating the phase difference; a charge pump that receives the phase difference signal output from the phase comparator and outputs a charge and discharge current corresponding to the phase difference indicated by the phase difference signal; and The loop filter receives the charge and discharge current output from the charge pump and outputs the control voltage value increased or decreased according to the charge and discharge current to the voltage controlled oscillator.

11. The PLL circuit according to claim 10, wherein: The PLL circuit has a plurality of voltage controlled oscillators as the voltage controlled oscillators, The PLL circuit further includes a selection unit that selects and outputs an oscillation signal output from any one of the plurality of voltage-controlled oscillators.

12. The PLL circuit according to claim 11, wherein: The control voltage value is input to the other voltage controlled oscillators among the plurality of voltage controlled oscillators except the voltage controlled oscillator selected by the selection unit instead of the bias voltage value.

13. A CDR device, which inputs a digital signal in which a clock is embedded, restores data and clock according to the digital signal, and outputs the restored data and restored clock, wherein: The CDR device has: a sampler that samples the data of the digital signal at a timing indicated by the restored clock, and outputs the sampled data as the restored data in synchronization with the restored clock; as well as The PLL circuit according to any one of claims 10 to 12, wherein the restored data is input as the input signal to the phase comparator, the restored clock is output from the voltage controlled oscillator as the oscillation signal, and the restored clock is applied to the sampler.

14. A capacitor circuit, comprising: a variable capacitance element disposed between the node N1 and the node N2 and having a capacitance value corresponding to a voltage value between the two nodes; A capacitor element, which is arranged between the node N2 and the node N3; a detection circuit that applies a bias voltage value to the node N2 and detects an amount of leakage current flowing through the variable capacitance element; as well as a compensation circuit that allows a current that compensates for the leakage current according to a detection result of the detection circuit to flow through the node N1, The detection circuit comprises: A MOS transistor M1, wherein a source of the MOS transistor M1 is connected to a first potential supply terminal; a resistor portion disposed between the drain of the MOS transistor M1 and the node N2; as well as a differential amplifier having a first input terminal connected to the drain of the MOS transistor M1, a second input terminal to which a bias voltage value is input, and an output terminal connected to the gate of the MOS transistor M1, The compensation circuit comprises: a MOS transistor M2, wherein a source of the MOS transistor M2 is connected to the first potential supply terminal, and a gate of the MOS transistor M2 is connected to the output terminal of the differential amplifier; A MOS transistor M3, which is arranged between the second potential supply terminal and the drain of the MOS transistor M2; as well as The MOS transistor M4 is provided between the second potential supply terminal and the node N1, and constitutes a current mirror circuit together with the MOS transistor M3, and flows a current having the same amount as the current flowing through the MOS transistor M3.

15. A voltage controlled oscillator comprising a control voltage input terminal, a first output terminal, a second output terminal, and a power supply potential supply terminal, wherein: The voltage controlled oscillator has: a first inductor having one end connected to the power supply potential supply terminal and the other end connected to the first output terminal; a second inductor having one end connected to the power supply potential supply terminal and the other end connected to the second output terminal; a first variable capacitor and a first capacitor connected in series between the control voltage input terminal and the other end of the first inductor; a second variable capacitor and a second capacitor connected in series between the control voltage input terminal and the other end of the second inductor; a first current detector connected between a node between the first variable capacitor and the first capacitor and a bias input terminal; as well as a first feedback compensator connected between an output terminal of the first current detector and the control voltage input terminal, The first current detector comprises: a MOS transistor M1, wherein a source of the MOS transistor M1 is connected to a first power supply potential supply terminal; a resistor portion, which is disposed between the drain of the MOS transistor M1 and the node; as well as a differential amplifier having a first input terminal connected to the drain of the MOS transistor M1, a second input terminal to which a bias voltage value is input, and an output terminal connected to the gate of the MOS transistor M1, The first feedback compensator comprises: a MOS transistor M2 having a source connected to the power supply potential supply terminal and a gate connected to the output terminal of the differential amplifier; A MOS transistor M3, which is arranged between the second potential supply terminal and the drain of the MOS transistor M2; as well as The MOS transistor M4 is provided between the second potential supply terminal and a node between the first variable capacitor and the second variable capacitor, and together with the MOS transistor M3, constitutes a current mirror circuit, and flows a current of the same amount as the current flowing through the MOS transistor M3.

16. The voltage controlled oscillator according to claim 15, wherein: The voltage controlled oscillator has: a second current detector connected between a node between the second variable capacitor and the second capacitor and a bias input terminal; as well as A second feedback compensator is connected between an output terminal of the second current detector and the control voltage input terminal.

17. The voltage controlled oscillator according to claim 15, wherein: The first current detector is also connected between a node between the second variable capacitor and the second capacitor and a bias input terminal.

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