Control buffer in source driver and source driver of display panel

Abstract

A control buffer in a source driver, the control buffer comprising: a first CMOS inverter configured to output a switch signal to control the on and off of a switch; and a first tri-state inverter connected to the first CMOS inverter and configured to selectively adjust the size of the control buffer, wherein the source driver adjusts the conversion rate of the switch signal according to the size of the control buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2018-0088027 filed in the Korean Intellectual Property Office on Jul. 27, 2018, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The following description relates to a control buffer included in a source driver. The following description also relates to a control buffer capable of reducing electromagnetic interference (EMI). Furthermore, the following description relates to a source driver including such a control buffer. Background Art

[0004] An integrated circuit (IC) including a large number of transistors on one semiconductor chip is called a large scale integrated circuit (LSI), very LSI, or ultra LSI IC, depending on the integration density of transistors on these ICs.

[0005] As semiconductors become more integrated, electromagnetic interference (EMI) phenomena increase. Therefore, reducing EMI is an important issue in semiconductor and IC design.

[0006] An alternative technology discloses a clock driver that can reduce EMI by adjusting the conversion rate at each driving time. In more detail, a small driver is used for driving at the driving start time and the driving end time. During the transition period, a large-sized driver is used for driving to reduce the average conversion rate and EMI accordingly.

[0007] Meanwhile, in a display device, in order to provide a driving voltage to a source line of a display panel, each of the output switches of a source driver is turned on at the same time. When each output switch is turned on at the same time, a high peak current appears at the switch signal controlling each output switch. In addition, as the resolution of the display increases, the peak current of the switch signal also increases.

[0008] This approach may cause high levels of electromagnetic interference (EMI) to occur, which may affect the display image quality. High levels of EMI may also adversely affect the receiver sensitivity of the mobile phone. Summary of the invention

[0009] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0010] In a general aspect, a control buffer in a source driver includes: a first CMOS inverter configured to output a switching signal to control the on and off of a switch; and a first tri-state inverter connected to the first CMOS inverter and configured to selectively adjust the size of the control buffer, wherein a conversion rate of the switching signal is adjusted according to the size of the control buffer.

[0011] The first CMOS inverter may include: an input line configured to receive a first control signal; an output line configured to output a switching signal; and each of a first PMOS transistor and a first NMOS transistor, each of the first PMOS transistor and the first NMOS transistor including a gate commonly connected to the input line and a drain commonly connected to the output line, wherein the first CMOS inverter may be configured to invert the first control signal received from the input line, and the first CMOS inverter may be configured to output the inverted first control signal to the output line as the switching signal.

[0012] The first PMOS transistor and the first NMOS transistor may each be a 1 / 4-sized transistor.

[0013] Depending on the state of the second control signal, the first tri-state inverter can be configured to operate as an inverter that inverts the first control signal received from the input line and outputs the inverted first control signal to the output line of the first CMOS inverter; or regardless of the first control signal, the first tri-state inverter can be placed in a high impedance state and can be configured not to output the signal to the output line.

[0014] In response to the first tri-state inverter operating as the inverter, the size of the control buffer may be increased.

[0015] The first three-state inverter may include: a second NMOS transistor, which includes a gate configured to receive a second control signal; a second PMOS transistor, which includes a gate configured to receive a complementary signal of the second control signal; and each of a third PMOS transistor and a third NMOS transistor, each of the third PMOS transistor and the third NMOS transistor including a gate commonly connected to an input line and a drain commonly connected to an output line, wherein the drain of the second PMOS transistor can be connected to the source of the third PMOS transistor, and the drain of the second NMOS transistor can be connected to the source of the third NMOS transistor.

[0016] The third PMOS transistor and the third NMOS transistor may each be a 3 / 4 size transistor.

[0017] The control buffer may also include: a second CMOS inverter, which is configured to invert the switching signal to output a complementary signal of the switching signal; and a second three-state inverter, which is connected to the second CMOS inverter and configured to selectively adjust the size of the control buffer, wherein the conversion rate of the complementary signal of the switching signal can be adjusted according to the size of the control buffer.

[0018] The switch may include a PMOS transistor and an NMOS transistor connected in parallel, a gate of the PMOS transistor may be configured to receive a complementary signal of a switch signal, and a gate of the NMOS transistor may be configured to receive the switch signal.

[0019] In another general aspect, a control buffer in a source driver includes: a CMOS inverter configured to output a switching signal to control the on and off of a switch controlled by the control buffer; and tri-state inverters, each of which is connected to the CMOS inverter, and the tri-state inverters selectively adjust the size of the control buffer according to the state of each of the tri-state inverters, wherein the conversion rate of the switching signal is adjusted according to the size of the control buffer.

[0020] As the size of the control buffer is reduced, electromagnetic interference (EMI) of the switching signal can be reduced.

[0021] The CMOS inverter may include: an input line configured to receive a switch control signal; and an output line configured to output the switch signal, wherein the CMOS inverter may be configured to invert the switch control signal received from the input line, and the CMOS inverter may be configured to output the inverted switch control signal to the output line as the switch signal.

[0022] Depending on the state of the size control signal input into each tri-state inverter, each tri-state inverter can be configured to operate as an inverter that inverts the switch control signal received from the input line, and each tri-state inverter can be configured to output the inverted switch control signal to the output line of the CMOS inverter; or regardless of the size control signal, each tri-state inverter can be placed in a high impedance state and can be configured not to output the signal to the output line.

[0023] The size control signal may include a first size control signal, a second size control signal, and a third size control signal. The tri-state inverter may include: a first tri-state inverter configured to operate based on the first size control signal; a second tri-state inverter configured to operate based on the second size control signal; and a third tri-state inverter configured to operate based on the third size control signal. Each of the tri-state inverters may include: a corresponding second NMOS transistor including a gate configured to receive a corresponding size control signal; a corresponding second PMOS transistor including a gate configured to receive a corresponding complementary signal of the corresponding size control signal; and a corresponding third PMOS transistor and a corresponding third NMOS transistor, wherein the corresponding third PMOS transistor and the corresponding third NMOS transistor include a gate commonly connected to an input line and a drain commonly connected to an output line, wherein the drain of each corresponding second PMOS transistor may be connected to the source of each corresponding third PMOS transistor, and the drain of each corresponding second NMOS transistor may be connected to the source of each corresponding third NMOS transistor.

[0024] Each of the three-state inverters is characterized in that: according to the state of each of the size control signals, the corresponding third PMOS transistor or the corresponding third NMOS transistor can be configured to operate as an inverter, or the corresponding third PMOS transistor and the corresponding third NMOS transistor can be cut off, and as the size of the corresponding third PMOS transistor or the corresponding third NMOS transistor increases, the size of the control buffer can increase.

[0025] In response to the switch control signal being in a high state, the size of the control buffer can be adjusted by a combination of the third NMOS transistor of the first tri-state inverter, the third NMOS transistor of the second tri-state inverter, and the third NMOS transistor of the third tri-state inverter according to the state of each of the size control signals.

[0026] In response to the switch control signal being in a low state, the size of the control buffer can be adjusted by a combination of the third PMOS transistor of the first tri-state inverter, the third PMOS transistor of the second tri-state inverter, and the third PMOS transistor of the third tri-state inverter according to the state of each of the size control signals.

[0027] In response to the first, second and third size control signals being in a low state, the control buffer may have a minimum size; and in response to the first, second and third size control signals being in a high state, the control buffer may have a maximum size.

[0028] In another general aspect, a source driver for a display panel includes: a channel amplifier configured to receive a driving voltage to be output to a source line of the display panel for amplification; a switch connecting an output terminal of the channel amplifier to the source line; and a control buffer configured to provide a switching signal to the switch to control the switching on and off, wherein the size of the control buffer is selectively adjusted according to the load of the display panel.

[0029] As the load of the display panel increases, the size of the control buffer may increase; and as the load of the display panel decreases, the size of the control buffer may decrease.

[0030] The control buffer may include: a CMOS inverter configured to output a switching signal based on a switching control signal; and a tri-state inverter connected to the CMOS inverter, wherein the tri-state inverter is configured to selectively adjust the size of the control buffer based on the size control signal, wherein the operation of the tri-state inverter can be controlled according to the load of the display panel.

[0031] Depending on the state of the size control signal, the tri-state inverter can be configured to operate as an inverter that inverts the switch control signal, and the tri-state inverter can be configured to output the inverted switch control signal as the switch signal; or regardless of the size control signal, the tri-state inverter can be placed in a high impedance state and can be configured to output no signal.

[0032] Other features and aspects will be apparent from the appended claims and the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a circuit diagram for illustrating a source driver in an alternative technology;

[0034] Figure 2 is a diagram of a display device including a source driver according to one or more examples;

[0035] Figure 3 It is the control buffer in the alternative technology;

[0036] Figure 4 is a control buffer according to the example;

[0037] Figure 5 is a circuit diagram for explaining an example of control buffer reduction according to the present example;

[0038] Figure 6 is a circuit diagram for explaining an example of control buffer addition according to the present example;

[0039] Figure 7shows the simulation result of the peak current according to the switch control signal;

[0040] Figure 8 An extended example of a control buffer is shown; and

[0041] Fig. 9 Shows Figure 8 An example of the operating principle of the control buffer.

[0042] Like reference numerals refer to like elements throughout the drawings and detailed description. The drawings may not be drawn to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0043] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be obvious. For example, as will be obvious after understanding the disclosure of the application, the sequence of operations described herein is only an example, and is not limited to those set forth herein, but can be changed except that the operation must occur in a certain order. In addition, in order to increase clarity and simplicity, the description of features known in the art can be omitted.

[0044] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0045] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or one or more other elements may be present in between. Conversely, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there may be no other elements in between.

[0046] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of the associated listed items.

[0047] Although terms such as "first," "second," and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, component, region, layer, or portion mentioned in the examples may also be referred to as the second member, component, region, layer, or portion.

[0048] As shown in the accompanying drawings, for ease of description, spatially relative terms such as "above", "above", "below", and "under" may be used herein to describe the relationship of one element to another element. In addition to the orientation shown in the accompanying drawings, such spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, an element described as "above" or "above" relative to another element will be "below" or "under" relative to the other element. Therefore, the term "above" includes both an upper orientation and a lower orientation depending on the spatial orientation of the device. The device can also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein are interpreted accordingly.

[0049] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural forms as well. The terms "comprises", "includes" and "having" specify the presence of the features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0050] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes that occur during manufacturing.

[0051] As will be apparent after understanding the disclosure of the present application, the features of the examples described herein can be combined in various ways. In addition, as will be apparent after understanding the disclosure of the present application, although the examples described herein have various configurations, other configurations are also possible.

[0052] Throughout this document, it should be noted that use of the term "may" with respect to an example or implementation - e.g., with respect to what an example or implementation may include or implement - means that at least one example or implementation exists in which such a feature is included or implemented, but all examples or implementations are not limited thereto.

[0053] The present example is provided to solve the above-mentioned problem, and the control buffer according to the present example is intended to adjust the conversion rate of the switching signal controlling each output switch of the source driver according to the size of the control buffer.

[0054] A second object of the present example is to selectively adjust the size of the control buffer according to the load of the display panel, thereby providing a source driver that reduces electromagnetic interference (EMI) of a switching signal.

[0055] Figure 1 is a circuit diagram for explaining a source driver in an alternative technology. Figure 1 In the example of, each of the channel amplifiers AMP1 and AMP2 amplifies the driving voltage, and each of the output switches SW1 and SW2 of each channel amplifier corresponding to AMP1 and AMP2 respectively provides the amplified driving voltage to each source line of the display panel. When the source driver provides the driving voltage to each source line, the turn-on signals SW_ON and SW_ON_B output from the control buffer BUFFER are simultaneously input to each output switch SW1 and SW2. Therefore, when each of the output switches SW1 and SW2 is turned on at the same time, the driving voltage of each of the channel amplifiers AMP1 and AMP2 is provided to each source line. Throughout this disclosure, the term "control buffer" refers to a control buffer circuit.

[0056] As the display resolution increases, the number of source lines of the display panel increases proportionally. Therefore, a source driver matching the number of source lines of the display panel may be required. For example, assuming that FHD corresponds to a resolution of 1920×1080 pixels, at least 1080 channel amplifiers are required in a source driver that implements FHD or higher resolutions.

[0057] In an alternative technique, all source lines are driven by a single large control buffer. That is, as the number of source lines increases, the number of channel amplifiers also increases, and the number of output switches connected to the channel amplifiers also increases. Therefore, the size of the control buffer needs to be large, and as the number of source lines increases, the size of the control buffer becomes larger.

[0058] However, as the size of the control buffer increases, propagation delay occurs between the channel amplifier located at the center and the channel amplifier located at the edge. In addition, in such an example, when the output switch is turned on simultaneously with another output switch, a large electromagnetic interference (EMI) phenomenon is caused during the time when a high peak current is generated.

[0059] Figure 2 A display device including a source driver according to one or more examples is shown. A source driver according to one embodiment selectively adjusts the size of a control buffer according to a load of a display panel, can reduce EMI of a controlled switching signal, but can increase display resolution.

[0060] refer to Figure 2 In the example of FIG. 1 , the display device includes a display panel 20 and a source driver 10. The source driver 10 provides a driving voltage to each source line of the display panel 20. The source driver 10 includes a control buffer 100, a logic 200, a level shifter 300, a first channel amplifier 400, a second channel amplifier 500, a first switch 700, and a second switch 800. However, the source driver 10 is not limited to these elements and may include other elements as appropriate.

[0061] For ease of explanation, only two of the source driver channels processing n-bit digital data are shown for the first channel amplifier 400, the second channel amplifier 500, the first switch 700, and the second switch 800. In addition, as a non-limiting example, in this example, one control channel is used for 2 channels, but the example is not limited to this example, and one control buffer may be used for 4 channels or 8 channels.

[0062] The first channel amplifier 400 receives and amplifies a first driving voltage to be output to a first source line of the display panel 20. The second channel amplifier 500 receives and amplifies a second driving voltage to be output to a second source line of the second display panel 20.

[0063] The first switch 700 connects the output terminal of the first channel amplifier 400 to the first source line, and the second switch 800 connects the output terminal of the second channel amplifier 500 to the second source line.

[0064] The control buffer 100 provides a switching signal SW_ON and a complementary signal SW_ON_B of the switching signal to the first switch 700 and the second switch 800 , respectively, based on the first control signal SW_CON.

[0065] Each of the first switch 700 and the second switch 800 includes a PMOS transistor and an NMOS transistor connected in parallel. For each of the first switch 700 and the second switch 800, the gate of the PMOS transistor receives a complementary signal SW_ON_B, and the gate of the NMOS transistor receives a switch signal SW_ON.

[0066] Specifically, the present example allows the size of the control buffer 100 to be selectively controlled based on the load of the display panel 20 by adding the second control signal SIZE_OP input to the control buffer 100 .

[0067] The logic 200 generates a first control signal SW_CON and a second control signal SIZE_OP. The first control signal SW_CON is a signal for controlling the states of the switch signal SW_ON and the complementary signal SW_ON_B of the switch signal. The second control signal SIZE_OP is a signal for controlling the size of the control buffer 100. According to an example, the second control signal SIZE_OP may be determined according to the load of the display panel 20 and may be pre-stored in a one-time programmable (OTP) memory.

[0068] Therefore, the level shifter 300 receives the first control signal SW_CON and the second control signal SIZE_OP from the logic 200 and shifts the level of each of the first control signal SW_CON and the second control signal SIZE_OP to output it to the control buffer 100 .

[0069] As the load of the display panel 20 increases, the source driver 10 appropriately increases the size of the control buffer 100 and also increases the driving capability of each of the switching signal SW_ON and the complementary signal SW_ON_B of the switching signal.

[0070] However, when the load of the display panel 20 is reduced, the source driver 10 correspondingly reduces the size of the control buffer 100, thereby reducing the conversion rate of the first switch signal SW_ON and the second switch signal SW_ON_B. Therefore, the peak current of each of the switch signal SW_ON and the complementary signal SW_ON_B of the switch signal is reduced. Therefore, the generated EMI phenomenon is reduced.

[0071] Figure 3 An alternative technique for controlling a buffer is shown. Figure 4 A control buffer according to an example is shown. Figure 3In the example of , the control buffer is implemented with two inverters. In such an example, each inverter is implemented as a series connection of a PMOS transistor and an NMOS transistor. That is, one inverter is implemented by a series connection of a first PMOS transistor MP1 and a first NMOS transistor MN1, and the other inverter is implemented by a series connection of a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4.

[0072] like Figure 3 When the control buffer is implemented with two inverters, the control buffer 100 according to one or more examples may be as follows: Figure 4 This can be done as shown in the example. Figure 4 In the example of the embodiment of the present invention, the control buffer 100A includes a first CMOS inverter 110A, a first tri-state inverter 120A, a second CMOS inverter 130, and a second tri-state inverter 140. However, this is a non-limiting example, and other elements may also be present. The control buffer 100 according to the present example may also be implemented by reducing the size of the transistor of the first CMOS inverter 110A and by connecting the first tri-state inverter 120A to the output terminal of the first CMOS inverter 110A. In addition, the control buffer 100 may be implemented by reducing the size of the transistor of the second CMOS inverter 130 and by connecting the second tri-state inverter 140 to the output terminal of the second CMOS inverter 130.

[0073] For example, the first CMOS inverter 110A outputs the switch signal SW_ON in response to the first control signal SW_CON. Therefore, in such an example, the switch signal SW_ON controls the on / off operation of each of the first switch 700 and the second switch 800.

[0074] For example, the first CMOS inverter 110A includes an input line INLN, an output line OUTLN, a first PMOS transistor MP1, and a first NMOS transistor MN1. The input line INLN receives a first control signal SW_CON, and the output line OUTLN outputs a switch signal SW_ON.

[0075] In addition, the first PMOS transistor MP1 includes a gate connected to the input line INLN. When the first control signal SW_CON is a low signal, the first PMOS transistor MP1 outputs a high signal to the output line OUTLN. The first NMOS transistor MN1 includes a gate connected to the input line INLN. When the first control signal SW_CON is a high signal, the first NMOS transistor MN1 outputs a low signal to the output line OUTLN. In addition, the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1 are commonly connected to the output node ND.

[0076] In such an example, the first tri-state inverter 120A selectively adjusts the size of the control buffer 100A in response to the second control signal SIZE_OP and its complement SIZE_OP_B. Thus, the slew rate of each of the switch signal SW_ON and its complement SW_ON_B is adjusted based on the size of the control buffer 100A.

[0077] Additionally, in such an example, the first tri-state inverter 120A includes a second PMOS transistor MP2 , a third PMOS transistor MP3 , a second NMOS transistor MN2 , and a third NMOS transistor MN3 .

[0078] The third PMOS transistor MP3 includes a gate connected to the input line INLN. When the first control signal SW_CON is a low signal, the third PMOS transistor MP3 outputs a high signal to the output line OUTLN. The third NMOS transistor MN3 includes a gate connected to the input line INLN. When the first control signal SW_CON is a high signal, the third NMOS transistor MN3 outputs a low signal to the output line OUTLN. The drain of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3 are commonly connected to the output node ND.

[0079] The source of the second PMOS transistor MP2 is connected to the power supply Power, the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3, and the gate of the second PMOS transistor MP2 receives the complementary signal SIZE_OP_B of the second control signal. In addition, the source of the second NMOS transistor MN2 is connected to the ground GND, the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3, and the gate of the second NMOS transistor MN2 receives the second control signal SIZE_OP.

[0080] According to the states of the second control signal SIZE_OP and the complementary signal SIZE_OP_B of the second control signal, as a first case, the first tri-state inverter 120A inverts the first control signal SW_CON to output the first control signal SW_CON to the output line OUTLN; or as a second case, the first tri-state inverter 120A is placed in a high impedance, i.e., floating state, and the first tri-state inverter 120A does not output a signal to the output line OUTLN regardless of the first control signal SW_CON. In the second case, the first tri-state inverter 120A is placed in a cut-off state. Therefore, when the first tri-state inverter 120A operates as an inverter, the size of the control buffer 100A increases accordingly.

[0081] For example, the first tri-state inverter 120A selectively adjusts the size of the control buffer 100A in response to the second control signal SIZE_OP and the complementary signal SIZE_OP_B of the second control signal. Therefore, the slew rate of the switch signal SW_ON can be adjusted according to the size of the control buffer 100A.

[0082] Reference below Figure 5 and Figure 6 The specific operation method of the first tri-state inverter 120A is described in more detail with the example of FIG.

[0083] For example, the second CMOS inverter 130 outputs a complementary signal SW_ON_B of the switching signal by inverting the switching signal SW_ON of the first CMOS inverter 110A. The complementary signal SW_ON_B of the switching signal may control on / off of each of the first switch 700 and the second switch 800.

[0084] The second tri-state inverter 140 can selectively adjust the size of the control buffer 100A in response to the second control signal SIZE_OP and the complementary signal SIZE_OP_B of the second control signal. The conversion rate of the complementary signal SIZE_OP_B of the switching signal can be adjusted according to the size of the control buffer 100A.

[0085] The structure and operation of each of the second CMOS inverter 130 and the second tri-state inverter 140 are substantially the same or similar to the structure and operation of each of the first CMOS inverter 110A and the first tri-state inverter 120A, respectively. Therefore, for the sake of brevity, the discussion of the structure and operation of the second CMOS inverter 130 and the second tri-state inverter 140 is omitted.

[0086] If the size of the transistors MP1 , MP4 , MN1 , and MN4 of each of the inverters 110A and 130 is reduced from 1 to 1 / 4, the peak currents of the switching signals SW_ON and SW_ON_B are correspondingly reduced, and thus EMI is also reduced.

[0087] As the load of the display panel increases, tri-state inverters 120A and 140 connected to the output terminals of inverters 110A and 130 , respectively, increase the size of control buffer 100A to increase the slew rate of switching signals SW_ON and SW_ON_B and also increase the driving capability of switching signals SW_ON and SW_ON_B.

[0088] Figure 5 is a circuit diagram for explaining an example of reducing the size of the control buffer according to the present example.

[0089] Figure 6is a circuit diagram for explaining an example of increasing the size of the control buffer according to the present example.

[0090] Because the structure and operation of each of the second CMOS inverter 130 and the second tri-state inverter 140 are substantially the same as or similar to the structure and operation of each of the first CMOS inverter 110A and the first tri-state inverter 120A, as described above, for the sake of brevity, only the method of operating the first CMOS inverter 110A and the first tri-state inverter 120A is representatively shown and described.

[0091] refer to Figure 5 In the example of FIG. 1 , when the control signal SIZE_OP is in the low state L, the second NMOS transistor MN2 is turned off. In addition, at the same time, the complementary signal SIZE_OP_B of the second control signal is in the high state H, and the second PMOS transistor MP2 is also turned off. At this time, the voltage applied to the source of the third PMOS transistor MP3 and the source of the third NMOS transistor MN3 is zero. Therefore, the first tri-state inverter 120A is placed in a high impedance state.

[0092] At this time, when the first control signal SW_CON is in the high state H, the first NMOS transistor MN1 operates. Therefore, the size of the control buffer 100A becomes 1 / 4, which is also the size of the first NMOS transistor MN1.

[0093] In contrast, the first PMOS transistor MP1 is driven when the first control signal SW_CON is in the low state L. Therefore, the size of the control buffer 100A becomes 1 / 4, which is the size of the first PMOS transistor MP1.

[0094] In short, when the second control signal SIZE_OP is in the low state L, the peak current of the switch signal SW_ON is reduced because the size of the control buffer 100A is reduced to ¼ of the size that would otherwise be in alternative technologies.

[0095] refer to Figure 6 In the example of FIG. 1 , when the second control signal SIZE_OP is in the high state H, the second NMOS transistor MN2 is turned on, and the complementary signal SIZE_OP_B of the second control signal is in the low state L. Therefore, the second PMOS transistor MP2 is also turned on. Then, the third PMOS transistor MP3 and the third NMOS transistor are in a state where they can be conductive at any time. Therefore, here, the control buffer 100A is placed in a standby state.

[0096] At this time, when the first control signal SW_CON is in the high state H, the first NMOS transistor MN1 and the third NMOS transistor MN3 are driven accordingly. Therefore, the size of the control buffer 100A is 1, which is the sum of 1 / 4 of the size of the first NMOS transistor MN1 and 3 / 4 of the size of the third NMOS transistor MN3.

[0097] In contrast, when the first control signal SW_CON is in the low state L, the first and third PMOS transistors MP1 and MP3 are driven accordingly. Therefore, the size of the control buffer 100A is 1, which is the sum of 1 / 4 of the size of the first PMOS transistor MP1 and 3 / 4 of the size of the third PMOS transistor MP3.

[0098] In short, when the second control signal SIZE_OP is in the high state H, the size of the control buffer 100A increases to 1, and thus, the slew rate of the switch signal SW_ON also increases.

[0099] The above discussion is summarized in Table 1 below.

[0100] Table 1

[0101]

[0102] Figure 7 is a simulation result showing the peak current according to the switch control signal. When the first control signal SW_CON is in the high state H and the second control signal SIZE_OP for controlling the size of the control buffer is in the high state H, the peak current is about 320mA. However, when the second control signal SIZE_OP is in the low state L, the peak current is reduced by 45% to about 180mA.

[0103] Figure 8 An example of an expansion of the control buffer is shown. Figure 8 In the example of the embodiment of the present invention, a plurality of first tri-state inverters 120B-1, 120B-2, 120B-3 are connected to the output terminal of the first CMOS inverter 110B to output the switch signal SW_ON. In addition, in such an example, a plurality of second tri-state inverters are connected to the output terminal of the second CMOS inverter to output the complementary signal SW_ON_B of the switch signal.

[0104] Because the structure and operation of the second CMOS inverter and each of the plurality of second tri-state inverters are substantially the same as or similar to the structure and operation of the first CMOS inverter 110B and each of the plurality of first tri-state inverters 120B-1, 120B-2, 120B-3, for the sake of brevity, only a method of operating the first CMOS inverter 110B and the plurality of first tri-state inverters 120B-1, 120B-2, and 120B-3 is representatively illustrated and described.

[0105] Fig. 9 Shows Figure 8 An example of the operating principle of the control buffer. Figure 8 and Fig. 9 In the example of, when three tri-state inverters 120B-1, 120B-2, 120B-3 are connected to the output terminal of the inverter 110B, the second control signal for controlling the size of the control buffer may include three control signals. For example, let the three control signals be the first size control signal SIZE_OP_1, the second size control signal SIZE_OP_2, and the third size control signal SIZE_OP_3.

[0106] First, when the first, second, and third size control signals SIZE_OP_1, SIZE_OP_2, and SIZE_OP_3 are all in a low state L, the first PMOS transistor MP1 or the first NMOS transistor MN1 is driven according to the switch control signal SW_CON. Therefore, the size of the control buffer 100A is 1 / 4.

[0107] Second, when the first size control signal SIZE_OP_1 is in a high state H and the second size control signal SIZE_OP_2 and the third size control signal SIZE_OP_3 are in a low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_1 or the first NMOS transistor MN1 and the third NMOS transistor MN3_1 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 2 / 4.

[0108] Third, when the second size control signal SIZE_OP_2 is in a high state H and the first size control signal SIZE_OP_1 and the third size control signal SIZE_OP_3 are both in a low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_2 or the first NMOS transistor MN1 and the third NMOS transistor MN3_2 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 3 / 4.

[0109] Fourth, when the third size control signal SIZE_OP_3 is in a high state H and the first size control signal SIZE_OP_1 and the second size control signal SIZE_OP_2 are both in a low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_3 or the first NMOS transistor MN1 and the third NMOS transistor MN3_3 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 4 / 4.

[0110] Fifth, when the first size control signal SIZE_OP_1 and the second size control signal SIZE_OP_2 are both in the high state H and the third size control signal SIZE_OP_3 is in the low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_1, MP3_2 or the first NMOS transistor MN1 and the third NMOS transistor MN3_1, MN3_2 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 4 / 4.

[0111] Sixth, when the first size control signal SIZE_OP_1 and the third size control signal SIZE_OP_3 are both in the high state H and the second size control signal SIZE_OP_2 is in the low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_1, MP3_3 or the first NMOS transistor MN1 and the third NMOS transistor MN3_1, MN3_3 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 5 / 4.

[0112] Seventh, when the second size control signal SIZE_OP_2 and the third size control signal SIZE_OP_3 are in the high state H and the first size control signal SIZE_OP_1 is in the low state L, the first PMOS transistor MP1 and the third PMOS transistor MP3_2, MP3_3 or the first NMOS transistor MN1 and the third NMOS transistor MN3_2, MN3_3 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 6 / 4.

[0113] Eighth, when the first size control signal SIZE_OP_1, the second size control signal SIZE_OP_2, and the third size control signal SIZE_OP_3 are all in the high state H, the first PMOS transistor MP1 and the third PMOS transistor MP3_1, MP3_2, MP3_3 or the first NMOS transistor MN1 and the third NMOS transistor MN3_1, MN3_2, MN3_3 are driven according to the switch control signal SW_CON. Therefore, in this case, the size of the control buffer 100A is 7 / 4.

[0114] In summary, in response to the increase in the number of tri-state inverters operating as inverters, the size of the control buffer 100B increases. In addition, when the size of the transistor of each tri-state inverter is different, as the size of the transistor operating as an inverter increases, the size of the control buffer 100B increases.

[0115] Therefore, the control buffer according to the above example adjusts the slew rate of the switching signal, which controls the respective output switches of the source driver according to the control buffer.

[0116] In addition, the source driver including the control buffer according to the above-described example selectively adjusts the size of the control buffer according to the load of the display panel, thereby reducing EMI phenomena associated with the switching signal.

[0117] Although the present disclosure includes specific examples, it is obvious after understanding the disclosure of the present application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents, suitable results can be achieved. Therefore, the scope of the present disclosure is not limited by the detailed description, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents should be interpreted as included in the present disclosure.

Claims

1. A control buffer in a source driver, the control buffer include: a first CMOS inverter connected to the first tri-state inverter, wherein the output of the first tri-state inverter is provided to the input of the second CMOS inverter, wherein the output of the second CMOS inverter is provided to the input of the second tri-state inverter, Wherein, a switching signal is output from the output terminal of the first CMOS inverter, wherein a complementary signal of the switch signal is output from the output terminal of the second CMOS inverter, wherein the first CMOS inverter is configured to output the switch signal to control the on and off of the switch, and the first tri-state inverter is connected to the first CMOS inverter and configured to selectively adjust the size of the control buffer, and The source driver adjusts the conversion rate of the switch signal according to the size of the control buffer.

2. The control buffer according to claim 1, in, The first CMOS inverter comprises: an input line configured to receive a first control signal; an output line configured to output the switch signal; and a first PMOS transistor and a first NMOS transistor, wherein each of the first PMOS transistor and the first NMOS transistor includes a gate commonly connected to the input line and a drain commonly connected to the output line, The first CMOS inverter is configured to invert a first control signal received from the input line and output the inverted first control signal to the output line as the switch signal.

3. The control buffer according to claim 2, in, The first PMOS transistor and the first NMOS transistor are both 1 / 4 size transistors.

4. The control buffer according to claim 3, in, According to the state of the second control signal, The first tri-state inverter is configured to operate as an inverter that inverts a first control signal received from the input line and outputs the inverted first control signal to an output line of the first CMOS inverter, or Regardless of the first control signal, the first tri-state inverter is placed in a high impedance state and configured not to output a signal to the output line.

5. The control buffer according to claim 4, in, In response to the first tri-state inverter operating as an inverter that inverts the first control signal received from the input line and outputs the inverted first control signal to the output line of the first CMOS inverter, the size of the control buffer increases.

6. The control buffer according to claim 4, in, The first three-state inverter comprises: a second NMOS transistor comprising a gate configured to receive the second control signal; a second PMOS transistor including a gate configured to receive a complementary signal of the second control signal; and a third PMOS transistor and a third NMOS transistor, wherein each of the third PMOS transistor and the third NMOS transistor includes a gate commonly connected to the input line and a drain commonly connected to the output line, wherein the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, and A drain of the second NMOS transistor is connected to a source of the third NMOS transistor.

7. The control buffer according to claim 6, in, The third PMOS transistor and the third NMOS transistor are both 3 / 4 size transistors.

8. The control buffer according to claim 1, in, The source driver adjusts a conversion rate of a complementary signal of the switching signal according to a size of the control buffer.

9. The control buffer according to claim 8, in, The switch includes a PMOS transistor and an NMOS transistor connected in parallel, The gate of the PMOS transistor is configured to receive a complementary signal of the switch signal, and A gate of the NMOS transistor is configured to receive the switching signal.

10. A control buffer in a source driver, the control buffer include: a plurality of CMOS inverters configured to output switching signals to control the on and off of switches controlled by the control buffer; as well as a plurality of tri-state inverters, each of which is respectively connected to each of the CMOS inverters and selectively adjusts the size of the control buffer according to the state of each of the tri-state inverters, Among them, according to the state of the size control signal input to each tri-state inverter, Each of the tri-state inverters is configured to operate as an inverter that inverts a switch control signal received from an input line, and is configured to output the inverted switch control signal to an output line of the CMOS inverter, or Regardless of the switch control signal, each of the tri-state inverters is placed in a high impedance state and configured not to output a signal to the output line, The source driver adjusts the conversion rate of the switch signal according to the size of the control buffer.

11. The control buffer according to claim 10, in, As the size of the control buffer decreases, the electromagnetic interference (EMI) of the switching signal decreases.

12. The control buffer according to claim 10, in, The CMOS inverter comprises: the input line being configured to receive a switch control signal; and the output line being configured to output the switching signal, The CMOS inverter is configured to invert the switch control signal received from the input line, and is configured to output the inverted switch control signal to the output line as the switch signal.

13. The control buffer according to claim 10, in, The size control signal includes a first size control signal, a second size control signal and a third size control signal, The tri-state inverter comprises: a first tri-state inverter configured to operate based on the first size control signal, a second tri-state inverter configured to operate based on the second size control signal, and a third tri-state inverter configured to operate based on the third size control signal, and Each of the three-state inverters comprises: a corresponding second NMOS transistor including a gate configured to receive a corresponding size control signal, a respective second PMOS transistor including a gate configured to receive a respective complementary signal of the respective size control signal, and a corresponding third PMOS transistor and a corresponding third NMOS transistor, wherein the corresponding third PMOS transistor and the corresponding third NMOS transistor include a gate commonly connected to the input line and a drain commonly connected to the output line, wherein The drain of each respective second PMOS transistor is connected to the source of each respective third PMOS transistor, and the drain of each respective second NMOS transistor is connected to the source of each respective third NMOS transistor.

14. The control buffer according to claim 13, in, Each of the three-state inverters is characterized in that According to the state of each of the size control signals, the corresponding third PMOS transistor or the corresponding third NMOS transistor is configured to operate as an inverter, or the corresponding third PMOS transistor and the corresponding third NMOS transistor are turned off, and As the size of the corresponding third PMOS transistor or the corresponding third NMOS transistor increases, the size of the control buffer increases.

15. The control buffer according to claim 13, in, In response to the switch control signal being in a high state, The size of the control buffer is adjusted by a combination of a third NMOS transistor of the first tri-state inverter, a third NMOS transistor of the second tri-state inverter, and a third NMOS transistor of the third tri-state inverter according to a state of each of the size control signals.

16. The control buffer according to claim 13, in, In response to the switch control signal being in a low state, The size of the control buffer is adjusted by a combination of a third PMOS transistor of the first tri-state inverter, a third PMOS transistor of the second tri-state inverter, and a third PMOS transistor of the third tri-state inverter according to a state of each of the size control signals.

17. The control buffer according to claim 13, in, In response to the first size control signal, the second size control signal, and the third size control signal being in a low state, the control buffer has a minimum size; and In response to the first size control signal, the second size control signal, and the third size control signal being in a high state, the control buffer has a maximum size.

18. A source driver for a display panel, the source driver include: a channel amplifier configured to receive a driving voltage to be output to a source line of the display panel for amplification; a switch connecting an output terminal of the channel amplifier to the source line; a control buffer configured to provide a switching signal to the switch to control turning on and off the switch; a logic circuit configured to generate a switch control signal for controlling a state of the switch signal and a state of a complementary signal of the switch signal and a size control signal for adjusting a size of the control buffer; as well as a level shifter configured to receive the switch control signal and the size control signal and shift a level of each of the switch control signal and the size control signal to provide it to the control buffer, Wherein, the control buffer comprises: A first CMOS inverter configured to output the switch signal to control the on and off of the switch; and a first tri-state inverter connected to the first CMOS inverter and configured to selectively adjust the size of the control buffer, The source driver adjusts the conversion rate of the switch signal according to the size of the control buffer.

19. The source driver according to claim 18, in, As the load of the display panel increases, the size of the control buffer increases, and As the load of the display panel decreases, the size of the control buffer decreases.

20. The source driver according to claim 18, in, The control buffer comprises: a CMOS inverter configured to output the switching signal based on a switching control signal; and a tri-state inverter connected to the CMOS inverter, the tri-state inverter being configured to selectively adjust the size of the control buffer based on a size control signal, Wherein, the operation of the tri-state inverter is controlled according to the load of the display panel.

21. The source driver according to claim 20, in, According to the state of the size control signal, the tri-state inverter is configured to operate as an inverter that inverts the switch control signal and the tri-state inverter is configured to output the inverted switch control signal as the switch signal; Alternatively, regardless of the switch control signal, the tri-state inverter is placed in a high impedance state and is configured not to output a signal to the output line.

Images