Error correction circuit for performing error correction on user data and error correction method using the same

Abstract

An error correction circuit receives a codeword including user data and a parity check code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer, and a processor. The first buffer stores the codeword and sequentially outputs subgroup data obtained by dividing the codeword. The decoder generates integrity data for each subgroup data received from the first buffer, and performs an error correction operation on the user data using the parity check code. The second buffer sequentially stores the integrity data for each subgroup data. When at least one integrity data is updated in the second buffer, the processor determines whether there is an error in the codeword based on the integrity data stored in the second buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0090908 filed on August 3, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a semiconductor circuit, and more particularly, to an error correction circuit that performs an error correction operation on user data and a memory controller including the error correction circuit. Background Art

[0004] A semiconductor storage device is a device that stores data under the control of a host device such as a computer, a smart phone, a smart pad, etc. The storage device may be, for example, a device that stores data on a magnetic disk such as a hard disk drive (HDD) or a solid state drive (SSD), or a device that stores data on a semiconductor memory device such as a memory card, particularly a non-volatile memory.

[0005] Non-volatile memory may include, for example, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0006] With the advancement of semiconductor manufacturing technology, such storage devices are being continuously improved to have high integration and increased capacity. The high integration of storage devices has the benefit of reducing the production cost of storage devices. However, due to the high integration of storage devices, the scale of storage devices is reduced, which may lead to, for example, an increase in the error rate of data stored in the storage device. Summary of the invention

[0007] According to an exemplary embodiment of the present invention, an error correction circuit includes a first buffer, a decoder, a second buffer, and a first processor. The first buffer is configured to store a codeword and sequentially output a plurality of subgroup data obtained by dividing the codeword. The codeword includes user data and a parity code, and the error correction circuit is configured to receive the codeword and perform an error correction operation on the user data. The decoder is configured to generate a plurality of integrity data for each of the plurality of subgroup data received from the first buffer, and perform an error correction operation on the user data using the parity code. The second buffer is configured to sequentially store a plurality of integrity data for each of the plurality of subgroup data. The first processor is configured to determine whether there is an error in the codeword based on the plurality of integrity data stored in the second buffer when at least one of the plurality of integrity data is updated in the second buffer.

[0008] According to an exemplary embodiment of the inventive concept, an error correction circuit includes a decoder and a first processor. The decoder is configured to sequentially generate a plurality of integrity data for each of a plurality of subgroup data obtained by dividing a codeword, and repeatedly perform an error correction operation on user data using a parity check code. The codeword includes user data and a parity check code, and the error correction circuit is configured to receive the codeword and perform an error correction operation on the codeword. The first processor is configured to determine whether there is an error in the codeword based on the plurality of integrity data. The decoder is also configured to stop the error correction operation performed on the codeword based on the determination result of the first processor.

[0009] According to an exemplary embodiment of the present invention, an error correction method includes: receiving a codeword including user data and a parity check code; storing the codeword in a first buffer; generating a plurality of integrity data for each of a plurality of sub-group data obtained by dividing the codeword; sequentially storing the plurality of integrity data in a second buffer; and when at least one of the plurality of integrity data is updated in the second buffer, determining whether there is an error in the codeword based on the plurality of integrity data stored in the second buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0012] Figure 2 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0013] Figure 3 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0014] Figure 4 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0015] Figure 5 is a flowchart illustrating an operation of a decoder according to an exemplary embodiment of the inventive concept.

[0016] Fig. 6A and Figure 6B is a diagram illustrating an operation of an error correction circuit according to an exemplary embodiment of the inventive concept.

[0017] Figure 7 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0018] Figure 8 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0019] Fig.9A and Fig. 9B is a diagram illustrating a method of determining error correction completion according to an exemplary embodiment of the inventive concept.

[0020] Fig.10 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0021] Fig.11 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0022] Fig.12 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0023] Fig.13 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the inventive concept.

[0024] Fig.14 is a block diagram illustrating a memory card system including a memory system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0026] It will be understood that the terms "first", "second", "third", etc. herein are used to distinguish one element from another element, and these elements are not limited by these terms. Therefore, a "first" element in an exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0027] It should be further understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0028] Exemplary embodiments of the inventive concept provide an error correction circuit capable of determining whether correction is completed during decoding of a codeword, and a memory controller including the error correction circuit.

[0029] Exemplary embodiments of the inventive concept also provide an error correction method capable of determining whether correction is completed during decoding of a codeword.

[0030] Figure 1 is a block diagram illustrating a memory system 1000 according to an exemplary embodiment of the inventive concept.

[0031] refer to Figure 1 The memory system 1000 may be implemented in one of the following computing systems: for example, a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a computer tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a dashboard camera, a digital camera, a digital multimedia broadcasting (DMB) player, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, etc.

[0032] The memory system 1000 may include a memory controller 100 and a memory device 200. As an example, the host, the memory controller 100, and the memory device 200 may be provided as chips, packages, modules, etc., respectively. Alternatively, the memory controller 100 and the memory device 200 may be packaged and provided as packages such as, for example, package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic chip carrier with leads (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer level assembly package (WFP), wafer level processing stack package (WSP), etc.

[0033] The memory device 200 may be implemented as a non-volatile memory device or a volatile memory device. For example, the memory device 200 may be configured as a non-volatile memory device (such as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistance random access memory, phase change memory, magnetoresistive random access memory, etc.), or may be configured as a volatile memory device (such as static random access memory (SRAM), dynamic random access memory (DRAM), latch, flip-flop, register, etc.). The memory device 200 may be configured as a hybrid of at least one non-volatile memory device and at least one volatile memory device, and a hybrid of at least two non-volatile memory devices or at least two volatile memory devices. The memory device 200 may be configured as a single flash memory chip, or may be configured as a plurality of flash memory chips.

[0034] The memory controller 100 may include a processor 110, an encoder 120, an error correction circuit 130, a random access memory (RAM) 140, a host interface 150, a memory interface 160, and a bus 170. The processor 110 may be electrically connected to the encoder 120, the error correction circuit 130, the RAM 140, the host interface 150, and the memory interface 160 through the bus 170. The bus 170 may refer to an electrical transmission line that transmits information between components of the memory controller 100.

[0035] The processor 110 may control the overall operation of the memory system 1000. For example, the processor 110 may control the memory system 1000 to decode a command received from a host and perform an operation according to the decoding result. The processor 110 may provide a read command and an address to the memory device 200 during a read operation, and may provide a write command, an address, and an encoded codeword to the memory device 200 during a write operation. In addition, the processor 110 may perform a process of converting a logical address received from a host into a physical page address using metadata stored in the RAM 140.

[0036] Data sent from the host and data generated by the processor 110 may be temporarily stored in the RAM 140, or data read from the memory device 200 may be temporarily stored in the RAM 140. In addition, metadata read from the memory device 200 is stored in the RAM 140. The RAM 140 may be implemented as, for example, a DRAM, an SRAM, etc. The metadata may be information generated by the memory system 1000 for managing the memory device 200. When the metadata is management information, the metadata may include mapping table information for converting a logical address into a physical page address of the memory device 200. As an example, the metadata may include page mapping table information for performing an address mapping operation on a page basis. In addition, the metadata may include information for managing the storage space of the memory device 200.

[0037] The host interface 150 may have a data exchange protocol with a host accessing the memory device 200, and may connect the memory device 200 to the host. The host interface 150 may be implemented as, for example, an Advanced Technology Attachment (ATA) interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, a Universal Serial Bus (USB) or a Serial Attached Small Form Factor (SAS) computer system interface, a Small Computer System Interface (SCSI), an Embedded Multimedia Card (eMMC) interface, or a Unix File System (UFS) interface. However, exemplary embodiments of the inventive concept are not limited thereto. The host interface 150 may exchange commands, addresses, and data with the host according to the control of the processor 110.

[0038] The memory interface 160 may be electrically connected to the memory device 200. As an example, the memory interface 160 may be configured to support an interface with a NAND flash memory chip or a NOR flash memory chip. The memory interface 160 may be configured to selectively perform software and hardware interleaving operations via a plurality of channels.

[0039] When the memory system 1000 is powered on, the processor 110 may control the memory system 1000 to read metadata stored in the memory device 200 and store the metadata in the RAM 140. The processor 110 may control the memory system 1000 to update the metadata stored in the RAM 140 according to an operation that invokes a change in the metadata in the memory device 200. In addition, before the memory system 1000 is powered off, the processor 110 may control the memory system 1000 to write the metadata stored in the RAM 140 to the memory device 200.

[0040] The processor 110 may control the memory controller 100 to encode an information word received from the host at the encoder 120 by using, for example, a low-density parity check code (LDPC) during a write operation, and to decode data read from the memory device 200 at the error correction circuit 130 by using LDPC during a read operation.

[0041] The encoder 120 may generate a codeword by appending a plurality of parity bits specified by LDPC to user data received by the host. The parity bits included in the codeword may be set to comply with LDPC.

[0042] The error correction circuit 130 may include a decoder 132. The decoder 132 may recover user data by decoding the data read from the memory device 200 in units of codewords. As an example, the decoder 132 may decode user data using LDPC. LDPC may be represented by a bipartite graph called a Tanner graph. For example, with reference to the Tanner graph, an edge may only connect a variable node to a check node, and may not connect a variable node to another variable node or a check node to another check node. In such a graph, a set of nodes such as a variable node may correspond to a bit of a codeword and a set of other nodes, and a constraint node called a check node may correspond to a set of parity check constraints defining a code.

[0043] According to an exemplary embodiment of the inventive concept, the error correction circuit 130 may divide the codeword into sub-group data, and by determining whether the sub-group data has an error, the decoder 132 may stop the decoding process and output the codeword to the host based on the error determination result, even if the decoder 132 is decoding the codeword. Since the decoding process may be stopped after decoding only a portion of the entire codeword instead of decoding the entire codeword, the performance of the decoding process may be improved and the power consumption may be reduced. This will refer to Figure 2 , Fig. 6A and Figure 6B Describe in more detail.

[0044] although Figure 1 The error correction circuit 130 of FIG. 1 includes only the decoder 132 , but in an exemplary embodiment, the error correction circuit 130 may include both the encoder 120 and the decoder 132 .

[0045] Figure 2 1 is a block diagram showing an error correction circuit 130 according to an exemplary embodiment of the inventive concept. Figure 1 Further description of described components and technical aspects may be omitted.

[0046] refer to Figure 2 , the error correction circuit 130 may include a first buffer 131, a decoder 132, a second buffer 133, and a codeword error determiner 134. The first buffer 131 may include a memory element capable of storing data. As an example, the first buffer 131 may be configured as a volatile memory device such as an SRAM, a DRAM, a latch, a flip-flop, or a register. The first buffer 131 may receive the original codeword CW_org from the memory device 200. In addition, the first buffer 131 may receive an updated codeword CW_udt on which decoding is performed from the decoder 132.

[0047] The first buffer 131 may sequentially output first to nth subgroup data SGD_1 to SGD_n, which are obtained by dividing a data stream of an original codeword CW_org or an updated codeword CW_udt into units of data of a certain length, to the decoder 132 .

[0048] The decoder 132 may receive the k-th subgroup data SGD_k obtained by dividing the original codeword CW_org or the updated codeword CW_udt, where k is an integer equal to or greater than 1 and equal to or less than n, and n is an integer equal to or greater than 1, and the decoder 132 may decode the received k-th subgroup data SGD_k. As the lengths of the codewords CW_org and CW_udt increase, a decoding process performed in units of subgroup data obtained by dividing the codewords CW_org, CW_udt may be performed to improve the speed of the decoder 132 and reduce its area.

[0049] According to an exemplary embodiment of the inventive concept, the decoder 132 may perform iterative decoding on a codeword. As an example, when decoding a codeword received from the outside (e.g., Figure 1 After receiving the original codeword CW_org from the memory device 200, when error correction is not completed, the decoder 132 may store an updated codeword CW_udt on which error correction is primarily performed in the first buffer 131, and may perform the decoding process again using the updated codeword CW_udt.

[0050] For example, the decoder 132 may perform a decoding process on all sub-group data SGD_1 to SGD_n obtained by dividing the original codeword CW_org, and may determine whether the error correction is completed. As an example, the decoder 132 may determine whether the error correction is completed by using a parity check code included in the original codeword CW_org. The decoder 132 may store the updated codeword CW_udt in the first buffer 131, and when the error correction operation performed on the original codeword CW_org is not completed, the decoding process may be sequentially performed on a plurality of sub-group data obtained by dividing the updated codeword CW_udt. When the error correction operation performed on the codewords CW_org, CW_udt is completed, the decoder 132 may output the corrected codeword CW_crt to the outside (for example, to the Figure 1 host).

[0051] The decoder 132 may generate k th integrity data ID_k, which includes information on whether there is an error in the k th sub-group data SGD_k, during a decoding process, and may store the generated k th integrity data ID_k in the second buffer 133 .

[0052] As an example, when the decoder 132 completes the decoding process of the original codeword CW_org, the first to nth integrity data ID_1 to ID_n may be stored in the second buffer 133. Then, when the decoder 132 performs a decoding process on the kth sub-group data SGD_k selected from among the plurality of sub-group data SGD_1 to SGD_n obtained by dividing the updated codeword CW_udt by the decoder 132, the decoder 132 may update the kth integrity data ID_k.

[0053] When updating the k-th integrity data ID_k stored in the second buffer 133 , the codeword error determiner 134 may output a correction stop signal CSF to the decoder 132 based on the updated plurality of integrity data ID_1 to ID_n.

[0054] In an exemplary embodiment, each of the first to nth integrity data ID_1 to ID_n may include information about errors present in the first to nth subgroup data SGD_1 to SGD_n respectively corresponding thereto, and the codeword error determiner 134 may determine whether an error correction operation performed on the updated codeword CW_udt is completed or whether no error exists in the updated codeword CW_udt based on the first to nth integrity data ID_1 to ID_n.

[0055] When the codeword error determiner 134 determines that the error correction operation performed on the updated codeword CW_udt is completed based on the first integrity data ID_1 to the nth integrity data ID_n, the codeword error determiner 134 can output a correction stop signal CSF to the decoder 132, and accordingly, the decoder 132 can promptly output the updated codeword CW_udt stored in the first buffer 131 as a corrected codeword CW_crt to the host without performing an additional decoding process on the multiple sub-group data SGD_1 to SGD_n.

[0056] According to an exemplary embodiment of the inventive concept, the codeword error determiner 134 determines whether error correction is completed before the decoding process of the codewords CW_org, CW_udt by the decoder 132 is completed, and can stop the decoding process based on the determination result. As a result, the decoding speed can be improved and unnecessary power consumption can be prevented or reduced.

[0057] Although the first buffer 131 and the second buffer 133 Figure 2 For example, in an exemplary embodiment, the first buffer 131 and the second buffer 133 may be configured as one memory element.

[0058] Here, when describing performing an error correction operation on a codeword, it will be understood that this process does not necessarily mean that errors are present (and corrected) in the codeword. For example, performing an error correction operation on a codeword may refer to the process of determining whether an error is present in the codeword, and outputting an appropriate codeword based on determining whether an error is present in the codeword. For example, performing an error correction operation may include outputting the original codeword without modification (e.g., without error correction) when it is determined that there are no errors in the codeword, and outputting a corrected codeword (e.g., by error correction) when it is determined that there are errors in the codeword.

[0059] Figure 3 1 is a block diagram showing an error correction circuit 130 according to an exemplary embodiment of the inventive concept. Figure 2 Further description of described components and technical aspects may be omitted.

[0060] refer to Figure 3 , the error correction circuit 130 may include a first buffer 131, a decoder 132, a second buffer 133, a codeword error determiner 134, and an integrity data generator 135. Figure 2 The first buffer 131 , the decoder 132 , the second buffer 133 , and the codeword error determiner 134 are described, and thus repeated descriptions thereof will be omitted.

[0061] The integrity data generator 135 may receive the k-th subgroup data SGD_k from the first buffer 131, and may store the k-th integrity data ID_k corresponding to the k-th subgroup data SGD_k in the second buffer 133. Since the integrity data generator 135 generates the integrity data ID_1 to ID_n separately from the decoder 132, the codeword error determiner 134 may determine the presence of errors in the codewords CW_org, CW_udt based on the integrity data ID_1 to ID_n without affecting the decoding capability of the decoder 132.

[0062] According to an exemplary embodiment, the integrity data generator 135 and the codeword error determiner 134 may each be a processing device, which may be implemented using, for example, a processor, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor, or any other device capable of running software or executing instructions.

[0063] Therefore, reference Figure 3 In an exemplary embodiment, codeword error determiner 134 may be referred to as a first processor, and integrity data generator 135 may be referred to as a second processor.

[0064] Figure 4 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0065] refer to Figure 2 and Figure 4 In operation S110, the error correction circuit 130 may receive the original codeword CW_org and may store the original codeword CW_org in the first buffer 131. In operation S120, the error correction circuit 130 may sequentially generate a plurality of integrity data ID_1 to ID_n for each of a plurality of sub-group data SGD_1 to SGD_n obtained by dividing the codewords CW_org, CW_udt stored in the first buffer 131. In operation S130, the error correction circuit 130 may update the second buffer 133 by sequentially storing the generated plurality of integrity data ID_1 to ID_n in the second buffer 133.

[0066] When the second buffer 133 is updated, in operation S140, the error correction circuit 130 may determine whether there is an error in the codewords CW_org, CW_udt based on the plurality of integrity data ID_1 to ID_n stored in the second buffer 133. When there is no error in the codewords CW_org, CW_udt, in operation S150, the error correction circuit 130 may immediately output the codewords CW_org, CW_udt as corrected codewords CW_crt without error correction.

[0067] Figure 5 is a flowchart illustrating an operation of the decoder 132 according to an exemplary embodiment of the inventive concept.

[0068] refer to Figure 2 and Figure 5 , in operation S210, an initial value of the flag k is set to 1, and in operation S220, the decoder 132 may receive the kth sub-group data SGD_k from the first buffer 131. In operation S230, the decoder 132 may generate the kth integrity data ID_k from the kth sub-group data SGD_k, and may update the generated kth integrity data ID_k in the second buffer 133. In operation S240, the decoder 132 may determine whether the flag k is equal to the number (n) of the plurality of sub-group data SGD_1 to SGD_n.

[0069] When the flag k is not equal to the number (n) of the plurality of sub-group data SGD_1 to SGD_n, in operation S250, the decoder 132 may determine whether a correction stop signal CSF is received from the codeword error determiner 134. When the correction stop signal CSF is received, in operation S290, the decoder 132 may stop decoding and may output the codeword CW_crt. Otherwise, when the correction stop signal CSF is not received, in operation S260, the flag k is incremented by 1, and operations S220 to S240 may be repeated.

[0070] Referring again to operation S240, when the flag k is equal to the number (n) of the plurality of sub-group data SGD_1 to SGD_n, in operation S270, the decoder 132 may correct errors present in the user data by using the parity check code included in the codewords CW_org, CW_udt. In operation S280, the decoder 132 may determine whether the error correction operation performed on the codewords CW_org, CW_udt is completed. When the error correction is completed, in operation S290, the codeword CW_crt may be output. Otherwise, when the error correction is not completed, the decoder 132 may repeat operations S210 to S270.

[0071] Despite Figure 5 , an exemplary embodiment in which the decoder 132 generates integrity data ID_1 to ID_n is shown, but exemplary embodiments of the inventive concept are not limited thereto. Figure 5 The described method can be applied to Figure 3 The integrity data generator 135 shown in FIG. 1 generates an exemplary embodiment of integrity data ID_1 to ID_n as a separate element.

[0072] Fig. 6A and Figure 6B is a diagram illustrating the operation of the error correction circuit 130 according to an exemplary embodiment of the inventive concept. For example, Fig. 6A and Figure 6B is a diagram showing a decoding process for second sub-group data SGD_2 and third sub-group data SGD_3 included in an updated codeword CW_udt after first integrity data ID_1 to seventh integrity data ID_7 corresponding to each of first sub-group data SGD_1 to seventh sub-group data SGD_7 are stored in a second buffer 133 due to completion of decoding of the original codeword CW_org. Figure 6B Indicates that in chronological order Fig. 6A The operations that are performed after those of .

[0073] refer to Figure 2 and Fig. 6A , the decoder 132 may receive the second subgroup data SGD_2 included in the first codeword CW1 from the first buffer 131, and may perform an integrity check on the second subgroup data SGD_2. In an exemplary embodiment, the integrity check refers to a confirmation operation of checking whether there is an error in the subgroup data during the decoding process. In an exemplary embodiment, a partial syndrome method or a partial cyclic redundancy check may be used for the integrity check. However, exemplary embodiments of the inventive concept are not limited thereto. Reference will be made to Figures 7 to 12 A method for performing integrity checking is described in detail.

[0074] The decoder 132 may generate the second integrity data ID_2 from the second sub-group data SGD_2 through integrity checking. Fig. 6A In the example of , the second integrity data ID_2 may include information indicating that the second subgroup data SGD_2 includes no error (NE). Decoder 132 may update the second integrity data ID_2 in the second buffer 133, and codeword error determiner 134 may determine whether there is an error in the first codeword CW1 based on the first integrity data ID_1 to the seventh integrity data ID_7. Due to the third integrity data ID_3 including information indicating that there is an error (E) for the third subgroup data SGD_3, codeword error determiner 134 may determine that there is an error in the first codeword CW1 by combining the first integrity data ID_1 to the seventh integrity data ID_7. Therefore, codeword error determiner 134 may output 0 as the correction stop signal CSF to decoder 132, and decoder 132 may continue the decoding process of the first codeword CW1.

[0075] refer to Figure 2 and Figure 6B , the decoder 132 may receive the third subgroup data SGD_3 included in the first codeword CW1 from the first buffer 131, and may perform an integrity check on the third subgroup data SGD_3. The decoder 132 may generate the third integrity data ID_3 from the third subgroup data SGD_3 through the integrity check. Figure 6B In the example of , the third integrity data ID_3 may include information indicating that the third subgroup data SGD_3 includes no error (NE). The decoder 132 may update the third integrity data ID_3 in the second buffer 133 to indicate no error (NE), and the codeword error determiner 134 may determine whether there is an error in the first codeword CW1 based on the first integrity data ID_1 to the seventh integrity data ID_7.

[0076] When the third integrity data ID_3 is updated, information indicating that there is no error in all of the first integrity data ID_1 to the seventh integrity data ID_7 may be included in the second buffer 133, and the codeword error determiner 134 may determine that there is no error in the first codeword CW1 by combining the first integrity data ID_1 to the seventh integrity data ID_7. Therefore, the codeword error determiner 134 may output 1 as the correction stop signal CSF to the decoder 132, and the decoder 132 may output the first codeword CW1 to the outside (e.g., to the decoder 132) in response to receiving 1 as the correction stop signal CSF. Figure 1 host) without performing a decoding process on the fourth sub-group data SGD_4 to the seventh sub-group data SGD_7.

[0077] Therefore, if Fig. 6A and Figure 6B As shown in , according to an exemplary embodiment of the inventive concept, the decoding process of at least a portion (eg, SGD_4 to SGD_7) of a plurality of sub-group data may be skipped. As a result, the performance of the decoding process may be improved and power consumption may be reduced.

[0078] Despite Fig. 6A and Figure 6B , an exemplary embodiment in which the decoder 132 generates integrity data (eg, ID_1 to ID_7) is shown, but exemplary embodiments of the inventive concept are not limited thereto. Fig. 6A and Figure 6B The described operations can be applied to Figure 3 An exemplary embodiment of the integrity data generator 135 shown as a separate element generates integrity data (eg, ID_1 to ID_7).

[0079] Figure 7 is a block diagram showing an error correction circuit 130a according to an exemplary embodiment of the inventive concept. Figure 3 Further description of described components and technical aspects may be omitted.

[0080] refer to Figure 7 , the error correction circuit 130a may include a first buffer 131a, a decoder 132a, a second buffer 133a, a codeword error determiner 134a, and an integrity data generator 135a. The integrity data generator 135a may generate k-th syndrome data Sdr_k based on the k-th subgroup data SGD_k. The k-th syndrome data Sdr_k may be data indicating whether the k-th subgroup data SGD_k satisfies a specific conditional expression. For example, the specific conditional expression may indicate whether a Tanner graph according to LDPC (hereinafter referred to as an LDPC graph) is satisfied.

[0081] The integrity data generator 135a may update the first to nth syndrome data Sdr_1 to Sdr_n in the second buffer 133a using the kth syndrome data Sdr_k, and the codeword error determiner 134a may determine whether the first codeword CW1 satisfies a specific conditional expression based on the first to nth syndrome data Sdr_1 to Sdr_n. When the first codeword CW1 satisfies the specific conditional expression, the codeword error determiner 134a may output a correction stop signal CSF to the decoder 132a, and the decoder 132a may stop the decoding process and may output the first codeword CW1 to the outside (e.g., to the decoder). Figure 1 The host.

[0082] although Figure 7 FIG. 1 shows an exemplary embodiment in which the integrity data generator 135a generates the kth syndrome data Sdr_k, but exemplary embodiments of the inventive concept are not limited thereto. Figure 7 The described process may be applied to an exemplary embodiment in which the decoder 132 a generates k-th syndrome data Sdr_k.

[0083] Figure 8 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0084] refer to Figure 7 and Figure 8 , in operation S310, the error correction circuit 130a sets the initial value of the flag k to 1, and in operation S320, the kth check sub-data Sdr_k may be generated for the kth sub-group data SGD_k included in the first codeword CW1. In operation S330, the error correction circuit 130a may update the parity check matrix of the LDPC code stored in the second buffer 133a based on the kth check sub-data Sdr_k. In operation S340, the error correction circuit 130a may generate an LDPC graph based on the parity check matrix. In operation S350, the error correction circuit 130a may determine whether the error correction is completed based on the generated LDPC graph. When it is determined in operation S360 that the error correction is not completed, in operation S380, the flag k is incremented by 1, and operations S320 to S360 may be repeated. Alternatively, when it is determined in operation S360 that the error correction is completed, in operation S370, the first codeword CW1 may be output to the outside (e.g., to Figure 1 host).

[0085] Fig.9A and Fig. 9B is a diagram illustrating a method of determining completion of error correction according to an exemplary embodiment of the inventive concept.

[0086] refer to Figure 7 , Fig.9A and Fig. 9B, the variable nodes and check nodes of the first codeword CW1 can be constructed based on the parity check matrix H of the LDPC code. The parity check matrix H may include the first row R1 to the fourth row R4 and the first column C1 to the eighth column C8. The number of check nodes of the first codeword CW1 may be equal to the number of rows of the parity check matrix H. For example, the first check node CN1 to the fourth check node CN4 corresponding to the first row R1 to the fourth row R4 of the parity check matrix H, respectively, may be calculated by the integrity data generator 135a and may be updated by the kth check sub-data Sdr_k. The number of variable nodes of the first codeword CW1 may be equal to the number of columns of the parity check matrix H. For example, the first variable node VN1 to the eighth variable node VN8 corresponding to the first column C1 to the eighth column C8 of the parity check matrix H, respectively, may be calculated by the integrity data generator 135a and may be updated by the kth check sub-data Sdr_k.

[0087] Each element of the parity check matrix H may be represented as h(i, j). The variable i may refer to a row of the parity check matrix H, and the variable j may refer to a column of the parity check matrix H. In an exemplary embodiment, when a value of each element h(i, j) of the parity check matrix H is 1, the i-th check node and the j-th variable node are associated with each other, and when a value of each element h(i, j) of the parity check matrix H is 0, the i-th check node and the j-th variable node are not associated with each other. Fig. 9B Variable nodes VN1 to VN8 and check nodes CN1 to CN4 based on the parity check matrix H are shown.

[0088] Since at the first column C1 corresponding to the first variable node VN1, the value of the second row R2 and the value of the fourth row R4 are 1, the first variable node VN1 is associated with the second check node CN2 and the fourth check node CN4. Since at the second column C2 corresponding to the second variable node VN2, the value of the first row R1 and the value of the second row R2 are 1, the second variable node VN2 is associated with the first check node CN1 and the second check node CN2. Since at the third column C3 corresponding to the third variable node VN3, the value of the second row R2 and the value of the third row R3 are 1, the third variable node VN3 is associated with the second check node CN2 and the third check node CN3. Since at the fourth column C4 corresponding to the fourth variable node VN4, the value of the first row R1 and the value of the fourth row R4 are 1, the fourth variable node VN4 is associated with the first check node CN1 and the fourth check node CN4.

[0089] Since at the fifth column C5 corresponding to the fifth variable node VN5, the value of the first row R1 and the value of the fourth row R4 are 1, the fifth variable node VN5 is associated with the first check node CN1 and the fourth check node CN4. Since at the sixth column C6 corresponding to the sixth variable node VN6, the value of the second row R2 and the value of the third row R3 are 1, the sixth variable node VN6 is associated with the second check node CN2 and the third check node CN3. Since at the seventh column C7 corresponding to the seventh variable node VN7, the value of the third row R3 and the value of the fourth row R4 are 1, the seventh variable node VN7 is associated with the third check node CN3 and the fourth check node CN4. Since at the eighth column C8 corresponding to the eighth variable node VN8, the value of the first row R1 and the value of the third row R3 are 1, the eighth variable node VN8 is associated with the first check node CN1 and the third check node CN3.

[0090] The codeword error determiner 134a may determine completion of error correction of the first codeword CW1 based on the generated LDPC graph. When correction of the first codeword CW1 is completed, the codeword error determiner 134a may output a correction stop signal CSF to the decoder 132a, and the decoder 132a may output the first codeword CW1 to the outside (e.g., to the decoder 132a) in response to the correction stop signal CSF. Figure 1 host).

[0091] Fig.10 1 is a block diagram showing an error correction circuit 130b according to an exemplary embodiment of the inventive concept. Figure 3 Further description of described components and technical aspects may be omitted.

[0092] refer to Fig.10 , the error correction circuit 130b may include a first buffer 131b, a decoder 132b, a second buffer 133b, a codeword error determiner 134b, and an integrity data generator 135b. The integrity data generator 135b may generate the kth sub-CRC data SCRC_k by performing a CRC operation based on the kth sub-group data SGD_k. The integrity data generator 135b may store the kth sub-CRC data SCRC_k in the second buffer 133b.

[0093] In an exemplary embodiment, the CRC operation may be an error-detecting method for verifying the reliability of data in a data transmission and reception system. For example, the CRC operation may refer to an operation of dividing the sub-group data by a specific polynomial and generating sub-CRC data by a remainder. That is, the k-th sub-CRC data SCRC_k may correspond to a remainder (e.g., a result of a mod function) derived by dividing the k-th sub-group data SGD_k by a specific polynomial.

[0094] The first codeword CW1 may include user data including first CRC data CRC1, and the codeword error determiner 134b may receive the first CRC data CRC1 included in the first codeword CW1 from the first buffer 131b. In addition, the codeword error determiner 134b may generate second CRC data CRC2 based on the first sub-CRC data SCRC_1 to the n-th sub-CRC data SCRC_n received from the second buffer 133b. In an example, the codeword error determiner 134b may generate the second CRC data CRC2 using a remainder derived by dividing a result obtained by performing an addition operation or a multiplication operation on the first sub-CRC data SCRC_1 to the n-th sub-CRC data SCRC_n by a specific polynomial.

[0095] The codeword error determiner 134b may compare the generated second CRC data CRC2 with the first CRC data CRC1 received from the first buffer 131b. As a result of the comparison, when the first CRC data CRC1 is identical to the second CRC data CRC2, the codeword error determiner 134b may output a correction stop signal CSF to the decoder 132b, and the decoder 132b may stop the decoding process and may output the first codeword CW1 to the outside (e.g., to the decoder). Figure 1 host).

[0096] Despite Fig.10 FIG. 1 shows an exemplary embodiment in which the integrity data generator 135 b generates the kth sub-CRC data SCRC_k, but exemplary embodiments of the inventive concept are not limited thereto. Fig.10 The described operation may be applied to an exemplary embodiment in which the decoder 132 b generates the k-th sub-CRC data SCRC_k.

[0097] Fig.11 is a flowchart illustrating an error correction method according to an exemplary embodiment of the inventive concept.

[0098] refer to Fig.10 and Fig.11, in operation S410, the error correction circuit 130b sets the initial value of the flag k to 1, and in operation S420, the first CRC data CRC1 may be read from the first buffer 131b. In operation S430, the error correction circuit 130b may generate the kth sub-CRC data SCRC_k for the kth sub-group data SGD_k included in the first codeword CW1. In operation S440, the error correction circuit 130b may generate the second CRC data CRC2 based on the plurality of sub-CRC data SCRC_1 to SCRC_n.

[0099] In operation S450, the error correction circuit 130b may compare the generated second CRC data CRC2 with the first CRC data CRC1 received from the first buffer 131b. When it is determined in operation S460 that the first CRC data CRC1 is not identical to the second CRC data CRC2, the flag k is incremented by 1 in operation S480, and operations S430 to S460 are repeated. Alternatively, when it is determined in operation S460 that the first CRC data CRC1 is identical to the second CRC data CRC2, the first codeword CW1 may be output to the outside (e.g., to a CPU 100). Figure 1 host).

[0100] Fig.12 1 is a block diagram showing an error correction circuit 130c according to an exemplary embodiment of the inventive concept. Figure 3 Further description of described components and technical aspects may be omitted.

[0101] refer to Fig.12 , the error correction circuit 130c may include a first buffer 131c, a decoder 132c, a second buffer 133c, a codeword error determiner 134c, a first integrity data generator 135c and a second integrity data generator 136c. The first buffer 131c, the decoder 132c, the second buffer 133c and the codeword error determiner 134c may be respectively Figure 1 The first buffer 131, the decoder 132, the second buffer 133 and the codeword error determiner 134 are the same as, or may be similar to Figure 1 The first buffer 131, the decoder 132, the second buffer 133 and the codeword error determiner 134, and therefore, further description thereof will be omitted.

[0102] First integrity data generator 135c may receive odd-numbered subgroup data SGD_2k-1 and may generate odd-numbered integrity data ID_2k-1. In addition, second integrity data generator 136c may receive even-numbered subgroup data SGD_2k and may generate even-numbered integrity data ID_2k. Odd-numbered integrity data ID_2k-1 generated by first integrity data generator 135c and even-numbered integrity data ID_2k generated by second integrity data generator 136c may be sequentially stored in second buffer 133c as a plurality of integrity data ID_1 to ID_n. First integrity data generator 135c may utilize reference Figure 7 Syndrome data or reference for description Fig.10 The sub-CRC data described generates odd-numbered integrity data, and the second integrity data generator 136c can use the reference Figure 7 Syndrome data or reference for description Fig.10 The sub-CRC data described generates even-numbered integrity data.

[0103] According to an exemplary embodiment of the inventive concept, the error correction circuit 130c can quickly generate a plurality of integrity data ID_1 to ID_n corresponding to a plurality of sub-group data SGD_1 to SGD_n by including a plurality of integrity data generators 135c and 136c. As a result, the speed at which the error existence is determined by the codeword error determiner 134c can be improved. Therefore, the decoding process of the first codeword CW1 can be completed more quickly.

[0104] Despite Fig.12 , an exemplary embodiment including two integrity data generators is shown, but exemplary embodiments of the inventive concept are not limited thereto. For example, according to an exemplary embodiment, three or more integrity data generators may be included in the error correction circuit 130c. In addition, in an exemplary embodiment, the decoder 132c may be used as the first integrity data generator 135c or the second integrity data generator 136c.

[0105] Fig.13 1 is a block diagram showing an error correction circuit 130d according to an exemplary embodiment of the inventive concept. Fig.10 Further description of described components and technical aspects may be omitted.

[0106] refer to Fig.13The error correction circuit 130d may include a first buffer 131d, a decoder 132d, a second buffer 133d, a codeword error determiner 134d, an integrity data generator 135d, and a third buffer 137d. The first buffer 131d, the second buffer 133d, and the codeword error determiner 134d may be respectively Fig.10 The first buffer 131b, the second buffer 133b and the codeword error determiner 134b are the same as, or may be similar to Fig.10 The first buffer 131b, the second buffer 133b and the codeword error determiner 134b are described herein, and therefore, further description thereof will be omitted.

[0107] The decoder 132d may receive the k-th subgroup data SGD_k and may generate the k-th syndrome data Sdr_k. In addition, the decoder 132d may store the generated k-th syndrome data Sdr_k in the third buffer 137d. The third buffer 137d may include a memory element capable of storing data. In addition, as an example, the third buffer 137d may be configured as a volatile memory device such as an SRAM, a DRAM, a latch, a flip-flop, or a register.

[0108] The codeword error determiner 134d may perform a primary integrity check based on the first CRC data CRC1 received from the first buffer 131d and the second CRC data CRC2 generated from the plurality of sub-CRC data SCRC_1 to SCRC_n received from the second buffer 133d. In addition, the codeword error determiner 134d may perform a secondary integrity check based on the plurality of check sub-data Sdr_1 to Sdr_n received from the third buffer 137d. The codeword error determiner 134d may output a correction stop signal CSF to the decoder 132d based on the primary integrity check and the secondary integrity check.

[0109] In an exemplary embodiment, when both the result of the primary integrity check and the result of the secondary integrity check indicate that there is no error in the first codeword CW1, the codeword error determiner 134d may output a correction stop signal CSF to the decoder 132d. In an exemplary embodiment, when at least one of the result of the primary integrity check and the result of the secondary integrity check indicates that there is no error in the first codeword CW1, the codeword error determiner 134d may output a correction stop signal CSF to the decoder 132d.

[0110] The error correction circuit 130d according to an exemplary embodiment of the inventive concept may increase the probability of error correction and data reliability by stopping a decoding process based on different integrity check methods.

[0111] The control operations described herein can be implemented in various ways depending on the application. For example, the control operations can be implemented with hardware, firmware, software, or a combination thereof. When the control operations are implemented with hardware, the processing unit can be specifically implemented by an ASIC (Application Specific Integrated Circuit), a DSP (Digital Signal Processor), a DSPD (Digital Signal Processor Device), a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array), a processor, a controller, a microcontroller, a microprocessor, an electronic device, other electronic units designed to perform the functions described in the specification of the present invention, or a combination thereof.

[0112] Fig.14 is a block diagram illustrating a memory card system 3000 including the memory system 1000 according to an exemplary embodiment of the inventive concept.

[0113] refer to Fig.14 , the memory card system 3000 may include a host 3100 and a memory card 3200. The host 3100 may include a host controller 3110 and a host connection unit 3120. The memory card 3200 may include a card connection unit 3210, a card controller 3220, and a memory device 3230.

[0114] exist Figures 1 to 13 The memory controller 100 and the memory device 200 shown in FIG. Fig.14 32 and the memory device 3230 shown in FIG. 32. In response to a command received via the card connection unit 3210, the card controller 3220 may decode the data read from the memory device 3230 by applying the decoding method disclosed above according to the exemplary embodiment of the inventive concept. For example, the card controller 3220 may improve the performance of the decoding process and may reduce power consumption by stopping the decoding process based on a determination result of whether there is an error in the sub-group data during the decoding process of the codeword.

[0115] The host 3100 may write data to the memory card 3200 or may read data stored in the memory card 3200. The host controller 3110 may transmit a command CMD, a clock signal CLK generated by a clock generator in the host 3100, and data to the memory card 3200 via the host connection unit 3120.

[0116] The memory card 3200 may be implemented as, for example, a compact flash card (CFC), a micro drive, a smart media card (SMC), a multimedia card (MMC), a secure digital card (SDC), a memory stick, a USB flash drive, etc.

[0117] As is conventional in the art of the inventive concept, exemplary embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units and / or modules. Those skilled in the art will appreciate that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based fabrication techniques or other fabrication techniques.

[0118] In the case of blocks, units and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform some functions to perform other functions. Moreover, without departing from the scope of the present invention, each block, unit and / or module of the exemplary embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. In addition, without departing from the scope of the present invention, the blocks, units and / or modules of the exemplary embodiment can be physically combined into more complex blocks, units and / or modules.

[0119] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. An error correction circuit, comprising: a first buffer configured to store the codeword and sequentially output a plurality of sub-group data obtained by dividing the codeword, wherein the codeword includes user data and a parity check code, and the error correction circuit is configured to receive the codeword and perform an error correction operation on the user data; a decoder configured to generate a plurality of integrity data for each of a plurality of sub-group data received from the first buffer, and perform an error correction operation on the user data using a parity check code, wherein each of the plurality of integrity data includes information on whether an error exists in a corresponding one of the sub-group data; a second buffer configured to sequentially store a plurality of integrity data for each of the plurality of sub-groups of data; and The first processor is configured to determine whether there is an error in the codeword based on the plurality of integrity data stored in the second buffer when at least one of the plurality of integrity data is updated in the second buffer.

2. The error correction circuit according to claim 1, wherein: The decoder is further configured to store the codeword in the first buffer when it is determined that there is an error in the codeword, and The codeword is output when it is determined that there is no error in the codeword.

3. The error correction circuit according to claim 1, wherein: The first processor is further configured to output a correction stop signal to the decoder when there is no error in the codeword, and The decoder is further configured to output the codeword in response to the correction stop signal without performing an error determination on the codeword.

4. The error correction circuit according to claim 1, further comprising: The second processor is configured to receive a plurality of sub-group data from the first buffer, generate a plurality of integrity data for the plurality of sub-group data, and sequentially store the plurality of integrity data in a second buffer.

5. The error correction circuit according to claim 4, wherein: The second processor is further configured to determine whether each of the plurality of sub-group data satisfies a predetermined conditional expression, and sequentially store in the second buffer a plurality of syndrome data generated based on the determination result of the second processor.

6. The error correction circuit according to claim 5, wherein: The first processor is further configured to output a correction stop signal to the decoder based on the plurality of syndrome data stored in the second buffer when no error exists in the plurality of sub-group data.

7. The error correction circuit according to claim 4, wherein: The second processor is further configured to perform a cyclic redundancy check (CRC) operation on each of the plurality of sub-group data, and sequentially store in the second buffer a plurality of sub-CRC data generated by performing the CRC operation.

8. The error correction circuit according to claim 7, wherein: The user data includes first CRC data, and The first processor is further configured to receive the first CRC data and the plurality of sub-CRC data, and output a correction stop signal to the decoder based on the first CRC data and the second CRC data, wherein the second CRC data is generated based on the plurality of sub-CRC data.

9. The error correction circuit according to claim 8, wherein: The first processor is further configured to output a correction stop signal to the decoder when the first CRC data is identical to the second CRC data, and The first processor is further configured to not output a correction stop signal to the decoder when the first CRC data is not identical to the second CRC data.

10. An error correction circuit comprising: a decoder configured to sequentially generate a plurality of integrity data for each of a plurality of sub-group data obtained by dividing the codeword, and repeatedly perform an error correction operation on the user data using a parity check code, wherein each of the plurality of integrity data includes information on whether an error exists in a corresponding one of the sub-group data, wherein the codeword includes user data and a parity check code, and the error correction circuit is configured to receive the codeword and perform an error correction operation on the codeword; and A first processor is configured to determine whether there is an error in the codeword based on the plurality of integrity data, The decoder is further configured to stop the error correction operation performed on the codeword based on the determination result of the first processor.

11. The error correction circuit according to claim 10, wherein: The decoder is further configured to, when it is determined that there is an error in the codeword, sequentially regenerate a plurality of integrity data for each of a plurality of sub-group data obtained by dividing the codeword, and The codeword is output when it is determined that there is no error in the codeword.

12. The error correction circuit according to claim 10, wherein: The first processor is further configured to output a correction stop signal to the decoder when there is no error in the codeword, and The decoder is further configured to output the codeword in response to the correction stop signal without performing an error determination on the codeword.

13. The error correction circuit of claim 10, further comprising: The second processor is configured to receive the plurality of sub-groups of data and generate a plurality of integrity data for the plurality of sub-groups of data.

14. The error correction circuit according to claim 13, wherein: The second processor is further configured to determine whether each of the plurality of sub-group data satisfies a predetermined conditional expression, and sequentially generate a plurality of syndrome sub-data based on the determination result of the second processor, and The first processor is further configured to output a correction stop signal to the decoder based on the plurality of syndrome data when no error exists in the plurality of sub-group data.

15. The error correction circuit according to claim 13, wherein: The second processor is further configured to perform a cyclic redundancy check (CRC) operation on each of the plurality of sub-group data and sequentially generate a plurality of sub-CRC data based on a result of the CRC operation. The user data includes first CRC data, and The first processor is further configured to receive the plurality of sub-CRC data and the first CRC data, and output a correction stop signal based on the first CRC data and the second CRC data, The second CRC data is generated based on multiple sub-CRC data.

16. An error correction method, comprising: receiving a codeword including user data and a parity check code; storing the codeword in a first buffer; generating a plurality of integrity data for each of a plurality of sub-group data obtained by dividing the codeword, wherein each of the plurality of integrity data includes information on whether an error exists in a corresponding one of the sub-group data; sequentially storing the plurality of integrity data in a second buffer; and When at least one of the plurality of integrity data is updated in the second buffer, it is determined whether there is an error in the codeword based on the plurality of integrity data stored in the second buffer.

17. The error correction method according to claim 16, further comprising: When it is determined that there is an error in the codeword, storing the codeword in a first buffer; as well as When it is determined that there is no error in the codeword, the codeword is output to the host.

18. The error correction method according to claim 16, further comprising: When there is no error in the codeword, a correction stop signal is output to the decoder, and The decoder outputs a codeword in response to the correction stop signal without performing error determination on the codeword.

19. The error correction method according to claim 16, wherein: Generates multiple integrity data including: determining whether each of the plurality of subgroup data satisfies a predetermined conditional expression; and A plurality of integrity data is generated using a plurality of syndrome data generated as a result of determining whether a predetermined conditional expression is satisfied.

20. The error correction method according to claim 16, wherein: Generates multiple integrity data including: performing a cyclic redundancy check (CRC) operation on each of the plurality of sub-groups of data; and generating a plurality of integrity data using a plurality of sub-CRC data generated as a result of performing a CRC operation, wherein the user data includes first CRC data, Wherein, determining whether there is an error in the codeword includes: receiving a plurality of sub-CRC data and first CRC data; generating second CRC data based on the plurality of sub-CRC data; and It is determined whether there is an error in the codeword based on the second CRC data and the first CRC data.

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