Storage devices

Abstract

A storage device may include: a monitoring module that monitors a characteristic degradation rate of multiple blocks included in a cell array of a non-volatile memory; a group management module that designates the multiple blocks as one or more groups based on a monitoring result of the monitoring module; a refresh cycle management module that determines a refresh cycle for each of the one or more groups; and a processor that performs refresh on the one or more groups according to the determined refresh cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0090421 filed on August 2, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least some example embodiments relate to a storage device and / or a method for operating the storage device. Background Art

[0004] Various flash memory-based storage devices perform various data operations on storage cells. For example, after receiving a command for reading or writing data from a host, the storage device can perform various data operations such as reading, writing, programming, and erasing to process the command.

[0005] However, when a certain period of time has passed after the write operation, degradation of the characteristics (e.g., retention characteristics) of the NAND constituting the flash memory occurs. In order to compensate for the degradation of the characteristics in this case, a refresh operation can be performed by moving the data written in the block where the characteristic degradation occurred to another block, performing an erase operation on the block where the characteristic degradation occurred, and then performing a write operation on the block again.

[0006] However, the refresh operation may degrade the performance of the storage device. For example, when the refresh operation occurs simultaneously and frequently on a large number of blocks, it may be difficult to ensure the stability of the storage device because the storage device not only has difficulty in quickly processing the user's request but also causes performance deviation. Summary of the invention

[0007] Some example embodiments of the present disclosure provide a memory device capable of reducing overhead caused by a refresh operation for reducing characteristic degradation of a block.

[0008] Some example embodiments of the present disclosure also provide a method for operating a memory device capable of reducing overhead caused by a refresh operation for reducing characteristic degradation of a block.

[0009] According to an example embodiment of the present disclosure, a storage device is provided, the storage device including a processing circuit, the processing circuit being configured to: monitor a characteristic degradation rate of a plurality of blocks included in a cell array of a non-volatile memory to generate a monitoring result; designate the plurality of blocks as one or more groups based on the monitoring result; determine a refresh cycle of each of the one or more groups; and refresh the one or more groups according to the refresh cycle.

[0010] According to another example embodiment of the present disclosure, a storage device is provided, the storage device including a processing circuit configured to: designate a plurality of blocks included in a cell array of a non-volatile memory as one or more groups based on differences in characteristic degradation rates indicating a degree of degradation of retention characteristics of the plurality of blocks; determine a refresh cycle for each of the one or more groups; refresh the one or more groups based on the refresh cycle; and perform a block status check on each of the one or more groups.

[0011] According to another example embodiment of the present disclosure, a method for operating a storage device is provided, the method comprising: monitoring a characteristic degradation rate of a plurality of blocks included in a cell array of a non-volatile memory; designating the plurality of blocks into one or more groups based on the monitoring result; determining a refresh cycle for each of the one or more groups; and performing a refresh on the one or more groups according to the determined refresh cycle.

[0012] However, example embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other example embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0014] Figure 1 is a block diagram for explaining a storage device according to an example embodiment of the present disclosure;

[0015] Figure 2 It is used to illustrate Figure 1 A block diagram of a non-volatile memory of a storage device;

[0016] Figure 3 It is used to illustrate Figure 1 A block diagram of a controller of a storage device;

[0017] Figures 4 to 6 It is used to illustrate Figure 2 A diagram of block characteristics of a non-volatile memory;

[0018] Figures 7 to 10 It is used to illustrate Figure 1 FIG. 1 is a diagram of an example of operation of a storage device according to an example embodiment of the present disclosure;

[0019] Fig.11 It is used to illustrate Figure 1FIG. 1 is a diagram of an example of operation of a storage device according to an example embodiment of the present disclosure;

[0020] Fig.12 and Fig.13 It is used to illustrate Figure 1 FIG. 1 is a diagram of an example of operation of a storage device according to an example embodiment of the present disclosure;

[0021] Fig.14 It is used to illustrate Figure 1 FIG. 1 is a diagram of an example of operation of a storage device according to an example embodiment of the present disclosure;

[0022] Fig.15 is a block diagram for explaining a storage device according to another example embodiment of the present disclosure;

[0023] Figures 16 to 18 It is used to illustrate Fig.15 FIG. 1 is a diagram of an operation example of a storage device according to another example embodiment of the present disclosure;

[0024] Fig.19 is a block diagram for explaining a storage device according to another example embodiment of the present disclosure;

[0025] Fig. 20 It is used to illustrate Fig.19 A diagram of an operation example of a storage device according to another example embodiment of the present disclosure; and

[0026] Fig.21 is a flowchart for explaining a method for operating a storage device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram for explaining a storage device according to an example embodiment of the present disclosure.

[0028] refer to Figure 1 , a storage device 10 according to an example embodiment of the present disclosure includes a non-volatile memory (NVM) 100 , a controller 200 , and a buffer 300 .

[0029] The storage device 10 may receive a read or write request from the host 20. The storage device 10 may further include an interface for transmitting a request from the host 20 to the controller 200 or for providing the host 20 with data provided from the controller 200.

[0030] The controller 200 may access the nonvolatile memory 100 in response to a read or write request from the host 20. For example, the controller 200 may read data stored in the nonvolatile memory 100 as a response to a read request and provide the data to the host 20. In addition, as a response to a write request, the controller 200 may program the data provided from the host 20 to the nonvolatile memory 100. In addition, the controller 200 may also perform an erase operation on the nonvolatile memory 100.

[0031] The controller 200 may include a flash translation layer (FTL). The flash translation layer may be used to convert a logical address into a physical address. For example, the controller 200 may use the flash translation layer to convert a logical address associated with a read or write request received from the host 20 into a physical address of the non-volatile memory 100. To this end, the controller 200 may also manage an address mapping table that stores a mapping relationship between a logical address and a physical address.

[0032] The buffer 300 may include a memory used by the controller 200 to access the nonvolatile memory 100 and process a request of the host 20. In some example embodiments of the present disclosure, the buffer 300 may include a static random access memory (SRAM), but the scope of the present disclosure is not limited thereto.

[0033] Reference now Figure 2 , the nonvolatile memory 100 will be described in more detail.

[0034] Figure 2 It is used to illustrate Figure 1 A block diagram of a nonvolatile memory of a storage device.

[0035] refer to Figure 2 , the nonvolatile memory 100 includes a cell array 110 , an address decoder 120 , a read / write (R / W) logic 130 , a control logic 140 , and an input / output buffer (I / O buffer) 150 .

[0036] The cell array 110 is connected to the address decoder 120 via row lines RL, and is connected to the read / write logic 130 via bit lines BL. Here, the row lines include a plurality of string selection lines, a plurality of word lines, a plurality of ground selection lines, and the like.

[0037] The address decoder 120 is connected to the cell array 110, the control logic 140, and the I / O buffer 150. Under the control of the control logic 140, the address decoder 120 receives the address ADDR via the I / O buffer 150 and decodes the received address ADDR. For example, the address decoder 120 decodes the received address ADDR to obtain a block address, and can use the block address to access a memory block of the cell array 110.

[0038] The address decoder 120 may further include a row decoder. The address decoder 120 may acquire a row address by decoding the received address ADDR using the row decoder, and may select one of a plurality of word lines in a block selected in the cell array 110 using the row address.

[0039] In addition, the address decoder 120 may further include a column decoder. The address decoder 120 may obtain a column address by decoding the received address ADDR using the column decoder, and may transmit the column address to the read / write logic 130.

[0040] The read / write logic 130 is connected to the cell array 110 via the bit line BL and receives a column address decoded by the address decoder 120. The read / write logic 130 selects the bit line BL using the decoded column address under the control of the control logic 140.

[0041] For example, the read / write logic 130 may program the data DATA received via the I / O buffer 150 on a memory cell corresponding to a selected word line in the cell array 110. On the other hand, the read / write logic 130 may read the data DATA corresponding to the decoded column address in the cell array 110, and may transmit the data to the I / O buffer 150. In addition, the read / write logic 130 may also perform a copy-back operation of writing data read from one region of the cell array 110 to another region.

[0042] The read / write logic 130 may include elements such as a page buffer, a page register, a column selection circuit, a sense amplifier, and a write driver.

[0043] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, and the I / O buffer 150. The control logic 140 may control the overall operation of the nonvolatile memory 100 according to an externally provided control signal CTL.

[0044] The I / O buffer 150 is connected to the address decoder 120, the control logic 140, and the read / write circuit 130. The I / O buffer 150 may transmit an address ADDR and a control signal CTL provided from the outside to the address decoder 120 and the control logic 140, respectively.

[0045] Furthermore, the I / O buffer 150 may transmit data DATA received together with a write request from the host 20 to the read / write circuit 130 , or may transfer data DATA read from the cell array 110 by the read / write circuit 130 , for example, to the host 20 .

[0046] Reference now Figure 3 , the controller 200 will be described in more detail.

[0047] Figure 3 It is used to illustrate Figure 1 A block diagram of a controller of a storage device.

[0048] refer to Figure 3 , the controller 200 includes a processor 210 , a buffer management module 220 , a host interface 230 , and a non-volatile memory interface (NVM I / F) 240 .

[0049] The processor 210 , the buffer management module 220 , the host interface 230 , and the nonvolatile memory interface 240 are electrically connected to each other via a bus 290 .

[0050] The processor 210 controls the overall operation of the controller 200. For example, the processor 210 may execute software (e.g., firmware) for controlling the overall operation of the controller 200. In some example embodiments of the present disclosure, the processor 210 may be a CPU (central processing unit). However, the scope of the present disclosure is not limited thereto, and the processor 210 may be implemented as any other type of processor capable of executing software.

[0051] The buffer management module 220 controls the above Figure 1 For example, the buffer management module 200 may write data to the buffer 300 or read data from the buffer 300 under the control of the processor 210.

[0052] The host interface 230 implements an electrical connection between the host 20 and the controller 200 of the storage device 10. For example, the controller 200 may receive a read or write request from the host 20 via the host interface 230 and provide the host 20 with a result of processing the request.

[0053] The nonvolatile memory interface 240 implements electrical connection between the controller 200 and the nonvolatile memory 100 in the storage device 10. For example, the controller 200 may access the nonvolatile memory 100 via the nonvolatile memory interface 240 and may receive data stored in the nonvolatile memory 100.

[0054] In some example embodiments, the nonvolatile memory 100 may be a NAND type flash memory. In this case, after a certain period of time has passed after data is written on the nonvolatile memory 100, degradation of the characteristics (e.g., retention characteristics) of the NAND constituting the nonvolatile memory 100 may occur. In order to compensate for such degradation of the characteristics, a refresh operation may be performed to move the data written in the block where the characteristic degradation occurs in the nonvolatile memory 100 to another block, an erase operation may be performed on the block where the characteristic degradation occurs, and then a write operation may be performed again.

[0055] However, when refresh operations occur in bursts, overhead due to the refresh operations increases and performance degradation of the storage device 10 may occur. For example, when the storage device 10 is performing a burst refresh operation, the storage device 10 may have difficulty in normally processing data access requests from users.

[0056] In order to solve such a problem, the controller 200 according to at least some example embodiments further includes a monitoring module 250 , a group management module 260 , and a refresh cycle management module 270 .

[0057] The monitoring module 250 , the group management module 260 , and the refresh cycle management module 270 are electrically connected to each other via the bus 290 , and are also electrically connected to the processor 210 , the buffer management module 220 , the host interface 230 , and the nonvolatile memory interface 240 .

[0058] The monitoring module 250 monitors the characteristic degradation rate of a plurality of blocks included in the cell array 110 of the nonvolatile memory 100. Here, the characteristic degradation rate of a block means the degradation rate of the retention characteristic of a block formed by NAND flash memory cells (the speed at which the characteristic deteriorates over time). Figures 4 to 6 That is, the monitoring module 250 monitors the degree of degradation of the retention characteristics of the plurality of blocks in order to monitor the characteristic degradation rate of the plurality of blocks.

[0059] The group management module 260 designates the plurality of blocks into one or more groups based on the monitoring result of the monitoring module 250. That is, the group management module 260 designates the plurality of blocks into one or more groups based on the difference in characteristic degradation rate occurring among the plurality of blocks over time.

[0060] The refresh cycle management module 270 determines a refresh cycle for each of the one or more groups. Specifically, the refresh cycle management module 270 determines a shorter refresh cycle for a block with a higher characteristic degradation rate, and determines a longer refresh cycle for a block with a lower characteristic degradation rate. Thereafter, the processor 210 refreshes the one or more groups according to the determined refresh cycle.

[0061] According to this scheme, since the refresh operation of the blocks included in the cell array 110 is performed individually for each group according to a clear standard, it is possible to obtain such an effect: while the refresh operation is stably performed, the overhead caused by the refresh operation is dispersed in time. Therefore, in one or more example embodiments, the performance degradation of the memory device 10 caused by the refresh operation can be reduced, thereby providing a stable operation of the memory device 10.

[0062] In addition, since the time for monitoring the characteristic degradation rates of the plurality of blocks included in the cell array 110 is not limited to a specific time, even when the operating environment of the storage device 10 changes during the operation of the storage device 10, by monitoring the characteristic degradation rates of the plurality of blocks as needed or periodically, the refresh operation strategy of the storage device 10 can be dynamically and adaptively changed in the changed environment. Therefore, the effect of improving the performance of the storage device 10 can also be obtained.

[0063] In various example embodiments of the present disclosure, the monitoring module 250, the group management module 260, and the refresh cycle management module 270 may be implemented as software or hardware. That is, at least one of the monitoring module 250, the group management module 260, and the refresh cycle management module 270 may be implemented, for example, as part of firmware executed by the processor 210. Alternatively, at least one of the monitoring module 250, the group management module 260, and the refresh cycle management module 270 may be implemented as hardware such as a semiconductor circuit including a plurality of semiconductor elements.

[0064] Figures 4 to 6 It is used to illustrate Figure 2 Diagram of block characteristics of non-volatile memory.

[0065] refer to Figure 4 The characteristic degradation rate monitored by the monitoring module 250 can be represented by a graph in which the X-axis represents the elapsed time in days and the Y-axis represents the CDF (Cumulative Distribution Function).

[0066] Taking the first point P1 as an example, it indicates that when three days have passed after a write operation is performed on blocks included in the cell array 110 of the nonvolatile memory 100, characteristics of about 30% of all blocks of the cell array 110 are degraded.

[0067] When this is expressed graphically, as in Figure 5 As illustrated in FIG. 1 , it can be determined that when three days have passed after performing the write operation, the block BLK corresponding to the area A1 needs to perform the refresh operation, and the area A1 corresponds to about 30% of the cell array 110 including the plurality of blocks BLK.

[0068] On the other hand, taking the second point P2 as an example, it indicates that when seven days have passed after a write operation is performed on blocks included in the cell array 110 of the nonvolatile memory 100, characteristics of about 95% of all blocks of the cell array 110 are degraded.

[0069] When this is expressed graphically, as in Figure 6 As illustrated in , it can be determined that when seven days have passed after performing the write operation, the block BLK corresponding to the area A2 needs to perform the refresh operation, and the area A2 corresponds to about 95% of the cell array 110 including the plurality of blocks BLK.

[0070] Considering the distribution of the characteristic degradation rate, for example, when refreshing is performed on all blocks of the cell array 110 every day, the occurrence of reclaim is significantly reduced, but the overhead caused by the refresh is very high. As another example, when refreshing the entire block of the cell array 110 every seven days, the refresh overhead can be reduced, but the occurrence of reclaim may increase.

[0071] According to various example embodiments of the present disclosure, refresh operations of blocks included in the cell array 110 are divided for each group according to clear criteria and performed at different refresh cycles, thereby simultaneously achieving a reduction in refresh overhead and a reduction in the occurrence of recycling.

[0072] Figures 7 to 10 It is used to illustrate Figure 1 FIG. 1 is a diagram of an operation example of a storage device according to an embodiment of the present disclosure.

[0073] refer to Figure 7 , some of the plurality of blocks BLK included in the cell array 110 may be designated as the first group G1, some of the other blocks may be designated as the second group G2, and still other blocks may be designated as the third group G3. That is, the group management module 260 may designate the first group G1 to the third group G3 for the plurality of blocks BLK included in the cell array 110.

[0074] The first group G1 may include blocks having characteristic degradation rates determined to be refreshed after a first time has passed among the plurality of blocks BLK. For example, the first group G1 may include blocks having characteristic degradation rates determined to be refreshed after three days have passed from the time when a write operation is performed.

[0075] The second group G2 may include blocks having characteristic degradation rates determined to be refreshed after a second time different from the first time has passed among the plurality of blocks BLK. For example, the second group G2 may include blocks having characteristic degradation rates determined to be refreshed after five days have passed after the time when the write operation is performed.

[0076] The third group G3 may include a block having a characteristic degradation rate determined to be refreshed after a third time different from the first time and the second time among the plurality of blocks BLK. For example, the third group G3 may include a block having a characteristic degradation rate determined to be refreshed after seven days have passed from the time when the write operation was performed.

[0077] Next, the refresh period management module 270 may determine a first refresh period for the first group G1 , may determine a second refresh period for the second group G2 , and may determine a third refresh period for the third group G3 .

[0078] For example, the refresh cycle management module 270 may determine a first refresh cycle corresponding to three days for the first group G1, may determine a second refresh cycle corresponding to five days for the second group G2, and may determine a third refresh period corresponding to seven days for the third group G3.

[0079] In particular, it should be noted that when the characteristic degradation rate of one or more blocks designated as the first group G1 among the multiple blocks BLK is higher than the characteristic degradation rate of one or more blocks designated as the second group among the multiple blocks BLK, the refresh cycle management module 270 determines the first refresh cycle to be shorter than the second refresh cycle.

[0080] That is, if the characteristic degradation rate of the blocks of the first group G1 is higher than the specific degradation rate of the blocks of the second group G2, because this means that the characteristics of the blocks of the first group G1 degrade faster over time than those of the second group G2, the first refresh cycle is determined to be short to suppress the occurrence of recycling.

[0081] Similarly, when the characteristic degradation rate of one or more blocks designated as the second group G2 among the multiple blocks BLK is higher than the characteristic degradation rate of one or more blocks designated as the third group G3 among the multiple blocks BLK, the refresh cycle management module 270 determines the second refresh cycle to be shorter than the third refresh cycle.

[0082] In other words, if the characteristic degradation rate of the blocks of the second group G2 is higher than the specific degradation rate of the blocks of the third group G3, because this means that the characteristics of the blocks of the second group G2 degrade faster over time than those of the third group G3, the second refresh cycle is determined to be short to suppress the occurrence of recycling.

[0083] Reference now Figure 8 , the processor 210 may refresh the first group G1 according to a previously determined first refresh cycle, for example, using a garbage collector (GC) 400. That is, the processor 210 may refresh the first group G1 in a cycle of, for example, three days.

[0084] Next, refer to Fig. 9 , the processor 210 may, for example, use the garbage collector 400 to perform a refresh of the second group G2 according to the previously determined second refresh cycle. That is, the processor 210 may, for example, refresh the second group G2 in a five-day cycle.

[0085] Next, refer to Fig.10 , the processor 210 may perform a refresh of the third group G3 according to the previously determined third refresh cycle, for example, using the garbage collector 400. That is, the processor 210 may refresh the third group G3 in a cycle of, for example, seven days. Here, because the refresh of the first group G1 is performed in a cycle of three days, when the processor 210 refreshes the third group G3 once, the refresh of the first group G1 may be performed approximately twice.

[0086] In this way, by determining a shorter refresh cycle for blocks with a higher characteristic degradation rate and determining a longer refresh cycle for blocks with a lower characteristic degradation rate, the refresh operations are dispersed in a timely manner, and the degradation of the performance of the storage device 10 due to the refresh overhead can be avoided and the stable operation of the storage device 10 can be ensured.

[0087] Fig.11 It is used to illustrate Figure 1 FIG. 1 is a diagram of an operation example of a storage device according to an example embodiment of the present disclosure.

[0088] refer to Fig.11 , showing an example in which the storage device 10 manages blocks classified into groups.

[0089] For example, blocks B11 to B15 of the first group G1 designated as having a refresh cycle of 3 days, blocks B21 to B28 of the second group G2 designated as having a refresh cycle of 5 days, and blocks B31 to B41 of the third group G3 designated as having a refresh cycle of seven days can be managed with different data structures.

[0090] For example, any of various data structures can be used to implement blocks B11 to B15 of the first group G1, including a LIFO (last in, first out) stack structure, a FIFO (first in, first out) queue structure, and a linked list. Various data structures including stacks, queues, and linked lists can also be used to implement blocks B21 to B28 of the second group G2 and blocks B31 to B41 of the third group G3.

[0091] For convenience of explanation, in the present exemplary embodiment, it is assumed that blocks B11 to B15 of the first group G1 , blocks B21 to B28 of the second group G2 , and blocks B31 to B41 of the third group G3 are implemented using queues.

[0092] As described above, after the group management module 260 specifies the group and the refresh cycle management module 270 determines the refresh cycle of each group, the processor 210 performs refresh of each group according to the refresh cycle.

[0093] Fig.12 and Fig.13 It is used to illustrate Figure 1 FIG. 1 is a diagram of an operation example of a storage device according to an example embodiment of the present disclosure.

[0094] refer to Fig.12 and Fig.13 , the refresh cycle management module 270 may move one or more blocks designated as one group to another group or may move one or more blocks designated as another group to the one group based on the monitoring result provided from the monitoring module 250.

[0095] For example, when it is detected based on the monitoring result provided by the monitoring module 250 that the block recycling occurs more than the expected value, it may be necessary to change the refresh cycle assigned in advance through the refresh cycle management module. Fig.12 As shown, the refresh cycle management module 270 may move the block B21 designated as the second group G2 to the first group G1. In addition, the refresh cycle management module 270 may move the blocks B31 and B32 designated as the third group G3 to the second group G2 and the first group G1, respectively.

[0096] As another example, according to the monitoring result provided from the monitoring module 250 or the inspection result of the block status inspection module 280 to be described later, it may be necessary to change the refresh cycle assigned in advance by the refresh cycle management module 270. In this case, Fig.13 As shown, the refresh cycle management module 270 can move the blocks B11 and B12 designated as the first group G1 to the second group G2 and the third group G3, respectively. In addition, the refresh cycle management module 270 can move the block B21 designated as the second group G2 to the third group G3.

[0097] In addition, since the time for monitoring the characteristic degradation rate of the multiple blocks included in the cell array 110 is not limited to a specific time, the group management module 260 can release one or more groups previously designated for the multiple blocks BLK, and can designate the multiple blocks BLK as new one or more groups based on the monitoring results provided from the monitoring module 250, etc.

[0098] In addition, based on the monitoring results provided from the monitoring module 250, the refresh cycle management module 270 can change the first refresh cycle (e.g., 3 days) of the first group G1 to a third refresh cycle (e.g., 4 days) different from the first refresh cycle, or can change the second refresh cycle (e.g., 5 days) of the second group G2 to a fourth refresh cycle (e.g., 6 days) different from the second refresh cycle.

[0099] In this way, even when the operating environment of the storage device 10 changes during the operation of the storage device 10, by monitoring the characteristic degradation rates of multiple blocks as needed or periodically, the refresh operation strategy of the storage device 10 can be dynamically and adaptively changed in the changed environment.

[0100] Fig.14 It is used to illustrate Figure 1 FIG. 1 is a diagram of an operation example of a storage device according to an example embodiment of the present disclosure.

[0101] In the present disclosure, the refresh cycle is determined based on the time when a write operation is performed on the block BLK of the cell array 110. In this regard, reference is made to Fig.14 , shows an example of a method for managing a plurality of blocks BLK according to a refresh cycle.

[0102] For example, in the case where there are a plurality of blocks a to k defining 3 days as a refresh cycle, when write time is managed individually for each of the plurality of blocks a to k, a large amount of resources of the storage device are occupied and performance thereof may be deteriorated.

[0103] In this case, if Fig.14 As shown, a measure for managing a plurality of blocks a to k using a block list 510 corresponding to a unit time slot 500 of one hour may be considered.

[0104] Since the refresh cycle is 3 days, the unit time slot 500 of one hour will contain a total of 72 time slots. In the case of the 0th time slot, blocks a, b, c that perform write operations within the hour corresponding to the 0th time slot are managed as the 0th list. In the case of the first time slot, blocks d, e that perform write operations within the hour corresponding to the first time slot are managed as the first list. In this way, in the case of the 71st time slot, blocks j, k that perform write operations within the hour corresponding to the 0th time slot are managed as the 71st list.

[0105] As a result, the processor 210 refreshes the block f included in the third list corresponding to the third time slot, and thereafter again passes through the 4th to 71st time slots and the 0th to 2nd time slots, and again performs a refresh on the block f included in the 3rd list corresponding to the 3rd time slot after 72 hours corresponding to the refresh cycle.

[0106] According to this scheme, it is easy to refresh the corresponding block in each refresh cycle after performing a write operation without maintaining the execution time of the write operation for each block separately. However, this example embodiment is only an example of implementation of refresh, and the scope of the present disclosure is not limited thereto.

[0107] Fig.15 is a block diagram for explaining a storage device according to another example embodiment of the present disclosure, Figures 16 to 18 It is shown Fig.15 FIG. 1 is a diagram of an operation example of a storage device according to another example embodiment of the present disclosure.

[0108] refer to Fig.15 ,and Figure 3 A difference of the exemplary embodiment of FIG. 2 is that the controller 200 further includes a block status check module (BSCM) 280 .

[0109] The block status check module 280 checks the status of the plurality of blocks BLK of the cell array 110. In particular, the block status check module 280 checks the status of the plurality of blocks BLK according to a desired (or, alternatively, predetermined) check strategy. Here, the check strategy may include at least one of a check cycle, a check depth, and a check algorithm.

[0110] In some example embodiments, the block status checking module 280 may individually determine a checking policy for each of the one or more groups specified by the group management module 260 .

[0111] refer to Figures 16 to 18 , a portion of the plurality of blocks BLK included in the cell array 110 may be designated as the first group G1, some other blocks may be designated as the second group G2, and still other blocks may be designated as the third group G3. That is, the group management module 260 may designate the first group G1 to the third group G3 for the plurality of blocks BLK included in the cell array 110.

[0112] Next, the block status checking module 280 may determine a first checking strategy for the first group G1 , determine a second checking strategy for the second group G2 , and determine a third checking strategy for the third group G3 .

[0113] For example, the block status check module 280 determines the check period as P1, the check depth as D1, and the check algorithm to be used as A1 for the first group G1, and can perform a check on the block BLK corresponding to the first group G1. In some example embodiments of the present disclosure, the area identified as the first group G1 by the block status check module 280 can be the same as the area identified as the first group G1 by the refresh cycle management module. In other words, the block status check module 280 can distinguish the policy check of the group specified according to the refresh cycle.

[0114] Similarly, the block status check module 280 determines the check period as P2, the check depth as D2, and the check algorithm to be used as A2 for the second group G2, and can accordingly perform a check on the block BLK corresponding to the second group G2. In some example embodiments of the present disclosure, the area identified as the second group G2 by the block status check module 280 may be the same as the area identified as the second group G2 by the refresh cycle management module 270. In other words, the block status check module 280 can distinguish the policy check on the group specified according to the refresh cycle.

[0115] Similarly, the block status check module 280 determines the check period as P3, the check depth as D3, and the check algorithm to be used as A3 for the third group G3, and can accordingly perform a check on the third group BLK corresponding to the third group G3. In some example embodiments of the present disclosure, the area identified as the third group G3 by the block status check module 280 can be the same as the area identified as the third group G3 by the refresh cycle management module 270. In other words, the block status check module 280 can distinguish the policy check on the group specified according to the refresh cycle.

[0116] Fig.19 is a block diagram for explaining a storage device according to another example embodiment of the present disclosure, Fig. 20 It is used to illustrate Fig.19 FIG. 1 is a diagram of an operation example of a storage device according to another example embodiment of the present disclosure.

[0117] refer to Fig.19 ,and Figure 3 The difference of the embodiment is that the controller 200 does not include the monitoring module 250 , and the storage device 10 receives the operation mode information MODE from the host 20 .

[0118] Specifically, the storage device 10 receives operation mode information MODE from the host 20 via the host interface 230, and in accordance with the group configuration policy and refresh cycle policy set (or, optionally, preset) according to the operation mode information MODE, the group management module 260 designates multiple blocks BLK as one or more groups, and the refresh cycle management module 270 can determine the refresh cycle of each of the one or more groups.

[0119] Next, refer to Fig. 20 For example, when the operation mode information MODE received from the host 20 has a first value (eg, 1), the group management module 260 may designate a plurality of blocks BLK as one group, and the refresh cycle management module 270 may determine a refresh cycle of the group as one day.

[0120] As another example, when the operation mode information MODE received from the host 20 has a fourth value (e.g., 4), the group management module 260 designates multiple blocks BLK as 5 groups, and the refresh cycle management module 270 can determine the refresh cycle of each of the five groups to 1 day, 3 days, 5 days, 7 days, and 9 days, respectively.

[0121] Fig.21 is a flowchart for explaining a method for operating a storage device according to an example embodiment of the present disclosure.

[0122] refer to Fig.21 According to an example embodiment of the present disclosure, a method for operating a storage device includes: monitoring (S2101) a characteristic degradation rate of a plurality of blocks BLK included in a cell array 110 of a nonvolatile memory 100; designating (S2103) the plurality of blocks BLK as one or more groups based on the monitoring result and determining a refresh cycle of each of the one or more groups; and performing (S2105) a refresh on the one or more groups according to the determined refresh cycle.

[0123] In some example embodiments of the present disclosure, monitoring the characteristic degradation rate of the plurality of blocks BLK may include monitoring the degree of degradation of the retention characteristics of the plurality of blocks BLK.

[0124] In some example embodiments of the present disclosure, designating the plurality of blocks BLK into one or more groups may include designating the plurality of blocks BLK into one or more groups based on differences in characteristic degradation rates occurring among the plurality of blocks BLK over time.

[0125] In some embodiments of the present disclosure, one or more groups include a first group and a second group, and designating multiple blocks BLK as one or more groups may include designating blocks among the multiple blocks BLK having a characteristic degradation rate determined to be refreshed after one hour as the first group, and designating blocks among the multiple blocks BLK having a characteristic degradation rate determined to be refreshed after a second time different from the first time as the second group.

[0126] In some example embodiments of the present disclosure, designating multiple blocks BLK as one or more groups may include: releasing one or more groups designated (or, optionally, pre-designated) for the multiple blocks BLK; and designating the multiple blocks BLK as one or more new groups based on monitoring results.

[0127] In some example embodiments of the present disclosure, one or more groups include a first group and a second group, and when a characteristic degradation rate of one or more blocks BLK designated as the first group among the plurality of blocks BLK is higher than a characteristic degradation rate of one or more blocks BLK designated as the second group among the plurality of blocks BLK, determining a refresh period for each of the one or more groups may include determining a first refresh period for the first group and a second refresh period for the second group, such that the first refresh period is shorter than the second refresh period.

[0128] In some example embodiments of the present disclosure, determining the refresh period of each of one or more groups may include: based on the monitoring results provided from the monitoring module 250, changing the first refresh period of the first group to a third refresh period different from the first refresh period, or changing the refresh period of the second group to a fourth refresh period different from the second refresh period.

[0129] In some example embodiments of the present disclosure, determining the refresh cycle of each of one or more groups may include: based on the monitoring results provided from the monitoring module 250, moving one or more blocks designated as the first group BLK to the second group, or moving one or more blocks BLK designated as the second group to the first group.

[0130] In some example embodiments of the present disclosure, the method may further include individually determining a check policy for each of the one or more groups designated by the group management module 260 to check states of the plurality of blocks BLK.

[0131] In some embodiments of the present disclosure, each inspection strategy may include at least one of an inspection cycle, an inspection depth, and an inspection algorithm.

[0132] In some example embodiments of the present disclosure, the method further includes receiving operation mode information MODE from the host 20 via the host interface 230, designating the plurality of blocks BLK as one or more groups includes designating the plurality of blocks BLK as one or more groups based on a group configuration strategy preset according to the operation mode information MODE, and determining a refresh period for each of the one or more groups may include determining a refresh period for each of the one or more groups according to a refresh period strategy preset according to the operation mode information MODE.

[0133] According to the various exemplary embodiments of the present disclosure described above, since the refresh operation of the blocks included in the cell array 110 is performed individually for each group according to a clear standard, the effect of timely dispersing the overhead caused by the refresh operation while stably performing the refresh operation can be obtained. This makes it possible to avoid the performance degradation of the memory device 10 caused by the refresh operation and ensure the stable operation of the memory device 10.

[0134] In addition, since the time for monitoring the characteristic degradation rates of the plurality of blocks included in the cell array 110 is not limited to a specific time, even when there is a change in the operating environment of the storage device 10 during the operation of the storage device 10, by monitoring the characteristic degradation rates of the plurality of blocks as needed or periodically, the refresh operation strategy of the storage device 10 can be dynamically and adaptively changed in the changed environment. Therefore, the effect of improving the performance of the storage device 10 can also be obtained.

[0135] Summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed exemplary embodiments of the present disclosure are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A storage device, comprising: A processing circuit, the processing circuit being configured to: monitoring characteristic degradation rates of a plurality of blocks included in a cell array of a nonvolatile memory to generate monitoring results, assigning the plurality of blocks into a plurality of groups based on the monitoring result, determining a refresh period for each of the plurality of groups, refreshing the plurality of groups according to the refresh cycle, continuously monitoring the characteristic degradation rates of the plurality of blocks to update the monitoring results, and One or more blocks among the plurality of blocks are moved between the plurality of groups based on the updated monitoring result, so that a refresh cycle of the one or more blocks is changed.

2. The storage device according to claim 1, wherein: The processing circuit is configured to monitor the characteristic degradation rate by monitoring a degree of degradation of retention characteristics of the plurality of blocks.

3. The storage device according to claim 1, wherein: The processing circuit is configured to specify the plurality of blocks based on differences in the characteristic degradation rates occurring among the plurality of blocks over time.

4. The storage device according to claim 1, wherein: The plurality of groups include a first group and a second group, and the processing circuit is configured to: designating blocks having the characteristic degradation rate determined to be refreshed after a first time has elapsed among the plurality of blocks as the first group, and Blocks among the plurality of blocks having the characteristic degradation rate determined to be refreshed after a second time has passed, the second time being different from the first time, are designated as the second group.

5. The storage device according to claim 1, wherein: The processing circuit is configured to: releasing one or more previous groups previously assigned to the plurality of blocks, and The plurality of blocks are designated as one or more new groups based on the updated monitoring result.

6. The storage device according to claim 1, wherein: The multiple groups include a first group and a second group, and the processing circuit is configured to: when the characteristic degradation rate associated with one or more blocks designated as the first group among the multiple blocks is higher than the characteristic degradation rate associated with one or more blocks designated as the second group among the multiple blocks, respectively determine a first refresh cycle of the first group and a second refresh cycle of the second group, so that the first refresh cycle is shorter than the second refresh cycle.

7. The storage device according to claim 6, wherein: The processing circuit is configured to: based on the updated monitoring result, (i) change the first refresh cycle of the first group to a third refresh cycle, and / or (ii) change the second refresh cycle of the second group to a fourth refresh cycle, wherein the third refresh cycle and the fourth refresh cycle are different from the first refresh cycle and the second refresh cycle.

8. The storage device according to claim 6, wherein: The processing circuit is configured to move the one or more blocks by (i) moving the one or more blocks designated as the first group to the second group or (ii) moving the one or more blocks designated as the second group to the first group.

9. The storage device according to claim 1, wherein: The processing circuit is configured to: checking the status of the plurality of blocks, and An inspection strategy is determined individually for each of the plurality of groups.

10. The storage device according to claim 9, wherein: Each of the inspection strategies includes at least one of an inspection cycle, an inspection depth, and an inspection algorithm.

11. The storage device according to claim 1, wherein: The storage device is configured as follows: receiving operation mode information from a host via a host interface, assigning the plurality of blocks into a plurality of groups based on a group configuration policy, and A refresh period for each of the plurality of groups is determined based on a refresh period policy, the group configuration policy and the refresh period policy being based on the operation mode information.

12. A storage device, comprising: A processing circuit, the processing circuit being configured to: specifying a plurality of blocks included in a cell array of a nonvolatile memory as a plurality of groups based on a monitoring result indicating a difference in a characteristic degradation rate indicating a degree of degradation of retention characteristics of the plurality of blocks, determining a refresh period for each of the plurality of groups, refreshing the plurality of groups based on the refresh period, performing a block status check on each of the plurality of groups, continuously monitoring the characteristic degradation rates of the plurality of blocks to update the monitoring results, and One or more blocks among the plurality of blocks are moved between the plurality of groups based on the updated monitoring result, so that a refresh cycle of the one or more blocks is changed.

13. The storage device according to claim 12, wherein: The plurality of groups include a first group and a second group, and the processing circuit is configured to: designating blocks having a characteristic degradation rate determined to be refreshed after a first time has elapsed among the plurality of blocks as the first group, and Blocks having a characteristic degradation rate determined to be refreshed after a second time has passed, the second time being different from the first time, among the plurality of blocks are designated as the second group.

14. The storage device according to claim 12, wherein the processing circuit is further configured to: releasing one or more previous groups previously assigned to the plurality of blocks, and The plurality of blocks are designated as one or more new groups based on the updated monitoring result.

15. The storage device according to claim 12, wherein: The plurality of groups include a first group and a second group, The processing circuit is configured to, when one of the characteristic degradation rates associated with one or more blocks designated as the first group among the multiple blocks is higher than one of the characteristic degradation rates associated with one or more blocks designated as the second group among the multiple blocks, respectively determine a first refresh cycle of the first group and a second refresh cycle of the second group so that the first refresh cycle is shorter than the second refresh cycle.

16. The storage device according to claim 15, wherein: The processing circuit is configured to: Based on the updated monitoring result, (i) the first refresh cycle of the first group is changed to a third refresh cycle, and / or (ii) the second refresh cycle of the second group is changed to a fourth refresh cycle, the third refresh cycle and the fourth refresh cycle being different from the first refresh cycle and the second refresh cycle.

17. The storage device according to claim 15, wherein: The processing circuit is configured to: The one or more blocks are moved by (i) moving the one or more blocks designated as the first group to the second group or (ii) moving the one or more blocks designated as the second group to the first group.

18. The storage device according to claim 12, wherein: The processing circuit is configured to individually determine an inspection strategy for each of the plurality of groups.

19. The storage device according to claim 18, wherein: Each of the inspection strategies includes at least one of an inspection cycle, an inspection depth, and an inspection algorithm.

20. The storage device according to claim 12, wherein: The storage device is configured as follows: receiving operation mode information from a host via a host interface, assigning the plurality of blocks into one or more groups based on a group configuration policy, and A refresh period of each of the one or more groups is determined based on a refresh period policy, the group configuration policy and the refresh period policy being set based on the operation mode information.

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