Display device and method for driving a display panel using the same

Abstract

A display device and a method for driving a display panel using the display device are disclosed. The display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel is configured to display an image. The gate driver is configured to output a gate signal having a different application timing for a frame to the display panel according to a difference between a grayscale value of a current frame image and a grayscale value of a previous frame image. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission signal to the display panel.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a display device and a method of driving a display panel using the display device. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] The display panel includes a plurality of pixels, and each pixel includes a plurality of switching elements. According to the bias of the switching element, the current-voltage curve of the switching element may be shifted. Due to the shift of the current-voltage curve of the switching element, an undesirable afterimage may be generated.

[0004] The hysteresis of the switching element may be compensated to prevent afterimage. A gate initialization signal may be applied to the pixels of the display panel to compensate for the hysteresis of the switching element. However, when the display panel displays a low grayscale image, some pixels may not be turned on due to compensation for the hysteresis of the switching element. Summary of the invention

[0005] Exemplary embodiments of the inventive concept provide a display device capable of enhancing the display quality of a display panel.

[0006] Exemplary embodiments of the inventive concept also provide a method of driving a display panel using the display device.

[0007] In an exemplary embodiment of a display device according to the concept of the present invention, the display device includes a display panel, a gate driver, a data driver and an emission driver. The display panel is configured to display an image. The gate driver is configured to output a gate signal having different application timings for a frame to the display panel according to a difference between a grayscale value of a current frame image and a grayscale value of a previous frame image. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission signal to the display panel.

[0008] In an exemplary embodiment, when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is large, the application timing of the gate signal may be in a late region of the inactive period of the emission signal.

[0009] In an exemplary embodiment, when the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, the gate driver may be configured to output a gate signal having the same application timing for the frame regardless of the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image. When the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate driver may be configured to output a gate signal having different application timing for the frame according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0010] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the entire area of ​​the display panel. The grayscale value of the previous frame image may correspond to the entire area of ​​the display panel.

[0011] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the central portion of the display panel. The grayscale value of the previous frame image may correspond to the central portion of the display panel.

[0012] In an exemplary embodiment, the gate driver may be configured to output a data writing gate signal, a data initialization gate signal, and an organic light emitting element initialization gate signal to the display panel in an inactive period of the emission signal.

[0013] In an exemplary embodiment, the gate driver may be configured to output the data write gate signal to the pixel of the display panel after outputting the data initialization gate signal to the pixel of the display panel.

[0014] In an exemplary embodiment, the gate driver may be configured to simultaneously output a data writing gate signal and an organic light emitting element initialization gate signal to the pixels of the display panel.

[0015] In an exemplary embodiment, the gate driver may be configured to output a plurality of pulses of a data write gate signal, a plurality of pulses of a data initialization gate signal, and a plurality of pulses of an organic light emitting element initialization gate signal to the pixel in a single inactive period of the emission signal.

[0016] In an exemplary embodiment, the gate driver may be configured to output a single pulse of a data write gate signal, a single pulse of a data initialization gate signal, and a single pulse of an organic light emitting element initialization gate signal to the pixel in a single inactive period of the emission signal.

[0017] In an exemplary embodiment, the display device may further include a driving controller configured to adjust the driving timing of the gate driver. The driving controller may include an image analyzer configured to analyze input image data, a contrast difference calculator configured to determine the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image, and a timing determiner configured to generate a gate timing control signal that determines the application timing of the gate signal according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0018] In an exemplary embodiment, the timing determiner may be configured to determine the gate timing control signal as a first value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is equal to or less than a first threshold. The timing determiner may be configured to linearly determine the gate timing control signal between the first value and a second value greater than the first value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the first threshold and equal to or less than a second threshold. The timing determiner may be configured to determine the gate timing control signal as a second value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the second threshold.

[0019] In an exemplary embodiment, the display panel may include a plurality of pixels. Each pixel may include an organic light emitting element. Each pixel may be configured to receive a data write gate signal, a data initialization gate signal, an organic light emitting element initialization gate signal, a data voltage and an emission signal and cause the organic light emitting element to emit to display an image.

[0020] In an exemplary embodiment, at least one of the pixels may include a first pixel switching element, a second pixel switching element, a third pixel switching element, a fourth pixel switching element, a fifth pixel switching element, a sixth pixel switching element, a seventh pixel switching element, a storage capacitor, and an organic light emitting element, the first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, the second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node, the third pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node, the fourth pixel switching element including a control electrode to which a data initialization signal is applied a control electrode for applying a gate signal, an input electrode to which an initialization voltage is applied, and an output electrode connected to a first node; a fifth pixel switching element includes a control electrode to which an emission signal is applied, an input electrode to which a first power voltage is applied, and an output electrode connected to a second node; a sixth pixel switching element includes a control electrode to which an emission signal is applied, an input electrode connected to a third node, and an output electrode connected to an anode electrode of an organic light-emitting element; a seventh pixel switching element includes a control electrode to which an organic light-emitting element initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to an anode electrode of an organic light-emitting element; a storage capacitor includes a first electrode to which a first power voltage is applied, and a second electrode connected to the first node; and the organic light-emitting element includes an anode electrode and a cathode electrode to which a second power voltage is applied.

[0021] In an exemplary embodiment, at least one of the pixels may include a first pixel switching element, a second pixel switching element, a 3-1 pixel switching element, a 3-2 pixel switching element, a 4-1 pixel switching element, a 4-2 pixel switching element, a fifth pixel switching element, a sixth pixel switching element, a seventh pixel switching element, a storage capacitor, and an organic light emitting element, the first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, the second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node, the 3-1 pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the input electrode of the 3-2 pixel switching element, the 3-2 pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode connected to the output electrode of the 3-1 pixel switching element, and an output electrode connected to the third node, the 4-1 pixel switching element The device includes a control electrode applied with a data initialization gate signal, an input electrode connected to the output electrode of the 4-2 pixel switching element, and an output electrode connected to the first node, the 4-2 pixel switching element includes a control electrode applied with a data initialization gate signal, an input electrode applied with an initialization voltage, and an output electrode connected to the input electrode of the 4-1 pixel switching element, the fifth pixel switching element includes a control electrode applied with an emission signal, an input electrode applied with a first power voltage, and an output electrode connected to the second node, the sixth pixel switching element includes a control electrode applied with an emission signal, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the organic light-emitting element, the seventh pixel switching element includes a control electrode applied with an organic light-emitting element initialization gate signal, an input electrode applied with an initialization voltage, and an output electrode connected to the anode electrode of the organic light-emitting element, the storage capacitor includes a first electrode applied with the first power voltage and a second electrode connected to the first node, and the organic light-emitting element includes an anode electrode and a cathode electrode applied with a second power voltage.

[0022] In an exemplary embodiment of a method for driving a display panel, the method includes: outputting a gate signal having different application timings for a frame to the display panel according to a difference between a grayscale value of a current frame image and a grayscale value of a previous frame image; outputting a data voltage to the display panel; and outputting an emission signal to the display panel.

[0023] In an exemplary embodiment, when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is large, the application timing of the gate signal may be late in the inactive period of the emission signal.

[0024] In an exemplary embodiment, when the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, regardless of the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image, the gate signal with the same application timing for the frame can be output to the display panel. When the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate signal with different application timing for the frame can be output to the display panel according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0025] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the entire area of ​​the display panel. The grayscale value of the previous frame image may correspond to the entire area of ​​the display panel.

[0026] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the central portion of the display panel. The grayscale value of the previous frame image may correspond to the central portion of the display panel.

[0027] According to the display device and the method of driving the display panel, the input image is analyzed in each frame, so that the application timing of the gate signal can be adjusted in the inactive period of the emission signal according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0028] When the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is relatively large, the application timing of the gate signal can be adjusted to the later area in the non-activation period of the emission signal, thereby reducing or preventing display defects caused by the turned-off switching elements in low grayscale driving.

[0029] When the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is relatively small, the application timing of the gate signal can be adjusted to the early region in the non-activation period of the emission signal, thereby reducing or preventing the afterimage caused by the lag of the switching element.

[0030] Therefore, display defects caused by the turned-off switching element and afterimages caused by the hysteresis of the switching element can be effectively reduced or prevented, thereby enhancing the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features and aspects of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept;

[0033] Figure 2 It is shown Figure 1 A circuit diagram of a pixel of a display panel;

[0034] Figure 3 is shown applied to Figure 2 A timing diagram of an input signal of a pixel;

[0035] Figure 4 It is shown Figure 1 The block diagram of the drive controller;

[0036] Figure 5 It is shown Figure 4 A graph of the operation of a timing determiner;

[0037] Figure 6 is a diagram showing the gate signal applied to the substrate when the gate signal is adjusted to be in the late region of the inactive period of the emission signal. Figure 2 A timing diagram of an input signal of a pixel;

[0038] Figure 7 The figure shows that when the gate signal application timing is adjusted to be in the late region of the inactive period of the emission signal Figure 2 A graph of a current-voltage curve of a switching element of a pixel;

[0039] Figure 8 is a graph showing the gate signal applied to the emitter when the gate signal is adjusted to be in the early region of the inactive period of the emitter signal. Figure 2 A timing diagram of an input signal of a pixel;

[0040] Fig. 9 is a graph showing that when the gate signal application timing is adjusted to be in the early region of the inactive period of the emission signal Figure 2 A graph of a current-voltage curve of a switching element of a pixel;

[0041] Fig.10 is a timing diagram showing an input signal applied to a pixel of a display device according to an exemplary embodiment of the inventive concept when the application timing of a gate signal is adjusted to be in a late region in an inactive period of an emission signal;

[0042] Fig.11 is a graph showing the gate signal applied to the emitter when the gate signal is adjusted to be in the early region of the inactive period of the emitter signal. Fig.10 A timing diagram of input signals to pixels of a display device; and

[0043] Fig.12 is a circuit diagram illustrating a pixel of a display device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0044] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals always represent the same elements. However, the inventive concept can be implemented in various forms and should not be interpreted as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete, and the aspects and features of the inventive concept will be fully conveyed to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described. Unless otherwise stated, the same reference numerals indicate the same elements throughout the drawings and written descriptions, and therefore their descriptions will not be repeated. In the drawings, for clarity, the relative sizes of elements, layers and regions may be enlarged.

[0045] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present invention, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0046] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the concept of the present invention. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include plural forms. It should also be understood that when the terms "comprise", "comprising", "include" and "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or parts is indicated, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their clusters is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. The statement before a column of elements such as "at least one" modifies the entire column of elements, rather than modifying the individual elements in the column.

[0047] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than degree, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the inventive concept, the use of "may" refers to "one or more embodiments of the inventive concept." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. In addition, the term "exemplary" is intended to indicate an example or illustration.

[0048] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the inventive concepts described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver and an emission driver) can be implemented using any appropriate hardware, firmware (for example, a dedicated integrated circuit), software, or a combination of software, firmware and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB) or formed on a substrate. In addition, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard storage device (for example, such as a random access memory (RAM)). The computer program instructions can also be stored in other non-temporary computer-readable media (for example, such as CD-ROMs, flash drives, etc.). Furthermore, those skilled in the art should appreciate that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the inventive concept.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It should also be understood that unless explicitly defined as such herein, those terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology and / or specification, and should not be interpreted in an idealized or overly formal sense.

[0050] Exemplary embodiments of the inventive concept relate to a display device that adjusts an application timing of a gate signal (eg, a timing of gate signal application) according to an input image and a method of driving a display panel using the display device.

[0051] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0052] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0053] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0054] The display panel 100 includes a plurality of gate lines GWL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels, and the plurality of pixels are electrically connected to the gate lines GWL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0055] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. In some examples, the input image data IMG may include white image data. In some examples, the input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0057] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0058] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT1 may include a horizontal start signal and a load signal.

[0059] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0060] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0061] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0062] The gate driver 300 generates a gate signal driving the gate lines GWL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GWL, GIL, and GBL.

[0063] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0064] In exemplary embodiments, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500 .

[0065] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage using the gamma reference voltage VGREF and outputs the data voltage to the data line DL.

[0066] For example, the data driver 500 and the driving controller 200 may be integrally formed to form a timing controller embedded data driver (TED).

[0067] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0068] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel of the display panel 100. Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0069] Reference Figures 1 to 3 The display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0070] The pixel receives the data writing gate signal GW, the data initialization gate signal GI, the organic light emitting element initialization gate signal GB, the data voltage VDATA and the emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0071] At least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0072] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0073] For example, the first pixel switch element T1 may be a P-type thin film transistor, the control electrode of the first pixel switch element T1 may be a gate electrode, the input electrode of the first pixel switch element T1 may be a source electrode, and the output electrode of the first pixel switch element T1 may be a drain electrode.

[0074] The second pixel switching element T2 includes a control electrode to which the data write gate signal GW is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0075] For example, the second pixel switch element T2 may be a P-type thin film transistor, the control electrode of the second pixel switch element T2 may be a gate electrode, the input electrode of the second pixel switch element T2 may be a source electrode, and the output electrode of the second pixel switch element T2 may be a drain electrode.

[0076] The third pixel switching element T3 includes a control electrode to which the data write gate signal GW is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0077] For example, the third pixel switch element T3 may be a P-type thin film transistor, the control electrode of the third pixel switch element T3 may be a gate electrode, the input electrode of the third pixel switch element T3 may be a source electrode, and the output electrode of the third pixel switch element T3 may be a drain electrode.

[0078] The fourth pixel switching element T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the first node N1.

[0079] For example, the fourth pixel switch element T4 may be a P-type thin film transistor, the control electrode of the fourth pixel switch element T4 may be a gate electrode, the input electrode of the fourth pixel switch element T4 may be a source electrode, and the output electrode of the fourth pixel switch element T4 may be a drain electrode.

[0080] The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0081] For example, the fifth pixel switch element T5 may be a P-type thin film transistor, the control electrode of the fifth pixel switch element T5 may be a gate electrode, the input electrode of the fifth pixel switch element T5 may be a source electrode, and the output electrode of the fifth pixel switch element T5 may be a drain electrode.

[0082] The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0083] For example, the sixth pixel switch element T6 may be a P-type thin film transistor, the control electrode of the sixth pixel switch element T6 may be a gate electrode, the input electrode of the sixth pixel switch element T6 may be a source electrode, and the output electrode of the sixth pixel switch element T6 may be a drain electrode.

[0084] The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0085] For example, the seventh pixel switch element T7 may be a P-type thin film transistor, the control electrode of the seventh pixel switch element T7 may be a gate electrode, the input electrode of the seventh pixel switch element T7 may be a source electrode, and the output electrode of the seventh pixel switch element T7 may be a drain electrode.

[0086] The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0087] The organic light emitting element OLED includes an anode electrode connected to the output electrode of the sixth pixel switching element T6 and a cathode electrode to which the low power voltage ELVSS is applied.

[0088] exist Figure 3 In the embodiment, the bias of the first pixel switch element T1 in the emission duration before the first duration DU1 may be referred to as a data bias (DATA BIAS). During the emission duration before the first duration DU1, the gate-source voltage VGS of the first pixel switch element T1 has a level of (VDATA-VTH)-ELVDD.

[0089] During the first to seventh durations DU1 to DU7, the emission signal EM[n] may have an inactive period EM OFF. During the inactive period EM OFF of the emission signal EM[n], the pixel may be initialized and a new data voltage VDATA may be written to the pixel.

[0090] During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the first duration DU1, the initialization voltage VINT is applied to the first node N1. During the first duration DU1, the bias of the first pixel switch element T1 may be referred to as an on bias (ON BIAS). During the first duration DU1, the gate-source voltage VGS of the first pixel switch element T1 may have a level of VINT-ELVDD. During the first duration DU1, the gate voltage of the first pixel switch element T1 may be the initialization voltage VINT, and the source voltage of the first pixel switch element T1 may be the high power voltage ELVDD.

[0091] During the second duration DU2, in response to the data write gate signal GW, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA with the threshold voltage |VTH| compensated is written to the first node N1. During the second duration DU2, the bias of the first pixel switch element T1 may be referred to as a threshold voltage bias (VTHBIAS). During the second duration DU2, the gate-source voltage VGS of the first pixel switch element T1 may have a level of -VTH. During the second duration DU2, the gate voltage of the first pixel switch element T1 may be VDATA-VTH, and the source voltage of the first pixel switch element T1 may be VDATA.

[0092] During the second duration DU2 , the anode electrode of the organic light emitting element OLED may be initialized in response to the organic light emitting element initialization gate signal GB.

[0093] In the present exemplary embodiment, after the data initialization gate signal GI is output to the pixel, the data write gate signal GW may be output to the pixel of the display panel.

[0094] In this exemplary embodiment, the data write gate signal GW and the organic light emitting element initialization gate signal GB may be simultaneously (e.g., synchronously) output to the pixel of the display panel. Optionally, after the data write gate signal GW is output to the pixel, the organic light emitting element initialization gate signal GB may be output to the pixel of the display panel.

[0095] During the third duration DU3, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the third duration DU3, the initialization voltage VINT is applied to the first node N1. During the third duration DU3, the bias of the first pixel switch element T1 may be referred to as an on bias (ON BIAS). During the third duration DU3, the gate-source voltage VGS of the first pixel switch element T1 may have a level of VINT-VDATA. During the third duration DU3, the gate voltage of the first pixel switch element T1 may be the initialization voltage VINT, and the source voltage of the first pixel switch element T1 may be the data voltage VDATA.

[0096] The operation of the pixel during the fourth duration DU4 may be the same as or substantially similar to the operation of the pixel during the second duration DU2.

[0097] During the fourth duration DU4, in response to the data write gate signal GW, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA having the threshold voltage |VTH| compensated is written to the first node N1. During the fourth duration DU4, the bias of the first pixel switch element T1 may be referred to as a threshold voltage bias VTHBIAS.

[0098] During the fourth duration DU4 , the anode electrode of the organic light emitting element OLED may be initialized in response to the organic light emitting element initialization gate signal GB.

[0099] The operation of the pixel during the fifth duration DU5 may be the same as the operation of the pixel during the third duration DU3. During the fifth duration DU5, the bias of the first pixel switching element T1 may be referred to as an ON bias (ON BIAS).

[0100] In addition, the operation of the pixel during the sixth duration DU6 may be the same as the operation of the pixel during the fourth duration DU4. During the sixth duration DU6, the bias of the first pixel switching element T1 may be referred to as a threshold voltage bias VTHBIAS.

[0101] In the present exemplary embodiment, in a single inactive period EM OFF of the emission signal EM, a plurality of pulses of the data write gate signal GW, a plurality of pulses of the data initialization gate signal GI, and a plurality of pulses of the organic light emitting element initialization gate signal GB may be output to the pixel. For example, in a single inactive period EM OFF of the emission signal EM, three pulses of the data write gate signal GW, three pulses of the data initialization gate signal GI, and three pulses of the organic light emitting element initialization gate signal GB may be output to the pixel.

[0102] During the seventh duration DU7, the data initialization gate signal GI, the data write gate signal GW, and the organic light emitting element initialization gate signal GB may be inactivated. Therefore, during the seventh duration DU7, the threshold voltage bias VTH BIAS of the first pixel switching element T1 may be maintained.

[0103] After the seventh duration DU7, the emission signal EM[n] is activated. During the emission duration EM ON after the seventh duration DU7, the organic light emitting element OLED emits light in response to the emission signal EM so that the display panel 100 displays an image. During the emission duration EM ON after the seventh duration DU7, the bias of the first pixel switch element T1 may be referred to as a data bias (DATA BIAS). During the emission duration EM ON after the seventh duration DU7, the gate-source voltage of the first pixel switch element T1 may have a level of (VDATA-VTH)-ELVDD.

[0104] In the first duration DU1, the data initialization gate signal GI may have an activation level. For example, the activation level of the data initialization gate signal GI may be a low level. When the data initialization gate signal GI has the activation level, the fourth pixel switching element T4 is turned on so that the initialization voltage VINT may be applied to the first node N1. For example, the data initialization gate signal GI[n] of the current stage may be generated based on the scan signal of the previous stage.

[0105] In the second duration DU2, the data write gate signal GW may have an activation level. For example, the activation level of the data write gate signal GW may be a low level. When the data write gate signal GW has an activation level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VINT. The first data write gate signal GW[n] of the current stage may be generated based on the scan signal of the current stage.

[0106] A voltage generated by subtracting the absolute value |VTH| of the threshold voltage of the first pixel switching element T1 from the data voltage VDATA may be charged at the first node N1 along a path generated by the first, second, and third pixel switching elements T1, T2, and T3.

[0107] In addition, in the second duration DU2, the organic light emitting element initialization gate signal GB may have an activation level. For example, the activation level of the organic light emitting element initialization gate signal GB may be a low level. When the organic light emitting element initialization gate signal GB has the activation level, the seventh pixel switch element T7 is turned on so that the initialization voltage VINT can be applied to the anode electrode of the organic light emitting element OLED. In this exemplary embodiment, the organic light emitting element initialization gate signal GB[n] of the current stage may be generated based on the scan signal of the current stage. Alternatively, the organic light emitting element initialization gate signal GB[n] of the current stage may be generated based on the scan signal of the next stage.

[0108] The operation of the pixel in the third duration DU3 and the fifth duration DU5 may be substantially the same as the operation of the pixel in the first duration DU1 .

[0109] The operation of the pixel in the fourth duration DU4 and the sixth duration DU6 may be substantially the same as the operation of the pixel in the second duration DU2 .

[0110] In the emission duration EM ON after the seventh duration DU7, the emission signal EM[n] may have an activation level. The activation level of the emission signal EM[n] may be a low level. When the emission signal EM[n] has the activation level, the fifth pixel switch element T5 and the sixth pixel switch element T6 are turned on. In addition, the first pixel switch element T1 is turned on by the data voltage VDATA.

[0111] The driving current flows through the fifth pixel switching element T5, the first pixel switching element T1 and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the intensity of the driving current. The driving current ISD flowing through the path from the input electrode to the output electrode of the first pixel switching element T1 is determined as shown in the following equation 1.

[0112] Equation 1

[0113]

[0114] In Equation 1, μ is the mobility of the first pixel switch element T1. Cox is the capacitance per unit area of ​​the first pixel switch element T1. W / L is the width-to-length ratio of the first pixel switch element T1. VSG is the voltage between the input electrode (e.g., the second node N2) of the first pixel switch element T1 and the control electrode (e.g., the first node N1) of the first pixel switch element T1. |VTH| is the absolute value of the threshold voltage of the first pixel switch element T1.

[0115] The voltage VG of the first node N1 after compensation of the threshold voltage |VTH| during the second duration DU2 may be expressed as Equation 2 below.

[0116] Equation 2

[0117] VG=VDATA-|VTH|

[0118] When the organic light emitting element OLED emits light during the emission duration EMON after the seventh duration DU7 , the driving voltage VOV and the driving current ISD may be expressed as the following Equations 3 and 4. In Equation 3, VS is the voltage of the second node N2 .

[0119] Equation 3

[0120] VOV=VS-VG-|VTH|=ELVDD-(VDATA-|VTH|)-|VTH|=ELVDD-VDATA

[0121] Equation 4

[0122]

[0123] When the organic light emitting element OLED emits light during the emission duration EMON after the seventh duration DU7 , the threshold voltage |VTH| is compensated during the second duration DU2 regardless of the threshold voltage |VTH| of the first pixel switching element T1 so that the driving current ISD can be determined.

[0124] Figure 4 It is shown Figure 1 1 is a block diagram of a driving controller 200 . Figure 5 It is shown Figure 4 FIG. 2 is a graph showing the operation of the timing determiner 260 .

[0125] Reference Figures 1 to 5 , the gate driver 300 outputs gate signals having different application timings for frames to the display panel 100 according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0126] Herein, the gate signal may include a data writing gate signal GW, a data initialization gate signal GI, and an organic light emitting element initialization gate signal GB.

[0127] The driving controller 200 adjusts the driving timing of the gate driver 300 .

[0128] The driving controller 200 includes an image analyzer 220, a contrast difference calculator 240 and a timing determiner 260, the image analyzer 220 is used to analyze the input image data IMG, the contrast difference calculator 240 is used to calculate the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image, and the timing determiner 260 is used to generate a gate timing control signal FLTE for determining the application timing of the gate signal according to the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0129] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the entire area of ​​the display panel 100. The grayscale value of the current frame image may be an average value of the grayscale values ​​corresponding to the entire area of ​​the display panel 100. The grayscale value of the previous frame image may correspond to the entire area of ​​the display panel 100. The grayscale value of the previous frame image may be an average value of the grayscale values ​​corresponding to the entire area of ​​the display panel 100.

[0130] In an exemplary embodiment, the grayscale value of the current frame image may correspond to the central portion of the display panel 100. For example, the grayscale value of the current frame image may be an average value of grayscale values ​​corresponding to the central portion of the display panel 100. The grayscale value of the previous frame image may also correspond to the central portion of the display panel 100, and the grayscale value of the previous frame image may be an average value of grayscale values ​​corresponding to the central portion of the display panel 100. In the central portion of the display panel 100, display defects caused by turned-off pixels or residual images may be perceived by the user. Therefore, the contrast difference calculator 240 may be configured to calculate the difference MEANDF between the grayscale value of the current frame image (e.g., the average grayscale value of the current frame image) and the grayscale value of the previous frame image (e.g., the average grayscale value of the previous frame image) corresponding to the central portion of the display panel 100. Compared to calculating the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image corresponding to the entire area of ​​the display panel 100, when the contrast difference calculator 240 calculates the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image corresponding to the central part of the display panel 100, the storage area (e.g., memory) used to store the input image data IMG can be reduced.

[0131] For example, the gate timing control signal FLTE may be defined as the duration from the inactive edge of the emission signal EM to the active edge of the data initialization gate signal GI. For example, the gate timing control signal FLTE may be defined as the duration from the rising edge of the emission signal EM to the falling edge of the data initialization gate signal GI.

[0132] When the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is equal to or less than the first threshold MEANDFLT, the timing determiner 260 may determine the gate timing control signal FLTE to be the first value MINFLTE, which may be the minimum value of the gate timing control signal FLTE.

[0133] When the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the first threshold MEANDFLT and equal to or less than the second threshold MEANDFHT, the timing determiner 260 may linearly determine the gate timing control signal FLTE between the first value MINFLTE and the second value MAXFLTE greater than the first value MINFLTE. The second value MAXFLTE may be the maximum value of the gate timing control signal FLTE. The second value MAXFLTE may be determined so that the activation period of the gate signal does not exceed the inactivation period of the emission signal EM.

[0134] When the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the second threshold MEANDFHT, the timing determiner 260 may determine the gate timing control signal FLTE to be the second value MAXFLTE.

[0135] Figure 6 is a diagram showing the gate signal applied to the substrate when the gate signal is adjusted to be in the late region of the inactive period of the emission signal. Figure 2 Timing diagram of the pixel input signal. Figure 7 The figure shows that when the gate signal application timing is adjusted to be in the late region of the inactive period of the emission signal Figure 2 A graph showing a current-voltage curve of a switching element of a pixel. Figure 8 is a graph showing the gate signal applied to the emitter when the gate signal is adjusted to be in the early region of the inactive period of the emitter signal. Figure 2 Timing diagram of the pixel input signal. Fig. 9 is a graph showing that when the gate signal application timing is adjusted to be in the early region of the inactive period of the emission signal Figure 2 A graph showing a current-voltage curve of a switching element of a pixel.

[0136] Reference Figures 1 to 9 , the gate driver 300 outputs gate signals having different application timings for frames to the display panel 100 according to the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0137] For example, when the difference MEANDF between the grayscale values ​​of the current frame image and the previous frame image is large (eg, greater than a first grayscale difference threshold), the application timing of the gate signals GW, GI, and GB may be late in the inactive period EM OFF of the emission signal EM.

[0138] A large difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image may mean a large contrast change between the current frame image and the previous frame image.

[0139] like Figure 6 As shown in , when the contrast change between the current frame image and the previous frame image is large, the data bias (DATA BIAS) state of the first pixel switch element T1 may be maintained for a relatively long time. If the data bias (DATA BIAS) state of the first pixel switch element T1 is maintained for a long time, the hysteresis compensation degree of the first pixel switch element T1 may be small (for example, less than the second grayscale difference threshold).

[0140] exist Figure 7In the embodiment, when the previous frame image represents a high gray value image, the current-voltage curve of the first pixel switch element T1 may be the first curve CON, and when the previous frame image represents a low gray value image, the current-voltage curve of the first pixel switch element T1 may be the second curve COFF. When the hysteresis compensation degree of the first pixel switch element T1 is large, the distance between the first curve CON and the second curve COFF may be small. Figure 7 The hysteresis compensation degree of the first pixel switch element T1 is less than Fig. 9 The hysteresis compensation degree of the first pixel switch element T1 in FIG. Figure 7 The distance between the first curve CON and the second curve COFF in the Fig. 9 The distance between the first curve CON and the second curve COFF in .

[0141] When the hysteresis of the switching element is sufficiently (e.g., fully) compensated, some of the pixels in the low grayscale image may not be turned on, thereby generating display defects by one or more of the turned-off pixels. When the contrast change between the current frame image and the previous frame image is large, display defects caused by afterimages may not be generated. Therefore, when the contrast change between the current frame image and the previous frame image is large, the hysteresis compensation degree of the first pixel switching element T1 can be controlled to be small, thereby reducing or preventing display defects caused by turned-off pixels in low grayscale images.

[0142] For example, when the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is small, the application timing of the gate signals GW, GI, and GB may be early in the inactive period EM OFF of the emission signal EM.

[0143] A small difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image may mean a small contrast change between the current frame image and the previous frame image.

[0144] like Figure 8 As shown in , when the contrast change between the current frame image and the previous frame image is small, the threshold voltage bias VTH BIAS state of the first pixel switch element T1 can be maintained for a relatively long time. If the threshold voltage bias VTH BIAS state of the first pixel switch element T1 is maintained for a long time, the hysteresis compensation degree of the first pixel switch element T1 can be large.

[0145] exist Fig. 9In the embodiment, when the previous frame image represents a high gray value image, the current-voltage curve of the first pixel switch element T1 may be the first curve CON, and when the previous frame image represents a low gray value image, the current-voltage curve of the first pixel switch element T1 may be the second curve COFF. When the hysteresis compensation degree of the first pixel switch element T1 is large, the distance between the first curve CON and the second curve COFF may be small. Fig. 9 The hysteresis compensation degree of the first pixel switch element T1 is greater than Figure 7 The hysteresis compensation degree of the first pixel switch element T1 in FIG. Fig. 9 The distance between the first curve CON and the second curve COFF in the Figure 7 The distance between the first curve CON and the second curve COFF in .

[0146] When the hysteresis of the switching element is not sufficiently compensated, an afterimage may be generated due to the shift of the current-voltage curve. When the contrast change between the current frame image and the previous frame image is small, a display defect caused by the afterimage may be generated. Therefore, when the contrast change between the current frame image and the previous frame image is small, the hysteresis compensation degree of the first pixel switching element T1 can be controlled to be large, thereby reducing or preventing display defects caused by the afterimage.

[0147] In an exemplary embodiment, when the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, the gate driver 300 may output a gate signal having the same application timing for the frame regardless of the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image. When the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate driver 300 may output a gate signal having different application timing for the frame according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

[0148] When the display panel 100 displays a high grayscale image immediately after displaying a low grayscale image, a display defect caused by a turned-off pixel may be generated. Therefore, when the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate driver 300 may output a gate signal having a different application timing for the frame, thereby being able to reduce or prevent display defects caused by the turned-off pixel.

[0149] On the contrary, when the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, the hysteresis of the first pixel switch element T1 can be compensated, thereby reducing or preventing display defects caused by afterimages caused by the shift of the current-voltage curve.

[0150] According to the present exemplary embodiment, display defects due to a turned-off switching element and display defects due to an afterimage caused by a hysteresis of the switching element can be effectively reduced or prevented. Therefore, the display quality of the display panel 100 can be enhanced.

[0151] Fig.10 is a timing diagram illustrating an input signal applied to a pixel of a display device according to an exemplary embodiment of the inventive concept when an application timing of a gate signal is adjusted to be in a later region in an inactive period of an emission signal. Fig.11 is a graph showing the gate signal applied to the emitter when the gate signal is adjusted to be in the early region of the inactive period of the emitter signal. Fig.10 A timing diagram of an input signal to a pixel of a display device.

[0152] The display device and the method of driving the display panel according to the present exemplary embodiment are similar to those of the reference numerals except for the gate signal applied to the pixel. Figures 1 to 9 The display device and the method of driving the display panel of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 9 The same or similar parts as those described in the previous exemplary embodiments are described herein, and any repeated explanation regarding the above elements may be omitted.

[0153] Reference Figures 1 to 5 , Fig.10 and Fig.11 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0154] The display panel 100 includes a plurality of pixels, and each pixel includes an organic light emitting element OLED.

[0155] Each pixel is configured to receive a data write gate signal GW, a data initialization gate signal GI, an organic light emitting element initialization gate signal GB, a data voltage VDATA and an emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0156] In the inactive period of the emission signal EM, the gate driver 300 outputs the data write gate signal GW, the data initialization gate signal GI, and the organic light emitting element initialization gate signal GB to the display panel 100 .

[0157] The first pixel switching element T1 may have a bias state including at least one of a data bias (DATA BIAS) state, an on bias (ON BIAS) state, and a threshold voltage bias (VTH BIAS) state according to gate signals GW, GI, and GB.

[0158] In the present exemplary embodiment, in a single inactive period EM OFF of the emission signal EM, a single pulse of the data write gate signal GW, a single pulse of the data initialization gate signal GI, and a single pulse of the organic light emitting element initialization gate signal GB may be output to the pixel. For example, according to the characteristics of the display panel 100 and the characteristics of the gate driver 300, applying a single pulse of the data write gate signal GW, a single pulse of the data initialization gate signal GI, and a single pulse of the organic light emitting element initialization gate signal GB may be sufficient to operate data writing, data initialization, and organic light emitting element initialization.

[0159] The gate driver 300 outputs gate signals having different application timings for frames to the display panel 100 according to a difference MEANDF between a grayscale value of a current frame image and a grayscale value of a previous frame image.

[0160] For example, when the difference MEANDF between the grayscale values ​​of the current frame image and the previous frame image is large (eg, greater than a first grayscale difference threshold), the application timing of the gate signals GW, GI, and GB may be late in the inactive period EM OFF of the emission signal EM.

[0161] like Fig.10 As shown in , when the contrast change between the current frame image and the previous frame image is large (for example, greater than the first grayscale difference threshold), the data bias (DATA BIAS) state of the first pixel switch element T1 may be maintained for a relatively long time. If the data bias (DATA BIAS) state of the first pixel switch element T1 is maintained for a long time, the hysteresis compensation degree of the first pixel switch element T1 may be small.

[0162] When the hysteresis of the switching element is fully compensated, some of the pixels in the low grayscale image may not be turned on, thereby generating display defects due to the turned-off pixels. When the contrast change between the current frame image and the previous frame image is large, display defects caused by residual images may not be generated. Therefore, when the contrast change between the current frame image and the previous frame image is large, the hysteresis compensation degree of the first pixel switching element T1 can be controlled to be small (e.g., low), thereby reducing or preventing display defects caused by turned-off pixels in low grayscale value images.

[0163] For example, when the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is small, the application timing of the gate signals GW, GI, and GB may be early in the inactive period EM OFF of the emission signal EM.

[0164] like Fig.11 As shown in , when the contrast change between the current frame image and the previous frame image is small (for example, less than the second grayscale difference threshold), the threshold voltage bias VTH BIAS state of the first pixel switch element T1 can be maintained for a relatively long time. If the threshold voltage bias VTH BIAS state of the first pixel switch element T1 is maintained for a long time, the hysteresis compensation degree of the first pixel switch element T1 may be large.

[0165] When the hysteresis of the switching element is not sufficiently compensated, an afterimage may be generated due to the shift of the current-voltage curve. When the contrast change between the current frame image and the previous frame image is small, a display defect caused by the afterimage may be generated. Therefore, when the contrast change between the current frame image and the previous frame image is small, the hysteresis compensation degree of the first pixel switching element T1 can be controlled to be large, thereby reducing or preventing display defects caused by the afterimage.

[0166] According to the present exemplary embodiment, display defects caused by a turned-off switching element and display defects caused by an afterimage caused by a hysteresis of the switching element can be effectively reduced or prevented. Therefore, the display quality of the display panel 100 can be enhanced.

[0167] Fig.12 is a circuit diagram illustrating a pixel of a display device according to an exemplary embodiment of the inventive concept.

[0168] Except for the structure of the pixel, the display device and the method of driving the display panel according to the present exemplary embodiment are similar to those of the reference Figures 1 to 9 The display device and the method of driving the display panel of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 9 The same or similar parts as those described in the previous exemplary embodiments are described herein, and any repeated explanation regarding the above elements may be omitted.

[0169] Reference Figure 1 , Figures 3 to 9 and Fig.12 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0170] The display panel 100 includes a plurality of pixels, and each pixel includes an organic light emitting element OLED.

[0171] The pixel receives the data writing gate signal GW, the data initialization gate signal GI, the organic light emitting element initialization gate signal GB, the data voltage VDATA and the emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0172] At least one of the pixels may include a first pixel switching element T1, a second pixel switching element T2, a first third (3-1) pixel switching element T3-1, a second third (3-2) pixel switching element T3-2, a first fourth (4-1) pixel switching element T4-1, a second fourth (4-2) pixel switching element T4-2, a fifth pixel switching element T5, a sixth pixel switching element T6 and a seventh pixel switching element T7, a storage capacitor CST and an organic light emitting element OLED.

[0173] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0174] The second pixel switching element T2 includes a control electrode to which the data write gate signal GW is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0175] The first third (3-1) pixel switching element T3-1 includes a control electrode to which the data write gate signal GW is applied, an input electrode connected to the first node N1, and an output electrode connected to an input electrode of the second third (3-2) pixel switching element T3-2.

[0176] The second third (3-2) pixel switching element T3-2 includes a control electrode to which the data write gate signal GW is applied, an input electrode connected to the output electrode of the first third (3-1) pixel switching element T3-1, and an output electrode connected to the third node N3.

[0177] The first fourth (4-1) pixel switching element T4-1 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode connected to an output electrode of the second fourth (4-2) pixel switching element T4-2, and an output electrode connected to the first node N1.

[0178] The second fourth (4-2) pixel switching element T4-2 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the input electrode of the first fourth (4-1) pixel switching element T4-1.

[0179] The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0180] The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0181] The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0182] The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0183] The organic light emitting element OLED includes an anode electrode connected to the output electrode of the sixth pixel switching element T6 and a cathode electrode to which the low power voltage ELVSS is applied.

[0184] The gate driver 300 outputs gate signals having different application timings for frames to the display panel 100 according to a difference MEANDF between a grayscale value of a current frame image and a grayscale value of a previous frame image.

[0185] For example, when the difference MEANDF between the grayscale value of the current frame image and the grayscale value of the previous frame image is large, the application timing of the gate signals GW, GI, and GB may be late in the inactive period EM OFF of the emission signal EM.

[0186] According to the present exemplary embodiment, display defects due to a turned-off switching element and display defects due to an afterimage caused by a hysteresis of the switching element can be effectively reduced or prevented. Therefore, the display quality of the display panel 100 can be enhanced.

[0187] According to the inventive concept as explained above, the application timing of the gate signal is applied according to the input image, thereby being able to enhance the display quality of the organic light emitting display panel.

[0188] The foregoing is an illustration of the inventive concept and should not be construed as limiting it. Although some exemplary embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and aspects of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims and their equivalents. Therefore, it should be understood that the foregoing is an illustration of the inventive concept and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and the equivalents of the claims should be included therein.

Claims

1. A display device, comprising: a display panel configured to display an image; a gate driver configured to output gate signals having the same or different application timings for frames to the display panel according to a difference between a grayscale value of a current frame image and a grayscale value of a previous frame image; a data driver configured to output a data voltage to the display panel; as well as an emission driver configured to output an emission signal to the display panel, and Wherein, when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is large, the application timing of the gate signal is in the late duration of the inactive period of the emission signal.

2. The display device according to claim 1, wherein: When the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, regardless of the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image, the gate driver is configured to output the gate signal having the same application timing for frames, and Wherein, when the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate driver is configured to output the gate signal with different application timing for the frame according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

3. The display device according to claim 1, wherein: The grayscale value of the current frame image corresponds to the entire area of ​​the display panel, and The grayscale value of the previous frame image corresponds to the entire area of ​​the display panel.

4. The display device according to claim 1, wherein: The grayscale value of the current frame image corresponds to the central part of the display panel, and The grayscale value of the previous frame image corresponds to the central part of the display panel.

5. The display device according to claim 1, wherein: The gate driver is configured to output a data writing gate signal, a data initialization gate signal, and an organic light emitting element initialization gate signal to the display panel during an inactive period of the emission signal.

6. The display device according to claim 5, wherein: The gate driver is configured to output the data write gate signal to the pixel of the display panel after outputting the data initialization gate signal to the pixel of the display panel.

7. The display device according to claim 6, wherein: The gate driver is configured to simultaneously output the data writing gate signal and the organic light emitting element initialization gate signal to the pixels of the display panel.

8. The display device according to claim 5, wherein: The gate driver is configured to output multiple pulses of the data write gate signal, multiple pulses of the data initialization gate signal, and multiple pulses of the organic light emitting element initialization gate signal to pixels of the display panel in a single inactive period of the emission signal.

9. The display device according to claim 5, wherein: The gate driver is configured to output a single pulse of the data write gate signal, a single pulse of the data initialization gate signal, and a single pulse of the organic light emitting element initialization gate signal to pixels of the display panel in a single inactive period of the emission signal.

10. The display device according to claim 1, further comprising: a driving controller configured to adjust a driving timing of the gate driver, Wherein, the drive controller comprises: an image analyzer configured to analyze input image data; a contrast difference calculator configured to determine the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image; and A timing determiner is configured to generate a gate timing control signal for determining the application timing of the gate signal according to a difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

11. The display device according to claim 10, wherein: The timing determiner is configured to determine the gate timing control signal to be a first value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is equal to or less than a first threshold value, wherein the timing determiner is configured to linearly determine the gate timing control signal between the first value and a second value greater than the first value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the first threshold and equal to or less than a second threshold, and The timing determiner is configured to determine the gate timing control signal to be the second value when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is greater than the second threshold.

12. The display device according to claim 1, wherein: The display panel includes a plurality of pixels. wherein at least one of the pixels comprises an organic light emitting element, and Wherein, at least one of the pixels is configured to receive a data writing gate signal, a data initialization gate signal, an organic light emitting element initialization gate signal, the data voltage and the emission signal to enable the organic light emitting element to emit to display the image.

13. The display device according to claim 12, wherein: At least one of the pixels comprises: a first pixel switching element including a control electrode connected to the first node, an input electrode connected to the second node, and an output electrode connected to a third node; a second pixel switching element, the second pixel switching element comprising a control electrode to which the data write gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a third pixel switching element, the third pixel switching element comprising a control electrode to which the data writing gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element, the fourth pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode to which the first power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element, the sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the organic light emitting element; a seventh pixel switching element, the seventh pixel switching element comprising a control electrode to which an initialization gate signal of the organic light emitting element is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; a storage capacitor including a first electrode to which the first power voltage is applied and a second electrode connected to the first node; and The organic light emitting element includes the anode electrode and a cathode electrode to which a second power voltage is applied.

14. The display device according to claim 12, wherein: At least one of the pixels comprises: a first pixel switching element including a control electrode connected to the first node, an input electrode connected to the second node, and an output electrode connected to a third node; a second pixel switching element, the second pixel switching element comprising a control electrode to which the data write gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a first third pixel switch element, the first third pixel switch element comprising a control electrode to which a data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to an input electrode of a second third pixel switch element; the second third pixel switching element, the second third pixel switching element comprising a control electrode to which the data write gate signal is applied, an input electrode connected to the output electrode of the first third pixel switching element, and an output electrode connected to the third node; a first fourth pixel switching element, the first fourth pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode connected to the output electrode of the second fourth pixel switching element, and an output electrode connected to the first node; the second fourth pixel switching element, the second fourth pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the input electrode of the first fourth pixel switching element; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode to which the first power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element, the sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the organic light emitting element; a seventh pixel switching element, the seventh pixel switching element comprising a control electrode to which an initialization gate signal of the organic light emitting element is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; a storage capacitor including a first electrode to which the first power voltage is applied and a second electrode connected to the first node; and The organic light emitting element includes the anode electrode and a cathode electrode to which a second power voltage is applied.

15. A method for driving a display panel, the method comprising: outputting gate signals having the same or different application timings for frames to the display panel according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image; outputting a data voltage to the display panel; as well as outputting the emission signal to the display panel, and Wherein, when the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image is large, the application timing of the gate signal is in the late duration of the inactive period of the emission signal.

16. The method of claim 15, wherein: When the grayscale value of the current frame image is equal to or less than the grayscale value of the previous frame image, regardless of the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image, the gate signal having the same application timing for frames may be output to the display panel, and Among them, when the grayscale value of the current frame image is greater than the grayscale value of the previous frame image, the gate signal with different application timing for the frame will be output to the display panel according to the difference between the grayscale value of the current frame image and the grayscale value of the previous frame image.

17. The method of claim 15, wherein: The grayscale value of the current frame image corresponds to the entire area of ​​the display panel, and The grayscale value of the previous frame image corresponds to the entire area of ​​the display panel.

18. The method of claim 15, wherein: The grayscale value of the current frame image corresponds to the central part of the display panel, and The grayscale value of the previous frame image corresponds to the central part of the display panel.

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