Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a substrate having cell regions and power regions alternately arranged along a second direction. A gate structure extends along the second direction. The gate structures are spaced apart from each other along a first direction perpendicular to the second direction. A bonding layer is arranged on both sides of each gate structure. The bonding layer is arranged along the second direction so that each bonding layer has a flat portion close to the power region. A cutting pattern is arranged in the power region. The cutting pattern extends along the first direction so that each gate structure and each bonding layer in adjacent cell regions are separated from each other by the cutting pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0090472 filed on August 2, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] A logic device is a semiconductor device designed to perform a specific task. A logic device can be designed by combining multiple off-the-shelf standard cells, each of which performs a limited number of logic functions.

[0005] Each standard cell is an integrated circuit (IC) module that can be optimized for specific requirements and functions. Standard cells can include basic cells (e.g., Boolean logic functions (e.g., AND, OR, NOR, inverter), composite cells with multiple basic cells (e.g., OAI cells (OR / AND / inverter) and AOI cells (AND / OR / inverter)), and storage elements (e.g., master-slave flip-flops and latches). Logic devices are composed of basic cells, composite cells, and storage elements that are preferably selected to perform specific functions.

[0006] Over time, the size of standard cells has been reduced, and the integration of standard cells has been increased. Therefore, the density of logic devices has increased. For example, fin FETs and buried transistor structures have been applied to standard cells to minimize short channel effects and provide various other process improvements (e.g., process improvements to line edge roughness (LER)). LER can prevent electrical shorts between adjacent patterns despite a reduction in critical dimension (CD).

[0007] For example, some circuit lines of recent standard cells tend to extend from the cell area to the power area so that an integrated circuit is arranged in a part of the power area and the cell area, and the density of circuit lines increases within a standard cell of the same size.

[0008] However, since adjacent cells are electrically separated by the power area, the reduction in power area tends to cause electrical shorts between adjacent cells. Therefore, the reduced size of the standard cell may be more susceptible to electrical shorts between adjacent cells. Summary of the invention

[0009] A semiconductor device comprises: a substrate having a plurality of unit regions and a plurality of power regions, so that each of the plurality of unit regions is alternately arranged with each of the plurality of power regions along a second direction. A plurality of gate structures extend along the second direction. Each of the plurality of gate structures is spaced apart from each other along a first direction substantially perpendicular to the second direction. A plurality of bonding layers are arranged on both sides of each of the plurality of gate structures, and are arranged along the second direction so that each of the plurality of bonding layers has a structure close to a flat portion of the power region. A plurality of cutting patterns are arranged in the plurality of power regions, and a plurality of cutting patterns extend along the first direction so that each of the plurality of gate structures and each of the plurality of bonding layers in adjacent unit regions of the plurality of unit regions are separated from each other by the cutting patterns.

[0010] A method for manufacturing a semiconductor device includes: forming a plurality of active fins in at least one pair of cell regions extending along a first direction. The pair of cell regions are separated from each other by a power region. A plurality of dummy gate structures and a plurality of gap filling patterns are formed into a linear shape extending along a second direction substantially perpendicular to the first direction, so that each of the plurality of dummy gate structures and each of the plurality of gap filling patterns alternately cover the plurality of active fins relative to each other along the first direction. A linear cutting pattern extending along the first direction is formed in the power region, so that the plurality of dummy gate structures and the plurality of gap filling patterns are separated from each other in units of cell regions in the at least one pair of cell regions. A bonding layer is formed in a gap space between adjacent dummy gate structures of the plurality of dummy gate structures, so that the bonding layer contacts the plurality of active fins in the at least one pair of cell regions and has a flat portion in contact with the cutting pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure and its many attendant aspects may be obtained as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a plan view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] FIG. 2A to FIG. 2E are respectively along Figure 1 Cross-sectional views of the semiconductor device depicted in FIG. 1 taken along lines AA′, BB′, CC′, DD′, and EE′;

[0014] Figure 3is a plan view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] 4A to 4F are respectively along Figure 3 Cross-sectional views of the semiconductor device depicted in FIG. 1 taken along lines AA′, BB′, CC′, DD′, EE′, and FF′;

[0016] Figures 5 to 32E are diagrams illustrating process steps of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0017] Figures 33 to 40F are diagrams illustrating process steps of a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0018] Reference is now made to exemplary embodiments illustrated in the drawings, wherein like reference numerals may refer to like components throughout the specification and drawings.

[0019] Figure 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 2A to FIG. 2E are respectively along Figure 1 1 and 2 are cross-sectional views of the semiconductor device taken along lines AA′, BB′, CC′, DD′, and EE′.

[0020] refer to Figures 1 to 2E According to an exemplary embodiment of the inventive concept, a semiconductor device may include a substrate 100 having a plurality of cell regions C and a plurality of power regions PA, such that the cell regions C and the power regions PA may be alternately arranged along a second direction II. A plurality of gate structures 500 extend along the second direction II and are spaced apart from each other along a first direction I substantially perpendicular to the second direction II. A plurality of bonding layers 300 are arranged on both sides of the gate structure 500, and are arranged along the second direction II such that each of the plurality of bonding layers 300 may have a flat portion A around the power region PA. A plurality of cutting patterns CP are arranged in the power region PA, and the cutting patterns CP extend along the first direction I, such that the gate structures 500 and the bonding layers 300 in adjacent cell regions may be separated from each other by the cutting patterns CP.

[0021] For example, the substrate 100 may include a bulk substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, a gallium phosphorus (Ga-P) substrate, a gallium arsenide (Ga-As) substrate, a silicon antimony (Si-Sb) substrate. Alternatively, the substrate 100 may include a multilayer substrate, such as a semiconductor on insulator (SOI) substrate, a germanium on insulator (GOI) substrate.

[0022] The substrate 100 may include a plurality of cell regions C in which a plurality of cell transistors may be arranged and a power region PA in which a power rail 700 may be arranged. Hereinafter, adjacent cell regions around the power region PA may be referred to as a first cell region C1 and a second cell region C2, and the first cell region C1 and the second cell region C2 may be separated from each other by the power region PA.

[0023] According to an exemplary embodiment, each of the cell regions C may be divided into a PMOS region P and an NMOS region N, which may be separated from each other by a separation region PNS. Therefore, a plurality of PMOS transistors and NMOS transistors may be arranged in the cell region C, and the PMOS transistors and the NMOS transistors may be separated from each other by the separation region PNS, so that a CMOS transistor may be arranged in the cell region C. Hereinafter, the separation region PNS in the first cell region C1 may be referred to as a first separation region PNS1, and the separation region PNS in the second cell region C2 may be referred to as a second separation region PNS2.

[0024] A plurality of active fins 110 may be arranged in the cell region C. The active fins 110 may extend along a first direction I, and adjacent active fins 110 among the plurality of active fins 110 may be spaced apart from each other along a second direction II. The active fins 110 may protrude from the device isolation layer 120, and thus the active fins 110 may be divided into a lower fin 110a and an upper fin 110b, the lower fin 110a may be at least partially surrounded by the device isolation layer 120, and the upper fin 110b may extend from the device isolation layer 120. For example, the field region of the substrate 100 may be at least partially covered by the device isolation layer 210, and the active region of the substrate 100 may be provided as the active fin 110 protruding from the device isolation layer 120.

[0025] The gate structure 500 may be arranged on each active fin 110, and a plurality of gate structures 500 along the second direction II may be formed as a gate line GL. The plurality of gate lines GL may be spaced apart at the same gap distance along the first direction I. Side surfaces of the gate lines GL may be at least partially covered by the gate spacers 240, and the gate spacers 240 may be shaped as lines along the second direction II.

[0026] For example, the gate line GL may extend discontinuously along the second direction II through the power area PA. For example, the gate line GL may extend in the first unit area C1 along the second direction II and may be disconnected in the power area PA or otherwise not arranged in the power area PA. The gate line GL may also extend in the second unit area C2 along the second direction II.

[0027] Therefore, the gate lines GL may be exclusively arranged in the cell region C, and the gate lines GL in the first cell region C1 may be symmetrical with the gate lines GL in the second cell region C2 with respect to the gate cutting pattern CP. The gate structure 500 and the active fins 110 may be used solely as gate electrodes of cell transistors in the cell region C.

[0028] The cutting pattern CP may include an insulating material such as silicon nitride (SiN), and thus the gate structure 500 in the first cell region C1 may be electrically separated from the gate structure 500 in the second cell region C2 by the cutting pattern CP. For example, the gate structure 500 in the first cell region C1 may be separated from the gate structure 500 in the second cell region C2 by the power region PA.

[0029] In an exemplary embodiment, the gate structure 500 may include a gate insulation pattern 510, a work function control pattern 520, and a gate electrode 530, which may be sequentially stacked on the active fin 110 and the device isolation layer 120, and the gate structure 500 may be defined by the gate spacer 240. The gate trench defined by the work function control pattern 520 may extend along the second direction II, and the gate electrode 530 may fill the gate trench. The gate signal may be transmitted to the semiconductor device via the gate structure 500.

[0030] The bonding layer 300 may be arranged on both sides of the gate structure 500. The space between the adjacent gate spacers 240 may be provided as an inter-space trench IST in the cell region C, and the bonding layer 300 may be grown on the active fins 110 in the inter-space trench IST. For example, when the adjacent active fins 110 may be closely arranged in the inter-space trench IST, the bonding layers 300 on the adjacent active fins 110 may be connected to each other, extending in the second direction II in the cell region C like a line.

[0031] The bonding layer 300 may be grown on the active fin 110 around the gate structure 500 by a selective epitaxial growth (SEG) process, so that the epitaxial pattern may be used as the bonding layer 300. Therefore, when the adjacent active fins 110 may be closely arranged in the inter-spacer trench IST, the epitaxial pattern may grow along the second direction II and be connected to each other. Therefore, the bonding layer 300 may be selectively connected to each other and may be provided in the cell region C as a discontinuous line.

[0032] For example, the bonding layer 300 in the first unit area C1 can also be separated from the bonding layer 300 in the second unit area C2 by the power area PA, so that the bonding layer 300 in the first unit area C1 and the bonding layer 300 in the second unit area C2 can also be separated from each other by the cutting pattern CP in the power area PA.

[0033] Therefore, due to the cutting pattern CP in the power area PA, the bonding layer 300 in the first cell area C1 and the bonding layer 300 in the second cell area C2 do not contact each other under the SEG process. For example, an electrical short circuit of the bonding layer 300 between the first cell area C1 and the second cell area C2 can be substantially prevented by the cutting pattern CP in the power area PA.

[0034] The bonding layer 300 around the power region PA can grow horizontally and vertically toward the power region PA on the active fin 110, so the bonding layer 300 can also grow along the side surface of the cutting pattern CP in the third direction III. For example, the bonding layer 300 can be prohibited from growing toward the power region PA along the second direction II by the cutting pattern CP.

[0035] Therefore, the bonding layer 300 around the power area PA may grow along the side surface of the cutting pattern CP in the third direction III, and its size may be larger than the bonding layer 300 away from the power area PA. For example, the bonding layer 300 around the power area PA may have a flat portion A in contact with the cutting pattern CP, and its size may be larger than the size of the bonding layer 300 away from the cutting pattern CP along the same inter-spacer trench IST.

[0036] A larger bonding layer 300 can reduce the contact resistance of the contact structure 600, and the size of the bonding layer 300 can be changed according to the contact resistance. For example, the process conditions of SEG can be controlled so that the size of the flat portion A of the bonding layer 300 can be sufficiently adjusted to achieve the desired contact resistance.

[0037] The bonding layer 300 away from the cutting pattern CP may not have a growth limiting factor such as the cutting pattern CP, and thus the bonding layer 300 away from the cutting pattern CP may grow horizontally and vertically without any substantial restriction. Therefore, when adjacent active fins 110 may be sufficiently separated from each other in the second direction or the active fins 110 may be arranged around the separation region PNS, the bonding layer 300 may have a point portion B due to the non-restrictive isotropic epitaxial growth behavior.

[0038] For example, when adjacent active fins 110 may be closely arranged in the inter-spacer trench IST, adjacent bonding layers 300 may be bonded to each other in the second direction II due to horizontal growth of the SEC process. Therefore, the bonding layer 300 may be shaped as a virtual line extending along the second direction II.

[0039] When a growth limiting factor is not provided in the SEG process, the bonding layer 300 may not grow vertically but may be formed to have the tip B. Therefore, the bonding layer 300 having the tip B has a smaller size than the bonding layer having the flat portion A. Therefore, the size of the bonding layer 300 increases as it is closer to the cutting pattern CP, and the size of the bonding layer 300 decreases as it is closer to the separation region PNS.

[0040] The inter-spacer trench IST may be filled with a conductive contact structure 600 in contact with the bonding layer 300, so that the contact structure 600 may be formed as a line extending along the second direction II. In addition, the linear contact structure 600 may not be located in the separation region PNS, so that the contact structure 600 may be disconnected in the separation region PNS and may be discontinuous in the cell region C.

[0041] The gate structure 500 may be at least partially covered by the gate cap pattern 550 and the first interlayer dielectric pattern ILD1, and the bonding layer 300 around the gate structure 500 in the gap trench IST may be at least partially covered by the contact structure 600 extending along the second direction II. For example, the upper surface of the contact structure 600 may be substantially coplanar with the upper surface of the gate structure 500 or the gate line GL.

[0042] Although the gate line GL may be continuous in the cell region C, the contact structure 600 may be separated into an NMOS contact 612 and a PMOS contact 614 by the insulating pattern 400 filling the separation region PNS.

[0043] For example, the contact structure 600 may include a cell contact 610 in contact with the bonding layer 300 in the cell region C and a power contact 620 in contact with the flat portion surface of the bonding layer 300 in the power region PA. The cell contact 610 and the power contact 620 may be provided in one body. The cell contact 610 may include an NMOS contact and a PMOS contact, and may be provided as a contact plug in contact with a single bonding layer 300, and may be provided as a contact line in contact with a plurality of bonding layers 300 in the second direction.

[0044] The power contact 620 can make surface contact with the flat portion A of the bonding layer 300, and can be arranged in the peripheral portion of the power area PA in a configuration such that the power contact 620 can make surface contact with the side surface of the cutting pattern CP. The peripheral portion of the cutting pattern CP can be removed from the substrate 100, and the second contact hole CTH2 can be set to a configuration such that the flat portion A of the bonding layer 300 and the device isolation layer 120 can be exposed through the second contact hole CTH2. The power contact 620 can be arranged in the second contact hole CTH2 in a configuration such that the power contact 620 can contact the device isolation layer 120 and the upper surface of the power contact 620 can be coplanar with the upper surface of the cutting pattern CP. Since the power contact 620 can make surface contact with the flat portion A of the bonding layer 300, the contact resistance between the bonding layer 300 and the contact structure 600 can be substantially reduced in the semiconductor device.

[0045] Therefore, the cutting pattern CP may include a gate cutting pattern CP1 that cuts the gate line GL in the power area PA and has a first width w1, and a bonding cutting pattern CP2 that cuts the bonding layer 300 in the power area PA and has a second width w2 that is smaller than the first width w1. The gate cutting pattern CP1 and the bonding cutting pattern CP2 may be alternately arranged along the first direction I in the power area PA.

[0046] The power contact 620 in the first unit area C1 may be symmetrical with the power contact 620 in the second unit area C2 with respect to the joint cutting pattern CP2, so that the power contact 620 in the first unit area C1 may be substantially prevented from being connected to the power contact 620 in the second unit area C2 through the joint cutting pattern CP2. For example, an electrical short circuit of the joint layer 300 between the first unit area C1 and the second unit area C2 may be substantially prevented by the cutting pattern CP in the power area PA.

[0047] The cell contact 610 may be separated into an NMOS contact 612 and a PMOS contact 614 by the insulating pattern 400 in the cell region C. Therefore, the NMOS contact 612 and the PMOS contact 614 may also be electrically separated from each other by the insulating pattern 400 in the cell region C.

[0048] The power contact 620 may be connected to a power rail 700 that at least partially covers the power area PA. Since the power rail 700 may contact the upper surface of the cutting pattern CP, the upper surface of the power contact 620 may be coplanar with the upper surface of the cutting pattern CP. The power rail 700 may also contact the power contact 620 at the peripheral portion of the power area PA.

[0049] The power rail 700 may include a power plug 710 contacting the power contact 620 and extending upward. Additionally, the power rail 700 may include a power line 720 contacting the power plug 710 and extending along the first direction I on the first interlayer dielectric pattern ILD1. In the present exemplary embodiment, the power plug 710 and the power line 720 may be provided in one body.

[0050] The power plug 710 may be symmetrically arranged on both sides of the bonding cut pattern CP2 in a configuration such that the lower surface of the power plug 710 may contact the power contact 620 and the upper surface of the power plug 710 may be coplanar with the upper surface of the first interlayer dielectric pattern ILD1. The power line 720 may extend along the first direction I in the power area PA in a configuration such that the lower surface of the power line 720 may alternately contact the power plug 710 and the first interlayer dielectric pattern ILD1.

[0051] When a power signal may be applied to the power rail 700 from an external power source, the power signal may be transmitted to the bonding layer 300 via the power contact 620. For example, the power signal may be transmitted to the bonding layer 300 of the first unit region C1 and the bonding layer 300 of the second unit region C2 at the same time. Since the power contact 620 in the first unit region C1 may be insulated from the power contact 620 in the second unit region C2 by the bonding cut pattern CP2, the power signal may be transmitted separately to the bonding layer 300 in both the first unit region C1 and the second unit region C2.

[0052] In addition, since the cell contact 610 may be separated into the NMOS contact 612 and the PMOS contact 614 by the insulating pattern 400 in the cell region C, the power signal may be transmitted to one of the NMOS contact 612 and the PMOS contact 614. Therefore, the NMOS contact 612 and the PMOS contact 614 in the same cell region C may not simultaneously receive the power signal from the same power rail 700. Some of the power rails 700 may transmit the power signal to the NMOS contact 612, and the remaining power rails 700 may transmit the power signal to the PMOS contact 614.

[0053] In the present exemplary embodiment, the PMOS region P may be arranged around the power rail 700, and the NMOS region N may be arranged to be separated from the power rail 700 and disposed close to another power rail. Therefore, the power signal may be transmitted to the PMOS contact 614 through the power rail 700, and transmitted to the NMOS contact 612 through another power rail spaced apart from the power rail 700 in the second direction II.

[0054] The plurality of power rails 700 may extend in the first direction I and may be spaced apart from each other in the second direction II. The second interlayer dielectric pattern ILD2 may fill a gap space between adjacent power rails 700, and thus the adjacent power rails 700 may be insulated from each other by the second interlayer dielectric pattern ILD2.

[0055] According to the present exemplary embodiment of the semiconductor device, the gate line GL and the bonding layer 300 extending in the second direction II may be cut by the cutting pattern CP that may be arranged in the power area PA, and thus the gate line GL and the bonding layer 300 may be separated in units of the cell area C. Therefore, the gate line GL and the bonding layer 300 in the first cell area C1 may be substantially prevented from being connected to the gate line GL and the bonding layer 300 in the second cell area C2. Therefore, an electrical short circuit of the gate line GL and the bonding layer 300 between the first cell area C1 and the second cell area C2 may be substantially prevented.

[0056] In addition, the power contacts 620 in contact with the bonding layer 300 can be symmetrically arranged on both sides of the bonding cut pattern CP2 relative to the bonding cut pattern CP2. Therefore, the power signal can be transmitted to the first unit area C1 and the second unit area C2 separately and independently. For example, the power signal transmitted to the PMOS contact 614 in the first unit area C1 can be prevented from leaking to the PMOS contact 614 in the second unit area C2, and the power signal transmitted to the PMOS contact 614 in the second unit area C2 can be prevented from leaking to the PMOS contact 614 in the first unit area C1.

[0057] Furthermore, since the power contact 620 may make surface contact with the bonding layer 300 , the contact resistance between the bonding layer 300 and the contact structure 600 may be substantially reduced in the semiconductor device.

[0058] Therefore, when the power area PA can be reduced according to the recent size reduction of semiconductor devices, the electrical short circuit of the gate line GL and the bonding layer 300 between adjacent cell areas C that can be separated by the power area PA can be substantially prevented or minimized. For example, the electrical short circuit of the transistors between the adjacent cell areas C separated by the power area PA can be substantially prevented by the cutting pattern CA in the power area PA.

[0059] Although a cutting pattern for preventing electrical short circuits of adjacent transistors in different cell regions C may be arranged in the power region PA, electrical short circuits of adjacent transistors may also occur in the same cell region C via the separation region PNS. Therefore, the cutting pattern may also be provided in the separation region PNS as well as the power region PA.

[0060] Figure 3is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. 4A to 4F are respectively along Figure 3 1 and 2 are cross-sectional views of the semiconductor device taken along lines AA′, BB′, CC′, DD′, EE′, and FF′. Figure 3 The semiconductor devices in Figure 1 The semiconductor device shown in FIG. 1 has substantially the same structure except that a separation pattern SP may also be arranged in the separation region PNS in each cell region C. Figures 3 to 4F middle, Figures 1 to 2E Like reference numerals in the accompanying drawings may be used to denote like elements, and to the extent that further description of various elements is omitted, it can be assumed that these elements are at least similar to corresponding elements already described.

[0061] refer to Figures 3 to 4F , the separation pattern SP may be arranged in the separation region PNS so that the gate line GL and the bonding layer 300 in the PMOS region P may not be connected to the gate line GL and the bonding layer 300 in the NMOS region N.

[0062] Before forming the gate structure 500, the insulating pattern 400 may be removed from the substrate 100, and a separation region PNS may be formed. Fig.33 The separation hole SO in the separation region PNS. The separation hole may be formed in the entire separation region PNS or in a portion of the separation region PNS according to the layout of the semiconductor device.

[0063] In the present exemplary embodiment, the separation hole SO may extend through the gate spacer 240 along the first direction I, and may include a gate trench and an inter-spacer trench IST along the first direction I. Therefore, the separation pattern SP may extend along the first direction I in the cell region C, and at least one gate line GL and at least one bonding layer 300 may be separated by the separation pattern SP in the cell region C.

[0064] The separation pattern SP may have substantially the same insulating material as the cutting pattern CP. For example, the separation pattern SP may include silicon nitride (SiN), silicon oxynitride (SiON), and / or silicon oxycarbon nitride (SiOCN).

[0065] Therefore, the gate structure 500 in the PMOS region P and the gate structure 500 in the NMOS region N may be electrically separated by the separation pattern SP in the cell region C. In the same manner, the bonding layer 300 in the PMOS region P and the bonding layer 300 in the NMOS region N may also be electrically separated by the separation pattern SP in the cell region C. Therefore, although the size of the semiconductor device may be reduced, the PMOS transistor and the NMOS transistor may be sufficiently separated from each other by the separation pattern SP in the same cell region C. For example, the semiconductor device may be formed as a stable and reliable CMOS device.

[0066] Figures 5 to 32E 1 is a diagram showing process steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 5 to 32E In the drawings, the odd-numbered figures are plan views showing each process step of the manufacturing method, and the even-numbered figures are cross-sectional views corresponding to the odd-numbered figures. Each figure designated by a suffix "A" in the accompanying drawing number is taken along Figure 1 , and each of the figures designated by a suffix "B" in the figure numbers is a cross-sectional view taken along the line AA' of the semiconductor device shown in FIG. Figure 1 ' is a cross-sectional view taken along the line BB' of the semiconductor device shown in FIG. In addition, each figure designated by a suffix "C" in the figure number is a cross-sectional view taken along the line BB' of the semiconductor device shown in FIG. Figure 1 , and each of the figures designated by a subscript "D" in the figure numbers is a cross-sectional view taken along the line CC' of the semiconductor device shown in FIG. Figure 1 2 is a cross-sectional view taken along line DD' of the semiconductor device shown in FIG. Each of the figures designated by a suffix "E" in the accompanying drawings is a cross-sectional view taken along line DD' of the semiconductor device shown in FIG. Figure 1 0 is a cross-sectional view taken along line EE′ of the semiconductor device shown in .

[0067] refer to Figure 5 and FIG. 6A to FIG. 6B , an upper portion of the substrate 100 may be partially removed, and a plurality of recesses R may be formed on the substrate 100 so that a plurality of active fins 110 may be arranged on the substrate 100. Adjacent active fins 110 may be spaced apart from each other by the recesses R.

[0068] For example, the substrate 100 may include a bulk substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, a gallium phosphorus (Ga-P) substrate, a gallium arsenide (Ga-As) substrate, a silicon antimony (Si-Sb) substrate. Alternatively, the substrate 100 may include a multilayer substrate, such as a semiconductor on insulator (SOI) substrate, a germanium on insulator (GOI) substrate.

[0069] A mask pattern for defining an active region of the substrate 100 may be formed on the substrate 100, and the substrate 100 may be subjected to a dry etching process using the mask pattern as an etching mask, so that the upper portion of the substrate 100 may be partially removed, thereby forming a recess R on the substrate 100. The etched portion of the substrate 100 may serve as a field region F of the substrate 100, and the unetched portion of the substrate 100 may protrude upward from the bottom of the recess R like the fin 110 and serve as an active region A of the substrate 100. Therefore, the substrate 100 may have a field region F corresponding to the recess R and an active region A corresponding to the fin 110. The active region A shaped as a fin is referred to as an active fin 110. In the present exemplary embodiment, the active fin 110 may be formed as a line extending in the first direction I.

[0070] The substrate 100 may include a plurality of cell regions C and a power region PA, in which a plurality of cell transistors may be arranged, and in which a power rail 700 (e.g., a metal line) may be arranged. The cell regions C and the power region PA may be alternately arranged along the second direction II on the substrate 100. For example, the contact structure 600 may be formed in the power region PA, and a power signal may be simultaneously transmitted to an adjacent cell region close to the power region PA.

[0071] The first unit area C1 may be separated from the second unit area C2 by the power area PA, and may be symmetrical with respect to the power area PA and the second unit area C2. The power area PA may include a first power area PA1 for accommodating a contact structure 600 that can transmit a power signal to the first unit area C1 and a second power area PA2 for accommodating a contact structure 600 that transmits a power signal to the second unit area C2.

[0072] Each cell region C may include a PMOS region P and an NMOS region N. A PMOS transistor may be formed on the PMOS region P, and an NMOS transistor may be formed on the NMOS region N, so that a CMOS transistor may be formed in each cell region C. For example, since the first cell region C1 and the second cell region C2 may be symmetrical to each other with respect to the power region PA, the PMOS region P and the NMOS region N of the first cell region C1 may be folded onto the PMOS region P and the NMOS region N of the second cell region C2.

[0073] Therefore, the first power signal can be transmitted to both the PMOS transistors in the first cell region C1 and the second cell region C2 at the same time through the power rail 700 in the power region PA between the first cell region C1 and the second cell region C2. Then, the second power signal can be transmitted to both the NMOS transistors in the first cell region C1 and the second cell region C2 through another power rail that can be arranged at the top of the first cell region C1 and the bottom of the second cell region C2.

[0074] For example, the PMOS region P and the NMOS region N in each cell region C may be separated from each other by the separation region PNS. Therefore, the NMOS transistor and the PMOS transistor may be electrically separated from each other by the insulating pattern 400 in the separation region PNS of each cell region C. Therefore, when only a PMOS transistor or only an NMOS transistor is formed in the cell region C, the cell region C may not be provided with the separation region PNS. Hereinafter, for convenience, the separation region PNS in the first cell region C1 may be referred to as the first separation region PNS1, and the separation region PNS in the second cell region C2 may be referred to as the second separation region PNS2.

[0075] The active fin 110 may be formed in a line shape extending in the PMOS region P and the NMOS region N along the first direction. Fig. 6A A single active fin 110 may be formed in each of the PMOS region P and the NMOS region N, but represents a plurality of active fins 110 that may be spaced apart from each other along the second direction II. The configuration and structure of the plurality of active fins may vary according to the layout of the semiconductor device.

[0076] refer to Figure 7 and FIG. 8A to FIG. 8B , a device isolation layer 120 may be formed on the substrate 100 so that both sides of a lower portion of the active fin 110 (referred to as a lower fin 110 a ) may be surrounded by the device isolation layer 120 and an upper portion of the active fin 110 (referred to as an upper fin 110 b ) may protrude from the device isolation layer 120 .

[0077] For example, an insulating layer having a sufficient thickness to fill the recess R may be formed on the substrate 100 , and the insulating layer may be planarized until the top surface of the active fin 110 may be exposed.

[0078] Then, a mask pattern may be formed on the substrate 100 having the insulating layer so that the active fin 110 may be at least partially covered by the mask pattern. Then, the insulating pattern may be further removed by an etching process using the mask pattern as an etching mask until the top surface of the insulating layer may be lower than the top surface of the active fin 110, thereby forming a device isolation layer 120 at the lower portion of the recess R. For example, the device isolation layer 120 may cover the field region F at the lower portion of the recess R, and the upper surface of the device isolation layer 120 may be lower than the top surface of the active fin 110. For example, the device isolation layer 120 may include an insulating material such as silicon oxide (SiO).

[0079] Therefore, the entire surface of the substrate 100 except the active fin 110 may be covered by the device isolation layer 120. The lower fin 110a may be at least partially surrounded by the device isolation layer 120, and the upper fin 110b may be exposed to the surrounding environment.

[0080] Although the present exemplary embodiment discloses that the device isolation layer 120 may be formed by deposition, planarization, and etching processes, the device isolation layer 120 may be formed by other processes. For example, the device isolation layer 120 may be formed by a selective epitaxial growth (SEG) process using the bottom of the recess R as a seed.

[0081] refer to Fig. 9 and FIG. 10A to FIG. 10C , a preliminary dummy gate structure 200 a may be formed on the device isolation layer 120 as a line extending along the second direction II.

[0082] A dummy gate insulating layer may be formed on the device isolation layer 120 along the surface profile of the upper fins 110 b , and a dummy gate electrode layer having a sufficient thickness to fill a gap space between adjacent upper fins 110 b may be formed on the dummy gate insulating layer.

[0083] For example, the dummy gate insulating layer may include an oxide such as silicon oxide, and the dummy gate electrode layer may include polysilicon. A deposition process such as a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be performed to form the dummy gate insulating layer and the dummy gate electrode layer.

[0084] Then, a mask layer may be formed on the dummy gate electrode layer, and the mask layer may be partially removed from the dummy gate electrode layer through a photolithography process, thereby forming a linear mask pattern 230 extending in the second direction II on the dummy gate electrode.

[0085] The dummy gate insulating layer and the dummy gate electrode layer may be partially removed from the device isolation layer 120 by an etching process using the linear mask pattern 230 as an etching mask, thereby forming the dummy gate insulating pattern 210 and the dummy gate electrode pattern 220 as a line pattern extending in the second direction II. The linear dummy gate electrode pattern 220 and the dummy gate insulating pattern 210 may be formed as a preliminary dummy gate structure 200a extending in the second direction II. Adjacent preliminary dummy gate structures 200a may be spaced apart from each other by a gap distance in the first direction I.

[0086] refer to Fig.11 and FIG. 12A to FIG. 12C , gate spacers 240 may be formed on both sides of the preliminary dummy gate structure 200 a , and the dummy gate structure 200 defined by the gate spacers 240 may be formed on the device isolation layer 120 .

[0087] A spacer layer may be formed on the preliminary dummy gate structure 200a and the device isolation layer 120. Then, the spacer layer may be partially removed from the device isolation layer 120 by an anisotropic etching process, thereby forming a gate spacer 240 that at least partially covers the side surfaces of the dummy gate insulating pattern 210 and the dummy gate electrode pattern 220. For example, the gate spacer 240 may include a nitride such as silicon nitride (SiN) and silicon oxycarbonitride (SiOCN).

[0088] When the spacer layer may be subjected to an anisotropic etching process, the mask pattern 230 may also be removed from the dummy gate electrode pattern 220 , whereby the upper surface of the gate spacer 240 may be coplanar with the upper surface of the dummy gate electrode pattern 220 .

[0089] Therefore, the preliminary dummy gate structure 200a may be formed as a linear dummy gate structure 200 having a dummy gate insulation pattern 210 and a dummy gate electrode pattern 220 and extending in the second direction II, and both sides of the dummy gate structure 200 may be at least partially covered by the gate spacer 240. The gate spacer 240 may be shaped as a line extending in the second direction II, and the device isolation layer 120 and the active fin 110 may be alternately exposed in the second direction II through the gap space between adjacent gate spacers 240. Hereinafter, the gap space between adjacent gate spacers 240 is referred to as an inter-spacer trench IST, and thus the inter-spacer trench IST may extend in the second direction II.

[0090] refer to Fig.13 and FIG. 14A to FIG. 14C , a gap-fill pattern 250 may be formed in the inter-spacer trench IST so that the device isolation layer 120 and the active fin 110 may be at least partially covered by the gap-fill pattern 250 .

[0091] For example, a gap filling layer having a sufficient thickness may be formed on the entire surface of the substrate 100 having the dummy gate structure 200 and the gate spacer 240 to fill the inter-spacer trench IST. Therefore, the dummy gate structure 200 and the gate spacer 240 may be at least partially covered by the gap filling layer. The gap filling layer may include an oxide such as silicon oxide (SiO) and may be formed by a deposition process such as a CVD process and an ALD process.

[0092] Then, the gap-filling layer may be planarized by a planarization process such as a chemical mechanical polishing (CMP) process and an etch-back process until the upper surface of the dummy gate structure 200 may be exposed, so that the gap-filling layer may remain exclusively in the inter-spacer trenches IST as the gap-filling pattern 250. The gap-filling pattern 250 may be shaped as a line extending in the second direction II, and an upper surface of the gap-filling pattern 250 may be substantially coplanar with an upper surface of the dummy gate electrode pattern 220.

[0093] refer to Fig.15 and FIG. 16A to FIG. 16D , the dummy gate structure 200 , the gate spacer 240 , and the gap-filling pattern 250 may be removed from the device isolation layer 120 , thereby forming a cutting trench CT, wherein the device isolation layer 120 may be exposed along the first direction I in the power region PA through the cutting trench CT.

[0094] For example, a power cutting mask may be formed on the gap filling pattern 250 and the dummy gate structure 200 so that the cell region C may be at least partially covered by the power cutting mask and the power region PA may be exposed by the power cutting mask. Then, the dummy gate structure 200, the gate spacer 240, and the gap filling pattern 250 may be partially removed from the device isolation layer 120 in the power region PA by an etching process using the power cutting mask as an etching mask.

[0095] In the present exemplary embodiment, the gap filling pattern 250 may include silicon oxide, and the gate spacer 240 may include silicon nitride, and the dummy gate structure 200 may include silicon oxide and polysilicon. Therefore, the process conditions of the etching process may be controlled in consideration of oxide, nitride and polysilicon. The dummy gate structure 200, the gate spacer 240 and the gap filling pattern 250 may be removed by the etching process. For example, the dummy gate structure 200, the gate spacer 240 and the gap filling pattern 250 may be removed along the power region PA, and the device isolation layer 120 may be exposed along the power region PA in the first direction through the groove defined by the dummy gate structure 200, the gate spacer 240 and the gap filling pattern 250 in the cell region C. Therefore, the cutting groove CT may be formed on the substrate 100 in the power region PA along the first direction I.

[0096] The cell region C may be separated into a first cell region C1 and a second cell region C2 by the cutting trench CT.

[0097] Although the present exemplary embodiment discloses that the cutting groove CT may be formed in the entire power area PA, the cutting groove CT may be formed in a portion of the power area PA.

[0098] In this case, the dummy gate structure 200 , the gate spacer 240 , and the gap-filling pattern 250 may remain in the peripheral portion of the power area PA, and the cutting trench CT may be formed exclusively in the central portion of the power area PA.

[0099] refer to Fig.17 and 18A to 18D , the cutting pattern CP may be formed in the cutting trench CT.

[0100] For example, a cutting layer having a sufficient thickness to fill the cutting trench CT may be formed on the dummy gate structure 200, the gate spacer 240, and the gap-filling pattern 250, and then the cutting layer may be planarized until the top surfaces of the dummy gate structure 200, the gate spacer 240, and the gap-filling pattern 250 may be exposed. Therefore, the cutting layer may remain exclusively in the cutting trench CT, thereby forming the cutting pattern CP in the cutting trench CT.

[0101] The cutting layer may include nitride, such as silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN).Therefore, the cutting layer may have sufficient etching selectivity with respect to the gap-filling pattern 250 including oxide and the dummy gate electrode pattern 220 including polysilicon.

[0102] The cut layer may be planarized by one of a CMP process and an etch-back process until top surfaces of the dummy gate structure 200 , the gate spacers 240 , and the gap-filling patterns 250 may be exposed.

[0103] Therefore, the cutting pattern CP may be exposed in the power region PA, and the dummy gate electrode pattern 220, the gate spacer 240, and the gap-filling pattern 250 may be exposed in the first and second cell regions C1 and C2. The dummy gate structure 200, the gate spacer 240, and the gap-filling pattern 250 may be disconnected by the cutting pattern CP and may be separated in units of the cell region C.

[0104] refer to Fig.19 and FIG. 20A to FIG. 20D , the gap-fill pattern 250 may be removed from the substrate 100 in the cell region C, and the active fin 110 and the device isolation layer 120 may be exposed through the inter-spacer hole ISH.

[0105] For example, the gap-filling pattern 250 may be removed from the substrate 100 by an etching process using the dummy gate electrode pattern 220 and the gate spacer 240 as an etching mask. Since the dummy gate electrode pattern 220 may include polysilicon and the gate spacer 240 may include silicon nitride, and the gap-filling pattern 250 may include silicon oxide, the etching process may be performed in such a manner that an etching rate of silicon oxide may be substantially higher than etching rates of polysilicon and silicon nitride.

[0106] Thus, the inter-spacer trench IST may be formed as an inter-spacer hole ISH, and the inter-spacer hole ISH may be defined by the gate spacer 240 in the cell region C and the cutting pattern CP in the power region PA. The active fin 110 and the device isolation layer 120 may be exposed through the inter-spacer hole ISH.

[0107] For example, the active fin 110 in the spacer hole ISH may be further etched away in the etching process for removing the gap filling pattern 250, so that the upper portion of the upper fin 110b may be removed, thereby forming the active recess AR. Therefore, the height of the upper fin 110b of the spacer hole ISH may be less than the height of the upper fin 110b of the dummy gate structure 200.

[0108] refer to Fig.21 and FIG. 22A to FIG. 22D , the bonding layer 300 may be formed on the active fin 110 and the device isolation layer 120 in the inter-spacer hole ISH.

[0109] For example, a selective epitaxial growth (SEG) process may be performed in the inter-spacer hole ISH by using the upper fin 110 b as a seed, thereby forming an epitaxial layer in the inter-spacer hole ISH as the bonding layer 300 .

[0110] In an exemplary embodiment, a disilane (Si 2 H 6 ) gas and a carbon source gas such as SiHH3CH3 gas are used for the SEG process, and a single crystal silicon carbide (SiC) layer may be formed on the active fin 110 and the device isolation layer 120 as the bonding layer 300. In addition, the silicon source gas may be exclusively used for the SEG process, and a single crystal silicon (Si) layer may be formed on the active fin 110 and the device isolation layer 120 as the bonding layer 300.

[0111] In this case, an n-type impurity source gas such as phosphine (PH3) gas may be provided together with the silicon source gas and / or the carbon source gas in the SEG process, and the single crystal silicon carbide (SiC) layer and the single crystal silicon (Si) layer may be doped with n-type impurities. Therefore, the bonding layer 300 doped with n-type impurities may be used as a source / drain electrode for an NMOS transistor in the NMOS region N.

[0112] In an exemplary embodiment, a silane such as dichlorosilane (H 2 SiCl 2 ) and a silicon source gas such as germanium tetrahydride (GeHH 4 ) may be used for the SEG process, and a single crystal silicon germanium (SiGe) layer may be formed on the active fin 110 and the device isolation layer 120 as the bonding layer 300.

[0113] In this case, a gas such as diborane (B) may be provided together with the silicon source gas and / or the germanium source gas in the SEG process. 2 H 6 ) gas, and the single crystal silicon germanium (SiGe) layer may be doped with p-type impurities. Therefore, the bonding layer 300 doped with p-type impurities may be used as a source / drain electrode for a PMOS transistor in the PMOS region P.

[0114] The bonding layer 300 may grow in isotropic behavior in horizontal and vertical directions so that the bonding layer 300 may substantially fill the active recess AR and grow in the second direction II in the inter-spacer hole ISH. For example, the cross-sectional surface of the bonding layer 300 may be formed in a pentagonal / hexagonal shape.

[0115] When adjacent active fins 110 in the PMOS region P and the NMOS region N may be sufficiently adjacent to each other, adjacent bonding layers 300 on adjacent active fins 110 may be connected to each other along the second direction II. Therefore, the bonding layers 300 may be formed as disconnected wires in the PMOS region P and the NMOS region N.

[0116] As described above, a single active fin 110 in the PMOS region P and the NMOS region N represents a plurality of active fins 110 that may be spaced apart from each other in the second direction II. Therefore, the bonding layer 300 may be sparsely arranged on the active fins or may be arranged in a line across the plurality of active fins 110 in the second direction II.

[0117] The bonding layer 300 may be horizontally grown into the separation region PNS along the second direction II from the peripheral portions of the NMOS region N and the PMOS region P. For example, the bonding layer 300 in the first unit region C1 may be horizontally grown into the first separation region PNS1, and the bonding layer 300 in the second unit region C2 may be horizontally grown into the second separation region PNS2 along the second direction II.

[0118] For example, when the bonding layer 300 may grow around the power area PA in the second direction II, the horizontal growth may be restricted by the cutting pattern CP and may be forced to transform into vertical growth along the side surface of the cutting pattern CP in the third direction III.

[0119] Therefore, the degree of vertical growth of the bonding layer 300 around the power area PA may be greater than the degree of vertical growth of the bonding layer 300 away from the power area PA, and as a result, the size of the bonding layer 300 around the power area PA is larger than the size of the bonding layer 300 away from the power area PA. In addition, the bonding layer 300 may have a flat portion A in contact with the surface of the cutting pattern CP.

[0120] For example, since the epitaxial growth may occur in an isotropic behavior, the bonding layer 300 may be tilted upward from the active fin 110 toward the cutting pattern CP, and an air gap AG may be generated between the cutting pattern CP and the bonding layer 300 adjacent to the cutting pattern CP. Due to the isotropic behavior of the SEG process, an air gap may also be generated between adjacent bonding layers 300 in the PMOS region P and the NMOS region N.

[0121] The size of the flat portion A may vary according to process conditions of the SEG process. As described below, since the flat portion A may contact the power contact 620 , as the size of the flat portion A increases, the contact resistance between the bonding layer 300 and the contact structure 600 may decrease.

[0122] When the vertical epitaxial growth of the bonding layer 300 is uneven or unstable along the side surface of the cutting pattern CP, the flat portion A of the bonding layer 300 may be formed unevenly along the side surface of the cutting pattern CP. For example, when vertical epitaxial growth cannot be fully performed on the side surface of the cutting pattern CP, the flat portion A may be in point contact with the cutting pattern CP. In this case, the flat portion A may consist of all the contact points between the bonding layer 300 and the cutting pattern CP.

[0123] Because the bonding layer 300 away from the cutting pattern CP may not have a growth limiting factor such as the cutting pattern CP, the bonding layer 300 away from the cutting pattern CP in the second direction II may grow horizontally and vertically without any substantial restrictions. Therefore, the connection portion between adjacent bonding layers 300 may have a smaller size than the flat portion A between the bonding layer 300 and the cutting pattern CP. For example, when adjacent active fins 110 may be fully separated from each other in the second direction or the active fins 110 may be arranged around the separation region PNS, the bonding layer 300 may have a point portion B due to the non-restrictive isotropic epitaxial growth behavior.

[0124] Furthermore, since the bonding layer 300 around the cutting pattern CP may be connected to the power rail 700 via the power contact 620 (which will be described in detail below), the increased size of the bonding layer 300 around the cutting pattern CP may increase the process margin for forming the power contact 620 .

[0125] When the size of a conventional semiconductor device is reduced according to the recent device trend, the size of the power area PA can also be reduced, and as a result, the bonding layers separated from each other by the power area PA can be interconnected with each other across the power area PA. However, according to an exemplary embodiment of the present invention, although the size of the power area PA can be reduced in size, the bonding layers 300 in the first unit area C1 and the second unit area C2 can be fully separated from each other by the cutting pattern CP in the power area PA. Therefore, the electrical short circuit of the bonding layer 300 between the first unit area C1 and the second unit area C2 can be substantially prevented in the semiconductor device, thereby improving the yield rate of the semiconductor device.

[0126] refer to Fig.23 and FIG. 24A to FIG. 24D , the dummy gate structure 200 may be removed from the substrate 100 , thereby forming a gate trench extending along the second direction II and defined by the gate spacer 240 .

[0127] An insulating layer having a sufficient thickness to fill the inter-spacer hole ISH may be formed on the substrate 100 having the bonding layer 300. Thus, the gate spacer 240 and the dummy gate structure 200 may be at least partially covered by the insulating layer. For example, the insulating layer may include an oxide such as silicon oxide (SiO).

[0128] Then, the insulating layer may be planarized by a CMP process or an etch-back process until the upper surfaces of the dummy gate electrode pattern 220 and the gate spacer 240 are exposed. Therefore, the insulating layer may remain exclusively in the inter-spacer hole ISH and may be formed as the insulating pattern 400. Therefore, the bonding layer 300 may be at least partially covered by the insulating pattern 400.

[0129] Due to the planarization process, the upper surface of the insulation pattern 400 may be coplanar with the upper surfaces of the dummy gate electrode pattern 220 and the gate spacer 240 .

[0130] Thereafter, the dummy gate structure 200 may be removed from the substrate 100 , and the device isolation layer 120 and the active fin 110 may be exposed through the opening defined by the gate spacer 240 and the cutting pattern CP, thereby forming a gate trench extending in the second direction II in the cell region C.

[0131] For example, since the dummy gate electrode pattern 220 may include polysilicon and the dummy gate insulating pattern 210 may include silicon oxide, a dry etching process or a wet etching process may be performed by using the gate spacer 240 and the cutting pattern CP as an etching mask to remove the dummy gate electrode pattern 220 and the dummy gate insulating pattern 210. In the etching process for removing the dummy gate electrode pattern 220 and the dummy gate insulating pattern 210, damage to the bonding layer 300 may be prevented from occurring due to the insulating pattern 400.

[0132] The gate trench may be defined by the gate spacer 240 in the first direction, and defined by the cutting pattern CP in the second direction. The device isolation layer 120 and the active fin 110 may be exposed through the gate trench.

[0133] refer to Fig.25 and FIG. 26A to FIG. 26D , the gate structure 500 may be formed in the gate trench.

[0134] For example, a gate insulating layer and a work function control layer may be sequentially formed on the substrate 100 along the surface profile of the gate trench, and a gate electrode layer may be formed on the work function control layer so that the gate electrode layer can fully fill the gate trench. In a modified exemplary embodiment, an interface layer may also be formed between the active fin 110 and the gate insulating layer.

[0135] The gate insulating layer may include a high dielectric metal oxide, such as hafnium oxide (HfO 2 ), Tantalum Oxide (Ta 2 O 5 )、ZrO 2). The work function control layer may include metal nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or metal alloys such as titanium aluminide (TiAL). In addition, the gate electrode layer may include low-resistance metals and nitrides of low-resistance metals. Examples of low-resistance metals may include aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), and other metals with similar resistance. These materials may be used alone or in combination. The work function control layer and the gate electrode layer may be formed by one of a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process. Thereafter, the gate electrode layer may be further subjected to a heat treatment such as rapid thermal annealing (RTA), spike RTA, flash RTA, and laser annealing.

[0136] Then, the gate electrode layer, the work function control layer, and the gate insulating layer may be planarized until the upper surfaces of the insulating pattern 400 and the cutting pattern CP may be exposed, thereby forming a gate insulating pattern 510, a work function control pattern 520, and a gate electrode 530, which may be sequentially formed on the active fin 110 and the device isolation layer 120 and may fill the gate trench as a gate structure 500. The gate electrode 530 may be at least partially surrounded by the work function control pattern 520 in the gate trench. The gate structure 500 may be arranged in the gate trench and may be formed as a gate line GL extending in the second direction II in the cell region C.

[0137] The gate structure 500 and the bonding layer 300 in the PMOS region P may constitute a PMOS transistor, and the gate structure 500 and the bonding layer 300 in the NMOS region N may constitute an NMOS transistor. In the present exemplary embodiment, the gate structure 500 may protrude from the device isolation layer 120 to expand the channel area of ​​the transistor, so the PMOS transistor and the NMOS transistor may be used as fin field effect transistor (finFET) devices.

[0138] The gate structures 500 in the first and second cell regions C1 and C2 may be separated from each other in the second direction II by the cutting patterns CP in the power region PA. As described above, the bonding layers 300 in the first and second cell regions C1 and C2 may also be separated from each other in the second direction II by the cutting patterns CP in the power region PA.

[0139] Therefore, an electrical short of the gate structure 500 between the first and second cell regions C1 and C2 may be substantially prevented by the cutting pattern CP, and an electrical short of the bonding layer 300 between the first and second cell regions C1 and C2 may also be substantially prevented by the same cutting pattern CP.

[0140] refer to Fig. 27 and FIG. 28A to FIG. 28E , a first contact hole CTH1 may be formed in the cell region C, and a second contact hole CTH2 may be formed in the power region PA. The bonding layer 300 in the PMOS region P and the NMOS region N may be exposed through the first contact hole CTH1, and the device isolation layer 200 may be exposed through the second contact hole CTH2.

[0141] A gate cap layer and a first interlayer dielectric layer may be sequentially formed on the insulating pattern 400, the gate structure 500, and the cutting pattern CP. Then, the gate cap layer and the first interlayer dielectric layer may be patterned into a gate cap pattern 550 and a first interlayer dielectric pattern ILD1, and the insulating pattern 400 and the cutting pattern CP may be exposed by the gate cap pattern 550 and the first interlayer dielectric pattern ILD1. For example, the gate structure 500 and the gate spacer 240 may be at least partially covered by the gate cap pattern 550, and the gate cap pattern 500 may be at least partially covered by the first interlayer dielectric pattern ILD1.

[0142] In the present exemplary embodiment, the gate insulating pattern 510 may include nitride such as silicon nitride (SiN), and the first interlayer dielectric pattern ILD1 may include substantially the same material as the insulating pattern 400. However, the first interlayer dielectric pattern ILD1 may include an insulating material different from that of the insulating pattern 400.

[0143] Thereafter, the outer portion of the cutting pattern CP may be removed from the outer portion of the power area PA, thereby forming a second contact hole CTH2 in the power area PA, and the device isolation layer 120 may be exposed through the second contact hole CTH2. Therefore, the cutting pattern CP may be formed as a joint cutting pattern CP2, the width of which is reduced to the same extent as the size of the second contact hole CTH2. The joint cutting pattern CP2 may be arranged at the central portion of the power area PA near the insulating pattern 400. In contrast, the cutting pattern CP near the gate structure 500 may not be removed from the power area PA, so the width of the cutting pattern CP may remain unchanged. Compared to the joint cutting pattern CP2, the unreduced cutting pattern CP near the gate structure 500 may be referred to as a gate cutting pattern CP1.

[0144] Thereafter, the insulating pattern 400 may be partially removed from the NMOS region N and the PMOS region P to form a first contact hole CTH1 through which the bonding layer 300 may be exposed. Therefore, the first contact hole CTH1 may include a PMOS contact hole PCTH through which the bonding layer 300 in the PMOS region P may be exposed, and an NMOS contact hole NCTH through which the bonding layer 300 in the NMOS region N may be exposed.

[0145] For example, the insulating pattern 400 may not be removed from the separation region PNS of the cell region C. For example, the insulating pattern 400 at least partially covering the separation region PNS may remain on the device isolation layer 120 of the separation region PNS. Therefore, the PMOS contact hole PCTH and the NMOS contact hole NCTH may be separated from each other by the insulating pattern 400 in the separation region PNS.

[0146] In addition, since the bonding cut pattern CP2 can remain in the central portion of the power area PA, the second contact holes CTH2 can be arranged on both sides of the bonding cut pattern CP2. For example, the second contact holes CTH2 in the first cell area C1 can be symmetrical with the second contact holes CTH2 in the second cell area C2 with respect to the bonding cut pattern CP2.

[0147] In a modified exemplary embodiment, a metal silicide layer may be further formed on the bonding layer 300 exposed through the first contact hole CTH1 .

[0148] refer to Fig.29 and FIG. 30A to FIG. 30E , the first contact hole CTH1 and the second contact hole CTH2 may be filled with a conductive material, thereby forming a contact structure 600 in the first contact hole CTH1 and the second contact hole CTH2.

[0149] For example, a barrier layer may be formed on the insulating pattern 400, the first interlayer dielectric pattern ILD1, and the bottom walls and sidewalls of the first and second contact holes CTH1 and CTH2 along the surface profiles of the first and second contact holes CTH1 and CTH2. A conductive layer having a sufficient thickness may be formed on the barrier layer to fill the first and second contact holes CTH1 and CTH2.

[0150] The barrier layer may include metals such as tantalum and titanium and nitrides thereof, and the conductive layer may include a low resistance metal such as tungsten (W), copper (Cu), and / or aluminum (Al).

[0151] The conductive layer and the barrier layer may be planarized until the upper surface of the first interlayer dielectric pattern ILD1 may be exposed, thereby forming a conductive line filling the first contact hole CTH1 and the second contact hole CTH2 and extending along the second direction II. Therefore, the conductive line may alternately pass through the cell region C and the power region PA along the second direction II. Thereafter, the conductive line may also be planarized until the upper surfaces of the insulating pattern 400 and the bonding cutting pattern CP2 may be exposed, thereby forming a contact structure 600 in the PMOS region P and the NMOS region N with a configuration in which the upper surface of the contact structure 600 may be coplanar with the upper surface of the insulating pattern 400 and the upper surface of the bonding cutting pattern CP2.

[0152] The contact structure 600 may include a unit contact 610 and a power contact 620, wherein the unit contact 610 contacts the bonding layer 300 in the PMOS region P and the NMOS region N, and the power contact 620 contacts the device isolation layer 120 in the power region PA and is connected to the unit contact 610 in one body.

[0153] The unit contact 610 may be connected to the bonding layer 300 in the NMOS region N and the PMOS region P, and the power contact 620 may extend from the unit contact 610 to the power region PA. For example, a pair of power contacts 620 may be formed symmetrically on both sides of the bonding cut pattern CP2 relative to the bonding cut pattern CP2. Therefore, although the size of the power region PA may be reduced, the power contact 620 in the first unit region C1 may be separated from the power contact 620 in the second unit region C2, and the bonding layer 300 in the first unit region C1 may not be connected to the power contact 620 in the second unit region C2.

[0154] As described below, the power contacts 620 may contact the power rail 700 , and the power signal may be transmitted from the power rail 700 to the NMOS transistor and the PMOS transistor.

[0155] Therefore, the bonding layer 300 in the first cell region C1 can be sufficiently separated from the power contact 620 in the second cell region C2 by the bonding cutting pattern CP2, and a pair of power contacts 620 can be arranged in the power region PA in a configuration in which the power contacts in the first cell region C1 and the power contacts in the second cell region C2 are simultaneously in contact with the power rail 700. Therefore, the power signal can be transmitted to the first cell region C1 and the second cell region C2 simultaneously via the pair of power contacts 620. For example, transistors in the first cell region C1 and the second cell region C2 can be simultaneously operated by a single power rail 700.

[0156] refer to Fig.31 and FIG. 32A to FIG. 32E , a second interlayer dielectric pattern ILD2 may be formed on the contact structure 600 and the first interlayer dielectric pattern ILD1, and a power rail 700 may be formed on the first interlayer dielectric pattern ILD1 and may contact the power contact 620 and the bonding cut pattern CP2.

[0157] For example, a second interlayer dielectric layer can be formed on the contact structure 600 and the first interlayer dielectric pattern ILD1, and the second interlayer dielectric pattern ILD1 can be partially removed from the power area PA so that the first interlayer dielectric pattern ILD1, the power contact 620 and the bonding cutting pattern CP2 can be exposed, thereby forming a second interlayer dielectric pattern ILD2 having a power groove, wherein the power contact 620 and the bonding cutting pattern CP2 can be exposed through the power groove.

[0158] In the present exemplary embodiment, the second interlayer dielectric pattern ILD2 may include silicon oxide. In a modified exemplary embodiment, the second interlayer dielectric pattern ILD2 may include a low dielectric material such as silicon oxide doped with carbon (C), silicon oxide doped with fluorine (F), porous silicon oxide, organic polymers, and inorganic polymers (e.g., HSSQ and MSSQ).

[0159] Then, a conductive layer having a sufficient thickness to fill the power trench may be formed on the second interlayer dielectric pattern ILD2 , and the conductive layer may be planarized until an upper surface of the second interlayer dielectric pattern ILD2 may be exposed, thereby forming a power rail 700 .

[0160] Therefore, the power rail 700 may include a power line 720 extending in the first direction I and disposed on the first interlayer dielectric pattern ILD1 , and a power plug 710 extending downward from the power line 720 and contacting the power contact 620 and the bonding cutting pattern CP2 .

[0161] The power plug 710 may be shaped as a vertical rod, and an upper surface of the power plug 710 may have the same horizontal plane as an upper surface of the first interlayer dielectric pattern ILD1. The power line 720 may be arranged on the first interlayer dielectric pattern ILD1 and the power plug 710 along the first direction I. An external power signal may be applied to the power line 720, and may be transmitted to the NMOS transistor and the PMOS transistor in the cell region C via the power plug 710 and the power contact 620. For example, transistors in both the first cell region C1 and the second cell region C2 may be operated simultaneously through a pair of power contacts 620.

[0162] A plurality of additional interlayer dielectric patterns may be further formed on the second interlayer dielectric pattern ILD2 and the power rail 700 , and additional contact structures and wirings may be further formed on the additional interlayer dielectric patterns to be connected to the transistors in the cell region C.

[0163] According to the method of manufacturing a semiconductor device, the cutting pattern CP may be formed in the power region PA, and thus the horizontal growth of the bonding layer 300 may be restricted by the cutting pattern CP. Therefore, although the power region PA may be reduced in size, the bonding layer 300 in the first unit region C1 may be substantially prevented from being connected to the bonding layer 300 in the second unit region C2, thereby preventing an electrical short circuit of the bonding layer 300 between the first unit region C1 and the second unit region C2.

[0164] In addition, the gate structure 500 in the first unit region C1 can also be sufficiently separated from the gate structure 500 in the second unit region C2 by the cutting pattern CP, so that although the power area PA is reduced in size, the gate structure 500 in the first unit region C1 can be substantially prevented from being connected to the gate structure 500 in the second unit region C2, thereby preventing an electrical short circuit of the gate structure 500 between the first unit region C1 and the second unit region C2.

[0165] In addition, a pair of power contacts 620 can be formed symmetrically on both sides of the joint cutting pattern CP2 with respect to the joint cutting pattern CP2, so that the power contacts 620 in the first unit region C1 can be sufficiently separated from the power contacts 620 in the second unit region C2. Therefore, due to the joint cutting pattern CP, the power contacts 620 in the first unit region C1 are not connected to the power contacts 620 in the second unit region C2, thereby preventing electrical short circuits of the power contacts 620.

[0166] Although the size of the power area PA can be reduced according to the recent size reduction of semiconductor devices, the gate structure 500 and the bonding layer 300 in different unit regions can be sufficiently separated in units of unit regions. Therefore, although the size of the power area PA is reduced, the electrical short circuit of the gate structure 500 and the bonding layer 300 can be substantially prevented.

[0167] Although the present exemplary embodiment discloses the cutting pattern CP for sufficiently separating the gate structure 500 and the bonding layer 300 in units of cell regions when the size of the power region PA is reduced, electrical short circuits of the gate structure 500 and the bonding layer 300 may also occur in the separation region PNS in the cell region C. Therefore, separation of the gate structure 500 and the bonding layer 300 may also be used between the NMOS region N and the PMOS region P.

[0168] Figures 33 to 40F 1 is a diagram showing process steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 33 to 40FIn the drawings, the odd-numbered figures are plan views showing each process step of the manufacturing method, and the even-numbered figures are cross-sectional views corresponding to the odd-numbered figures. Each figure designated by a suffix "A" in the accompanying drawing number is taken along Figure 3 , and each of the figures designated by a suffix "B" in the figure numbers is a cross-sectional view taken along the line AA' of the semiconductor device shown in FIG. Figure 3 ' is a cross-sectional view taken along the line BB' of the semiconductor device shown in FIG. In addition, each figure designated by a suffix "C" in the figure number is a cross-sectional view taken along the line BB' of the semiconductor device shown in FIG. Figure 3 , and each of the figures designated by a subscript "D" in the figure numbers is a cross-sectional view taken along the line CC' of the semiconductor device shown in FIG. Figure 3 2 is a cross-sectional view taken along line DD' of the semiconductor device shown in FIG. Each of the figures designated by a suffix "E" in the accompanying drawings is a cross-sectional view taken along line DD' of the semiconductor device shown in FIG. Figure 3 , and each of the figures designated by a suffix “F” in the figure numbers is a cross-sectional view taken along the line EE′ of the semiconductor device shown in FIG. Figure 3 0 is a cross-sectional view taken along line FF′ of the semiconductor device shown in .

[0169] refer to Fig.33 and FIG. 34A to FIG. 34D , can be obtained by comparing with the above reference Figures 5 to 24D The same process as described in detail forms a gate trench on the substrate 100, and then, a separation opening SO may be formed in the separation region PNS.

[0170] For example, an additional mask pattern AMP may be formed on the entire surface of the substrate 100 having the gate trench so that the PMOS region P, the NMOS region N, and the power region PA may be at least partially covered by the additional mask pattern AMP and the separation region PNS may be partially or fully exposed by the additional mask pattern AMP. In this case, the gate trench may be filled with the additional mask pattern AMP.

[0171] Then, the gate spacers 240 and the insulating pattern 400 may be partially or entirely removed from the substrate 100 through a dry etching process using the additional mask pattern AMP as an etching mask, thereby forming separation openings SO that may expose the device isolation layer 120 .

[0172] For example, the separation opening SO may be disposed on the gate trench and the bonding layer 300 along the first direction I. The bonding layer 300 in the PMOS region P may extend in the separation region PNS, and the bonding layer 300 in the NMOS region N may extend in the separation region PNS, and the separation opening SO may be formed in a gap space between a pair of bonding layers 300.

[0173] When the size of the cell region C can be reduced, the gate structures 500 of the PMOS region P and the NMOS region N may be connected to each other in the separation region PNS, and the bonding layers 300 of the PMOS region P and the NMOS region N may be connected to each other in the separation region PNS. Therefore, when the size of the cell region C can be reduced, an electrical short circuit of the gate structure 500 and the bonding layer 300 may occur in the separation region PNS.

[0174] However, according to an exemplary embodiment of the present invention, a separation pattern SP may be provided in the separation region PNS for fully separating the gate structure 500 and the bonding layer 300 in the PMOS region P from the gate structure 500 and the bonding layer 300 in the NMOS region N, thereby preventing electrical short circuits between the gate structures 500 in different cell regions C and between the bonding layers 300.

[0175] refer to Fig.35 and FIG. 36A to FIG. 36D , a separation pattern SP may be formed in the separation opening SO for separating the PMOS region P and the NMOS region N in the cell region C.

[0176] For example, an additional gap-filling layer having a sufficient thickness may be formed on the additional mask pattern AMP to fill the separation opening SO, and then the additional gap-filling layer may be planarized until the upper surfaces of the insulating pattern 400 and the cutting pattern CP may be exposed. Therefore, the additional gap-filling layer may exclusively remain in the separation opening SO, thereby forming a separation pattern SP in the separation opening SO, and the PMOS region P and the NMOS region N may be sufficiently separated from each other by the separation pattern SP.

[0177] The separation pattern SP may include the same material as the cutting pattern CP. Therefore, the separation pattern SP may include silicon nitride (SiN), silicon oxynitride (SiON), and / or silicon oxycarbon nitride (SiOCN).

[0178] Thereafter, the additional mask pattern AMP may be removed from the substrate 100 , and the gate trench may be exposed again.

[0179] refer to Fig.37 and FIG. 38A to FIG. 38D , the gate structure 500 may be formed in the gate trench.

[0180] For example, a gate insulating layer and a work function control layer may be sequentially formed on the substrate 100 along the surface profile of the gate trench, and a gate electrode layer may be formed on the work function control layer so that the gate electrode layer can fully fill the gate trench. Therefore, the active fin 110, the device isolation layer 120, the gate spacer 240, the insulating pattern 400, the cutting pattern CP and the separation pattern SP may be at least partially covered by the gate insulating layer, the work function control layer and the gate electrode layer. In a modified exemplary embodiment, an interface layer may also be formed between the active fin 110 and the gate insulating layer.

[0181] Then, the gate electrode layer, the work function control layer, and the gate insulating layer may be planarized until the upper surfaces of the insulating pattern 400, the separation pattern SP, and the cutting pattern CP may be exposed, thereby forming a gate insulating pattern 510, a work function control pattern 520, and a gate electrode 530, which may be sequentially formed on the active fin 110 and the device isolation layer 120 and may fill the gate trench as a gate structure 500. The gate electrode 530 may be at least partially surrounded by the work function control pattern 520 in the gate trench. The gate structure 500 may be arranged in the gate trench and may be formed as a gate line GL extending in the second direction II in the cell region C.

[0182] For example, the gate structure 500 extending from the PMOS region P may be sufficiently separated from the gate structure 500 extending from the NMOS region N by the separation pattern SP. Therefore, electrical short of the gate structure 500 in the separation region PNS may be substantially prevented by the separation pattern SP.

[0183] The gate structure 500 can be substantially similar to the above reference Figures 23 to 24D The components are formed by the same process as described in detail, and thus, to the extent any further detailed description of various elements is omitted, it can be assumed that these elements are at least similar to corresponding elements already described.

[0184] Afterwards, as referenced Fig.39 and FIG. 40A to FIG. 40F As shown, the contact structure 600, the first interlayer dielectric pattern ILD1, the second interlayer dielectric pattern ILD2, and the power rail 700 can be substantially connected to the reference Figures 27 to 32E Therefore, to the extent that any further detailed description of the method of forming the contact structure 600, the first interlayer dielectric pattern ILD1, the second interlayer dielectric pattern ILD2, and the power rail 700 is omitted, it can be assumed that these elements are at least similar to corresponding elements already described.

[0185] Therefore, the gate structure 500 and the bonding layer 300 may be sufficiently separated from each other in the separation region PNS by the separation pattern SP. Therefore, although the size of the cell region C is reduced, the NMOS transistor and the PMOS transistor may be sufficiently separated from each other in the separation region PNS by the separation pattern SP.

[0186] According to an exemplary embodiment of the inventive concept, the cutting pattern CP may be formed in the power area PA, and thus the horizontal growth of the bonding layer 300 may be restricted by the cutting pattern CP. Therefore, although the power area PA may be reduced in size, the bonding layer 300 in the first unit area C1 may be substantially separated from the bonding layer 300 in the second unit area C2, thereby preventing an electrical short circuit of the bonding layer 300 between the first unit area C1 and the second unit area C2.

[0187] In addition, the gate structure 500 in the first unit region C1 can also be sufficiently separated from the gate structure 500 in the second unit region C2 by the cutting pattern CP, so that although the power area PA is reduced in size, the gate structure 500 in the first unit region C1 can be substantially prevented from being connected to the gate structure 500 in the second unit region C2, thereby preventing an electrical short circuit of the gate structure 500 between the first unit region C1 and the second unit region C2.

[0188] In addition, the gate structure 500 and the bonding layer 300 can be sufficiently separated from each other in the separation region PNS by the separation pattern SP. Therefore, although the size of the cell region C is reduced, the NMOS transistor and the PMOS transistor can be sufficiently separated from each other in the separation region PNS by the separation pattern SP. The semiconductor device can be formed as a CMOS device with high reliability and stability.

[0189] In addition, a pair of power contacts 620 can be formed symmetrically on both sides of the joint cutting pattern CP2 with respect to the joint cutting pattern CP2, so that the power contacts 620 in the first unit region C1 can be sufficiently separated from the power contacts 620 in the second unit region C2. Therefore, due to the joint cutting pattern CP, the power contacts 620 in the first unit region C1 are not connected to the power contacts 620 in the second unit region C2, thereby preventing electrical short circuits of the power contacts 620.

[0190] Although the size of the power area PA can be reduced according to the recent size reduction of semiconductor devices, the gate structure 500 and the bonding layer 300 in different unit regions can be sufficiently separated in units of unit regions. Therefore, although the size of the power area PA is reduced, the electrical short circuit of the gate structure 500 and the bonding layer 300 can be substantially prevented.

[0191] For example, when a CMOS device having a cutting pattern in the power area PA and / or a separation pattern SP in the separation area PNS can be stored in a standard cell library as a CMOS standard cell, a logic device requiring a CMOS cell can be stably manufactured with high reliability by using the CMOS standard cell, and the occurrence of electrical short circuits in the power area PA and the separation area PNS can be substantially reduced in the logic device.

[0192] The foregoing is an explanation of exemplary embodiments of the present invention, and the present invention should not be construed as being limited to the embodiments shown. Although some exemplary embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications may be made in the exemplary embodiments shown without departing substantially from the novel teachings and aspects of the present invention. Therefore, all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate, comprising a first region, a second region and a third region, wherein the second region is disposed between the first region and the third region; a first fin disposed on the first region of the substrate; a second fin disposed on the first region of the substrate; a third fin disposed on the third region of the substrate; a fourth fin, disposed on the third region of the substrate; A first spacer is disposed on the first region of the substrate and between the first fin and the second fin; a second spacer disposed on the substrate and between the second fin and the third fin; a third spacer disposed on the third region of the substrate and between the third fin and the fourth fin; A first gate is disposed on the first fin, the second fin, the first spacer, and the second spacer; a second gate disposed on the third fin, the fourth fin, the second spacer and the third spacer; a third gate, disposed on the first fin, the second fin, the first spacer, and the second spacer; a fourth gate, disposed on the third fin, the fourth fin, the second spacer and the third spacer; a first epitaxial source / drain, disposed on the first fin and between the first gate and the third gate; A second epitaxial source / drain, disposed on the second fin and between the first gate and the third gate; a third epitaxial source / drain, disposed on the third fin and between the second gate and the fourth gate; a fourth epitaxial source / drain, disposed on the fourth fin and between the second gate and the fourth gate; A first contact portion, disposed on the first epitaxial source / drain; A second contact portion, disposed on the second epitaxial source / drain; A third contact portion, disposed on the third epitaxial source / drain; A fourth contact portion, disposed on the fourth epitaxial source / drain; a first insulating pattern disposed on the first spacer and between the first contact portion and the second contact portion and between the first epitaxial source / drain and the second epitaxial source / drain; a second insulating pattern disposed on the third spacer and between the third contact portion and the fourth contact portion and between the third epitaxial source / drain and the fourth epitaxial source / drain; a cutting pattern, arranged on the second spacer; as well as A power rail, disposed on the cutting pattern, wherein the cutting pattern is arranged between the first gate and the second gate, between the third gate and the fourth gate, between the second epitaxial source / drain and the third epitaxial source / drain, and between the second contact portion and the third contact portion, The cutting pattern is arranged on the second area of ​​the substrate, Each of the first epitaxial source / drain, the second epitaxial source / drain, the third epitaxial source / drain, and the fourth epitaxial source / drain is asymmetrically shaped relative to a vertical center line perpendicular to the substrate, and A bottom surface of the power rail is arranged to be higher than a top surface of the first gate. 2 . The semiconductor device according to claim 1 , wherein each of the first region of the substrate and the third region of the substrate is a cell region, and the second region of the substrate is a power region.

3. The semiconductor device according to claim 1, wherein The first gate and the second gate are aligned along a first straight line, and The third gate and the fourth gate are aligned along a second straight line.

4. The semiconductor device according to claim 1, wherein: A first sidewall of the first insulating pattern includes a recess contacting the first epitaxial source / drain. 5 . The semiconductor device according to claim 1 , further comprising a fifth contact portion disposed on the second spacer and on the first sidewall of the cutting pattern, the fifth contact portion contacting the second contact portion and the second epitaxial source / drain.

6. The semiconductor device according to claim 5, wherein: The first sidewall of the cutting pattern is in surface contact with the fifth contact portion.

7. The semiconductor device according to claim 5, wherein: The power rail contacts the fifth contact.

8. The semiconductor device according to claim 5, wherein: A sidewall of the fifth contact portion includes a protrusion contacting the second epitaxial source / drain.

9. The semiconductor device according to claim 1, wherein: The cutting pattern completely separates the first gate and the second gate, so that a top of the first gate is separated from a top of the second gate by the cutting pattern, and a bottom of the first gate is separated from a bottom of the second gate by the cutting pattern.

10. The semiconductor device according to claim 1, further comprising an interlayer dielectric pattern disposed on the first gate, the second gate, and the cutting pattern, in, The power rail is disposed on the interlayer dielectric pattern.

11. A semiconductor device comprising: A substrate, comprising a first region, a second region and a third region, wherein the second region is disposed between the first region and the third region; a first fin disposed on the first region of the substrate; a second fin disposed on the first region of the substrate; a third fin disposed on the third region of the substrate; a fourth fin, disposed on the third region of the substrate; A first spacer is disposed on the first region of the substrate and between the first fin and the second fin; a second spacer disposed on the substrate and between the second fin and the third fin; a third spacer disposed on the third region of the substrate and between the third fin and the fourth fin; A first gate is disposed on the first fin, the second fin, the first spacer, and the second spacer; a second gate disposed on the third fin, the fourth fin, the second spacer and the third spacer; a third gate, disposed on the first fin, the second fin, the first spacer, and the second spacer; a fourth gate, disposed on the third fin, the fourth fin, the second spacer and the third spacer; a first epitaxial source / drain, disposed on the first fin and between the first gate and the third gate; A second epitaxial source / drain, disposed on the second fin and between the first gate and the third gate; a third epitaxial source / drain, disposed on the third fin and between the second gate and the fourth gate; a fourth epitaxial source / drain, disposed on the fourth fin and between the second gate and the fourth gate; a cutting pattern, disposed on the second spacer and comprising an insulating material; A first contact portion, disposed on the first epitaxial source / drain; A second contact portion, disposed on the second epitaxial source / drain; A third contact portion, disposed on the third epitaxial source / drain; A fourth contact portion, disposed on the fourth epitaxial source / drain; a fifth contact portion, disposed on the second spacer and on the first sidewall of the cutting pattern, the fifth contact portion contacting the second contact portion and the second epitaxial source / drain; a sixth contact portion, disposed on the second spacer and on the second sidewall of the cutting pattern, the sixth contact portion contacting the third contact portion and the third epitaxial source / drain; a first insulating pattern disposed on the first spacer and between the first contact portion and the second contact portion and between the first epitaxial source / drain and the second epitaxial source / drain; a second insulating pattern disposed on the third spacer and between the third contact portion and the fourth contact portion and between the third epitaxial source / drain and the fourth epitaxial source / drain; as well as a power rail disposed on the cutting pattern and contacting the fifth contact portion and the sixth contact portion, wherein the cutting pattern is arranged between the first gate and the second gate, between the third gate and the fourth gate, between the second epitaxial source / drain and the third epitaxial source / drain, and between the second contact portion and the third contact portion, The cutting pattern is arranged on the second area of ​​the substrate, The cutting pattern completely separates the first gate and the second gate, so that the top of the first gate is separated from the top of the second gate by the cutting pattern, and the bottom of the first gate is separated from the bottom of the second gate by the cutting pattern, and The first region of the substrate includes a PMOS region and an NMOS region.

12. The semiconductor device according to claim 11, wherein Each of the first epitaxial source / drain, the second epitaxial source / drain, the third epitaxial source / drain, and the fourth epitaxial source / drain is asymmetrically shaped relative to a vertical center line perpendicular to the substrate.

13. The semiconductor device according to claim 11, wherein A bottom surface of the power rail is arranged to be higher than a top surface of the first gate.

14. The semiconductor device according to claim 11, further comprising an interlayer dielectric pattern disposed on the first gate, the second gate, and the cutting pattern, in, The power rail is disposed on the interlayer dielectric pattern.

15. The semiconductor device according to claim 11, wherein The first sidewall of the first insulating pattern includes a recessed portion contacting the first epitaxial source / drain, and A first sidewall of the fifth contact portion includes a protrusion contacting the second epitaxial source / drain.

16. A semiconductor device comprising: A substrate, comprising a first region, a second region and a third region, wherein the second region is disposed between the first region and the third region; a first fin disposed on the first region of the substrate; a second fin disposed on the first region of the substrate; a third fin disposed on the third region of the substrate; a fourth fin, disposed on the third region of the substrate; A first spacer is disposed on the first region of the substrate and between the first fin and the second fin; a second spacer disposed on the substrate and between the second fin and the third fin; a third spacer disposed on the third region of the substrate and between the third fin and the fourth fin; A first gate is disposed on the first fin, the second fin, the first spacer, and the second spacer; a second gate disposed on the third fin, the fourth fin, the second spacer and the third spacer; a third gate, disposed on the first fin, the second fin, the first spacer, and the second spacer; a fourth gate, disposed on the third fin, the fourth fin, the second spacer and the third spacer; a first epitaxial source / drain, disposed on the first fin and between the first gate and the third gate; A second epitaxial source / drain, disposed on the second fin and between the first gate and the third gate; a third epitaxial source / drain, disposed on the third fin and between the second gate and the fourth gate; a fourth epitaxial source / drain, disposed on the fourth fin and between the second gate and the fourth gate; a cutting pattern, disposed on the second spacer and comprising an insulating material; A first contact portion, disposed on the first epitaxial source / drain; A second contact portion, disposed on the second epitaxial source / drain; A third contact portion, disposed on the third epitaxial source / drain; A fourth contact portion, disposed on the fourth epitaxial source / drain; a fifth contact portion, disposed on the second spacer and on the first sidewall of the cutting pattern, the fifth contact portion contacting the second contact portion and the second epitaxial source / drain; a sixth contact portion, disposed on the second spacer and on the second sidewall of the cutting pattern, the sixth contact portion contacting the third contact portion and the third epitaxial source / drain; a first insulating pattern disposed on the first spacer and between the first contact portion and the second contact portion and between the first epitaxial source / drain and the second epitaxial source / drain; a second insulating pattern disposed on the third spacer and between the third contact portion and the fourth contact portion and between the third epitaxial source / drain and the fourth epitaxial source / drain; an interlayer dielectric pattern, disposed on the first gate, the second gate and the cutting pattern; as well as a power rail disposed on the interlayer dielectric pattern and contacting the fifth contact portion and the sixth contact portion, the power rail being disposed on the cutting pattern, wherein the cutting pattern is arranged between the first gate and the second gate, between the third gate and the fourth gate, between the second epitaxial source / drain and the third epitaxial source / drain, and between the second contact portion and the third contact portion, The cutting pattern is arranged on the second area of ​​the substrate, The first sidewall of the first insulating pattern includes a recessed portion contacting the first epitaxial source / drain, The first sidewall of the fifth contact portion includes a protrusion contacting the second epitaxial source / drain, The first gate and the second gate are aligned along a first straight line, and The third gate and the fourth gate are aligned along a second straight line.

17. The semiconductor device according to claim 16, wherein: A bottom surface of the power rail is arranged to be higher than a top surface of the first gate.

18. The semiconductor device according to claim 16, wherein: The cutting pattern completely separates the first gate and the second gate, so that a top of the first gate is separated from a top of the second gate by the cutting pattern, and a bottom of the first gate is separated from a bottom of the second gate by the cutting pattern.

19. The semiconductor device according to claim 16, wherein: Each of the first epitaxial source / drain, the second epitaxial source / drain, the third epitaxial source / drain, and the fourth epitaxial source / drain is asymmetrically shaped relative to a vertical center line perpendicular to the substrate.

20. The semiconductor device according to claim 16, wherein The cutting pattern includes nitride.

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