Ceramic package for high current signals

Abstract

A ceramic package for high current signals is disclosed. A sealed ceramic package (100) for high current signals includes a substrate (102) made of a plurality of ceramic green sheets (409) forming an upper body portion (102U) having an upper surface (101) and a lower body portion (102L) having a lower surface (103) and an intermediate surface (105) between the upper and lower surfaces. A first conductive plate (110C, 110D) is formed on the intermediate surface and a first plurality of conductive pad vias (112A, 112B) are formed in the lower body portion extending from the first conductive plate to the lower surface of the lower body portion. A heat sink (106) is coupled to the lower surface of the lower body portion and a first conductive pad (108A, 108B) is also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.

Description

[0001] Priorities under 35 U.S.SC §119(e) and 37 C.FR §1.78

[0002] This non-provisional application claims priority to the following prior U.S. provisional patent applications: (i) Ceramic Package with Multiple Heat Sinks used as Pins for High Current Signals, filed August 3, 2018, in the names of Joao Carlos Brito, Javier Valle Mayorga, and Hector Torres, and (ii) Ceramic Package for High Current Signals, filed December 28, 2018, in the names of Joao Carlos Felicio Brito, Javier Antonio Valle Mayorga, and Hector Torres, each of which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed embodiments generally relate to the field of electronic circuit packaging. More specifically, but without limitation, this disclosure pertains to ceramic packages for high-current signals. Background Technology

[0004] For certain types of integrated circuits, the Defense Logistics Agency requires ceramic packages. When high-current signals are required within these ceramic packages, conventional solutions use multiple pins coupled in parallel to reduce resistance. This approach necessitates large packages with a large number of pins for high-current signals in order to reduce resistance. Large packages require large printed circuit boards (PCBs), thus increasing the physical size of the system solution. While smaller packages are generally desirable for most circuits, ceramic packages for outer space must be removed from Earth's gravity well, further increasing the need for smaller, lighter packages. Summary of the Invention

[0005] The disclosed embodiments provide a ceramic package having one or more conductive / conductive pads that resemble a heat sink but are used to carry current. In one embodiment, a main conductive pad serves as a heat sink for heat dissipation, while one or more typically smaller conductive pads serve as pins or connections for one or more high-current signals. The conductive pads used as pins can provide direct connections to a PCB and exhibit lower resistance compared to package wiring and lead resistance. This combination can also provide a smaller package size.

[0006] In one aspect, embodiments of a hermetically sealed ceramic package for high-current signals are disclosed. The ceramic package includes: a substrate comprising a plurality of ceramic green sheets forming an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper and lower surfaces; a first conductive plate formed on the intermediate surface of the lower body portion; a first plurality of conductive pad vias formed in the lower body portion and extending from the first conductive plate to the lower surface of the lower body portion; a heat sink coupled to the lower surface of the lower body portion; and a first conductive pad coupled to the lower surface of the lower body portion such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.

[0007] In another aspect, an embodiment of a method for providing a hermetically sealed ceramic package for high-current signals is disclosed. The method includes forming a substrate comprising a plurality of ceramic green sheets, the ceramic green sheets forming an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface located between the upper and lower surfaces, a first conductive plate disposed on the intermediate surface, a first plurality of conductive pad vias extending from the first conductive plate to the lower surface, and a first plurality of pin vias extending from the first conductive plate to the lower surface; attaching a heat sink to the lower surface of the lower body portion; attaching a first conductive pad to the lower surface of the lower body portion such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias; and attaching a first plurality of pins to the substrate such that each of the first plurality of pins is electrically coupled to a corresponding one of the first plurality of pin vias. Attached Figure Description

[0008] In the accompanying drawings, embodiments of the present disclosure are illustrated by way of example and not limitation, in which the same reference numerals indicate similar elements. It should be noted that different references to “a” or “one” embodiments in this disclosure do not necessarily refer to the same embodiment, and such references may refer to at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with embodiments, it is claimed that implementing such features, structures, or characteristics in combination with other embodiments is within the knowledge of those skilled in the art, whether explicitly described or not. As used herein, the terms “coupled” or “coupled” are intended to mean an indirect or direct electrical connection, unless limited to “communicable coupling,” which may include wireless connections. Thus, if a first device is coupled to a second device, the connection may be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0009] The accompanying drawings are incorporated in and form a part of this specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of this disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, wherein:

[0010] Figure 1AA view depicting the bottom of an exemplary hermetically sealed ceramic package for high-current signals according to an embodiment of the present disclosure;

[0011] Figures 1B to 1E Depicting embodiments according to this disclosure Figure 1A Different cross sections of ceramic packages;

[0012] Figure 2 A high-level schematic pin layout for a ceramic package for high-current signals is depicted according to embodiments of the present disclosure;

[0013] Figure 3 Depicting embodiments according to this disclosure Figure 2 A diagram showing the mount bond of a ceramic package.

[0014] Figure 4A and Figure 4B Top perspective view and bottom perspective view of a ceramic package according to an embodiment of the present disclosure are depicted respectively.

[0015] Figure 4C A bottom perspective view depicting a ceramic package according to an embodiment of the present disclosure;

[0016] Figure 5 A flowchart illustrating a method for providing a ceramic package for high-current signals;

[0017] Figure 5A Depicting Figure 5 Other elements of the method; and

[0018] Figure 6 depicts a ceramic package for high-current signals according to the prior art. Detailed Implementation

[0019] Specific embodiments of the invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0020] Due to material limitations, ceramic packages used in space and defense applications exhibit high resistance. This is particularly limiting for power applications that require low resistance to operate efficiently at high currents. As mentioned earlier, conventional solutions for high-current signals use multiple pins in parallel to reduce resistance. This approach requires large packages with many pins to reduce resistance. Large packages require large PCBs, thus increasing the physical size of the system solution.

[0021] Figure 6 shows an example of a prior art ceramic package 600 for power applications. Figure 6 depicts a package for a buck regulator that provides 12 amps at 3.3 volts, with a peak efficiency of 90%. The ceramic package is 14.4 × 14.4 mm. 2 Excluding leads, this means the ceramic package delivers approximately 190 mW / mm². 2 Additionally, the ceramic package 600 requires 64 pins 602 to carry the required signals with low resistance. When the device is shipped by the manufacturer, the leads are intentionally extended so that they can be trimmed and shaped to fit a customer-specific PCB footprint.

[0022] Figure 1A A bottom view depicting a hermetically sealed ceramic package 100 for high-current signals according to an embodiment of the present disclosure is shown. A substrate 102 forms the body of the ceramic package. In one embodiment, the substrate 102 is formed from a plurality of ceramic green sheets, which are formed and used as follows: Ceramic powder and glass powder mixed with a small amount of binder and solvent form a homogeneous slurry, which is cast to form a sheet of uniform thickness and dried to produce a so-called ceramic green sheet. The ceramic green sheet is cut into shapes including holes to form through-holes that can be filled with metal paste. These through-holes create vertical connections for electrical feedthrough, while planar wires and conductive planes are defined on the ceramic sheet by screen printing, also using metal paste. Once the various metal structures are defined, the ceramic green sheets are stacked and laminated in a specific order to connect the individual sheets, thereby producing a three-dimensional structure with hermetically sealed electrical feedthrough. The multilayer ceramic is co-fired at high temperature to form a solid and hermetically sealed ceramic.

[0023] In addition to the substrate 102, the hermetically sealed ceramic package 100 includes a plurality of conductive pins 104 and a plurality of conductive slugs or pads, some of which serve as pins or connections for high-current signals. In the illustrated embodiment, the large conductive slug serves as a heat sink 106 for heat dissipation, while two smaller conductive pads 108 serve as pins. Each of the conductive pads 108 is designed to attach directly to the PCB and present low resistance for the associated high-current signals.

[0024] The conductive pad 108 provides significantly lower resistance than the pins 104 and enables a smaller package with fewer pins while still efficiently driving large currents. In one embodiment, the heatsink 106 and conductive pad 108 are formed of copper-tungsten (CuW), although other materials can also be used. In one embodiment, the disclosed ceramic package carries a buck regulator that provides 18 amps at 3.3 volts and 90 percent peak efficiency. By using the conductive pad 108, the size of the hermetically sealed ceramic package 100 (excluding leads) has been reduced to 7.37 × 20.3 mm.2 This enables the package to deliver approximately 400mW / mm. 2 Where area becomes critical, smaller packages can offer a higher level of integration, especially in space applications where power design is often a last resort. Size and weight are important characteristics for space applications because these elements translate into high fuel costs for launch or flight components. The hermetic ceramic package 100 is positioned at three different cross-sections... Figure 1A As shown in the figure, and labeled by the reference numerals showing each cross section.

[0025] Figure 1B A longitudinal section is depicted through the cross-section indicator 1B according to an embodiment of the present disclosure. Figure 1B As shown in the figure, the substrate 102 is composed of an upper body portion 102U and a lower body portion 102L with different dimensions. The upper body portion 102U has an upper surface 101; the lower body portion 102L includes a lower surface 103 and an intermediate surface 105 located between the upper surface 101 and the lower surface 103. The intermediate surface 105 is partially exposed and partially located below the upper body portion 102U. As can be seen in the figure, the heat sink 106 and the conductive pad 108 are directly attached to the lower surface 103 of the lower body portion 102L, wherein the heat sink 106 is located below the opening 113 extending from the upper surface 101 of the upper body portion 102U to the lower surface 103 of the lower body portion 102L, so that the die 114 can be directly mounted to the heat sink 106 for effective heat dissipation. The conductive pad 108 is mounted to the lower body portion 102L such that it is electrically coupled to each of the conductive pads 108 through a plurality of conductive pad through-holes 112 in the lower body portion 102L. The conductive pad 108 can be mounted to the lower body portion 102L using, for example, a conductive adhesive (such as a silicone or epoxy adhesive containing, for example, silver, nickel, and / or graphite). In one embodiment, AgCu soldering material is fired to attach both the conductive pad 108 and the heat sink 106 to the substrate. A conductive plate 110 on the intermediate surface 105 is electrically coupled to a plurality of conductive pad vias 112 and provides areas for attaching bonding wires 116, such that high-current signals from the IC chip 114 are conducted from the bonding wires 116 to the conductive plate 110, the conductive pad vias 112, the conductive pad 108, and ultimately to connections on the PCB (not specifically shown). It should be understood that although only one bonding wire 116 is shown in this figure, in practice, many bonding wires 116 can be used to couple the IC chip 114 to the conductive plate 110 for specific signals. The locations of the two cross sections 1C and 1D of the hermetically sealed ceramic package 100 are also... Figure 1B As shown in the image. Figure 1C This is a cross-section of the hermetic ceramic package 100 taken at position 1C. Figure 1DThis is a cross-section of the hermetic ceramic package 100 taken at position 1D.

[0026] In Figure 1C In the illustrated embodiment, the cross section passes through the IC chip 114 at the locations where it is coupled to two pins 104A and 104B of the IC chip 114. Conductive plate 110A is coupled to pin 104A through a pin via 113A in the lower body portion 102L, and conductive plate 110B is coupled to pin 104B through a pin via 113B in the lower body portion 102L. Bonding wire 116 couples each of conductive plates 110A and 110B to a corresponding bonding pad (not specifically shown) on the IC chip 114.

[0027] Figure 1D A second cross-section of the hermetic ceramic package 100 passing through the conductive pad 108 is depicted. Although the IC chip 114 is not visible in this figure, each of the conductive plates 110C and 110D can be coupled to the IC chip 114 using bonding wires (not specifically shown). The conductive plate 110C is coupled to the conductive pad 108A through a plurality of conductive pad vias 112A, five of which are shown in this figure. The conductive plate 110C is also coupled to the pin 104C through pin vias 113C. The number of conductive pad vias 112 for carrying current between the conductive plate 110C and the conductive pad 108A will generally be determined by the overall design of the package and the amount of current the conductive pad is expected to carry, although from Figure 1A and Figure 1D As can be seen, multiple conductive pad vias are laterally and longitudinally aligned between corresponding pairs of conductive plates 110 and conductive pads 108 within the lower main body portion 102L. Similarly, conductive plate 110D is coupled to conductive pad 108B through multiple conductive pad vias 112B, five of which are shown again. Conductive plate 110D is also coupled to pin 104D through pin vias 113D.

[0028] Figure 1E repeat Figure 1C The cross-section is shown, with many reference numerals removed to illustrate the finished package including the cover 118. The cover 118 can be attached, for example, to the upper surface 101 of the upper body portion 102U using an adhesive to provide a hermetically sealed cavity 120 protecting the IC chip 114 from damage. In one embodiment, the cover 118 is formed from the same ceramic green sheet used to form the substrate 102. In the disclosed embodiment, the cover 118 is shown as a flat plate, which can be fastened to the upper body portion 102U, for example, by an adhesive. It should be understood that the cover 118 can also have different shapes, such as a dome shape, to provide more space for the bonding lines 116 or a lip (not specifically shown), thereby providing a surface for positioning and locking the cover 118 in the desired location.

[0029] Figure 2 The outline of the ceramic package 200 is depicted, with the locations of the heat sink 106 and conductive pad 108 shown as dashed lines, and the location of the IC chip 114 within the opening 113 shown for reference. Thirty-four pins for signals utilized in this embodiment, and the signal associated with each of these pins, are also shown. The package 200 provides power in space-dependent applications and has three signals that carry high current at least at certain times: the power supply voltage input signal PVIN, the power supply ground signal PGND, and the switching signal PH. Of these three high-current signals PVIN, PGND, and PH, the switching signal PH will carry an average current of approximately 18A, the power supply ground signal PGND will carry approximately 70% of that current, and the power supply voltage input signal PVIN will carry approximately 30%. In the illustrated embodiment, the power supply voltage input signal PVIN has been assigned to five pins numbered 7-11; the power supply ground PGND has been assigned to six pins numbered 12-17 and conductive pad 108B; and the switching signal PH has been assigned to eleven pins numbered 18-28 and conductive pad 108A. The remaining signals are assigned to one of the pins numbered 1-6 and 29-34, respectively.

[0030] Figure 3 A mounting bonding diagram of package 300 is depicted, showing the horizontal plane of conductive plate 110 according to an embodiment of the present disclosure. In the illustrated embodiment, there are eighteen conductive plates numbered 110-1 to 110-18, and bonding wires 116 coupling IC chip 114 to conductive plate 110. It should be understood that the connections are provided as examples only and do not limit the disclosed embodiments. IC chip 114 includes a plurality of bonding pads 302, and bonding wires 116 may be soldered or otherwise attached to bonding pads 302. Conductive plate 110-1 corresponds to the ground signal GND at pin 1, which provides a local ground for logic level circuitry; six bonding pads on IC chip 114 are coupled to conductive plate 110-1. Conductive plates 110-2, 110-3, 110-5, and 110-6 correspond to the enable signal EN at pin 2, the resistor timing signal RT at pin 3, the first synchronization signal SYNC1 at pin 5, and the second synchronization signal SYNC2 at pin 6, respectively. Each of the conductive plates 110-2, 110-3, 110-5, and 110-6 is coupled to the corresponding bonding pad 302 on the IC chip 114 via a single bonding wire. Conductive plate 110-4, corresponding to the logic level voltage input signal VIN, is coupled to the IC chip 114 via four bonding wires.

[0031] Conductive plate 110-7 corresponds to the power supply voltage input signal PVIN, which is shared between pins 7 and 11; conductive plate 110-7 is coupled to IC chip 114 via more than twenty bonding wires. Power ground signal PGND is shared between conductive plates 110-8 and 110-9. More than twenty first multiple bonding wires 311A ​​couple the first conductive plate formed by conductive plates 110-8 and 110-9 to IC chip 114; the first conductive plate couples the power ground signal PGND to first multiple pins 12 to 17 via first multiple pin vias (e.g., pin via 113C), and also couples the power ground signal PGND to the first conductive pad 108B via first multiple conductive pad vias 112B. Switching signal PH is also shared among the multiple conductive plates. In the illustrated embodiment, the second conductive plate formed by conductive plates 110-10, 110-11, and 110-12 is coupled to the IC chip 114 via more than fifty second multiple bonding wires 311B, and further coupled to a second multiple pins 18 to 28 via a second multiple pin via (e.g., pin via 113D), and also coupled to a second conductive pad 108A via a second multiple conductive pad via 112A.

[0032] The remaining signals include PWRGD, RSC, the soft-start / tracking signal SS / TR, the voltage sensing signal VSENSE, the compensation signal COMP, and the reference capacitor signal REFCAP. PWRGD is an open-drain output; if the output voltage is low for a specific reason, this open-drain output is asserted as low. PWRGD is assigned to pin 29 and conductive plates 110-13. RSC is assigned to pin 30 and conductive plates 110-14. The soft-start / tracking signal SS / TR is assigned to pin 31 and conductive plates 110-15. The voltage sensing signal VSENSE is assigned to pin 32 and conductive plates 110-16. The compensation signal COMP is assigned to pin 33 and conductive plates 110-17. The reference capacitor signal REFCAP is assigned to pin 34 and conductive plates 110-18. Each signal assigned to pins 29 through 34 is attached to IC chip 114 via a single bonding wire.

[0033] Figure 4A and Figure 4B Top and bottom perspective views of a ceramic package 400 according to an embodiment of the device are provided, and are depicted herein to better illustrate the three main layers of the disclosed ceramic package embodiment. Figure 4A , Figure 4B The design in the middle is roughly similar to Figures 1A to 1EThe embodiments shown differ slightly in several dimensions and the placement of several features. In the embodiment shown in the perspective view of the ceramic package 400, the upper surface 401 provides support for a cover added to the final product. An intermediate surface 405 is disposed horizontally to the upper surface 401 and provides a plurality of conductive plates 410, which are connected to... Figures 1B to 1D The through holes 112 and 113 seen therein are together Figure 3 The bonding wire 304, as seen, provides a signal path between the pin 404 and the conductive pad 408. An opening 411 extends from the intermediate surface 405 to the lower surface 403; through the opening 411, a portion of the mounted heatsink 406 can be seen. Observing the bottom view of the ceramic package 400, the heatsink 406 and conductive pad 408 are mounted to the lower surface 403 of the ceramic package 400. Figure 4C A bottom perspective view of a ceramic package 400' is depicted, which is an embodiment with a smaller overall heat sink 406. This figure is provided primarily to illustrate the formation of the upper body portion 102U and the lower body portion 102L (e.g., Figures 1A to 1D The visible portion of the ceramic green sheet 409 (as shown).

[0034] Figure 5 A method 500 for providing a hermetically sealed ceramic package for high-current signals according to embodiments of the present disclosure is described. Method 500 begins by forming (505) a substrate from a plurality of ceramic green sheets, wherein the substrate includes an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface located between the upper and lower surfaces. A first conductive plate is disposed on the intermediate surface. A first plurality of conductive pad vias extend from the first conductive plate to the lower surface, and a first plurality of pin vias extend from the first conductive plate to the lower surface. The method then continues by attaching (510) a heat sink to the lower surface of the lower body portion and attaching (515) a first conductive pad to the lower surface of the lower body portion, such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias. A first plurality of pins are attached (520) to the substrate, such that each of the first plurality of pins is electrically coupled to a corresponding one of the first plurality of pin vias. An IC chip is attached (525) to the heat sink, and corresponding bonding wires are attached (530) between the first plurality of bonding pads and the first conductive plate on the IC chip. The method ends with attaching (535) the cover to the upper surface of the upper body portion.

[0035] Figure 5A Describe the additional components that are implemented when a second conductive pad is provided on the package. It should be understood that... Figure 5AThe components are executed before the cover is attached to the substrate. In this case, the method includes providing (540) a second conductive plate on the intermediate surface, wherein a second plurality of conductive pad vias extend from the second conductive plate to the lower surface and a second plurality of pin vias extend from the second conductive plate to the lower surface. The second conductive pads are attached (545) to the lower surface of the lower body portion such that the second conductive pads are electrically coupled to the second plurality of conductive pad vias, and the second plurality of pins are attached (550) to the substrate such that each of the second plurality of pins is electrically coupled to a corresponding one of the second plurality of pin vias. Corresponding bonding wires are attached (555) between the second plurality of bonding pads and the second conductive plate on the IC chip.

[0036] The applicant has disclosed a hermetically sealed ceramic package for high-current applications and a method for forming the hermetically sealed ceramic package. By utilizing portions of a heat sink as pins, the number of pins required for high-current signals can be reduced, resulting in a smaller ceramic package and higher power density. The example shown in this application uses conductive pads and regular pins to carry signals with the highest current. In space and defense applications, due to the size of the hermetically sealed ceramic package and the thermal cycling the device undergoes in outer space, pins need to be soldered to a printed circuit board for board-level reliability purposes. However, some embodiments may include only conductive pads for a given signal if the desired resistance level and board-level reliability considerations can be met without additional pins. Additional benefits of using conductive pads may include a higher level of integration into regionally critical applications and lower cost when the ceramic package is deployed into space.

[0037] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed descriptions should be construed as implying that any particular component, element, step, action, or function is necessary such that it must be included within the scope of the claims. Unless expressly stated otherwise, references to the singular form of an element are not intended to mean "one and only one," but rather "one or more." All structural and functional equivalents of the elements of the above embodiments known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by these claims. Therefore, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and variations within the spirit and scope of the appended claims.

Claims

1. A hermetically sealed ceramic package for high-current signals, the ceramic package comprising: A substrate comprising a plurality of ceramic green sheets forming an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface; A first conductive plate is formed on the intermediate surface of the lower body portion; A plurality of conductive pad through-holes are formed in the lower body portion and extend from the first conductive plate to the lower surface of the lower body portion; A heat sink, located on the lower surface of the lower body portion; as well as A first conductive pad, on the lower surface of the lower body portion, such that the first conductive pad is electrically coupled to the first plurality of conductive pad through-holes. The first conductive pad is formed from a portion of the heat sink and is designed to be directly attached to the PCB.

2. The ceramic encapsulation component according to claim 1, further comprising: A first pin is attached to the substrate; as well as A first pin via is formed in the lower body portion and extends from the first conductive plate to the first pin.

3. The ceramic encapsulation component according to claim 1, further comprising: A plurality of pins are attached to the substrate; as well as A plurality of pin vias are formed in the lower body portion, each of the plurality of pin vias being coupled between a corresponding pin and the first conductive plate.

4. The ceramic encapsulation component according to claim 3, further comprising: An opening extends from the intermediate surface to the lower surface of the lower body portion, such that the opening covers the heat sink.

5. The ceramic encapsulation component according to claim 4, further comprising: A second conductive plate is formed on the intermediate surface of the lower body portion; A second plurality of conductive pad through-holes are formed in the lower body portion and extend from the second conductive plate to the lower surface of the lower body portion; as well as A second conductive pad is coupled to the lower surface of the lower body portion, such that the second conductive pad is electrically coupled to the second plurality of conductive pad vias.

6. The ceramic encapsulation component according to claim 5, further comprising: The second plurality of pins are attached to the substrate; as well as A second plurality of pin vias are formed in the lower body portion, each of the second plurality of pin vias being coupled between a corresponding pin and the second conductive plate.

7. The ceramic package according to claim 6 further includes an integrated circuit chip, i.e., an IC chip, mounted on the heat sink within the opening.

8. The ceramic package according to claim 7, further comprising: The first plurality of bonding wires are coupled between the first plurality of bonding pads on the IC chip and the first conductive plate; as well as The second plurality of bonding wires are coupled between the second plurality of bonding pads on the IC chip and the second conductive plate.

9. The ceramic package of claim 8, further comprising a cap fastened to the upper surface of the upper body portion.

10. A method of providing a hermetically sealed ceramic package for high-current signals, the method comprising: A substrate comprising a plurality of ceramic green sheets is formed, the plurality of ceramic green sheets forming an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface, a first conductive plate being provided on the intermediate surface, a first plurality of conductive pad vias extending from the first conductive plate to the lower surface, and a first plurality of pin vias extending from the first conductive plate to the lower surface. The heat sink is attached to the lower surface of the lower body portion; The first conductive pad is attached to the lower surface of the lower body portion such that the first conductive pad is electrically coupled to the first plurality of conductive pad through holes; as well as A first plurality of pins are attached to the substrate such that each of the first plurality of pins is electrically coupled to a corresponding one of the first plurality of pin vias. The first conductive pad is formed from a portion of the heat sink and is designed to be directly attached to the PCB.

11. The method of claim 10, further comprising providing a second conductive plate on the intermediate surface, a second plurality of conductive pad vias extending from the second conductive plate to the lower surface, and a second plurality of pin vias extending from the second conductive plate to the lower surface.

12. The method of claim 11, further comprising: The second conductive pad is attached to the lower surface of the lower body portion such that the second conductive pad is electrically coupled to the second plurality of conductive pad vias; as well as A second plurality of pins are attached to the substrate such that each of the second plurality of pins is electrically coupled to a corresponding one of the second plurality of pin vias.

13. The method of claim 12, further comprising: Attach the integrated circuit chip, i.e., the IC chip, to the heat sink; The corresponding bonding wires are attached between the first plurality of bonding pads on the IC chip and the first conductive plate. as well as The corresponding bonding wires are attached between the second plurality of bonding pads and the second conductive plate on the IC chip.

14. The method of claim 13, further comprising attaching a cover to the upper surface of the substrate.

Images