Phase-locked loop and method for the same

Abstract

A phase-locked loop is provided. The phase-locked loop includes a first loop, the first loop including a controlled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate a first signal indicating a timing difference between a reference signal and the oscillation signal. In addition, the phase-locked loop includes a second loop, the second loop is configured to generate a second signal indicating a timing error of a cycle time of the oscillation signal, and a correction signal is generated based on the second signal. The phase-locked loop also includes a combiner, the combiner is configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

Description

Technical Field

[0001] Examples relate to analog or digital Phase-Locked Loops (PLLs), and methods therefor. Background Art

[0002] In a conventional PLL (e.g. analog or digital PLL, DPLL), the phase noise is determined by the phase noise of the components of the PLL (e.g. voltage controlled oscillator, VCO; digitally controlled oscillator, DCO; phase detector such as time to digital converter TDC) and the reference frequency.

[0003] In a transmitter, the phase noise of the PLL affects the Error Vector Magnitude (EVM) of the transmitted and received signals. Therefore, there is a high motivation to improve the phase noise of the PLL.

[0004] Traditionally, attempts have been made to improve the phase noise of a PLL by improving the phase noise of the basic components of the PLL (e.g., DCO, TDC, or reference frequency source). In some cases, further improving the phase noise of the basic components of the PLL is simply not practical or possible. In addition, improvements in the phase noise performance of the basic components typically result in higher costs and power consumption.

[0005] Therefore, there may be a need for improved phase noise reduction within a PLL. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some examples of apparatus and / or methods will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0007] Figure 1 An example of a PLL is illustrated;

[0008] Figure 2 Another example of a PLL is illustrated;

[0009] Figure 3 An example of a self-triggered TDC is illustrated;

[0010] Figure 4 Pictured Figure 3 An example of a flash TDC implementation of a self-triggered TDC;

[0011] Figure 5 An example of an oscillating signal and its delayed replica input to a self-triggered TDC is illustrated;

[0012] Figure 6 Another example of a PLL is illustrated;

[0013] Figure 7 Another example of a PLL is shown;

[0014] Figure 8 An example of phase noise attenuation with frequency is illustrated;

[0015] Fig. 9 illustrates an example of comparison between a conventional PLL and a PLL according to the proposed architecture;

[0016] Fig.10 An example of a mobile device including a PLL is illustrated; and

[0017] Fig.11 A flow chart illustrating an example of a method for a PLL. DETAILED DESCRIPTION

[0018] Various examples will now be described more fully with reference to the accompanying drawings, which illustrate some examples.In the accompanying drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0019] Therefore, although other examples can have various modifications and alternative forms, some specific examples thereof are shown in the drawings and will be described in detail later. However, this detailed description does not limit other examples to the specific forms described. Other examples may encompass all modifications, equivalents, and substitutes that fall within the scope of the present disclosure. Similar reference numerals always refer to similar or similar elements in the description of the drawings, which can be implemented identically or in a modified form when compared to each other, while providing the same or similar functions.

[0020] It is to be understood that when an element is referred to as being "connected" or "coupled" to another element, these elements may be directly connected or coupled or connected or coupled via one or more intervening elements. If two elements A and B are combined using "or", it is to be understood that all possible combinations are to be disclosed, i.e., only A, only B, and A and B. An alternative wording for the same combination is "at least one of A and B". The same applies to combinations of more than 2 elements.

[0021] The terms used herein for describing specific examples are not intended to limit other examples. Whenever singular forms such as "one", "an" and "the" are used and only a single element is neither explicitly nor implicitly limited to mandatory, other examples may also use multiple elements to implement the same function. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to implement the same function. It is also to be understood that the terms "include", "include" and / or "include", "include" indicate the existence of the described features, integers, steps, operations, processes, actions, elements and / or components when used, but do not exclude the existence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) are used herein according to their common meaning in the art to which the examples belong.

[0023] Figure 1 A PLL 100 is illustrated. The PLL 100 includes a first loop 110, the first loop 110 including a controlled oscillator 130 and a phase detector 140. The controlled oscillator 130 is configured to generate an oscillation signal 131. The phase detector 140 is configured to generate a first signal 141, the first signal 141 indicating a timing difference between a reference signal 101 and the oscillation signal 131. In addition, the PLL 100 includes a second loop 120, the second loop 120 is configured to generate a second signal 121 indicating a timing error of a cycle time of the oscillation signal, and to generate a correction signal 122 based on the second signal 121. The PLL 100 also includes a combiner 150, the combiner 150 is configured to generate a control signal 151 for the controlled oscillator 130 by combining the correction signal 122 and a third signal 161 derived from the first signal 131.

[0024] PLL 100 includes an additional second loop 120 to achieve phase noise elimination with high accuracy compared to conventional PLLs. In the case where the controlled oscillator 130 generates an oscillation signal 131 based on a control signal 151, the phase noise of the PLL 100 can be compensated by adjusting the control signal 151 via a correction signal 122. Therefore, the second loop 120 can allow the phase noise of the PLL 100 to be improved without improving the phase noise performance of the basic components of the PLL 100 (i.e., without improving the phase noise performance of the first loop 110). The additional second loop 120 can therefore enable the PLL 100 to operate with reduced power consumption and improved phase compared to a PLL with conventional phase noise reduction. In addition, the proposed phase noise elimination can be achieved without increasing the chip area required for the PLL and without increasing manufacturing costs compared to conventional PLLs.

[0025] The PLL 100 may be an analog PLL as well as a DPLL. Therefore, the phase detector 140 and the controlled oscillator 130 may be analog components or digital components. For example, the phase detector 140 may be a TDC. The controlled oscillator may be a VCO or a DCO.

[0026] The frequency of the oscillating signal 131 may range from a few Hz to tens or even hundreds of GHz.

[0027] The first loop 110 may additionally include additional elements of a conventional PLL. For example, the first loop 110 may additionally include a frequency divider (feedback frequency divider) coupled between the output of the controlled oscillator 130 and the phase detector 140. In addition, the first loop 110 may further include a loop filter configured to generate a third signal 161 by (loop) filtering the first signal 131.

[0028] The second loop 120 estimates the timing error of the cycle time of the oscillation signal, i.e., the difference between the actual cycle time of the oscillation signal and the nominal (reference) cycle time of the oscillation signal. Therefore, the second loop 120 may include a TDC (not shown) configured to generate a fourth signal indicating the actual cycle time of the oscillation signal based on the oscillation signal 131 and the delayed replica of the oscillation signal 131.

[0029] The delayed replica of the oscillating signal 131 may be generated by a delay element of the second loop 120 , which is configured to delay the oscillating signal 131 (by a predetermined delay time, which may be adjustable).

[0030] The sampling frequency of the TDC may in some examples be substantially equal to the oscillation frequency of the oscillating signal 131. However, the sampling frequency of the TDC may also be much lower than the oscillation frequency of the oscillating signal 131. For example, the sampling frequency of the TDC may be more than 20 times lower than the oscillation frequency of the oscillating signal 131. Although the oscillation frequency of the oscillating signal 131 may be very high (GHz range), the TDC may operate at a low duty cycle (e.g., a sampling / gating rate between 40 and 100 MHz) because most phase noise power densities are below 10 MHz. Therefore, the phase noise estimation performed by the TDC may consume very little power.

[0031] The second loop 120 may also include a second combiner (not shown) configured to generate the second signal 121 by combining a fourth signal output by the TDC and a fifth signal indicating the nominal cycle time of the oscillation signal 131. The fifth signal may be generated in many different ways. For example, the fifth signal may be based on the average output of the TDC over a predetermined number of oscillation cycles of the oscillation signal 131. Phase noise is eliminated over the number of oscillation cycles, so that the average output of the TDC indicates the TDC output for the nominal cycle time of the oscillation signal 131. Alternatively, a reference output of the TDC for each oscillation frequency of the oscillation signal 131 may be determined in the calibration.

[0032] Different schemes may also be used to generate the correction signal 122 from the second signal 121. For example, the second loop 120 may include an integrator (not shown) configured to generate the correction signal 122 by continuously integrating the second signal 121. Thus, the estimated timing error of the period time of the oscillation signal is continuously summed.

[0033] Alternatively, the second loop 120 may include a third combiner configured to generate a sample of the correction signal 122 by combining the second signal 121 with a previous sample of the correction signal 122. For example, a second delay element may be coupled between the output and the input of the third combiner such that the second delay element delays the previous sample of the correction signal 122 so that it may be combined with the current (subsequent) sample of the second signal 121.

[0034] In addition, the second loop 120 may include a filter configured to bandpass filter the correction signal 122. Thus, the correction signal 122 may be bandpass filtered to limit the bandwidth of the correction signal 122. This may allow for improved phase noise cancellation within the PLL 100. For example, the filter may be configured to lowpass filter the correction signal 122. Thus, high frequency components of the correction signal 122 may be removed. This may allow for improved phase noise attenuation within the PLL 100.

[0035] Next, we will combine Figures 2 to 7 Discussion Figure 1 Detailed description of the implementation of the PLL 100 is provided in more detail below.

[0036] Figure 2 A further PLL 200 implemented as a DPLL is illustrated. The PLL 200 comprises a first loop 210 having a DCO 230 as a controlled oscillator, a TDC 240 as a phase detector and a digital loop filter 260.

[0037] Initially, the second loop 220 for compensating the phase noise of the PLL 200 is ignored. Then, the output frequency of the DPLL, that is, the oscillation frequency of the oscillation signal 131 is:

[0038]

[0039] where ω DPLL represents the angular frequency, denotes a phase constant, and PN(t) denotes a phase noise of the PLL 200 .

[0040] Therefore, the instantaneous phase θ of PLL 200 is inst , that is, the oscillation signal 131 is:

[0041]

[0042] And the instantaneous DCO cycle time T DPLL_inst , that is, the cycle time of the oscillation signal 131 is:

[0043] T DPLL_inst =T DPLL_nominal +ΔT PN (t) (3),

[0044] Where T DPLL_nominal represents the nominal PLL cycle time (ie, the nominal cycle time of the oscillation signal 131), and ΔT PN (t) represents the phase noise timing error (ie, the timing error of the cycle time of the oscillation signal 131 ), which is different for each oscillation cycle of the oscillation signal 131 (ie, each DCO cycle).

[0045] Using the proposed architecture, the DCO timing error ΔT PN(t) is measured and subtracted from the DCO output. Therefore, PLL 200 includes a second loop 220, i.e., a phase noise cancellation loop, in addition to the first loop 210 (which is a conventional DPLL). Therefore, PLL 200 has two loops: the basic DPLL loop 210, which is slow and controls the accuracy of the DPLL output frequency (because it is locked to the reference frequency 101), and a second fast inner loop 220 for phase noise cancellation.

[0046] The second loop 220 includes a TDC 270. The TDC 270 receives as input the oscillating signal 131 and a delayed replica of the oscillating signal 131 (which is provided by a delay element 275 based on the oscillating signal 131). Therefore, the TDC 270 is self-triggered. Since the TDC 270 is self-triggered, the measurement is not affected by any external phase noise (e.g., from a reference source providing a reference signal).

[0047] A more detailed view of the self-triggered TDC 270 is shown in Figure 3 The oscillation period D[n] of the oscillation signal 131 is the first input of the TDC 270 . The oscillation period D[n] is further delayed by k TDC periods via the delay element 275 . The delayed oscillation period D[nk] is the second input of the TDC 270 .

[0048] Examples of the oscillation period D[n] and the delayed oscillation period D[nk] of the oscillation signal 131 are shown in Figure 5 The shapes of the oscillation period D[n] and the delayed oscillation period D[nk] are essentially the same - just offset by k TDC periods. Figure 5 Also illustrated is the fine grid of the TDC 270 , which allows the actual cycle time of the oscillating signal 131 to be determined with high accuracy.

[0049] Based on the above two quantities, TDC 270 outputs an estimate M[n] of the DCO period, ie, the actual period time of oscillation signal 131 .

[0050] An exemplary implementation of TDC 270 as flash TDC 470 is shown in Figure 4 The flash TDC 470 includes a delay line 410 having a plurality of delay elements 415 - 1 , 415 - 2 , . . . , 415 - n . The plurality of delay elements 415 - 1 , 415 - 2 , . . . , 415 - n iteratively delay an oscillation period D[n] of the oscillation signal 131 to generate a delayed oscillation period of the oscillation signal 131 .

[0051] In addition, the flash TDC 470 includes a plurality of flip-flop circuits 420 - 1 , 420 - 2 , . . . , 420 - n . Each of the plurality of flip-flop circuits 420 - 1 , 420 - 2 , . . . , 420 - n receives one of the delayed oscillation period D[nk] and the delayed oscillation period of the oscillation signal 131 .

[0052] The plurality of flip-flop circuits 420-1, 420-2, ..., 420-n output binary values ​​based on the respective time differences between the delayed oscillation period D[nk] and one of the delayed oscillation periods of the oscillation signal 131. These binary values ​​are provided to a decoder 430, which is configured to generate an output signal indicative of an actual cycle time of the oscillation signal 131.

[0053] Instead of one flip-flop circuit per delay element, also a plurality of flip-flop circuits can be used respectively.Thereby, a random flash TDC is provided which can further increase the time resolution of the TDC.

[0054] However, be careful Figure 2 and Figure 3 The TDC 270 shown in FIG. 2 is not shown as a flash TDC. In general, any TDC technology (architecture) can be used for the TDC 270 .

[0055] As noted above, the sampling frequency of the TDC 270 may be substantially equal to the oscillation frequency of the oscillation signal 131 , or much lower than the oscillation frequency of the oscillation signal 131 in order to achieve low power consumption of the TDC 270 .

[0056] Return to reference Figure 2 The second loop 220 further comprises a combiner 280 (eg an adder) which combines the TDC output signal with another signal 102 indicating a nominal period time of the oscillating signal 131 so as to generate a signal 121 indicating a timing error of the period time of the oscillating signal 131 .

[0057] This signal is then continuously integrated by integrator 290 to generate correction signal 122 .

[0058] The combiner (adder) 250 combines the output signal 161 of the loop filter 260 with the correction signal 122 to generate the control signal 151 for the DCO 250 .

[0059] Combining the first (conventional) DPLL 210 and the second phase noise cancellation loop 220 results in the following DCO cycle time, i.e. the actual cycle time of the oscillating signal 131:

[0060] T DPLL_inst =T DPLL_nominal +ΔT PN (t)-ΔT PN(t-τ)+ΔT TDC_Q (t) (4),

[0061] Where ΔT PN (t-τ) represents the delayed phase noise timing error (i.e., the delayed timing error of the cycle time of the oscillation signal 131), τ represents the phase noise cancellation delay (i.e., the delay of the second loop 220), and ΔT TDC_Q (t) represents the quantization error of the self-triggered TDC 270.

[0062] As is apparent from expression (4), the effectiveness of phase noise cancellation is not determined by the level of phase noise (in the first loop 210 ), but by the quantization of the self-triggered TDC 270 and the delay of the phase noise cancellation loop 220 .

[0063] Based on expression (4), the output frequency of the DPLL, that is, the oscillation frequency of the oscillation signal 131 is as follows:

[0064]

[0065] where PN(t-τ) represents the delayed estimate of the phase noise of the DPLL (i.e., the delayed phase noise of the first loop 210), and PN TDC_Q (t) represents the phase noise due to the quantization error of the self-triggered TDC 270 .

[0066] This corresponds to filtering the phase noise by a high-pass filter:

[0067] PN(t)-PN(t-τ)+PN TDC_Q (t)=PN(t)·(δ(t)-δ(t-τ))+PN TDC_Q (t) = PN (t) * h (t, τ) + PN TDC_Q (t) (6)

[0068]

[0069] The amplitude of this filter is given by:

[0070] |H(f,τ)| 2 =|1-e -j2πfτ | 2 =2·(1-cos(2πfτ)) (8)

[0071] An exemplary filter response is Figure 8 Medium picture. Figure 8 The graph shows the phase noise decay with the oscillation frequency. Figure 8 In the example of FIG. 1 , a phase noise cancellation delay of τ=20 ns (i.e., the delay of the second loop 220) is assumed. Figure 8It is evident that high attenuation is achieved for frequencies below 1 MHz, which is the bandwidth of the DPLL (ie, the first loop 210).

[0072] The spectral density S of the PLL phase noise θ (f) (i.e., the spectral density of the phase noise of the oscillating signal 131) is given by:

[0073]

[0074] Where S PN (f) represents the spectral density of the phase noise of the PLL 200 without the second loop 220, and S TDC_Q (f) represents the spectral density of the phase noise caused by the quantization error of the self-triggered TDC 270.

[0075] The resulting PLL phase noise is Fig. 9 910. For reference, the phase noise of a conventional PLL is also illustrated by line 920. Fig. 9 It is clearly seen that for frequencies below 1 MHz, i.e. for frequencies below the bandwidth of the first loop, the phase noise is greatly reduced (by about 20 dBc). In this region, the phase noise of the PLL is mainly due to the quantization error of the self-triggered TDC 270. For higher frequencies, the phase noise is essentially equal to the one of the conventional PLL. This is due to the phase noise cancellation delay. In order to achieve better phase noise cancellation, the phase noise cancellation delay needs to be reduced.

[0076] exist Fig. 9 In the example of FIG. 1 , it is assumed that the second loop 220 additionally includes Figure 6 The filter shown in FIG. 1 is used to bandpass filter the correction signal. Figure 6 The PLL 600 shown in FIG. 1 is substantially equivalent to Figure 2 . However, the second loop 220 additionally includes a filter 695 configured to bandpass filter the correction signal 122. For example, the filter 695 can be configured to lowpass filter the correction signal. Therefore, due to the removal of high frequency components from the correction signal 122, improved phase noise cancellation can be achieved. The resulting filter correction signal 122' is combined with the output signal 161 of the loop filter 260.

[0077] Another alternative implementation of the second loop is Figure 7 Medium picture. Figure 7 The PLL 700 shown in FIG. 7 is substantially equivalent to Figure 2However, the second loop 720 of PLL 700 includes an additional combiner 790 instead of integrator 290. Combiner 790 is configured to generate samples of correction signal 122 by combining signal 121 indicating a timing error of a cycle time of oscillation signal 131 with a previous sample of correction signal 122.

[0078] like Figure 7 As shown in , an additional delay element 795 can be coupled between the output and input of the combiner 790, so that the second delay element 795 delays a previous sample of the correction signal 122 so that it can be combined with a current (subsequent) sample of the signal 121.

[0079] The first loop 210 of the PLL described above may also include other elements (e.g., frequency dividers) of a conventional PLL. In addition, the DCO 230 may be replaced by a VCO. In the case of using a VCO, the PLL may additionally include a digital-to-analog converter (DAC). The DAC may, for example, be arranged in the second loop 220 to convert the digital correction signal 122 into an analog representation. The analog correction signal may then be combined with an analog signal 161 (i.e., the first loop is analog) from the loop filter of the first loop. Alternatively, the DAC may be arranged between the combiner 150 and the VCO so that the DAC converts the digital control signal 151 output by the combiner 250 into an analog control voltage for the VCO. Practical functions such as calibration or burr elimination may also be added to the PLL. However, the basic principle of phase noise elimination remains unchanged for these modified PLLs.

[0080] For all PLLs disclosed herein, the phase noise is determined by the phase noise of the first loop, the quantization error of the self-triggered TDC, and the phase noise cancellation delay.

[0081] Examples of implementations using a PLL according to one or more aspects of the proposed architecture or one or more of the examples described above are described in Fig.10 Medium picture. Fig.10 An example of a mobile device 1000 (eg, a mobile phone, a smartphone, a tablet or a laptop) comprising a PLL 1010 according to the examples described herein is schematically illustrated.

[0082] For example, the transmitter 1030 may include the PLL 1010. The transmitter 1030 may additionally include a mixing circuit (not shown) configured to up-convert a baseband transmit signal using a signal derived from an oscillating signal (generated by the PLL 1010).

[0083] Alternatively or additionally, the mobile device 1000 may include a receiver 1040, which may include the PLL 1010. The receiver 1040 may additionally include a mixing circuit (not shown) configured to down-convert a radio frequency reception signal using a signal derived from an oscillating signal (generated by the PLL 1010).

[0084] Where the mobile device 1000 includes a transmitter 1030 and a receiver 1040, they may share a common PLL for generating an oscillating signal. The signals for their respective mixing circuits may be derived from the oscillating signal of the PLL, for example by means of a frequency divider and / or one or more filters and delay circuits.

[0085] At least one antenna element 1020 of the mobile device 1000 may be coupled to a transmitter 1030 , or to a receiver 1040 .

[0086] To this end, a mobile device may be provided to implement a transmission and / or reception signal with improved EVM caused by a low noise oscillation signal provided by the PLL 1010 .

[0087] The proposed PLL is not limited to mobile devices. The proposed PLL can be used in any electronic device for generating an oscillating signal with improved phase noise.

[0088] An example of a method 1100 for a PLL is Fig.11 1100 is illustrated by a flow chart. The PLL includes a first loop and a second loop, wherein the first loop includes a controlled oscillator and a phase detector. The method 1100 includes generating 1102 an oscillation signal using the controlled oscillator and generating 1104 a first signal indicating a timing difference between a reference signal and the oscillation signal using the phase detector. Additionally, the method 1100 includes generating 1106 a second signal indicating a timing error of a cycle time of the oscillation signal using the second loop. The method 1100 also includes generating 1108 a correction signal based on the second signal using the second loop. Additionally, the method 1100 includes generating 1110 a control signal for the controlled oscillator by combining the correction signal with a third signal derived from the first signal.

[0089] More details and aspects of the method are combined with the proposed concept or one or more examples described above (e.g. Figure 1-10 The method may include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more examples described above.

[0090] The examples described in this article can be summarized as follows:

[0091] Example 1 is a phase-locked loop, comprising: a first loop including a controlled oscillator and a phase detector, wherein the controlled oscillator is configured to generate an oscillation signal, and wherein the phase detector is configured to generate a first signal indicating a timing difference between a reference signal and the oscillation signal; a second loop configured to generate a second signal indicating a timing error of a cycle time of the oscillation signal based on the oscillation signal, and to generate a correction signal based on the second signal; and a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

[0092] In Example 2, the controlled oscillator in the phase-locked loop of Example 1 is configured to generate the oscillation signal based on the control signal.

[0093] In Example 3, the second loop in the phase-locked loop as described in Example 1 or Example 2 includes a time-to-digital converter configured to generate a fourth signal indicating an actual cycle time of the oscillating signal based on the oscillating signal and a delayed replica of the oscillating signal.

[0094] In Example 4, a sampling frequency of the time-to-digital converter in the phase-locked loop of Example 3 is at least 20 times lower than an oscillation frequency of the oscillation signal.

[0095] In Example 5, the second loop in the phase-locked loop as described in Example 3 or Example 4 further includes a delay element configured to generate a delayed replica of the oscillating signal by delaying the oscillating signal.

[0096] In Example 6, the second loop in the phase-locked loop as described in any one of Examples 3 to 5 also includes a second combiner configured to generate the second signal by combining the fourth signal and a fifth signal indicating a nominal cycle time of the oscillation signal.

[0097] In Example 7, the second loop in the phase-locked loop as described in Example 6 further includes an integrator configured to generate the correction signal by continuously integrating the second signal.

[0098] In Example 8, the second loop in the phase-locked loop of Example 6 further includes a third combiner configured to generate a sample of the correction signal by combining the second signal with a previous sample of the correction signal.

[0099] In Example 9, the second loop in the phase-locked loop of Example 8 further includes a second delay element coupled between the output and the input of the third combiner, wherein the delay element is configured to delay a previous sample of the correction signal.

[0100] In Example 10, the second loop in the phase-locked loop as described in any one of Examples 7 to 9 further includes a filter configured to bandpass filter the correction signal.

[0101] In Example 11, the first loop in the phase-locked loop as in any preceding example further comprises a loop filter configured to generate the third signal by filtering the first signal.

[0102] In Example 12, the phase detector in the phase locked loop as in any of the preceding examples is a time to digital converter.

[0103] In Example 13, the controlled oscillator in the phase locked loop as in any preceding example is a digitally controlled oscillator.

[0104] In Example 14, the controlled oscillator in the phase-locked loop as described in any one of Examples 1 to 12 is a voltage-controlled oscillator.

[0105] Example 15 is a transmitter comprising a phase-locked loop according to any one of Examples 1 to 14.

[0106] In Example 16, the transmitter of Example 15 further includes a mixing circuit configured to up-convert a baseband transmit signal using a signal derived from the oscillating signal.

[0107] Example 17 is a receiver comprising a phase-locked loop according to any one of Examples 1 to 14.

[0108] In Example 18, the receiver of Example 17 further includes a mixing circuit configured to down-convert a radio frequency receive signal using a signal derived from the oscillating signal.

[0109] Example 19 is a mobile device comprising at least one of the transmitter according to any one of Examples 15 and 16 and the receiver according to any one of Examples 17 and 18.

[0110] In Example 20, the mobile device of Example 19 further comprises at least one antenna element coupled to the transmitter or coupled to the receiver.

[0111] Example 21 is a method for a phase-locked loop comprising a first loop and a second loop, wherein the first loop comprises a controlled oscillator and a phase detector, the method comprising: generating an oscillation signal using the controlled oscillator; generating a first signal indicating a timing difference between a reference signal and the oscillation signal using the phase detector; generating a second signal indicating a timing error of a cycle time of the oscillation signal using the second loop; generating a correction signal based on the second signal using the second loop; and generating a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

[0112] In Example 22, generating the oscillation signal in the method of Example 21 is based on the control signal.

[0113] In Example 23, generating the second signal in the method of Example 21 or Example 22 includes generating a fourth signal indicating an actual cycle time of the oscillating signal based on the oscillating signal and a delayed replica of the oscillating signal.

[0114] In Example 24, generating the second signal in the method of Example 23 further comprises generating a delayed replica of the oscillating signal by delaying the oscillating signal.

[0115] In Example 25, generating the second signal in the phase-locked loop as described in Example 23 or Example 24 further includes combining the fourth signal and a fifth signal indicating a nominal cycle time of the oscillation signal.

[0116] In Example 26, generating the correction signal in the method as described in Example 25 further includes continuously integrating the second signal.

[0117] In Example 27, generating the correction signal in the method of Example 25 further comprises generating samples of the correction signal by combining the second signal with previous samples of the correction signal.

[0118] In Example 28, generating the correction signal in the method as described in Example 26 or Example 27 also includes bandpass filtering the correction signal.

[0119] In Example 29, the method as in any preceding example further comprises generating the third signal by filtering the first signal.

[0120] Aspects and features mentioned and described in conjunction with one or more of the previously detailed examples and figures may also be combined with one or more other examples in order to replace similar features of the other examples or to additionally introduce the features to the other examples.

[0121] Examples may also be or may relate to a computer program with a program code, which, when executed on a computer or processor, is used to perform one or more of the above methods. The steps, operations or processes of various above methods may be performed by a programmed computer or processor. Examples may also cover program storage devices, such as digital data storage media, which are machine, processor or computer readable and encode machine executable, processor executable or computer executable instruction programs. Instructions execute or cause some or all of the actions of the above methods to be performed. Program storage devices may include or may be, for example, digital memories, magnetic storage media such as disks and tapes, hard drives or optically readable digital data storage media. Other examples may also cover computers, processors or control units programmed to perform the actions of the above methods or (field) programmable logic arrays ((field) programmable logic arrays, (F) PLAs) or (field) programmable gate arrays ((field) programmable gate arrays, (F) PGAs) programmed to perform the actions of the above methods.

[0122] The description and drawings are merely illustrative of the principles of the present disclosure. In addition, most of the examples recorded herein are explicitly intended to be used only for teaching purposes to help readers understand the principles of the present disclosure and the concepts contributed by the inventors to advance the prior art. All statements recording the principles, aspects and examples of the present disclosure and their specific examples herein are intended to cover their equivalents.

[0123] The functions of the various elements shown in the drawings, including any functional blocks labeled as "means", "means for providing sensor signals", "means for generating transmission signals", etc., may be implemented in the form of dedicated hardware, such as "signal providers", "signal processing units", "processors", "controllers", etc., as well as hardware capable of executing software in conjunction with appropriate software. When provided by a processor, these functions may be provided by a single dedicated processor, by a single shared processor, or by multiple individual processors, some or all of which may be shared. However, the term "processor" or "controller" is by no means limited to hardware that is only capable of executing software, but may include digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), read only memory (ROM), random access memory (RAM) and non-volatile storage devices for storing software. Other hardware, conventional and / or custom, may also be included.

[0124] Block diagrams, for example, may illustrate high-level circuit diagrams that implement the principles of the present disclosure. Similarly, flow charts, job diagrams, state transition diagrams, pseudocodes, and the like may represent various processes, operations, or steps, which, for example, may be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or in the claims may be implemented by an apparatus having means for performing each of the individual actions of these methods.

[0125] It is to be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a specific order, unless otherwise explicitly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order, unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Such sub-actions may be included in a part of the disclosure of this single action, unless explicitly excluded.

[0126] In addition, the attached claims are hereby incorporated into the detailed description, wherein each claim may be independently used as a separate example. Although each claim may be independently used as a separate example, it is noted that although a dependent claim may refer to a specific combination with one or more other claims in a claim, other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly proposed herein unless a specific combination is stated to be undesirable. In addition, it is desirable to also include the features of a claim to any other independent claim, even if the claim is not directly dependent on the independent claim.

Claims

1. A phase-locked loop (100), include: A first loop (110) comprising a controlled oscillator (130) and a phase detector (140), wherein the controlled oscillator (130) is configured to generate an oscillation signal (131), and wherein the phase detector (140) is configured to generate a first signal (141) indicating a timing difference between a reference signal (101) and the oscillation signal (131); a second loop (120) configured to generate a second signal (121) based on the oscillation signal (131), and to generate a correction signal (122) based on the second signal (121), wherein the second signal (121) indicates a timing error of a cycle time of the oscillation signal; as well as a combiner (150) configured to generate a control signal (151) for the controlled oscillator (130) by combining the correction signal (122) and a third signal (161) derived from the first signal (141), The second loop (120) comprises: A time-to-digital converter is configured to generate a fourth signal based on the oscillating signal (131) and a delayed copy of the oscillating signal (131), the fourth signal indicating an actual cycle time of the oscillating signal.

2. The phase-locked loop of claim 1, wherein the controlled oscillator (130) is configured to generate the oscillation signal (131) based on the control signal (151).

3. The phase-locked loop of claim 1, wherein a sampling frequency of the time-to-digital converter is at least 20 times lower than an oscillation frequency of the oscillation signal.

4. The phase-locked loop of claim 1, wherein the second loop (120) further comprises: include: A delay element is configured to generate a delayed replica of the oscillating signal (131) by delaying the oscillating signal (131).

5. The phase-locked loop of claim 1, wherein the second loop (120) further comprises: include: A second combiner is configured to generate the second signal (121) by combining the fourth signal and a fifth signal, the fifth signal indicating a nominal cycle time of the oscillating signal.

6. The phase-locked loop of claim 5, wherein the second loop (120) further comprises: include: An integrator is configured to generate the correction signal (122) by continuously integrating the second signal (121).

7. The phase-locked loop of claim 5, wherein the second loop (120) further comprises: include: A third combiner is configured to generate samples of the correction signal (122) by combining the second signal (121) with previous samples of the correction signal (122).

8. The phase-locked loop of claim 7, wherein the second loop (120) further comprises: include: A second delay element is coupled between the output and the input of the third combiner, wherein the delay element is configured to delay a previous sample of the correction signal (122).

9. The phase-locked loop of claim 6, wherein the second loop (120) further comprises: include: A filter is configured to bandpass filter the correction signal (122).

10. The phase locked loop of claim 1 or claim 2, wherein the first loop (110) further comprises a loop filter configured to generate the third signal (161) by filtering the first signal (131).

11. A phase locked loop as claimed in claim 1 or claim 2, wherein the phase detector (140) is a time to digital converter.

12. A phase locked loop as claimed in claim 1 or claim 2, wherein the controlled oscillator (130) is a numerically controlled oscillator.

13. A phase locked loop as claimed in claim 1 or claim 2, wherein the controlled oscillator (130) is a voltage controlled oscillator.

14. A transmitter (1030) comprising the phase locked loop (1010) according to claim 1.

15. The transmitter according to claim 14, further comprising: include: A mixing circuit is configured to up-convert a baseband transmit signal using a signal derived from the oscillating signal.

16. A receiver (1040) comprising the phase locked loop (1010) according to claim 1.

17. The receiver of claim 16, further comprising: include: A mixing circuit is configured to down-convert a radio frequency reception signal using a signal derived from the oscillating signal.

18. A method (1100) for a phase-locked loop, the phase-locked loop comprising a first loop and a second loop, wherein the first loop comprises a controlled oscillator and a phase detector, the method include: generating (1102) an oscillating signal using the controlled oscillator; generating (1104) a first signal using the phase detector, the first signal indicating a timing difference between a reference signal and the oscillating signal; generating (1106) a second signal using the second loop, the second signal indicating a timing error in a period time of the oscillating signal; generating (1108) a correction signal based on the second signal using the second loop; as well as generating (1110) a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal, Wherein generating (1106) the second signal comprises: generating a fourth signal based on the oscillating signal and a delayed replica of the oscillating signal, the fourth signal indicating an actual cycle time of the oscillating signal.

19. The method of claim 18, wherein generating (1102) the oscillating signal is based on the control signal.

20. The method of claim 18, wherein generating (1106) the second signal further comprises generating a delayed replica of the oscillating signal by delaying the oscillating signal.

21. The method of claim 18, wherein generating (1106) the second signal further comprises combining the fourth signal with a fifth signal, the fifth signal being indicative of a nominal cycle time of the oscillating signal.

22. The method of claim 21, wherein generating (1108) the correction signal further comprises continuously integrating the second signal.

23. The method of claim 21, wherein generating (1108) the correction signal further comprises: include: Samples of the correction signal are generated by combining the second signal and previous samples of the correction signal.

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