A parameter detection circuit and method

Abstract

A parameter detection circuit and method provide two different reference voltage signals by different circuits, and detect another original reference voltage source through one of the reference voltage signals to determine whether there is a fault in the other original reference voltage source, so as to improve the detection accuracy of the parameter detection circuit.

Description

Technical Field

[0001] This application belongs to the technical field of electronic circuits, and particularly relates to a parameter detection circuit and method. Background Art

[0002] Currently, in the field of electric energy metering, a sampling network is usually used to sample the measured voltage and current signals, and then input them into an analog-to-digital converter to convert them into digital signals. Finally, a signal processor is used to process the digital signals to obtain the measurement values. However, when the parameters of the components in the sampling network change due to a fault, a sampling error will occur, and ultimately a measurement error will occur. For this situation, the measurement system needs to be able to detect it and perform corresponding processing.

[0003] A detection signal generation circuit is usually used to detect the sampling network, which can determine whether the parameters of the sampling network have changed, and then locate the fault source. Specifically, by introducing an additional detection signal generated based on a reference voltage source into the nodes of the sampling network, and analyzing the measurement results of the detection signal by the signal processor, it is determined whether the parameters of the sampling network have changed, and then the fault source is located.

[0004] In the traditional technology, the reference voltage source provides the reference voltage for both the detection signal generation circuit and the analog-to-digital converter. To ensure the accuracy of the system, it is usually required that the reference voltage has a fast response and low noise. Specifically, the reference voltage source needs to be connected to an external pin, and a capacitor is added to the external pin. Since the reference voltage source is connected to the external pin, it is more likely to be damaged when the chip is working, resulting in a change in the voltage value of the reference voltage source. However, when the voltage value of the reference voltage source changes, the detection signal generated by the detection signal generation circuit will change proportionally, and the digital signal converted by the analog-to-digital converter will change inversely, ultimately making the detection value remain unchanged and the same as the reference value.

[0005] It can be seen that the traditional measurement system cannot detect the fault that the reference voltage source has changed, and the change in the reference voltage value provided by the reference voltage source cannot be recognized. Summary of the Invention

[0006] The purpose of this application is to provide a parameter detection circuit and method with a reference detection function, aiming to solve the problem that the traditional parameter detection circuit cannot detect the fault of the reference voltage source.

[0007] A parameter detection circuit includes:

[0008] A first reference voltage source for providing a first reference voltage;

[0009] A crystal oscillator for generating a clock reference signal;

[0010] A phase-locked loop, connected to the crystal oscillator, generates a second reference voltage according to the clock reference signal;

[0011] A detection signal generation circuit;

[0012] A selection switch, connected to the first reference voltage source, the phase-locked loop and the detection signal generation circuit, the selection switch is used to selectively connect the detection signal generation circuit to either the first reference voltage source or the phase-locked loop to provide the first reference voltage or the second reference voltage to the detection signal generation circuit; the detection signal generation circuit is configured to generate a first detection signal and a second detection signal according to the first reference voltage and the second reference voltage respectively;

[0013] A sampling network, used to be connected to the measurement signal and the detection signal generation circuit, and is configured to access the first detection signal and the second detection signal, and output a first detection sampling signal and a second detection sampling signal respectively;

[0014] An analog-to-digital converter, connected to the sampling network and the first reference voltage source, is used to convert the first detection sampling signal and the second detection sampling signal into corresponding digital signals under the condition that the first reference voltage source provides the first reference voltage;

[0015] A signal processor, connected to the analog-to-digital converter, is used to determine whether there is a fault in the first reference voltage source according to the first detection sampling signal and the second detection sampling signal converted into digital signals.

[0016] In one embodiment, the signal processor is specifically configured to determine whether there is a fault in the first reference voltage source according to the change of the calibration value and the detection value of the first detection sampling signal converted into a digital signal and the change of the calibration value and the detection value of the second detection sampling signal converted into a digital signal.

[0017] In one embodiment, the signal processor is further configured to determine whether there is a fault in the sampling network according to the change of the calibration value and the detection value of the first detection sampling signal converted into a digital signal.

[0018] In one embodiment, the sampling network accesses the measurement signal and also outputs a measurement sampling signal, the analog-to-digital converter converts the measurement sampling signal into a digital signal, and the signal processor is further configured to perform power measurement and its calibration according to the first detection sampling signal and / or the second detection sampling signal converted into a digital signal, and the measurement sampling signal.

[0019] In one embodiment, the frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement signal, and are non-integer multiples of the measurement signal.

[0020] In one embodiment, the phase-locked loop and the signal processor are on-chip circuits of an integrated circuit, and at least some of the devices of the first reference voltage source, the crystal oscillator, the detection signal generation circuit, and the sampling network are off-chip circuits of the integrated circuit

[0021] In one embodiment, the phase-locked loop includes a phase detector, a low-pass filter, and a voltage-controlled oscillator. A first input end of the phase detector is connected to an output end of the crystal oscillator. An input end of the low-pass filter is connected to an output end of the phase detector. An output end of the low-pass filter serves as an output end of the phase-locked loop. An input end of the voltage-controlled oscillator is connected to the output end of the low-pass filter, and an output end of the voltage-controlled oscillator is connected to a second input end of the phase detector

[0022] In one embodiment, the crystal oscillator includes a quartz crystal, an inverting amplifier, a feedback resistor, a first load capacitor, and a second load capacitor. Two ends after parallel connection of the quartz crystal, the inverting amplifier, and the feedback resistor are respectively grounded through the first load capacitor and the second load capacitor, and an output end of the inverting amplifier serves as an output end of the crystal oscillator

[0023] In addition, a parameter detection method is provided, including:

[0024] Generating a first detection signal based on a first reference voltage generated by a first reference voltage source and loading the first detection signal onto a sampling network to generate a first detection sampling signal

[0025] Generating a second detection signal based on a second reference voltage generated by a phase-locked loop and loading the second detection signal onto the sampling network to generate a second detection sampling signal, where the phase-locked loop generates the second reference voltage according to a clock reference signal generated by a crystal oscillator

[0026] Based on the first reference voltage, respectively converting the first detection sampling signal and the second detection sampling signal into digital signals

[0027] Determining whether there is a fault in the first reference voltage source according to the first detection sampling signal and the second detection sampling signal that are converted into digital signals

[0028] In one embodiment, the determining whether there is a fault in the first reference voltage source according to the first detection sampling signal and the second detection sampling signal that are converted into digital signals includes:

[0029] Determining whether there is a fault in the first reference voltage source according to changes in calibration values and detection values of the first detection sampling signal converted into a digital signal and changes in calibration values and detection values of the second detection sampling signal converted into a digital signal

[0030] In one embodiment, it further includes determining whether there is a fault in the sampling network according to the change of the calibration value and the detected value of the first detected sampling signal converted into a digital signal.

[0031] In one embodiment, it further includes:

[0032] Loading a measurement signal on the sampling network to generate a measurement sampling signal;

[0033] Based on a first reference voltage, converting the measurement sampling signal into a digital signal;

[0034] Performing power measurement and calibration according to the first detected sampling signal and / or the second detected sampling signal converted into a digital signal, and the measurement sampling signal.

[0035] The above parameter detection circuit and method provide two different reference voltage signals by different circuits, and detect another original reference voltage source through one of the reference voltage signals to determine whether there is a fault in the other original reference voltage source, so as to improve the detection accuracy of the parameter detection circuit. Description of the Drawings

[0036] Figure 1 It is a schematic structural diagram of the parameter detection circuit provided by the embodiment of the present application;

[0037] Figure 2 It is a circuit diagram of the crystal oscillator in the parameter detection circuit provided by the embodiment of the present application;

[0038] Figure 3 It is a circuit diagram of the phase-locked loop in the parameter detection circuit provided by the embodiment of the present application;

[0039] Figure 4 It is a flowchart of the parameter detection method provided by the embodiment of the present application. Detailed Embodiment

[0040] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] It should be noted that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0042] Please refer toFigure 1 In the parameter detection circuit according to the embodiment of the present application, it includes: a first reference voltage source 10 for providing a first reference voltage, a crystal oscillator 20 for generating a clock reference signal, a phase-locked loop 25, a detection signal generation circuit 30, a selection switch 40, a sampling network 50, an analog-to-digital converter 60, and a signal processor 70.

[0043] The phase-locked loop 25 is connected to the crystal oscillator 20 and generates a second reference voltage according to the clock reference signal provided by the crystal oscillator 20. The selection switch 40 is connected to the first reference voltage source 10, the phase-locked loop 25, and the detection signal generation circuit 30. The selection switch 40 is used to selectively connect the detection signal generation circuit 30 to either the first reference voltage source 10 or the phase-locked loop 25 to provide the first reference voltage or the second reference voltage to the detection signal generation circuit 30. The detection signal generation circuit 30 is configured to generate a first detection signal and a second detection signal according to the first reference voltage and the second reference voltage respectively.

[0044] The sampling network 50 is used to be connected to the measurement signal and the detection signal generation circuit 30, and is configured to access the first detection signal and the second detection signal, and output a first detection sampling signal and a second detection sampling signal respectively. The analog-to-digital converter 60 is connected to the sampling network 50 and the first reference voltage source 10, and is used to convert the first detection sampling signal and the second detection sampling signal into corresponding digital signals under the condition that the first reference voltage source 10 provides the first reference voltage. The signal processor 70 is connected to the analog-to-digital converter 60, and is used to determine whether the first reference voltage source 10 has a fault according to the first detection sampling signal and the second detection sampling signal converted into digital signals.

[0045] In this embodiment, the analog-to-digital converter 60 is provided with a reference voltage by the first reference voltage source 10, and the first reference voltage source 10 needs to be connected to an external pin. The detection signal generation circuit 30 can select to be provided with a reference voltage by the first reference voltage source 10 or the phase-locked loop 25 through the selection switch. The crystal oscillator 20, the phase-locked loop 25, and the first reference voltage source 10 are independent circuits, and the probability of simultaneous failure is greatly reduced, improving the reliability of the detection system.

[0046] The working process of the present application is divided into two stages: the calibration stage and the use stage.

[0047] Among them, the calibration stage means that: during the initial factory shipment, the sampling network 50 will be calibrated through the detection signal. The calibration stage is divided into two times: when selecting the first reference voltage source 10 to provide a reference voltage for the detection signal generation circuit 30, calibrate the value of the first detection sampling signal to the calibration value V EDTA0 . When selecting the crystal oscillator 20 and the phase-locked loop 25 as the reference voltage for the detection signal generation circuit 30, calibrate the value of the second detection sampling signal to the calibration value VEDTB0 ; The usage stage means that during the usage process, when the first reference voltage source 10 is selected to provide a reference voltage for the detection signal generation circuit 30, the detected value V of the first detection sampling signal EDTAN is compared with the calibration value V EDTA0 . Periodically, when the crystal oscillator 20 and the phase-locked loop 25 are selected to provide a reference voltage for the detection signal generation circuit 30, the detected value V of the second detection sampling signal EDTBN is compared with the calibration value V EDTB0 .

[0048] Therefore, in one embodiment, the signal processor 70 is specifically configured to determine whether the first reference voltage source 10 has a fault according to the change of the calibration value V EDTA0 and the detected value V EDTAN of the first detection sampling signal converted into a digital signal, and the change of the calibration value V EDTB0 and the detected value V EDTBN of the second detection sampling signal converted into a digital signal. Specifically, if the detected value V EDTAN of the first detection sampling signal of the digital signal is the same as the calibration value V EDTA0 , but the detected value V EDTBN of the second detection sampling signal of the digital signal is different from the calibration value V EDTB0 , it indicates that the first reference voltage source 10 has changed, that is, there is an abnormality and a possible fault.

[0049] The detection signal generation circuit 30 can be a voltage / current generation circuit.

[0050] In addition, in one embodiment, the signal processor 70 is further configured to determine whether the sampling network 50 is abnormal according to the change of the calibration value and the detected value of the first detection sampling signal converted into a digital signal. Specifically, if the detected value V EDTAN of the first detection sampling signal converted into a digital signal is different from the calibration value V EDTA0 , it indicates that the parameters of the sampling network 50 have changed.

[0051] Furthermore, the sampling network 50 accesses the measurement signal and also outputs a measurement sampling signal. The analog-to-digital converter 60 converts the measurement sampling signal into a digital signal. The signal processor is further configured to perform power measurement and its calibration according to the first detection sampling signal and / or the second detection sampling signal converted into a digital signal, and the measurement sampling signal.

[0052] Further, the signal processor 70 processes the first detection sampling signal and the second detection sampling signal that have been converted into digital signals to obtain the amplitude value and phase value of the first detection sampling signal and the amplitude value and phase value of the second detection sampling signal, and determines whether the circuit parameters of the sampling network 50 are abnormal according to at least one of the amplitude value change of the first detection sampling signal, the amplitude value change of the second detection sampling signal, the phase change of the first detection sampling signal, and the phase change of the second detection sampling signal. And calibrate the measurement sampling signal according to the abnormal situation of the circuit parameters of the sampling network 50, and then perform power measurement with the accurate measurement sampling signal.

[0053] In one embodiment, the frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement sampling signal and are non-integer multiples of the measurement signal.

[0054] In one embodiment, the phase-locked loop 25 and the signal processor 70 are on-chip circuits of an integrated circuit, and at least some of the devices of the first reference voltage source 10, the crystal oscillator 20, the detection signal generation circuit 30, and the sampling network 50 are off-chip circuits of the integrated circuit. Among them, the external capacitor in the first reference voltage source 10 and the pin connecting the capacitor are off-chip circuits of the integrated circuit.

[0055] Please refer to Figure 2 , in one embodiment, the crystal oscillator 25 includes a quartz crystal, an inverting amplifier U1, a feedback resistor R0, a first load capacitor C0, and a second load capacitor C1. The two ends after the parallel connection of the quartz crystal, the inverting amplifier U1, and the feedback resistor R0 are grounded through the first load capacitor C0 and the second load capacitor C1 respectively. The output end of the inverting amplifier U1 is used as the output end of the crystal oscillator 25 to output a clock reference signal CLK. The quartz crystal is an off-chip device of the integrated circuit and is a flat piezoelectric resistance material. This material allows the conversion of mechanical energy and electrical energy, and this energy exchange is most efficient at a certain special frequency, which is called the resonance frequency. The quartz crystal behaves as an inductor between the series resonance frequency and the parallel resonance frequency, and an oscillator can be formed with this inductor and a capacitive amplifier. The feedback resistor R_{0} is used to introduce a DC bias; the inverting amplifier U1 provides the necessary gain and generates a 180° phase shift; the load capacitors C_{0}, C_{1} set the feedback factor of the circuit, and combine with the inductive reactance of the quartz crystal to generate an additional 180° phase shift required for oscillation, generating a high-precision clock reference signal CLK.

[0056] Please refer to Figure 3, in one embodiment, the phase-locked loop 25 includes a phase detector 251, a low-pass filter 252, and a voltage-controlled oscillator 253. The first input terminal of the phase detector 251 is connected to the output terminal of the crystal oscillator 20. The input terminal of the low-pass filter 252 is connected to the output terminal of the phase detector 251. The output terminal of the low-pass filter 252 serves as the output terminal of the phase-locked loop 25. The input terminal of the voltage-controlled oscillator 253 is connected to the output terminal of the low-pass filter 252. The output terminal of the voltage-controlled oscillator 253 is connected to the second input terminal of the phase detector 251. The feedback system composed of the phase detector 251, the low-pass filter 252, and the voltage-controlled oscillator 253. The phase detector 251 compares the phase of the feedback signal V OUT of the voltage-controlled oscillator 253 and the phase of the clock reference signal CLK, generates an error, and the error is filtered by the low-pass filter 252 to change the oscillation frequency of the voltage-controlled oscillator 253 until the phases are aligned, that is, the loop is locked. Among them, the output V PD of the phase detector 251 is composed of a DC component (desired) and a high-frequency component (undesired). The low-pass filter 252 is used to suppress the high-frequency components of the output of the phase detector 251 and only send the DC component V CONT to the voltage-controlled oscillator 253. The voltage-controlled oscillator 253 generates a specific output frequency according to the input control voltage. In this embodiment, the output voltage V CONT of the low-pass filter 252 is used as the second reference voltage.

[0057] In other embodiments, the first and second reference voltages can also be generated by a reference circuit composed of semiconductor devices.

[0058] In addition, please refer to Figure 4 , and a parameter detection method is also provided, including the following steps:

[0059] Step S110, generating a first detection signal based on the first reference voltage generated by the first reference voltage source and loading it onto the sampling network to generate a first detection sampling signal;

[0060] Step S120, generating a second detection signal based on the second reference voltage generated by the phase-locked loop and loading it onto the sampling network to generate a second detection sampling signal. The phase-locked loop generates the second reference voltage according to the clock reference signal generated by the crystal oscillator;

[0061] Step S130, converting the first detection sampling signal and the second detection sampling signal into digital signals based on the first reference voltage;

[0062] Step S140, determining whether the first reference voltage source has a fault according to the first detection sampling signal and the second detection sampling signal converted into digital signals.

[0063] In one embodiment, determining whether a first reference voltage source has a fault based on a first detection sampling signal and a second detection sampling signal converted into digital signals includes:

[0064] Determining whether the first reference voltage source has a fault based on the change between the calibrated value and the detected value of the first detection sampling signal converted into a digital signal and the change between the calibrated value and the detected value of the second detection sampling signal converted into a digital signal.

[0065] In one embodiment, it further includes determining whether a sampling network has a fault based on the change between the calibrated value and the detected value of the first detection sampling signal converted into a digital signal.

[0066] In one embodiment, it further includes:

[0067] Loading a measurement signal on the sampling network to generate a measurement sampling signal;

[0068] Converting the measurement sampling signal into a digital signal based on the first reference voltage;

[0069] Performing power measurement and calibration based on the first detection sampling signal and / or the second detection sampling signal converted into digital signals and the measurement sampling signal.

[0070] The above-mentioned parameter detection circuit and method provide two different reference voltage signals by different circuits, and detect another original reference voltage source through one of the reference voltage signals to determine whether the other original reference voltage source has a fault, so as to improve the detection accuracy of the parameter detection circuit.

[0071] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A parameter detection circuit, characterized in that Comprising: A first reference voltage source for providing a first reference voltage; A crystal oscillator for generating a clock reference signal; A phase-locked loop connected to the crystal oscillator for generating a second reference voltage according to the clock reference signal; A detection signal generation circuit; A selection switch connected to the first reference voltage source, the phase-locked loop and the detection signal generation circuit, the selection switch being configured to selectively connect either the first reference voltage source or the phase-locked loop to the detection signal generation circuit to provide the first reference voltage or the second reference voltage to the detection signal generation circuit; The detection signal generation circuit is configured to generate a first detection signal and a second detection signal according to the first reference voltage and the second reference voltage respectively; A sampling network for connecting to a measurement signal and the detection signal generation circuit, configured to access the first detection signal and the second detection signal and output a first detection sampling signal and a second detection sampling signal respectively; An analog-to-digital converter connected to the sampling network and the first reference voltage source, for converting the first detection sampling signal and the second detection sampling signal into corresponding digital signals under the condition that the first reference voltage source provides the first reference voltage; And A signal processor connected to the analog-to-digital converter, for determining whether the first reference voltage source is abnormal according to the first detection sampling signal and the second detection sampling signal converted into digital signals; Specifically, the signal processor is configured to determine whether the first reference voltage source is abnormal according to the change of the calibration value and the detection value of the first detection sampling signal converted into a digital signal and the change of the calibration value and the detection value of the second detection sampling signal converted into a digital signal; The signal processor is further configured to determine whether the sampling network is abnormal according to the change of the calibration value and the detection value of the first detection sampling signal converted into a digital signal.

2. The parameter detection circuit according to claim 1, wherein The sampling network accesses the measurement signal and also outputs a measurement sampling signal, the analog-to-digital converter converts the measurement sampling signal into a digital signal, and the signal processor is further configured to perform power measurement and its calibration according to the first detection sampling signal and / or the second detection sampling signal converted into digital signals, and the measurement sampling signal.

3. The parameter detection circuit according to claim 2, wherein The frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement signal and are non-integer multiples of the measurement signal.

4. The parameter detection circuit according to claim 1, characterized in that, The phase-locked loop and the signal processor are on-chip circuits of an integrated circuit, and at least some of the devices of the first reference voltage source, the crystal oscillator, the detection signal generation circuit and the sampling network are off-chip circuits of the integrated circuit.

5. The parameter detection circuit according to any one of claims 1 to 4, characterized in that The phase-locked loop includes a phase detector, a low-pass filter and a voltage-controlled oscillator. The first input terminal of the phase detector is connected to the output terminal of the crystal oscillator, the input terminal of the low-pass filter is connected to the output terminal of the phase detector, the output terminal of the low-pass filter serves as the output terminal of the phase-locked loop, the input terminal of the voltage-controlled oscillator is connected to the output terminal of the low-pass filter, and the output terminal of the voltage-controlled oscillator is connected to the second input terminal of the phase detector.

6. The parameter detection circuit according to any one of claims 1 to 4, characterized in that, The crystal oscillator includes a quartz crystal, an inverting amplifier, a feedback resistor, a first load capacitor, and a second load capacitor. Both ends of the parallel connection of the quartz crystal, the inverting amplifier, and the feedback resistor are grounded through the first load capacitor and the second load capacitor respectively. The output end of the inverting amplifier serves as the output end of the crystal oscillator.

7. A parameter detection method, characterized in that, Comprising: Generating a first detection signal based on a first reference voltage generated by a first reference voltage source and loading the first detection signal onto a sampling network to generate a first detection sampling signal; Generating a second detection signal based on a second reference voltage generated by a phase-locked loop and loading the second detection signal onto the sampling network to generate a second detection sampling signal, where the phase-locked loop generates the second reference voltage according to a clock reference signal generated by a crystal oscillator; Converting the first detection sampling signal and the second detection sampling signal into digital signals respectively based on the first reference voltage; Determining whether the first reference voltage source is abnormal according to the first detection sampling signal and the second detection sampling signal converted into digital signals; The determining whether the first reference voltage source is abnormal according to the first detection sampling signal and the second detection sampling signal converted into digital signals includes: Determining whether the first reference voltage source is abnormal according to the change between the calibration value and the detection value of the first detection sampling signal converted into a digital signal and the change between the calibration value and the detection value of the second detection sampling signal converted into a digital signal.

8. The parameter detection method according to claim 7, characterized in that It further includes determining whether the sampling network is abnormal according to the change between the calibration value and the detection value of the first detection sampling signal converted into a digital signal.

9. The parameter detection method according to claim 7, characterized in that, It further includes: Loading a measurement signal onto the sampling network to generate a measurement sampling signal; Converting the measurement sampling signal into a digital signal based on the first reference voltage; Performing power measurement and calibration according to the first detection sampling signal and / or the second detection sampling signal converted into digital signals, and the measurement sampling signal.

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