Method and system for compensating for degradation of resistive memory devices

Abstract

A memory controller can control a resistive memory device including a memory cell, can control the resistive memory device to program the memory cell to a first resistance state, control the resistive memory device to read data from the programmed memory cell, receive a bit error rate (BER) of the memory cell occurring in a read operation from the resistive memory device, can determine the number of programming operations performed on the memory cell corresponding to the BER, and can control the programming of the memory cell to the first resistance state by using a write current having a current level higher than a current level of a minimum write current based on the determined number of programming operations, the minimum write current being necessary to change the memory cell to the first resistance state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0092049 filed on August 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to nonvolatile memory devices, and more particularly, to a method of compensating for degradation of a resistive memory device. Background Art

[0004] Resistive memory devices such as phase change RAM (PRAM), resistive RAM (RRAM) and magnetic RAM (MRAM) are called non-volatile memory devices. In such a resistive memory device, a variable resistance device that stores data according to a change in resistance conditions is used as a memory cell. The resistive memory device includes a cross-point type resistive memory device. The cross-point type resistive memory device can be formed by placing a memory cell of the memory device at an intersection where a plurality of bit lines and a plurality of word lines intersect each other. The resistive memory device can access the memory cell therein by applying a voltage to two opposite terminals of the memory cell, and the accessed memory cell can store a logic "1 (set data)" (low resistance state) or a logic "0 (reset data)" (high resistance state) with reference to the threshold resistance of the memory cell.

[0005] Criteria in resistive memory devices are the retention time for which data can be retained and the endurance level for which normal operations can be performed without being worn out when data is written. The data retention and endurance of a resistive memory device may depend on an environment that degrades the characteristics of the memory cell, such as high temperature and / or the number of programming times. Due to degradation of the memory cell, the sensing margin between set data logic "1" and reset data logic "0" may be reduced. As a result, time overhead or multiple bit errors may result, and the time overhead means that the sensing of the set data or reset data becomes less reliable or slower. The degradation of the resistive memory device results in a reduction in the capacity of a storage device including the resistive memory device. Summary of the invention

[0006] The inventive concept provides methods and systems for compensating for degradation of a resistive memory device.

[0007] According to some example embodiments conceived in the present invention, a method of operating a memory controller may include: controlling a resistive memory device to program a plurality of memory cells to a first resistance state, controlling the resistive memory device to perform a read operation on the plurality of memory cells programmed to the first resistance state, receiving an indicator indicating a degree of degradation of the plurality of memory cells from the resistive memory device, and, based on the indicator indicating the degree of degradation, controlling the plurality of memory cells to be programmed to the first resistance state based on using a write current having a current level greater than a minimum write current, the minimum write current being necessary to program the plurality of memory cells to the first resistance state, wherein the memory controller is configured to control the resistive memory device, the resistive memory device including the plurality of memory cells.

[0008] According to some example embodiments of the inventive concept, a resistive memory device may include: a memory cell array including a plurality of memory cells; a write circuit configured to perform a write operation by using a write current according to a control voltage to program the plurality of memory cells to a first resistance state; a read circuit configured to perform a read operation to read data from the plurality of memory cells programmed to the first resistance state; and a control circuit configured to count a bit error rate (BER) of the plurality of memory cells occurring in the read operation, and output the BER to the outside of the resistive memory device. The control circuit may be configured to control the control voltage in response to a control signal based on the BER received from the outside of the resistive memory device so that the write current increases to a current level having a current level greater than a minimum write current necessary to change the plurality of memory cells to the first resistance state.

[0009] According to some example embodiments of the present inventive concept, a memory system may include a resistive memory device and a memory controller. The resistive memory device may include: a memory cell array including a plurality of memory cells; a write circuit configured to perform a write operation by using a write current according to a control voltage to program the plurality of memory cells to a first resistance state; a read circuit configured to perform a read operation to read data from the plurality of memory cells programmed to the first resistance state; and a control circuit configured to count a bit error rate (BER) of the plurality of memory cells occurring in the read operation, and output the BER. The memory controller may be configured to control the resistive memory device. The control circuit of the resistive memory device may be configured to output the BER to the memory controller. The memory controller may be configured to determine the number of programming operations performed on the plurality of memory cells corresponding to the BER, and control the write operation based on the determined number of programming operations on the plurality of memory cells so that the write current increases to a current level having a current level greater than a minimum write current, the minimum write current being necessary to change the plurality of memory cells to the first resistance state. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram for describing a memory system according to some example embodiments;

[0012] Figure 2 is used to describe the Figure 1 A block diagram of a memory device in the illustrated memory system;

[0013] Figure 3 It is used to describe in detail Figure 2 A circuit diagram of a memory cell array shown;

[0014] Figure 4A , Figure 4B , Figure 4C and Figure 4D It is shown separately Figure 3 A circuit diagram of a modified embodiment of the memory cell shown;

[0015] Figure 5 Shown is included in Figure 3 An example of a variable resistance device in a memory cell of;

[0016] Figure 6 is shown applied to Figure 5 A graph showing write current of a memory cell;

[0017] Fig. 7A, Figure 7B and Figure 7C are used to describe Figure 5 A graph showing the characteristics of a memory cell when the memory cell is a single-level cell;

[0018] Figure 8 It shows that Figure 5 A graph showing distribution of memory cells according to resistance when the memory cell is a multi-level cell;

[0019] Fig. 9 It is used to explain Fig. 7A A diagram showing a threshold voltage distribution of a memory cell in a reset data state;

[0020] Fig.10 is a circuit diagram for describing a write circuit of a memory device according to some example embodiments of the inventive concept;

[0021] Fig.11 is a graph for describing a write current according to the number of program operations on a memory cell according to some example embodiments of the inventive concept;

[0022] Fig.12 is a flowchart describing a method of compensating for degradation of a memory device by using a memory controller according to some example embodiments;

[0023] Fig.13 It is used to explain Fig. 7A A diagram showing a threshold voltage distribution of a memory cell in a set data state;

[0024] Fig.14 is a flowchart describing a method of compensating for degradation of a memory device by using a memory controller according to some example embodiments;

[0025] Fig.15 is a block diagram schematically illustrating a configuration of a memory system according to some example embodiments of the inventive concept, the memory system adopting a method of compensating for degradation of a memory device by using a memory controller; and

[0026] Fig.16 is a block diagram illustrating a system to which methods of preventing degradation of a memory device according to some example embodiments of the inventive concepts are directed. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram of a memory system 1 according to some example embodiments. The memory system 1 may be included in an electronic device, a computing device, or the like.

[0028] refer to Figure 1, the memory system 1 may include a memory device 10 and a memory controller 20. The memory controller 20 may be implemented by one or more instances of circuits, including instances of processing circuits (e.g., processor devices). The memory device 10 may include a memory cell array 11, a write / read circuit 12, and a control circuit 13. It should be understood that the memory device 10 described herein may be a resistive memory device.

[0029] The memory controller 20 may control the memory device 10 to read data from the memory device 10 or write data to the memory device 10 in response to a read / write request from the host. The memory controller 20 may control programming (e.g., writing) and reading operations on the memory device 10 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 10. In addition, data DATA for a programming operation and data DATA read from the memory device 10 may be transmitted and received between the memory controller 20 and the memory device 10.

[0030] Although not shown, the memory controller 20 may include a random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM may be used as an operating memory of the processing unit, and the processing unit may control the operation of the memory controller 20. The host interface may include a protocol for data exchange between the host and the memory controller 20. For example, the memory controller 20 may be configured to communicate with the host via at least one of various protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0031] The memory cell array 11 may include a plurality of memory cells, which are respectively placed at regions where a plurality of first signal lines and a plurality of second signal lines intersect each other. In some example embodiments, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. In some example embodiments, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines. In some example embodiments, the memory cells of the memory cell array 11 include one or more multi-level cells. In some example embodiments, the memory cells of the memory cell array 11 include one or more single-level cells.

[0032] In some example embodiments, the plurality of memory cells may include a resistance memory cell, each resistance memory cell including a variable resistance device having a variable resistance. For example, when the variable resistance device includes a phase change material (e.g., Ge-Sb-Te (GST)) and changes resistance according to temperature, the memory device 10 may be a phase change memory (PRAM). As another example, when the variable resistance device includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the memory device 10 may be a resistance random access memory (RRAM). As yet another example, when the variable resistance device includes a magnetic upper electrode, a magnetic lower electrode, and a dielectric material therebetween, the memory device 10 may be a magnetoresistive random access memory (MRAM).

[0033] The write / read circuit 12 can perform write operations and read operations on the memory cells. The write / read circuit 12 can repeatedly program the memory cells to the same data state and read data from the memory cells programmed to the same data state. The write / read circuit 12 can perform a programming operation by applying a minimum current to the memory cell, which is necessary for the phase change layer of the memory cell to cause a phase change, and can perform a read operation to read data from the programmed memory cell by using multiple read voltages. Alternatively, the write / read circuit 12 can perform a programming operation by applying multiple write currents to the memory cell, which write current includes the minimum current necessary for the phase change layer of the memory cell to cause a phase change, and can perform a read operation to read data from the programmed memory cell.

[0034] The control circuit 13 may count the bit error rate (BER) of the memory cell occurring in the read operation, the number of on-cells, and the number of off-cells. The control circuit 13 may provide the BER, the number of on-cells, and the number of off-cells to the outside of the memory device 10, for example, to the memory controller 20. The control circuit 13 may provide data on the BER, the number of on-cells, and the number of off-cells to the memory controller 20 according to a plurality of write currents, and / or provide data on the BER according to a plurality of read voltages, the number of on-cells, and the number of off-cells to the memory controller 20. The data on the BER, the number of on-cells, and the number of off-cells may be used as indicators indicating the degree of degradation of the memory cell. The data on the BER, the number of on-cells, and the number of off-cells may be values ​​generated according to a previously performed read operation. The read operation may include a normal read operation and a dummy read operation, and the read voltage level in the normal read operation and the voltage level in the dummy read operation may be set to be different from each other.

[0035] Configurations for detecting the degree of degradation of one or more memory cells of a memory device 10, where the memory device 10 may be a resistive memory device, are described in detail in US Application No. 16 / 377,952, the entire contents of which are incorporated herein by reference in their entirety.

[0036] According to some example embodiments, the control circuit 13 may count the number (“quantity”) of programming operations performed in the memory cell array 11, for example, count the number of programming operations of memory cells in a specific resistance state. The control circuit 13 may provide (“output”) the number of programming operations performed in the memory cell array 11 to the outside of the memory device 10, for example, to the memory controller 20.

[0037] In some example embodiments, the number of programming operations on the memory cell corresponding to the bit error rate (BER) occurring in the read operation performed on the memory cell may be an indicator indicating the degree of degradation of the memory cell. In some example embodiments, the number of programming operations to program the memory cell to a specific resistance state may be an indicator indicating the degree of degradation of the memory cell. The memory controller 20 may sense the degree of degradation of the memory device 10 based on the BER and / or the number of programming operations received from the memory device 10, and compensate for the degradation of the memory device 10. In order to compensate for the degradation of the memory device 10, the memory controller 20 may control the write operation by increasing the write current applied to the memory cell to a current level having a current level higher than the minimum current required for the phase change layer of the memory cell to cause a phase change. The memory controller 20 may change the current level of the write current based on data about the BER, the number of turn-on cells, the number of turn-off cells, or the number of programming times. For example, in the case where the number of programming times is equal to or greater than a specific value, the memory controller 20 may control the write current, in which the write current is applied to the memory cell more strongly than the write current in the case where the number of programming times is equal to or less than a specific value.

[0038] The memory controller 20 and the memory device 10 may be integrated into one semiconductor device. For example, the memory controller 20 and the memory device 10 may be integrated into one semiconductor device to form a memory card. For example, the memory controller 20 and the memory device 10 may be integrated into one semiconductor device to form a personal computer (PC) memory card, a Compact Flash (CF) card, a Smart Media (SM) card (SMC), a memory stick, a Multi Media Card (MMC) (Reduced Size MMC Card, RS-MMC, Multi-Media Card micro, MMCmicro), a Secure Digital (SD) card (SD, mini SD, micro SD) and a Universal Flash Storage (UFS), etc. As another example, the memory controller 20 and the memory device 10 may be integrated into one semiconductor device to form a solid state disk / drive (SSD).

[0039] Figure 2 is used to describe the Figure 1 A block diagram of a memory device 10 in a memory system 1 is shown.

[0040] refer to Figure 2, the memory device 10 may include a memory cell array 11, a write / read circuit 12, a control circuit 13, a voltage generator 14, a row decoder 15, and a column decoder 16, and the write / read circuit 12 may include a write circuit 121 and a read circuit 122. The row decoder 15 may be referred to as a row decoder circuit in this article. The column decoder 16 may be referred to as a column decoder circuit in this article.

[0041] The memory cell array 11 may be connected to a plurality of first signal lines and a plurality of second signal lines, and may include a plurality of memory cells respectively placed at regions where the plurality of first signal lines and the plurality of second signal lines cross each other. Hereinafter, some example embodiments of the inventive concept will be described by taking the case where the plurality of first signal lines are bit lines BL and the plurality of second signal lines are word lines WL as an example.

[0042] like Figure 3 As shown, the memory cell array 11 may be a two-dimensional memory cell array having a horizontal structure, and may include a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells MC. The memory cell array 11 may include a plurality of memory blocks. In each memory block, a plurality of memory cells may be arranged in rows and columns. Herein, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may be modified differently according to some example embodiments. However, the inventive concept is not limited thereto, and in some example embodiments, the memory cell array 11 may be a three-dimensional memory cell array having a vertical structure.

[0043] According to some example embodiments, each of the plurality of memory cells MC may include a variable resistance device R and a selection device D. Here, the variable resistance device R may be referred to as a variable resistance material, and the selection device D may be referred to as a switching device.

[0044] In some example embodiments, the variable resistance device R may be connected between one of the plurality of bit lines BL1 to BLm and the selection device D, and the selection device D may be connected between the variable resistance device R and one of the plurality of bit lines WL1 to WLn. However, the inventive concept is not limited thereto, and the selection device D may be connected between one of the plurality of bit lines BL1 to BLm and the variable resistance device R, and the variable resistance device R may be connected between the selection device D and one of the plurality of word lines WL1 to WLn.

[0045] The selection device D may be connected between one of the plurality of word lines WL1 to WLn and the variable resistance device R, and may control a current supplied to the variable resistance device R according to a voltage applied to the word line and the bit line connected to the switching device D. Although the selection device D is Figure 3, but it is merely an example embodiment of the inventive concept, and in some example embodiments, the selection device D may be replaced by another device that can be switched.

[0046] The modification of the memory cell MC can be as follows Figure 4A , Figure 4B , Figure 4C and Figure 4D Implement as shown. Figure 4A , the memory cell MCa may include a variable resistance device Ra, which may be connected to a bit line BL and a word line WL. The memory cell MCa may store data by using voltages respectively applied to the bit line BL and the word line WL.

[0047] exist Figure 4B In the embodiment, the memory cell MCb may include a variable resistance device Rb and a unidirectional diode Da. The variable resistance device Rb may include a resistance material for storing data. The unidirectional diode Da may be a switching device, that is, a selection device that provides current to the variable resistance device R / blocks the current flowing to the variable resistance device R according to the bias of the word line WL and the bit line BL. The unidirectional diode Da may be connected between the variable resistance device Rb and the word line WL, and the variable resistance device R may be connected between the bit line BL and the unidirectional diode Da. The positions of the unidirectional diode Da and the variable resistance device R may be changed with each other.

[0048] In some example embodiments, the unidirectional diode Da may be a PN junction diode or a PIN junction diode, an anode of the unidirectional diode Da may be connected to the variable resistance device Rb, and a cathode of the unidirectional diode Da may be connected to one of a plurality of word lines WL1 to WLn. In this case, when a voltage difference between an anode and a cathode of the unidirectional diode Da is greater than a threshold voltage, the unidirectional diode Da may be turned on, and current may be provided to the variable resistance device Ra.

[0049] exist Figure 4C In the embodiment, the memory cell MCc may include a variable resistance device Rc and a bidirectional diode Db. The variable resistance device Rc may include a resistance material for storing data. The bidirectional diode Db is connected between the variable resistance device Rc and the word line WL, and the variable resistance device Rc may be connected between the bit line BL and the bidirectional diode Db. The positions of the bidirectional diode Db and the variable resistance device Rc may be changed with each other. The leakage current flowing in the non-selected resistance unit may be blocked by using the bidirectional diode Db.

[0050] exist Figure 4DIn the embodiment, the memory cell MCd may include a variable resistance device Rd and a transistor TR. The transistor TR may be a switching device, that is, a selection device that provides current to the variable resistance device Rd / blocks the current flowing to the variable resistance device Rd according to the voltage of the word line WL. The transistor TR may be connected between the variable resistance device Rd and the word line WL, and the variable resistance device Rd may be connected between the bit line BL and the transistor TR. The positions of the transistor TR and the variable resistance device Rd may be changed with each other. The memory cell MCd may be selected or not selected according to the on / off state of the transistor TR driven by the word line WL.

[0051] Reference again Figure 2 The write circuit 121 may perform a program operation (ie, a write operation) by connecting to the selected bit line BL and supplying a program current to the selected memory cell MC, and thus, may input data DATA to be stored in the memory cell array 11. Herein, the program current may be referred to as a write current.

[0052] When a write command is received from the memory controller 20, the write circuit 121 may perform a write operation on the memory cell MC. The write circuit 121 may perform a reset write operation to program the memory cell MC in a direction in which the resistance of the memory cell MC increases. The write circuit 121 may also perform a set write operation to program the memory cell MC in a direction in which the resistance of the memory cell MC decreases.

[0053] In some example embodiments, the write circuit 121 may increase the reset write current according to the write operation control of the control circuit 13 so that it has a current level higher than the current level of the minimum reset write current required for the memory cell to enter the HRS (High Resistance State) state, and program the memory cell MC with the reset data in the HRS state by providing the increased reset write voltage to the memory cell MC. Alternatively, the write circuit 121 may increase the set write current according to the write operation control of the control circuit 13 so that it has a current level higher than the current level of the minimum set write current required for changing the memory cell MC to the LRS (Low Resistance State), and program the memory cell with the set data in the LRS state by providing the increased set write current to the memory cell MC.

[0054] The read circuit 122 may be connected to the selected bit line BL and read the data DATA stored in the selected memory cell MC. When a read command is received from the memory controller 20, the read circuit 122 may perform a read operation on the memory cell MC. The read circuit 122 may read data from each of the memory cells MC and provide the read result to the control circuit 13.

[0055] The control circuit 13 may output various control signals CTRL_OP and CTRL_VOL based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 20 to write data DATA to the memory cell array 11 or read data DATA from the memory cell array 11. The control circuit 13 may provide the operation control signal CTRL_OP to the write / read circuit 12. The operation control signal CTRL_OP may include a write enable signal WEN, a write control signal WCS, a read enable signal REN, a precharge signal PRE, a discharge signal DIS, etc. In addition, the control circuit 13 may provide the voltage control signal CTRL_VOL to the voltage generator 14. In addition, the control circuit 13 may provide the row address X_ADDR to the row decoder 15, and provide the column address Y_ADDR to the column decoder 16.

[0056] The control circuit 13 can control the memory cells MC in the entire or partial area of ​​the memory block within the memory cell array 11 to be repeatedly programmed with the same data.

[0057] In some example embodiments, the control circuit 13 may control the memory cells MC in the memory block to be programmed with reset data, and may store the number of reset data bits programmed in the memory block area. The control circuit 13 may compare the number of programmed reset data bits with the number of reset data bits read from the read circuit 122, and output the difference between the numbers of reset data bits as a BER to the memory controller 20. The control circuit 13 may increase the reset write current to have a current level higher than the current level of the minimum reset write current required to change the memory cell MC to a high resistance state (HRS), and the control circuit 13 may control the memory cell MC to be programmed by using the increased reset write current.

[0058] In some example embodiments, the control circuit 13 may control the memory cells in the memory block to be programmed with the set data, and store the number of set data bits programmed in the memory block area. The control circuit 13 may compare the number of programmed set data bits with the number of set data bits read from the read circuit 122, and output the difference between the numbers of set data bits as a BER to the memory controller 20. The control circuit 13 may increase the set write current to have a current level higher than the current level of the minimum set write current required to change the memory cell MC to a low resistance state, and the control circuit 13 may control the memory cell MC to be programmed by using the increased set write current.

[0059] In some example embodiments, the control circuit 13 may count the number of programming times (“quantity”) of reset data or set data performed on the memory block and output the number of program times (NPC) to the memory controller 20 .

[0060] The voltage generator 14 may generate various voltages for performing write and read operations on the memory cell array 11 based on the voltage control signal CTRL_VOL. The voltage generator 14 may generate a first driving voltage VWL driving a plurality of word lines WL and a second driving voltage VBL driving a plurality of bit lines BL.

[0061] The voltage generator 14 may generate a control voltage VC to control the magnitude of a write current I provided to the memory cell MC in a write operation. The voltage generator 14 may increase the magnitude of the control voltage VC in response to the voltage control signal CTRL_VOL. As the magnitude of the control voltage VC increases, the magnitude of the write current I provided to the memory cell MC also increases.

[0062] The row decoder 15 may be connected to the memory cell array 11 via a plurality of word lines WL, and activate a word line selected from among the plurality of word lines WL in response to a row address X_ADDR received from the control circuit 13. The row decoder 15 may control a voltage applied to a selected word line from among the plurality of word lines WL, or control a connection relationship of the selected word line in response to the row address X_ADDR.

[0063] The column decoder 16 may be connected to the memory cell array 11 through a plurality of bit lines BL, and may activate a selected bit line among the plurality of bit lines BL in response to a column address Y_ADDR received from the control circuit 13. The column decoder 16 controls a voltage applied to a selected bit line among the plurality of bit lines BL, or controls a connection relationship of the selected bit line, in response to the column address Y_ADDR.

[0064] Figure 5Shown is included in Figure 3 An example of a variable resistance device in a memory cell MC is shown.

[0065] refer to Figure 5 , the memory cell MC may include a variable resistance device R and a switch device SW. The switch device SW may be implemented by using various devices such as a transistor and a diode. Figure 5 Enlarged and described, the variable resistance device R may include a phase change layer 51, an upper electrode 52 formed on the phase change layer 51, and a lower electrode 53 formed under the phase change layer 51, wherein the phase change layer 51 includes a compound of germanium (Ge), antimony (Sb), and tellurium (Te).

[0066] The upper electrode 52 and the lower electrode 53 may include various metals, metal oxides or metal nitrides. The upper electrode 52 and the lower electrode 53 may include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAlyNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium dioxide (IrO2), strontium zirconate oxide (StZrO3), etc. The phase change layer 51 may be formed of a bipolar resistance memory material or a unipolar resistance memory material. Due to the polarity of the current, the bipolar resistance memory material can be programmed to a set state or a reset state, and the perovskite-based material can be used for the bipolar resistance memory material. Meanwhile, since the current is unipolar, the unipolar resistance memory material can be programmed to a set state or a reset state, and a transition metal oxide such as NiOX or TiOx can be used for the unipolar resistance memory material.

[0067] The GST material can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. The GST material can be programmed by heating the GST material. The intensity and time period of the heating can be used to determine whether the GST material remains in the amorphous state or the crystalline state. The high resistivity and the low resistivity can each be indicated as a logic "0" or a logic "1" of the programming value, and can be detected by measuring the resistivity of the GST material. Conversely, the high resistivity and the low resistivity can each be indicated as a logic "1" or a logic "0" of the programming value.

[0068] exist Figure 5In the embodiment, when the write current I is applied to the memory cell MC, the write current I applied to the memory cell MC flows through the lower electrode 53. When the write current I is applied to the memory cell MC for a short period of time, only the layer adjacent to the lower electrode 53 is heated by Joule heat. In this case, due to the difference between the heating curves, a limited portion ( Figure 5 The shaded portion 51a in FIG. 5A becomes a crystalline state (eg, a set state) or an amorphous state (eg, a reset state), while the remaining portion 51b of the phase change layer 51 may be suppressed from entering the crystalline state or the amorphous state.

[0069] Figure 6 is shown applied to Figure 5 Graph showing the write current of the memory cell MC.

[0070] refer to Figure 6 , in order to put the phase change layer 51 in an amorphous state (e.g., a reset state), a high reset write current Irst is applied to the memory cell MC for a short period of time and then removed. In order to put the phase change layer 51 in a crystalline state (e.g., a set state), a set write current Iset lower than the reset write current Irst is applied to the memory cell MC, and the set write current Iset applied to the memory cell MC is maintained for a period of time to crystallize the phase change layer 51, and then removed. According to the above method, the memory cell MC can be set to be in one of the crystalline state and the amorphous state. In this case, TP1 indicates the crystallization temperature of the phase change layer 51, and TP2 indicates the melting point of the phase change layer 51.

[0071] Fig. 7A , Figure 7B and Figure 7C are used to describe Figure 5 The graph of the characteristics of the memory cell MC shown is when the memory cell MC is a single-level cell (SLC).

[0072] Fig. 7A shows the ideal threshold voltage distribution for an SLC where the memory cell is programmed with 1 bit. Fig. 7A , the horizontal axis indicates the threshold voltage, and the vertical axis indicates the number of memory cells.

[0073] The variable resistance device R of the memory cell MC can be in a low resistance state (LRS) or a high resistance state (HRS). The operation of switching the variable resistance device R from HRS to LRS by applying a write current to the memory cell MC is called a set operation or a set write operation. The operation of switching the variable resistance device R from LRS to HRS by applying a write current to the memory cell MC is called a reset operation or a reset write operation.

[0074] A specific voltage between the distribution according to the LRS and the distribution according to the HRS may be set as the read voltage Vread. In a read operation for the memory cell MC, a read result equal to or greater than the read voltage Vread may be determined as reset data (logic "0") in the HRS, and a read result equal to or less than the read voltage Vread may be determined as set data (logic "1") in the LRS. When the memory cell MC is repeatedly programmed with reset data (logic "0") or set data (logic "1"), as shown in FIG. Figure 7B and 7C As shown, the resistance characteristics of the memory cell MC may be reduced.

[0075] Figure 7B is an example of the characteristics of a memory cell MC that is repeatedly programmed with reset data logic "0" due to a high current applied to the memory cell MC. Figure 7B , the horizontal axis indicates the number of programming cycles and the vertical axis indicates the resistance. Initially, the phase change layer 51 has a high resistance due to the effect of the resistivity of the memory cell MC. However, when the memory cell MC is continuously programmed with reset data logic "0" without intervening programming with set data logic "1", the resistance of the memory cell MC may decrease. Therefore, the sensing margin between the set data logic "1" and the reset data logic "0" is reduced, and as a result, the sensing of the reset data logic "0" becomes uncertain, slower, or generally becomes less reliable. Therefore, the resistive memory device may have a time overhead and / or reduced reliability.

[0076] Figure 7C It is shown that the degradation that occurs for reset data logic "0" may also occur for set data logic "1". When the memory cell MC is continuously programmed with set data logic "1" without any intervening programming with reset data data "0", the resistance of the memory cell MC may increase as a function of the number of programming cycles. The increase in the resistivity of the set data logic "1" reduces the sensing margin between the set data logic "1" and the reset data logic "0", and may also reduce the reliability of the resistive memory device.

[0077] Figure 8 It shows that Figure 5 The graph of the distribution of the resistance of the memory cell MC when the memory cell MC is a multi-level cell is shown. Figure 8 , the horizontal axis indicates the threshold voltage Vth, and the vertical axis indicates the number of memory cells MC.

[0078] refer to Figure 8, when the memory cell MC is a multi-level cell programmed with 2-bit data, the memory cell MC may have one of a first resistance state RS1, a second resistance state RS2, a third resistance state RS3, and a fourth resistance state RS4. In some example embodiments, the memory device 10 may be controlled to program the memory cell MC of the memory cell array 11 to one or more resistance states of the first resistance state RS1 to the fourth resistance state RS4. The memory controller 20 may be configured to control the memory device 10 to program the memory cell MC of the memory cell array 11 to one or more resistance states of the first resistance state RS1 to the fourth resistance state RS4.

[0079] However, the inventive concept is not limited thereto, and in some example embodiments, the plurality of memory cells may include a three-level cell storing 3-bit data, and the three-level cell may each have one of eight resistance states. In some example embodiments, the plurality of memory cells may include a memory cell that may each store at least 4-bit data.

[0080] Compared with SLC, the difference between resistance distributions in MLC is narrow, so in MLC, read errors may occur due to slight changes in threshold voltage. Therefore, in order to ensure read margin, resistance states RS1, RS2, RS3, and RS4 may have threshold voltage ranges that do not overlap with each other.

[0081] Each of the resistance states RS1, RS2, RS3, and RS4 may correspond to one of data "00", data "01", data "10", and data "11". In some example embodiments, the resistance level may increase in the order of data "11", data "01", data "00", and data "10". In other words, the first resistance state RS1 may correspond to data "11", the second resistance state RS2 may correspond to data "01", the third resistance state RS3 may correspond to data "00", and the fourth resistance state RS4 may correspond to data "10".

[0082] Fig. 9 It is used to explain Fig. 7A FIG. 1 is a graph showing the threshold voltage distribution of memory cells in the reset data state.

[0083] Fig. 9The figure shows the change of the threshold voltage distribution of the reset data according to the programming operation after performing the programming operation by applying multiple reset write currents Irst1, Irst2 and Irst3 to the memory cell MC. At the beginning of the programming operation, the threshold voltage distributions of the reset data of the memory cell MC programmed in response to the multiple reset write currents Irst1, Irst2 and Irst3 have approximately the same shape as each other. Next, when the NPC increases to about M times, the shape of the threshold voltage distribution changes to have a larger width (A).

[0084] For example, assuming that the highest current among the plurality of reset write currents Irst1, Irst2, and Irst3 is the first reset write current Irst1, and the lowest current is the third reset write current Irst3. Due to the stress caused by programming M times, the threshold voltage distribution of the reset data of the memory cell MC programmed by using the third reset write current Irst3 may move to the left, i.e., toward the LRS of the set data, and become significantly widened.

[0085] When reading data from the memory cell MC, when the memory cell MC programmed by using the third reset write current Irst3 is read by using the first read voltage Vread1, although the memory cells in the shaded area are programmed with reset data, these memory cells may be determined to be programmed with set data due to the reduction in threshold voltage. That is, the number of memory cells included in the shaded area is expressed as BER, and the BER in the shaded area is high. It can be expected that the BER of the reset data according to the third reset write current Irst3 may increase according to the increase of NPC.

[0086] According to some example embodiments, the BER of reset data may vary according to the level of the read voltage. In some example embodiments, the BER may be determined according to the level of the read voltage used to perform a read operation on the memory cell. For example, the read direction at the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may be set in a direction in which the voltage level increases from the third read voltage Vread3 to the first read voltage Vread1. Therefore, the BER according to the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may increase.

[0087] Here, when the current level of the third reset write current Irst3 increases, the BER of the reset data according to the third reset write current Irst3 as the lowest reset write current can be reduced. In addition, when the memory cell MC is programmed by using a reset write current having a current level higher than the current level of the minimum reset write current necessary for the phase change layer 51 of the memory cell MC to cause a phase change to a reset state, the BER of the reset data of the memory cell MC can be reduced.

[0088] Fig.10 is a circuit diagram of a write circuit of a memory device according to some example embodiments of the inventive concepts.

[0089] refer to Fig.10 , the memory cell MC may be placed at a region where the bit line BL and the word line WL cross each other, and may include a variable resistance device R and a selection device D. The column decoder 16 may include a bit line selection transistor Ty, and the bit line selection transistor Ty may connect the memory cell MC to the write / read circuit 12 in response to a column selection signal Yi. Hereinafter, some example embodiments in which the column selection signal Yi is activated and the memory cell MC and the write / read circuit 12 are connected to each other will be described.

[0090] The write circuit 121 may provide a write current I to program the memory cell MC. The write circuit 121 may include a first transistor T11, a second transistor T12, a current pulse generator CPG, and a latch circuit LC. When the write enable signal WIN is activated, the first transistor T11 is turned on, and the write circuit 121 may be connected to the memory cell MC.

[0091] The current generator CPG may include a third transistor T13, a fourth transistor T14, and a fifth transistor T15. The third transistor T13 and the fourth transistor T14 may each be connected to a power supply voltage Vdd and may jointly form a current mirror, and the fifth transistor T15 connected between the third transistor T13 and the fourth transistor T14 may provide a write current I to the memory cell MC in response to a control voltage VC applied to a gate of the fifth transistor T15. As the magnitude of the control voltage VC increases, the magnitude of the write current I provided to the memory cell MC may also increase. Fig.10 As shown, the write circuit 121 may be configured to provide a write current I via the fourth transistor T14.

[0092] like Fig.11 As shown, the write current I can be set to have an amplitude that increases according to the increase of the NPC of the memory cell. The amplitude (“current level”) of the write current I can be changed by the control voltage VC. In response to the voltage control signal CTRL_VOL (see Figure 2 ), the control voltage VC can be generated in the voltage generator 14, and the voltage control signal CTRL_VOL is in response to the memory controller 20 (see Figure 1 ) is generated by the control signal CTRL of the control voltage VC. As the magnitude of the control voltage VC increases, the magnitude of the write current I supplied to the memory cell MC also increases.

[0093] In some example embodiments, when the memory cell MC is Fig. 7A When the SLC is shown, the memory cell MC can be switched to one of HRS and LRS as the magnitude of the write current I changes. The magnitude of the write current I can be increased to be greater than the magnitude of the minimum reset write current, which is necessary to change the memory cell MC from LRS to HRS. Alternatively, the magnitude of the write current I can be increased to be greater than the magnitude of the minimum set write current, which is necessary to change the memory cell MC from HRS to LRS.

[0094] In some example embodiments, when the memory cell MC is Figure 8 In the MLC shown in FIG. 1 , as the magnitude of the write current I changes, the memory cell MC can be switched from the first resistance state RS1 to one of the second resistance state RS2, the third resistance state RS3, and the fourth resistance state RS4, so that the resistance level of the memory cell MC increases. In addition, the memory cell MC can be switched from the second resistance state RS2 to the third resistance state RS3 or the fourth resistance state RS4. In addition, the memory cell MC can be switched from the third resistance state RS3 to the fourth resistance state RS4.

[0095] For example, when a first write current is applied to the memory cell MC, the memory cell MC may switch from the first resistance state RS1 to the second resistance state RS2. The amplitude of the first write current may increase to a value having a larger amplitude than the minimum reset write current, which is necessary to change the memory cell from the first resistance state RS1 to the second resistance state RS2. When a second write current is applied to the memory cell MC, the memory cell MC may switch from the first resistance state RS1 to the third resistance state RS3. The amplitude of the second write current may increase to a value having a larger amplitude than the minimum reset write current, which is necessary to change the memory cell from the first resistance state RS1 to the third resistance state RS3. In addition, when a third write current is applied to the memory cell MC, the memory cell MC may switch from the first resistance state RS1 to the fourth resistance state RS4. The amplitude of the third write current may increase to a value having a larger amplitude than the minimum reset write current, which is necessary to change the memory cell from the first resistance state RS1 to the fourth resistance state RS4.

[0096] As the magnitude of the write current I changes, the memory cell MC can be switched from the fourth resistance state RS4 to one of the first resistance state RS1, the second resistance state RS2, and the third resistance state RS3, so that the resistance level of the memory cell MC is reduced. In addition, the memory cell MC can be switched from the third resistance state RS3 to the first resistance state RS1 or the second resistance state RS2. In addition, the memory cell MC can be switched from the second resistance state RS2 to the first resistance state RS1.

[0097] For example, when a first write current is applied to the memory cell MC, the memory cell MC may be switched from the fourth resistance state RS4 to the first resistance state RS1. The amplitude of the first write current may be increased to have a value greater than the amplitude of the minimum set write current, which is necessary to change the memory cell from the fourth resistance state RS4 to the first resistance state RS1. In addition, when a second write current is applied to the memory cell MC, the memory cell MC may be switched from the fourth resistance state RS4 to the second resistance state RS2. The amplitude of the second write current may be increased to have a value greater than the amplitude of the minimum set write current, which is necessary to change the memory cell from the fourth resistance state RS4 to the second resistance state RS2. In addition, when a third write current is applied to the memory cell MC, the memory cell MC may be switched from the fourth resistance state RS4 to the third resistance state RS3. The amplitude of the third write current may be increased to have a value greater than the amplitude of the minimum set write current, which is necessary to change the memory cell from the fourth resistance state RS4 to the third resistance state RS3.

[0098] The latch circuit LC may output a gate voltage in response to the write control signal WCS so that the second transistor T12 may be selectively turned on according to the logic level of the input data DI. The input data DI is data obtained from the data DATA provided by the memory controller 20.

[0099] In some example embodiments, when the write control signal WCS indicates a write operation in the reset direction, the latch circuit LC may turn on the second transistor T12 according to a logic level '0' of the input data DI, and turn off the second transistor T12 when the logic level of the input data is '1'.

[0100] In some example embodiments, when the write control signal WCS indicates a write operation in a set direction, the latch circuit LC may turn off the second transistor T12 when the logic level of the input data DI is "0", and may turn on the second transistor T12 when the logic level of the input data DI is "1".

[0101] The read circuit 122 may read data stored in the memory cell MC. The read circuit 122 may include a first transistor T21, a second transistor T22, a third transistor T23, and a sense amplifier (SA). When the read enable signal REN is activated, the first transistor T21 is turned on, and the read circuit 122 may be connected to the memory cell MC.

[0102] When the precharge signal PRE is activated, the second transistor T12 may be turned on and the bit line BL may be precharged to the precharge voltage Vpre. Meanwhile, when the discharge signal DIS is activated, the third transistor T13 may be turned on and the bit line BL may be discharged to the ground voltage.

[0103] The sense amplifier SA activated in response to the sense enable signal SEN may compare the voltage VSN of the sense node SN with the reference voltage Vref and output output data DO indicating whether the memory cell MC is turned on or off. The reference voltage Vref may be set to the read voltages Vread1 to Vread3 (see Fig. 9 ). The output data DO may be provided as data DATA to the outside of the memory device 10 , for example, the memory controller 20 .

[0104] Fig.12 is a flowchart describing a method of compensating for degradation of a memory device by using the memory controller 20 according to some example embodiments.

[0105] References Figure 1 , Figure 2 , Fig. 9 and Fig.10 Related Fig.12 , in operation S1210 , the memory controller 20 may control the memory cells MC in the memory device 10 to be programmed with reset data.

[0106] Under the write operation control of the memory controller 20, the memory device 10 can perform a reset data write operation. The write circuit 121 can perform a reset data write operation. Figure 8As described, the write circuit 121 may, for example, apply reset write currents Irst1, Irst2, and Irst3 to the memory cell MC, thereby programming the memory cell MC with reset data. The control circuit 13 may program the memory cells in the entire or partial area of ​​the memory block in the memory cell array 11 with reset data. In this case, the control circuit 13 may store the number of reset data bits programmed in the memory block area. The control circuit 13 may store the determined number of memory cells programmed to the resistance state in the write operation. The number of memory cells so programmed may be the same as the number of reset data bits programmed in the memory block area. The control at S1210 may include controlling the memory device 10 to program the memory cells MC in all or some memory blocks in the memory cell array 11 to the resistance state. The resistance state may be one of a plurality of resistance states. In some example embodiments, the resistance state may be a first resistance state RS1. In some example embodiments, the resistance state may be a fourth resistance state RS4. In some example embodiments, the resistance state is a high resistance state (HRS) among a plurality of resistance states (e.g., resistance states RS1 to RS4). Programming may include repeatedly programming the memory cell MC to a resistance state.

[0107] In operation S1220, the memory controller 20 may control memory cells in the memory device 10 to be read. The control at operation S1220 may include controlling the memory device 10 to perform a read operation on the memory cells, which may have been programmed to a resistance state at operation S1210.

[0108] The memory device 10 may perform a reset data read operation under the read operation control of the memory controller 20. The read circuit 122 may perform a reset data read operation. The read circuit 122 may read the memory cells programmed in response to the reset write currents Irst1, Irst2, and Irst3 by using the voltage level of the reference voltage Vref or the voltage level of the read voltage Vread.

[0109] In operation S1230, the memory controller 20 may check the NPC based on the BER of the read data provided by the memory device 10. The memory device 10 (e.g., the control circuit 13) may control the memory cells MC of the memory block in the memory cell array 11 to be programmed with the reset data, and store the number of reset data bits programmed in the area of ​​the memory block. The memory device 10 (e.g., the control circuit 13) may compare the number of reset data bits programmed with the number of reset data bits output via the read circuit 122, and may output the difference between the number of reset data bits programmed and the number of reset data bits as the BER to the memory controller 20. The memory device 10 (e.g., the control circuit 13) may compare the determined number of memory cells in the resistance state read in the read operation at operation S1220 with the determined number of memory cells programmed to the resistance state at operation S1210. The memory device 10 (e.g., the control circuit 13) may output the difference between the determined number of memory cells in the resistance state at operation S1220 and the determined number of memory cells programmed to the resistance state at operation S1210 as the BER. According to some example embodiments, the control circuit 13 may count the number of programming operations performed in the memory cell array 11 ("quantity"), such as the number of programming operations performed on the memory cells in the resistance state, and may provide ("output") the number to the outside of the memory device 10, such as the memory controller 20. The memory controller 20 may receive one or more indicators indicating the degree of degradation of the memory cells of the memory device 10, so that the memory controller 20 may sense the degree of degradation of one or more memory cells of the memory device 10. Such one or more indicators may include data on the BER, the number of on cells, and / or the number of off cells. For example, the memory controller 20 may check the NPC of the memory device 10 corresponding to the BER to sense the degree of degradation of the memory device 10. In some example embodiments, the memory controller 20 may receive an indicator indicating the number of programming operations on the memory cell corresponding to a bit error rate (BER) occurring in a read operation on the memory cell at operation S1220. In some example embodiments, the memory controller 20 may receive an indicator indicating the number of programming operations to program the memory cell to a resistance state at operation S1210. According to some example embodiments, the memory controller 20 may check the NPC of the reset data provided by the control circuit 13 of the memory device 10 to sense the degree of degradation of the memory device 10. A configuration for detecting the degree of degradation of the memory device 10, which may be a resistance memory device, is described in detail in U.S. Application No. 16 / 377,952, the entire contents of which are incorporated herein by reference in their entirety.

[0110] In operation S1240, the memory controller 20 may increase the magnitude of the write current I so that the reset write current Irst increases according to the NPC checked in operation S1230, and the memory cell may be programmed by using the increased write current I. Thus, the memory controller 20 may control one or more memory cells of the memory device 10 to be programmed to the resistance state to which the (multiple) memory cells were programmed at operation S1210 based on the use of a write current having a current level greater than the current level of the minimum write current, based on the indicator indicating the degree of degradation, the minimum write current being necessary to program the (multiple) memory cells to the resistance state. For example, in the case where the resistance state in question is HRS, the magnitude (“current level”) of the write current I may be increased to be greater than the magnitude (“current level”) of the minimum reset write current, which is necessary (“necessary”) for the memory cell to change from LRS to HRS. In some example embodiments, operation S1240 may include the memory controller 20 providing a control signal to the control circuit 13 of the memory device 10 based on the determined BER, which in response may cause the control circuit 13 to control the control voltage VC to change the write current I to increase in current level to a current level having a current level greater than a minimum write current necessary to change a memory cell of the memory device 10 to a resistance state. The control circuit 13 may, for example, control the control voltage VC to change the write current I to increase in current level to a current level having a current level greater than a minimum reset write current necessary to change a memory cell of the memory device 10 to an HRS.

[0111] In the method of compensating for degradation of the memory device 10 by using the memory controller 20, as the magnitude of the write current I increases, the reset write current Irst of the memory cell MC increases, and the threshold voltage distribution of the reset data can be moved to the HRS. Therefore, the reset data sensing becomes more reliable and faster, and the time overhead can be eliminated. Therefore, the function of a computing device, an electronic device, etc. including the memory controller 20 and the memory device 10 can be improved.

[0112] Fig.13 It is used to explain Fig. 7A FIG. 4 is a diagram showing the threshold voltage distribution of a memory cell in a set data state.

[0113] Fig.131 shows a change in the threshold voltage distribution of the set data according to the programming operation after performing the programming operation by applying a plurality of set write currents Iset1, Iset2, and Iset3 to the memory cell MC. At the beginning of the programming operation, the threshold voltage distributions of the reset data of the memory cell MC programmed in response to the plurality of set write currents Iset1, Iset2, and Iset3 have shapes approximately the same as each other. Next, when the NPC increases to about M times, the shape of the threshold voltage distribution changes to have a larger width (B).

[0114] For example, assuming that the highest current among a plurality of set write currents Iset1, Iset2, and Iset3 is the first set write current Iset1, and the lowest current is the third set write current Iset3. Due to the stress caused by M-time programming, the threshold voltage of the set data of the memory cell MC programmed by using the third set write current Iset3 may move to the right, i.e., to the HRS of the reset data, and become significantly widened.

[0115] When reading the memory cells MC, when the memory cells MC programmed by using the third set write current Iset3 are read by using the read voltage Vread, although the memory cells in the shadow area are programmed with the set data, these memory cells may be determined to be programmed with the reset data due to the reduction in the threshold voltage. In other words, it can be assumed that the BER of the memory cells in the shadow area is high, and the BER of the set data according to the third set write current Iset3 can increase as the NPC increases.

[0116] According to some example embodiments, the BER of reset data may vary according to the level of the read voltage. For example, the read direction of the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may be set in a direction in which the voltage level decreases from the third read voltage Vread3 to the first read voltage Vread1. Therefore, the BER according to the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may increase. Therefore, the BER may be determined according to the level of the read voltage used to perform a read operation on the memory cell at operation S1220.

[0117] Here, when the current level of the third setting write current Iset3 increases, the BER of the setting data according to the third setting write current Iset3 as the lowest setting write current can be reduced. In addition, when the memory cell MC is programmed by using a current greater than the minimum reset write current necessary for the phase change layer 51 of the memory cell MC to cause a phase change to the set state, the BER of the setting data of the memory cell MC can be reduced.

[0118] Fig.14 is a flowchart describing a method of compensating for degradation of the memory device 10 by using the memory controller 20 according to some example embodiments.

[0119] References Figure 1 , Figure 2 , Fig.10 and Fig.13 Related Fig.14 , in operation S1410 , the memory controller 20 may control the memory cells MC in the memory device 10 to be programmed with set data.

[0120] Under the write operation control of the memory controller 20, the memory device 10 can perform a set data write operation. The write circuit 121 can perform a set data write operation. Fig.13 As described, the write circuit 121 may, for example, apply set write currents Iset1, Iset2, and Iset3 to the memory cell MC, thereby programming the memory cell MC with the set data. The control circuit 13 may program the set data in the memory cells in the entire or partial area of ​​the memory block in the memory cell array 11. In this case, the control circuit 13 may store the number of set data bits programmed in the memory block area. The control circuit 13 may store the determined number of memory cells programmed to the resistance state in the write operation. The determined number of memory cells programmed in this way may be the same as the number of set data bits programmed in the memory block area. The control at S1410 may include controlling the memory device 10 to program the memory cells MC in all or some memory blocks in the memory cell array 11 to the resistance state. The resistance state may be one resistance state among a plurality of resistance states. In some example embodiments, the resistance state may be a first resistance state RS1. In some example embodiments, the resistance state may be a fourth resistance state RS4. In some example embodiments, the resistance state is a low resistance state (LRS) among a plurality of resistance states (e.g., resistance states RS1 to RS4). Programming may include repeatedly programming the memory cell MC to a resistance state.

[0121] In operation S1420, the memory controller 20 may control memory cells MC in the memory device 10 to be read. The control at operation S1420 may include controlling the memory device 10 to perform a read operation on the memory cells, which may have been programmed to a resistance state at operation S1410.

[0122] The memory device 10 may perform a set data read operation under the read operation control of the memory controller 20. The set data read operation may be performed by the read circuit 122. The read circuit 122 may read the memory cells programmed in response to the set write currents Iset1, Iset2, and Iset3 by using the voltage level of the reference voltage Vref or the voltage level of the read voltage Vread.

[0123] In operation S1430, the memory controller 20 may check the NPC based on the BER of the read data provided by the memory device 10. The memory device 10 (e.g., the control circuit 13) may control the memory cells MC of the memory block in the memory cell array 11 to be programmed with the set data, and store the number of set data bits programmed in the memory block area. The memory device 10 (e.g., the control circuit 13) may compare the number of programmed set data bits with the number of set data bits output via the read circuit 122, and may output the difference between the number of programmed reset data bits and the number of reset data bits as the BER to the memory controller 20. The memory device 10 (e.g., the control circuit 13) may compare the determined number of memory cells in the resistance state read in the read operation at operation S1420 with the determined number of memory cells programmed to the resistance state at operation S1410. The memory device 10 (e.g., the control circuit 13) may output the difference between the determined number of memory cells in the resistance state at operation S1420 and the determined number of memory cells programmed to the resistance state at operation S1410 as the BER. According to some example embodiments, the control circuit 13 may count the number of programming operations performed in the memory cell array 11 ("quantity"), such as the number of programming operations performed on the memory cells in the resistance state, and may provide ("output") the number to the outside of the memory device 10, such as the memory controller 20. The memory controller 20 may receive one or more indicators indicating the degree of degradation of the memory cells of the memory device 10, so that the memory controller 20 may sense the degree of degradation of one or more memory cells of the memory device 10. Such one or more indicators may include data on the BER, the number of on cells, and / or the number of off cells. For example, the memory controller 20 may check the NPC of the memory device 10 corresponding to the BER to sense the degree of degradation of the memory device 10. In some example embodiments, the memory controller 20 may receive an indicator indicating the number of programming operations performed on the memory cell corresponding to a bit error rate (BER) occurring in a read operation performed on the memory cell at operation S1420. In some example embodiments, the memory controller 20 may receive an indicator indicating the number of programming operations to program the memory cell to a resistance state at operation S1410. A configuration for detecting a degree of degradation of the memory device 10, which may be a resistance memory device, is described in detail in U.S. Application No. 16 / 377,952, the entire contents of which are incorporated herein by reference in their entirety.

[0124] According to some example embodiments, the memory controller 20 may check the NPC of the reset data provided by the control circuit 13 of the memory device to sense the degree of degradation of the memory device 10 .

[0125] In operation S1440, the memory controller 20 may increase the magnitude of the write current I so that the set write current Iset increases according to the NPC checked in operation S1430, and the memory cell may be programmed by using the increased write current I. Thus, the memory controller 20 may control one or more memory cells of the memory device 10 to be programmed to the resistance state to which the (multiple) memory cells were programmed at operation S1410 based on the use of a write current having a current level greater than the current level of the minimum write current, based on an indicator indicating the degree of degradation, the minimum write current being necessary to program the (multiple) memory cells to the resistance state. For example, in the case where the resistance state in question is LRS, the magnitude (“current level”) of the write current I may be increased to be greater than the magnitude (“current level”) of the minimum set write current, which is necessary to change the memory cell MC from HRS to LRS. In some example embodiments, operation S1440 may include the memory controller 20 providing a control signal to the control circuit 13 of the memory device 10 based on the determined BER, which in response may cause the control circuit 13 to control the control voltage VC to change the write current I to increase in current level to a current level having a current level greater than a minimum write current necessary to change a memory cell of the memory device 10 to a resistance state. The control circuit 13 may, for example, control the control voltage VC to change the write current I to increase in current level to a current level having a current level greater than a minimum set write current necessary to change a memory cell of the memory device 10 to an LRS.

[0126] In the method of compensating for degradation of the memory device 10 by using the memory controller 20, as the magnitude of the write current I increases, so that the set write current Iset of the memory cell MC increases, the threshold voltage distribution of the set data can be moved to the LRS. Therefore, the set data sensing becomes more reliable and faster, and the time overhead can be eliminated. Therefore, the function of a computing device, an electronic device, etc. including the memory controller 20 and the memory device 10 can be improved.

[0127] Fig.15 1 is a block diagram schematically illustrating a configuration of a memory system employing a method of compensating for degradation of a memory device by using a memory controller according to some example embodiments of the inventive concept. Such a memory system 1500 may be referred to herein as a computing device, an electronic device, etc.

[0128] refer to Fig.15 , the memory system 1500 may include a memory controller 1510, a plurality of nonvolatile memory devices 1520 to 152n, and a volatile memory device 1530. The memory controller 1510 may control a write operation and / or a read operation of the plurality of nonvolatile memory devices 1520 to 152n in response to a request from a host connected to the memory system 1500.

[0129] According to some example embodiments, the host may be any computing system, such as a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television (TV), a set-top box, a music player, a portable game console, and a navigation system.

[0130] A plurality of nonvolatile memory devices 1520 to 152n are used as storage media of the memory system 1500. Each of the nonvolatile memory devices 1520 to 152n may be, for example, a resistive memory device. The plurality of nonvolatile memory devices 1520 to 152n may be connected to the memory controller 1510 via a channel. Each of the nonvolatile memory devices 1520 to 152n may perform a write operation and / or a read operation in response to a request from a host provided via the channel.

[0131] The volatile memory device 1530 may temporarily store write data provided from the host or read data provided from the nonvolatile memory devices 1520 to 152n (including the nonvolatile memory device 152n where n is greater than zero). The volatile memory device 1530 may store metadata or cache data to be stored in the nonvolatile memory devices 1520 to 152n. DRAM, SRAM, etc. may be included in the volatile memory device 1530.

[0132] Each of the nonvolatile memory devices 1520 to 152n may be a reference Figures 1 to 14The memory device 10 described above corresponds to a resistance memory device. Each of the nonvolatile memory devices 1520 to 152n may include: a memory cell array 310 including a plurality of memory cells; a write / read circuit 320 for programming the memory cells to a first resistance state by using a write current according to a control voltage and reading data from the programmed memory cells; and a control circuit 330 for counting the BER of the memory cells occurring in a read operation and outputting the BER to the memory controller 1510. In response to a BER-based control signal received from the memory controller 1510, the control circuit 330 may provide a control voltage so that the write current I has a magnitude greater than a magnitude of a minimum write current required to change the memory cell to the first resistance state.

[0133] The memory controller 1510 can compensate for degradation for each of the nonvolatile memory devices 1520 to 152n. The memory controller 1510 can perform the following operations: control each of the nonvolatile memory devices 1520 to 152n to program a memory cell to a first resistance state; control the memory device to read data from the memory cell programmed to the first resistance state; receive the BER of the memory cell occurring in the read operation from each of the nonvolatile memory devices 1520 to 152n; determine the NPC of the memory cell corresponding to the BER; and, based on the determined NPC, control the memory cell in the nonvolatile memory devices 1520 to 152n to be programmed to the first resistance state by using a write current greater than a minimum write current, the minimum write current being necessary to change the memory cell to the first resistance state.

[0134] Fig.16 1 is a block diagram illustrating a system 1600 to which a method of compensating for degradation of a memory device by using a memory controller may be applied. The system 1600 may be referred to herein as a computing device, an electronic device, or the like.

[0135] refer to Fig.16 , the system 1600 may include a processing unit 1610 (also referred to herein as a processor, an instance of a processing circuit, etc.), a volatile memory unit 1620 (also referred to herein as a memory, a memory device, a storage device, etc.), a resistive memory unit 1630 (also referred to herein as a resistive memory device, a resistive storage device, a memory device, etc.), and a mass storage unit 1640 (also referred to herein as a mass storage device). The system 1600 may be a general-purpose or special-purpose computer system, such as a mobile device, a personal computer, a server computer, a programmable home appliance, a mainframe computer.

[0136] In terms of implementation independence, the functional units described in some example embodiments may be classified as modules. For example, a module may be implemented in a custom Very-Large-Scale Integration (VLSI) circuit or hardware circuit including an off-the-shelf semiconductor (such as a gate array, a logic chip, a transistor, or another discrete component). A module may be implemented in a programmable hardware device, such as a programmable gate array, a programmable gate logic, a programmable gate device, etc. In addition, a module may be implemented in software that configures executable code, an object, a process, or a function.

[0137] The processing unit 1610 can run an operating system and multiple software systems and perform specific calculations or tasks. The processing unit 1610 can be a microprocessor or a central processing unit (CPU).

[0138] The volatile memory unit 1620 is a medium that temporarily or occasionally stores data, and serves as an operational memory or cache memory of the system 1600. The volatile memory unit 1620 may include at least one memory device, such as a dynamic random access memory (DRAM).

[0139] The resistive memory unit 1630 may be used as a cache for the large-capacity memory unit 1640. Part of the data frequently accessed by an application or an operating system may be stored in the resistive memory unit 1630. The resistive memory unit 1630 may include at least one memory device, such as a PRAM. Since access to the resistive memory unit 1630 is faster than when data is accessed via the large-capacity storage unit 1640 (e.g., an HDD (hard disk drive)), the resistive memory unit 1630 may be used as a cache. The resistive memory unit 1630 may be used to store data in a high-speed manner. Figures 1 to 14 The example embodiments shown are implemented.

[0140] The resistance memory cell 1630 may include: a memory cell array including a plurality of memory cells; a write circuit configured to perform a write operation by using a write current according to a control voltage to program the memory cell to a first resistance state; a read circuit configured to perform a read operation to read data from the memory cell programmed to the first resistance state; and a control circuit configured to count the BER of the memory cell occurring in the read operation and output the BER to the memory controller. The control circuit may provide a control voltage in response to a control signal based on the BER received from the memory controller 1510 so that the write current is greater than a minimum write current required to change the memory cell to the first resistance state.

[0141] The mass storage unit 1640 can be implemented in a hard disk drive (HDD), a solid state drive (Solid State Drive, SDD), a high-speed peripheral component interconnect (Peripheral Component Interconnect express, PCIe) memory module, a high-speed non-volatile memory (Non-Volatile Memory express, NVMe), etc. Optionally, one or more levels in the mass storage unit 1640 can be implemented in one or more network-accessible devices and / or services, such as multiple clients, multiple servers, Fabric-based NVMe (NVMe-oF) and / or Remote Direct Memory Access (Remote Direct Memory Access, RDMA), (multiple) server groups, (multiple) server clusters, (multiple) application servers, or (multiple) message servers. The mass storage unit 1640 is a storage medium that the system 1600 attempts to store user data for a long time. The mass storage unit 1640 can store applications, program data, etc.

[0142] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A method of operating a memory controller, the memory controller being configured to control a resistive memory device, the resistive memory device comprising a plurality of memory cells, the method comprising: controlling the resistive memory device to program the plurality of memory cells to a first resistance state; controlling the resistive memory device to perform a read operation on the plurality of memory cells programmed to the first resistance state; receiving an indicator from the resistive memory device indicating a degree of degradation of the plurality of memory cells; as well as Based on the indicator indicating the degree of degradation, controlling the plurality of memory cells to be programmed to the first resistance state based on using a write current having a current level greater than a minimum write current, wherein the minimum write current is necessary to program the plurality of memory cells to the first resistance state, wherein the indicator includes a bit error rate BER occurring in a read operation on the plurality of memory cells.

2. The method according to claim 1, wherein The indicator indicates a number of program operations performed on the plurality of memory cells corresponding to a bit error rate BER.

3. The method according to claim 1, wherein The BER is determined according to a level of a read voltage used for a read operation on the plurality of memory cells.

4. The method according to claim 1, wherein The indicator indicates a number of programming operations to program the plurality of memory cells to the first resistance state.

5. The method according to claim 1, wherein The plurality of memory cells comprises a plurality of single level cells, and The first resistance state is a high resistance state or a low resistance state.

6. The method according to claim 5, wherein A current level of the write current is greater than a current level of a minimum reset write current necessary to change the plurality of memory cells to the high resistance state.

7. The method according to claim 5, wherein A current level of the write current is greater than a current level of a minimum set write current necessary to change the plurality of memory cells to the low resistance state.

8. The method according to claim 1, wherein The plurality of memory cells comprises a plurality of multi-level cells, and The first resistance state is one resistance state among a plurality of resistance states.

9. The method according to claim 8, wherein The first resistance state is a high resistance state among the plurality of resistance states, and A current level of the write current is greater than a current level of a minimum reset write current necessary to change the plurality of memory cells to the high resistance state.

10. The method according to claim 8, wherein The first resistance state is a low resistance state among the plurality of resistance states, and A current level of the write current is greater than a current level of a minimum set write current necessary to change the plurality of memory cells to the low resistance state.

11. A resistive memory device comprising: a memory cell array comprising a plurality of memory cells; a write circuit configured to perform a write operation by using a write current according to a control voltage to program the plurality of memory cells to a first resistance state; a read circuit configured to perform a read operation to read data from the plurality of memory cells programmed to the first resistance state; and a control circuit configured to count bit error rates BER of the plurality of memory cells occurring in a read operation and output the BER to the outside of the resistive memory device, wherein the control circuit is configured to, in response to a control signal based on the BER received from outside the resistive memory device, control the control voltage so that the write current increases to a current level having a current level greater than a minimum write current, wherein the minimum write current is necessary to change the plurality of memory cells to the first resistance state.

12. The resistive memory device according to claim 11, wherein The control circuit is configured to output a number of programming operations performed on a plurality of memory cells in the first resistance state to the outside of the resistance memory device.

13. The resistive memory device according to claim 11, wherein The BER is determined according to the level of a read voltage used for a read operation.

14. The resistive memory device according to claim 11, wherein The control circuit is configured to: storing a determined number of memory cells programmed to the first resistance state in a write operation, comparing the determined number of memory cells in the first resistance state read in a read operation to the number of memory cells programmed to the first resistance state, and A difference between the number of memory cells in the first resistance state and the number of memory cells programmed to the first resistance state is output as the BER.

15. The resistive memory device according to claim 11, wherein The plurality of memory cells are single level cells, and The first resistance state is a high resistance state or a low resistance state.

16. The resistive memory device of claim 15, wherein The control circuit is configured to control the control voltage so that a current level of the write current increases to a current level greater than a current level of a minimum reset write current necessary to change the plurality of memory cells to the high resistance state.

17. The resistive memory device according to claim 15, wherein The control circuit is configured to control the control voltage so that a current level of the write current increases to a current level higher than a current level of a minimum set write current necessary to change the plurality of memory cells to the low resistance state.

18. The resistive memory device of claim 11, wherein The plurality of memory cells are multi-level cells, and The first resistance state is one resistance state among a plurality of resistance states.

19. The resistive memory device of claim 18, wherein The first resistance state is a high resistance state among the plurality of resistance states, and The control circuit is further configured to control the control voltage so that a current level of the write current increases to a current level greater than a current level of a minimum reset write current necessary to change the plurality of memory cells to the high resistance state.

20. The resistive memory device of claim 18, wherein The first resistance state is a low resistance state among the plurality of resistance states, and The control circuit is further configured to control the control voltage so that a current level of the write current increases to a current level greater than a current level of a minimum reset write current necessary to change the plurality of memory cells to the low resistance state.

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