Method and system for detecting degradation of a resistive memory device

Abstract

The memory controller may detect degradation based on a bit error rate (BER) of a resistive memory device including a memory cell. The memory controller may control the memory cell to be programmed to a first resistance state, read the programmed memory cell, and receive the BER of the memory cell generated during the read operation from the resistive memory device. The memory controller may determine the number of programming loops for the memory cell based on the BER. The number may be determined based on reference to a lookup table indicating a correlation between the BER and the number of programming loops.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0092050 filed on August 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to nonvolatile memory devices, and more particularly, to methods and systems for detecting degradation of resistive memory devices. Background Art

[0004] As non-volatile memory devices, resistive memory devices such as phase change random access memory (RAM) (PRAM), resistive RAM (RRAM), magnetic RAM (MRAM), etc. are known. The resistive memory device uses a variable resistance device as a memory cell, and the variable resistance device is configured to store data according to a change in resistance state. The resistive memory device includes: a cross-point resistive memory device, including one or more memory cells located at the intersection of multiple bit lines and multiple word lines. The resistive memory device can access the memory cell by applying a voltage to both ends of the memory cell therein, and can store a logic "1 (set data)" (low resistance state) or a logic "0 (reset data)" (high resistance state) regarding the threshold resistance of the memory cell.

[0005] Important criteria in resistive memory devices are retention time, which is the time that data can be retained, and endurance level, which is the level at which normal operations can be performed without exhaustion when data is written. Data retention and endurance may depend on environments that deteriorate the characteristics of the memory cell, such as high temperatures and / or programming cycles. Degradation of the memory cell may reduce the sensing margin between a logic "1" as set data and a logic "0" as reset data. As a result, the sensing of the set data or reset data may become more uncertain or slower, or may result in multiple bit errors. Degradation of the resistive memory device reduces the performance of the memory device including the resistive memory device. Summary of the invention

[0006] The inventive concept provides a method and system for detecting degradation of a resistive memory device.

[0007] According to one aspect of the present invention, a method for operating a memory controller is provided, wherein the memory controller is configured to control a resistive memory device, and the resistive memory device includes a plurality of memory cells, the method may include: controlling the resistive memory device to program the plurality of memory cells to a first resistance state; controlling the resistive memory device to read the programmed plurality of memory cells; receiving a bit error rate (BER) of the memory cells generated during a read operation from the resistive memory device; and determining the number of programming loops of the memory cells based on the BER.

[0008] According to some example embodiments, a resistive memory device may include: a memory cell array including a plurality of memory cells; a write circuit configured to program the plurality of memory cells to a first resistance state; a read circuit configured to read the programmed plurality of memory cells; and a control circuit configured to output a bit error rate (BER) of the memory cells generated during a read operation to the outside of the resistive memory device so as to enable determination of a number of programming cycles of the plurality of memory cells based on the BER.

[0009] According to some example embodiments, a memory system may include a resistive memory device and a memory controller configured to control the resistive memory device. The resistive memory device may include: a memory cell array including a plurality of memory cells; a write circuit configured to program the plurality of memory cells to a first resistance state; a read circuit configured to read the programmed plurality of memory cells; and a control circuit configured to provide a bit error rate (BER) of the plurality of memory cells generated during a read operation. The control circuit may be configured to provide the BER to the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 It is shown Figure 1 A block diagram of a memory device included in a memory system;

[0013] Figure 3 It is shown Figure 2 A detailed circuit diagram of a memory cell array;

[0014] Figure 4A , Figure 4B , Figure 4C and Figure 4D It is shown Figure 3 A modified circuit diagram of a memory cell;

[0015] Figure 5 Shown in Figure 3 An example of a variable resistance element included in a memory cell of;

[0016] Figure 6 is used to describe the Figure 5 A graph showing a write current of a memory cell;

[0017] Fig. 7A , Figure 7B and Figure 7C It is shown in Figure 5 A diagram of characteristics of a memory cell when the memory cell is a single-layer cell.

[0018] Figure 8 It means in Figure 5 A graph of memory cell distribution depending on resistance when the memory cell is a multi-level cell (MLC);

[0019] Fig. 9 It is used to indicate the reset data state. Fig. 7A A graph of threshold voltage distribution of memory cells;

[0020] Fig.10 , Fig.11 , Fig.12 and Fig.13 is a diagram illustrating a method of detecting degradation of a memory device according to some example embodiments of the inventive concept;

[0021] Fig.14 is a flowchart illustrating a method according to some example embodiments of the inventive concept, the method being performed by a memory controller detecting degradation of a memory device;

[0022] Fig.15 It is used to indicate the state of the set data. Fig. 7A A graph showing a threshold voltage distribution of a memory cell;

[0023] Fig.16 , Fig.17 , Fig.18 and Fig.19 is a diagram illustrating a method of detecting degradation of a memory device according to some example embodiments of the inventive concept;

[0024] Fig. 20 is a flowchart illustrating a method of detecting degradation of a memory device according to some example embodiments of the inventive concept;

[0025] Fig.21is a block diagram illustrating a schematic configuration of a memory system according to some example embodiments of the inventive concept, the memory system employing a method performed by a memory controller detecting degradation of a memory device; and

[0026] Fig. 22 is a block diagram illustrating a system according to some example embodiments of the inventive concept, to which a method performed by a memory controller to detect degradation of a memory device is applied. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram illustrating a memory system 1 according to an exemplary embodiment of the inventive concept. The memory system 1 may be included in an electronic device, a computing device, and the like.

[0028] refer to Figure 1 , the memory system 1 may include a memory device 10 and a memory controller 20. The memory controller 20 may be implemented by one or more instances of circuits, including instances of processing circuits (e.g., processor devices). The memory device 10 may include a memory cell array 11, a write / read circuit 12, and a control circuit 13. It should be understood that the memory device 10 described herein may be a resistive memory device.

[0029] The memory controller 20 may control the memory device 10 to read data stored in the memory device 10 or write data to the memory device 10 in response to a read / write request from the host HOST. The memory controller 20 may control a programming (e.g., writing) operation and a reading operation on the memory device 10 by providing an address signal ADDR, a command signal CMD, and a control signal CTRL to the memory device 10. Data DATA for a programming operation and read data DATA may be transmitted and received between the memory controller 20 and the memory device 10.

[0030] Although not shown, the memory controller 20 may include a RAM, a processing unit, a host interface, a memory interface, a read-only memory (ROM), or a non-volatile memory. The RAM may be used as an operating memory of the processing unit. The processing unit may control the operation of the memory controller 20. The host interface may include a protocol for performing data exchange between the host HOST and the memory controller 20. For example, the memory controller 20 may be configured to communicate with the host HOST via at least one of various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, SCSI, ESDI, Integrated Drive Electronics (IDE), etc.

[0031] The memory controller 20 can quickly detect the degree of degradation of the memory device 10 with reference to the lookup table LUT. The lookup table LUT can be stored in the memory controller 20. The lookup table LUT can be set to the ratio of the number of programming loops to the bit error rate (BER) of the memory device 10. The lookup table LUT can indicate: the correlation between the BER according to multiple reset read voltage levels and / or the BER according to multiple reset write current levels and the number of programming loops. Alternatively, the lookup table LUT can indicate: the correlation between the BER according to multiple set read voltage levels and / or the BER according to multiple set write current levels and the number of programming loops. The lookup table LUT can be stored in a ROM or a non-volatile memory.

[0032] The memory cell array 11 may include a plurality of memory cells, and the plurality of memory cells are arranged in a region where a plurality of first signal lines and a plurality of second signal lines intersect each other. In some example embodiments, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. In some example embodiments, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines. In some example embodiments, the memory cells of the memory cell array 11 include one or more multi-layer cells. In some example embodiments, the memory cells of the memory cell array 11 include one or more single-layer cells.

[0033] In some example embodiments, the plurality of memory cells may include a resistance memory cell or a resistance memory cell including a variable resistance element having a variable resistance. For example, when the variable resistance element is a phase change material (GST, Ge-Sb-Te) and the resistance changes with temperature, the memory device 10 may be a PRAM. In another example, when the variable resistance element includes an upper electrode, a lower electrode, and a composite metal oxide between the upper electrode and the lower electrode, the memory device 10 may be an RRAM. As another example, when the variable resistance element includes an upper electrode of a magnetic material, a lower electrode of a magnetic material, and a dielectric material between the upper electrode and the lower electrode, the memory device 10 may be an MRAM.

[0034] The write / read circuit 12 can program the memory cell and read the programmed memory cell. The write / read circuit 12 can repeatedly program the memory cell to a data state and read the programmed memory cell. The write / read circuit 12 can perform a programming operation by applying a plurality of write currents to the memory cell, and use a read voltage to perform a read operation of reading the programmed memory cell. The plurality of write currents may include a minimum write current required to cause a phase change layer of the memory cell to cause a phase change. Alternatively, the write / read circuit 12 can perform a programming operation by applying a minimum write current required to cause a phase change layer of the memory cell to cause a phase change, and use a plurality of read voltages to perform a read operation of reading the programmed memory cell.

[0035] The control circuit 13 may count the BER of the memory cell generated during the read operation. The control circuit 13 may provide the BER to the memory controller 20. The control circuit 13 may provide the memory controller 20 with the BER according to a plurality of write currents and / or the BER according to a plurality of read voltages.

[0036] The memory controller 20 and the memory device 10 may be integrated into one semiconductor device. For example, the memory controller 20 and the memory device 10 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 20 and the memory device 10 may be integrated into a single semiconductor device to configure a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD), a universal flash memory (UFS), etc. As another example, the memory controller 20 and the memory device 10 may be integrated into a single semiconductor device to configure a solid state disk / drive (SSD).

[0037] Figure 2 It is shown Figure 1 1 is a block diagram of a memory device 10 included in a memory system 1.

[0038] refer to Figure 2 , the memory device 10 may include a memory cell array 11, a write / read circuit 12, a control circuit 13, a voltage generator 14, a row decoder 15, and a column decoder 16. The write / read circuit 12 may include a write circuit 121 and a read circuit 122. The row decoder 15 may be referred to as a row decoder circuit herein. The column decoder 16 may be referred to as a column decoder circuit herein.

[0039] The memory cell array 11 may be connected to a plurality of first signal lines and a plurality of second signal lines, and may include a plurality of memory cells respectively disposed in regions where the plurality of first signal lines and the plurality of second signal lines cross each other. Hereinafter, some example embodiments of the inventive concept will be described by taking an example where the plurality of first signal lines are bit lines BL and the plurality of second signal lines are word lines WL.

[0040] The memory cell array 11 may be a two-dimensional memory cell array of a horizontal structure, and may include a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells MC, such as Figure 3 As shown. The memory cell array 11 may include a plurality of memory blocks. Each memory block may have a plurality of memory cells arranged in rows and columns. Here, according to some example embodiments, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may be changed differently. However, the inventive concept is not limited thereto, and in some example embodiments, the memory cell array 11 may be a three-dimensional memory cell array of a vertical structure.

[0041] According to some example embodiments, each of the plurality of memory cells MC may include a variable resistance element R and a selection element D. Here, the variable resistance element R may be referred to as a variable resistance material, and the selection element D may be referred to as a switching element.

[0042] In some example embodiments, the variable resistance element R may be connected between one of the plurality of bit lines BL1 to BLm and the selection element D, and the selection element D may be connected between the variable resistance element R and one of the plurality of word lines WL1 to WLn. However, the inventive concept is not limited thereto, and the selection element D may be connected between one of the plurality of bit lines BL1 to BLm and the variable resistance element R, and the variable resistance element R may be connected to the selection element D and one of the plurality of word lines WL1 to WLn.

[0043] The selection element D may be connected between any one of the plurality of word lines WL1 to WLn and the variable resistance element R, and may control current supply to the variable resistance element R according to voltages applied to the connected word line and bit line. Figure 3 In FIG. 1 , the selection element D is illustrated as a diode, but this is merely an example embodiment of the inventive concept, and in some example embodiments, the selection element D may be changed to another switchable element.

[0044] You can Figure 4A , Figure 4B , Figure 4C and Figure 4D The modification of the memory cell MC is shown. Figure 4A, the memory cell MCa may include a variable resistance element Ra, and the variable resistance element Ra may be connected to a bit line BL and a word line WL. The memory cell MCa may store data according to voltages respectively applied to the bit line BL and the word line WL.

[0045] exist Figure 4B In the embodiment, the memory cell MCb may include a variable resistance element Rb and a unidirectional diode Da. The variable resistance element Rb may include a resistance material for storing data. The unidirectional diode Da may be a selection element (i.e., a switching element) that provides current to the variable resistance element R or blocks current according to the bias of the word line WL and the bit line BL. The unidirectional diode Da may be connected between the variable resistance element Rb and the word line WL, and the variable resistance element R may be connected between the bit line BL and the unidirectional diode Da. The positions of the unidirectional diode Da and the variable resistance element R may be switched with each other.

[0046] In some example embodiments, the unidirectional diode Da may be a PN junction or a PIN junction diode, an anode of the unidirectional diode Da may be connected to the variable resistance element Rb, and a cathode of the unidirectional diode Da may be connected to one of the plurality of word lines WL1 to WLn. At this time, when the voltage difference between the anode and the cathode of the unidirectional diode Da is greater than the threshold voltage of the unidirectional diode Da, the unidirectional diode Da may be turned on, and thus current may be provided to the variable resistance element Ra.

[0047] exist Figure 4C In the embodiment, the memory cell MCc may include a variable resistance element Rc and a bidirectional diode Db. The variable resistance element Rc may include a resistance material for storing data. The bidirectional diode Db may be connected between the variable resistance element Rc and the word line WL, and the variable resistance element Rc may be connected between the bit line BL and the bidirectional diode Db. The positions of the bidirectional diode Db and the variable resistance element Rc may be exchanged with each other. The leakage current flowing in the unselected resistance unit may be blocked by the bidirectional diode Db.

[0048] exist Figure 4D In the embodiment, the memory cell MCd may include a variable resistance element Rd and a transistor TR. The transistor TR may be a selection element (i.e., a switching element) that provides current to the variable resistance element Rd or blocks current according to the voltage of the word line WL. The transistor TR may be connected between the variable resistance element Rd and the word line WL, and the variable resistance element Rd may be connected between the bit line BL and the transistor TR. The positions of the transistor TR and the variable resistance element Rd may be interchanged with each other. The memory cell MCd may be selected or not selected depending on whether the transistor TR driven by the word line WL is turned on or off.

[0049] Refer again Figure 2The write circuit 121 may be connected to the selected bit line BL and provide a programming current to the selected memory cell MC to perform a programming operation (ie, a writing operation) to input data DATA to be stored in the memory cell array 11. Here, the programming current may be referred to as a writing current.

[0050] When a write command is received from the memory controller 20, the write circuit 121 may perform a write operation on the memory cell MC. The write circuit 121 may perform a reset write operation, which programs the memory cell MC in a direction in which the resistance of the memory cell MC increases. In addition, the write circuit 121 may perform a set write operation, which programs the memory cell MC in a direction in which the resistance of the memory cell MC decreases.

[0051] In some example embodiments, the write circuit 121 may provide a minimum reset write current required for the memory cell MC to become a high resistance state to program the memory cell MC to reset data of the high resistance state. Alternatively, the write circuit 121 may provide a plurality of reset write currents to the memory cell MC to program the memory cell MC to reset data of the high resistance state. The plurality of reset write currents may include a minimum reset write current required for the memory cell MC to become a high resistance state.

[0052] In some example embodiments, the write circuit 121 may provide a minimum set write current required for the memory cell MC to become a low resistance state to program the memory cell MC to the set data of the low resistance state. Alternatively, the write circuit 121 may provide a plurality of set write currents to the memory cell MC to program the memory cell MC to the set data of the low resistance state. The plurality of set write currents may include the minimum set write current required for the memory cell MC to become a low resistance state.

[0053] The read circuit 122 may be connected to the selected bit line BL to read the data DATA stored in the selected memory cell MC. When a read command is received from the memory controller 20, the read circuit 122 may perform a read operation on the memory cell MC. The read circuit 122 may read the data of each memory cell MC and provide the read result to the control circuit 13.

[0054] In some example embodiments, the read circuit 122 may perform a read operation on the memory cells MC programmed to the minimum reset write current using a plurality of reset read voltages. Alternatively, the read circuit 122 may perform a read operation on the memory cells MC programmed to a plurality of reset write currents using a reset read voltage.

[0055] In some example embodiments, the read circuit 122 may perform a read operation on the memory cells MC programmed to the minimum set write current using a plurality of set read voltages. Alternatively, the read circuit 122 may perform a read operation on the memory cells MC programmed to a plurality of set write currents by using the set read voltages.

[0056] The control circuit 13 may output various control signals CTRL_OP. CTRL_VOL is used to write data DATA to the memory cell array 11 or read data DATA from the memory cell array 11 based on the command signal CMD, the address signal ADDR and the control signal CTRL received from the memory controller 20. The control circuit 13 may provide the operation control signal CTRL_OP to the write / read circuit 12. In addition, the control circuit 13 may provide the voltage control signal CTRL_VOL to the voltage generator 14. In addition, the control circuit 13 may provide the row address X_ADDR to the row decoder 15 and the column address Y_ADDR to the column decoder 16.

[0057] The control circuit 13 may control the same data to be repeatedly programmed to the memory cells MC in all or some memory blocks in the memory cell array 11 .

[0058] In some example embodiments, the control circuit 13 may control the reset data to be programmed in the memory cells MC of the memory block and store the number of programmed reset data bits in the memory block area. The control circuit 13 may compare the number of programmed reset data bits with the number of reset data bits read by the read circuit 122 and output the difference as the BER. The control circuit 13 may provide the memory controller 20 with the BER of the memory cells programmed to the multiple reset write currents and / or the BER of the memory cells read at the levels of the multiple reset read voltages. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the multiple reset write voltages and / or the BER according to the levels of the multiple reset read voltages.

[0059] In some example embodiments, the control circuit 13 may control the set data to be programmed in the memory cells MC of the memory block, and store the number of set data bits programmed in the memory block area. The control circuit 13 may compare the number of programmed set data bits with the number of set data bits read by the read circuit 122, and output the difference as the BER. The control circuit 13 may provide the memory controller 20 with the BER of the memory cells programmed to the multiple set write currents and / or the BER of the memory cells read at the levels of the multiple set read voltages. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the multiple set write voltages and / or the BER according to the levels of the multiple set read voltages.

[0060] The voltage generator 14 may generate various voltages for performing write and read operations on the memory cell array 11 based on the voltage control signal CTRL_vol. More specifically, the voltage generator 14 may generate a first driving voltage V for driving a plurality of word lines WL. WL and a second driving voltage V for driving a plurality of bit lines BL BL .

[0061] The row decoder 15 may be connected to the memory cell array 11 through a plurality of word lines WL, and may activate a selected word line among the plurality of word lines WL in response to a row address X_ADDR received from the control circuit 13. The row decoder 15 may control a voltage applied to the selected word line among the plurality of word lines WL, or control a connection relationship of the selected word line in response to the row address X_ADDR.

[0062] The column decoder 16 may be connected to the memory cell array 11 through a plurality of bit lines BL, and may activate a selected bit line among the plurality of bit lines BL in response to a column address Y_ADDR received from the control circuit 13. The column decoder 16 may control a voltage applied to a selected bit line among the plurality of bit lines BL, or control a connection relationship of the selected bit line in response to the column address Y_ADDR.

[0063] Figure 5 Shown included in Figure 3 An example of a variable resistance element R in a memory cell MC.

[0064] refer to Figure 5 , the memory cell MC may include a variable resistance element R and a switch element SW. The switch element SW may be implemented using various elements such as a transistor, a diode, etc. Figure 5As shown in the figure, the variable resistance element R may include: a phase change film 51 including a mixture of germanium, antimony and tellurium (GST, Ge—Sb—Te); an upper electrode 52 formed on the phase change film 51; and a lower electrode 53 formed under the phase change film 51.

[0065] The upper electrode 52 and the lower electrode 53 may include various metals, metal oxides, or metal nitrides. The upper electrode 52 and the lower electrode 53 may include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAlyNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO 2 ), strontium zirconate (StZrO 3 )wait.

[0066] The phase change film 51 may include a bipolar resistance storage material or a unipolar resistance storage material. The bipolar resistance storage material may be programmed to a set state or a reset state by the polarity of the current, and the bipolar resistance storage material may be a perovskite-based material. At the same time, the unipolar resistance storage material may be programmed to a set state or a reset state by a current of the same polarity, and a transition metal oxide such as NiOx or TiOx may be used for the unipolar resistance storage material.

[0067] The GST material can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. The GST material can be programmed by heating the GST material. The amplitude and time of the heating can determine whether the GST material remains in the amorphous state or the crystalline state. The high resistivity and the low resistivity can each be represented by a programming value logic "0" or logic "1", and can be detected by measuring the resistivity of the GST material. Conversely, the high resistivity and the low resistivity can each be represented by a programming value logic "1" or logic "0".

[0068] exist Figure 5 In the embodiment, when the write current I is applied to the memory cell MC, the applied write current I may flow through the lower electrode 53. When the write current I is applied to the memory cell MC for a very short time, the applied write current I may be heated to Joule heat only by the adjacent film of the lower electrode 53. At this time, a limited portion (e.g., Figure 5 The shaded portion 51a) in FIG. 5 may enter a crystalline state (eg, a set state) or an amorphous state (eg, a reset state) due to the difference in the heating curve, while the remaining portion 51b of the phase change film 51 may avoid entering the crystalline state or the amorphous state.

[0069] Figure 6 is used to describe the Figure 5 FIG. 5 is a graph showing the write current of the memory cell MC.

[0070] Reference Figure 6 In order to change the phase change film 51 to an amorphous state (e.g., a reset state), a high reset write current Irst may be applied to the memory cell MC for a short time, and then the high reset write current Irst may be removed. In order to change the phase change film 51 to a crystalline state (e.g., a set state), a low set write current Iset lower than the reset write current Irst may be applied to the memory cell MC, and the applied set write current Iset may be maintained for a predetermined time, and then the low set write current Iset may be removed, so that the phase change film 51 is crystallized. According to the above method, the memory cell MC may be set to a crystalline state or an amorphous state. Here, TP1 represents the crystallization temperature of the phase change film 51, and TP2 represents the melting point of the phase change film 51.

[0071] Fig. 7A , Figure 7B and Figure 7C It shows that Figure 5 A diagram showing characteristics of a memory cell MC when the memory cell MC is a single-layer cell (SLC).

[0072] refer to Fig. 7A , shows the ideal threshold voltage distribution of SLC, where the memory cell MC is programmed to 1 bit. Fig. 7A , the horizontal axis may represent the threshold voltage, and the vertical axis may represent the number of memory cells.

[0073] The variable resistance element R of the memory cell MC may have a low resistance state LRS or a high resistance state HRS. The operation of applying a write current to the memory cell MC and switching the variable resistance element R from the high resistance state HRS to the low resistance state LRS may be referred to as a set operation or a set write operation. The operation of applying a write current to the memory cell MC and switching the variable resistance element R from the low resistance state HRS to the high resistance state HRS may be referred to as a reset operation or a reset write operation.

[0074] A specific voltage between the scattering due to the low resistance state LRS and the scattering due to the high resistance state HRS can be set as the read voltage Vread. In the read operation of the memory cell MC, when the read result is equal to or higher than the read voltage Vread, the reset data (logic "0") in the high resistance state HRS can be determined, and when the read result is equal to or lower than the read voltage Vread, the set data (logic "1") in the low resistance state LRS can be determined. When the memory cell MC is repeatedly programmed to the reset data (logic "0") or the set data (logic "1"), as shown in FIG. Figure 7B and Figure 7C As shown, the resistance characteristic of the memory cell MC can be reduced.

[0075] refer to Figure 7B , shows an exemplary characteristic of a memory cell MC, which is continuously programmed to reset data of logic "0" by applying a high current. Figure 7B , the horizontal axis may represent the number of programming cycles, and the vertical axis may represent resistance. The resistivity of the memory cell MC may initially be well behaved, so that the phase change film 51 exhibits a high resistance. However, when the memory cell MC is continuously programmed to reset data of logic "0" without intermediate programming to set data of logic "1", the resistance of the memory cell MC may decrease. As a result, the sensing of the reset data of logic "0" may become more uncertain or slower, or generally less reliable, because the sensing margin between the set data of logic "1" and the reset data of logic "0" is reduced. Therefore, the reliability of the resistive memory device may be reduced.

[0076] refer to Figure 7C , degradation of the reset data of logic "0" may also exist in the set data of logic "1". When the memory cell MC is continuously programmed to the set data of logic "1" without intermediate programming to the reset data of logic "0", the resistance of the memory cell MC may increase according to the number of programming loops. The increase in the resistance of the set data of logic "1" may reduce the sensing margin between the set data of logic "1" and the reset data of logic "0", thereby reducing the reliability of the resistive memory device.

[0077] Figure 8 It means when Figure 5 A graph showing distribution of memory cell MCs depending on resistance when the memory cell MC is a multi-layer cell MLC. Figure 8 , the horizontal axis may represent the threshold voltage Vth, and the vertical axis may represent the number of memory cells MC.

[0078] refer to Figure 8 , when the memory cell MC is an MLC programmed to 2 bits, the memory cell MC may have one of a first resistance state RS1, a second resistance state RS2, a third resistance state RS3, and a fourth resistance state RS4. In some example embodiments, the memory device 10 may be controlled to program the memory cells MC of the memory cell array 11 to one or more resistance states of the first resistance state RS1 to the fourth resistance state RS4. The memory controller 20 may be configured to control the memory device 10 to program the memory cells MC of the memory cell array 11 to one or more resistance states of the first resistance state RS1 to the fourth resistance state RS4.

[0079] However, the inventive concept is not limited thereto, and in other embodiments, the plurality of memory cells may include a three-layer cell TLC storing three bits of data such that each memory cell can receive one of eight resistance states. In some example embodiments, the plurality of memory cells may include memory cells each storing four or more bits of data.

[0080] Since the intervals between the resistance distributions of the MLC are narrower than those of the SLC, a read error may occur due to a small change in the threshold voltage in the MLC. Therefore, the resistance states RS1, RS2, RS3, and RS4 may have threshold voltage ranges that do not overlap with each other to ensure a read margin.

[0081] Each of the resistance states RS1, RS2, RS3, and RS4 may correspond to any one of data '00', data '01', data '10', and data '11'. In some example embodiments, the resistance level may increase in the order of data '11', data '01', data '00', and data '10'. That is, the first resistance state RS1 may correspond to data '11', the second resistance state RS2 may correspond to data '01', the third resistance state RS3 may correspond to data '00', and the fourth resistance state RS4 may correspond to data '10'.

[0082] As the number of program loops of the memory cell MC increases, each resistance state RS1, RS2, RS3, and RS4 may extend the threshold voltage range. Therefore, the read margin of each resistance state RS1, RS2, RS3, and RS4 may be reduced.

[0083] Fig. 9 It is used to indicate the reset data state. Fig. 7A FIG. 5 is a diagram showing the threshold voltage distribution of memory cells MC.

[0084] Reference Fig. 9 , shows the threshold voltage distribution of reset data according to a programming operation performed by applying a plurality of reset write currents Irst1, Irst2, and Irst3 to the memory cell MC. In the initial programming operation, the threshold voltage distribution of the reset data of the memory cell MC programmed according to the plurality of reset write currents Irst1, Irst2, and Irst3 may have almost the same shape. Thereafter, when the number of programming loops increases to about M times, it can be seen that the shape of the threshold voltage distribution of the reset data is changed and widened (A).

[0085] For example, assuming that among a plurality of reset write currents Irst1, Irst2, and Irst3, the highest current is the first reset write current Irst1, and the lowest current is the third reset write current Irst3. It can be seen that the threshold voltage distribution of the reset data of the memory cell MC programmed to the lowest third reset write current Irst3 is shifted to the left (i.e., toward the low resistance state of the set data), and the threshold voltage distribution is greatly widened due to the stress according to M programming cycles.

[0086] When the memory cell MC is read using the read voltage Vread to read the memory cell MC programmed to the third reset write current Irst3, the memory cell MC belonging to the shaded portion may be programmed to the reset data, but may be determined as the set data due to the reduction in the threshold voltage. That is, the number of memory cells belonging to the shaded portion may be expressed as a BER, which may be large. It can be expected that as the number of programming loops increases, the BER of the reset data according to the third reset write current Irst3 will further increase. Therefore, the BER of the reset data according to the lowest third reset write current Irst3 may be a reference for detecting the degradation of the memory cell MC according to the number of programming loops. Here, when the BER of the reset data is monitored by using the minimum reset current required for the phase change film 51 of the memory cell MC to phase change to the reset state, the BER may be an optimal reference for detecting the degree of degradation of the memory cell MC and / or the degradation level of the memory device 10.

[0087] Fig.10 , Fig.11 , Fig.12 and Fig.13 is a diagram illustrating a method of detecting degradation of a memory device 10 according to some example embodiments of the inventive concepts.

[0088] exist Figures 10 to 13 In the embodiment, the memory controller 20 ( Figure 1) A method for detecting degradation of a memory device 10 using reset data of a memory cell MC. Under the control of a memory controller 20, the memory device 10 may apply a first reset write current to a third reset write current Irst1, Irst2, and Irst3 to the memory cell MC to perform a write operation so that the memory cell MC is programmed to the reset data. Thereafter, in order to determine the programming state of the memory cell MC, under the control of the memory controller 20, the memory device 10 may perform a read operation using a first reset read voltage to a third reset read voltage VR1, VR2, and VR3. Among the first reset write current to the third reset write current Irst1, Irst2, and Irst3, the first reset write current Irst1 may be the highest, and the third reset write current Irst3 may be the lowest, and may be set to the minimum reset write current required for the phase change film 51 of the memory cell MC to phase change to the reset state. Therefore, the third reset write current Irst3 may be the minimum reset write current required for the memory cell MC to change to a high resistance state. The reading direction among the first to third reset read voltages VR1 , VR2 , and VR3 may be set to a direction in which a voltage level decreases from the first reset read voltage VR1 to the third reset read voltage VR3 .

[0089] Reference Fig.10 , shows the reset data threshold voltage distribution when performing a programming operation of applying each of the first to third reset write currents Irst1, Irst2, and Irst3 to the memory cell MC, and in the initial programming operation, after N programming loops and M (M>N) programming loops thereafter, the data of the memory cell MC is read. It can be seen that the threshold voltage distribution shape in the initial programming operation shifts to the left and widens as the number of programming loops increases.

[0090] The threshold voltage distribution of the reset data shown in some example embodiments may correspond to Fig. 7A The distribution of the high resistance state HRS, or Figure 8 Any one of the distributions of the second resistance state to the fourth resistance state RS2, RS3, RS4. Figure 8 In the MLC of FIG. 1 , the threshold voltage distribution of the reset data shown in some example embodiments may correspond to the threshold voltage distribution of the fourth resistance state RS4 which is the highest resistance state.

[0091] According to some example embodiments, the memory controller 20( Figure 1 ) After programming the memory cell MC to a specific write current, the memory cell MC can be read to detect the degree of degradation of the memory cell MC. For example, when reading the memory cell MC programmed to the third reset write current Irst3 (such as Fig.11), the BER may vary according to the voltage levels of the first to third reset read voltages VR1, VR2, and VR3. As the number of programming loops increases, the BER according to the first to third reset read voltages VR1, VR2, and VR3 may increase. In some example embodiments, the number of reset read voltages VR1, VR2, and VR3 is three, but the inventive concept is not limited thereto, and the number of reset read voltage levels may be variously changed.

[0092] The BER according to the first to third reset read voltages VR1, VR2, and VR3 may be provided to the memory controller 20 ( Figure 1 ). The memory controller 20 may determine the BER according to the voltage levels of the first reset read voltage to the third reset read voltage VR1, VR2, and VR3, and detect the degree of degradation of the memory cell MC. The memory controller 20 may refer to the lookup table LUT when determining the BER. The lookup table LUT may show the correlation between the number of programming loops and the BER according to the plurality of reset read voltage levels, and the lookup table LUT may be stored in the memory controller 20. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the voltage levels of the first reset read voltage to the third reset read voltage VR1, VR2, and VR3.

[0093] According to some example embodiments, the memory controller 20 may program the memory cell MC to a plurality of reset write currents and then read the memory cell MC to a specific reset read level to detect the degree of degradation of the memory cell MC. For example, when the memory cell MC programmed to the first reset write current to the third reset write current Irst1, Irst2, and Irst3 (such as Fig.12 When a memory cell MC is reset (as shown in FIG. 1 ), the BER may vary according to the current levels of the first reset write current to the third reset write current Irst1, Irst2, and Irst3. As the number of programming loops increases, the BER according to the first reset write current to the third reset write current Irst1, Irst2, and Irst3 may increase. In some example embodiments, the number of reset write currents Irst1, Irst2, and Irst3 is three, but the inventive concept is not limited thereto, and the number of reset write current levels may be changed variously.

[0094] The BER according to the first reset write current to the third reset write current Irst1, Irst2, and Irst3 may be provided to the memory controller 20. The memory controller 20 may determine the BER according to the current level of the first reset write current to the third reset write current Irst1, Irst2, and Irst3, and detect the degree of degradation of the memory cell MC. The memory controller 20 may refer to the lookup table LUT when determining the BER. The lookup table LUT may show the relationship between the number of programming loops and the BER according to multiple reset write current levels, and the lookup table LUT may be stored in the memory controller 20. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the first reset write current to the third reset write current Irst1, Irst2, and Irst3.

[0095] The lookup table LUT can be set to the ratio of the number of programming cycles to the bit errors, such as Fig.13 As shown. Fig.13 In the embodiment of the present invention, the horizontal axis of the lookup table LUT may represent the BER according to a plurality of reset read voltages VR, and the vertical axis of the lookup table LUT may represent the BER according to a plurality of reset write currents Irst. The intersection of the horizontal axis and the vertical axis may be the number of programming loops NPC. The lookup table LUT may be determined when the memory controller 20 is manufactured and may be updated in real time.

[0096] The memory controller 20 may refer to the lookup table LUT to determine the number of program loops corresponding to the BER provided from the memory device 10, the BER being the BER according to a specific reset read voltage level and / or the BER according to a specific reset write current level. The memory controller 20 may determine the number of program loops corresponding to the BER and detect the degree of degradation of the memory device 10.

[0097] Fig.14 is a flowchart illustrating a method performed by a memory controller to detect degradation of a memory device according to some example embodiments of the inventive concept.

[0098] Combination Figure 1 and Figure 2 For reference Fig.14, in operation S1410, the memory controller 20 may control the memory cells MC of the memory device 10 to be programmed to the reset data. According to the write operation control of the memory controller 20, the memory device 10 may perform a reset data write operation. The control circuit 13 of the memory device 10 may program the reset data to the memory cells MC in all or some of the memory blocks in the memory cell array 11. At this time, the control circuit 13 may store the number of programmed reset data bits in the memory block area. The control at S1410 may include controlling the memory device 10 to program the memory cells MC in all or some of the memory blocks in the memory cell array 11 to a resistance state. The resistance state may be one of a plurality of resistance states. In some example embodiments, the resistance state may be a first resistance state RS1. In some example embodiments, the resistance state may be a fourth resistance state RS4. In some example embodiments, the resistance state is a high resistance state among a plurality of resistance states (e.g., resistance states RS1 to RS4). Programming may include repeatedly programming the memory cell MC to a resistance state.

[0099] In operation S1420, the memory controller 20 may determine the number (“quantity”) of program loops of the memory device 10 based on the BER according to the plurality of reset read voltages provided in the memory device 10. Fig.11 As described, the memory device 10 can program the memory cell MC to the reset data (e.g., program the memory cell MC to the first resistance state RS1) by applying a specific write current (e.g., Irst3) to the memory cell MC, and then control the memory device 10 to read the programmed memory cell MC according to the voltage levels of multiple reset read voltages (e.g., VR1, VR2, and VR3). The control circuit 13 of the memory device 10 can compare the number of programmed reset data bits with the number of read reset data bits, and provide the difference as BER to the memory controller 20. The control circuit 13 can output the BER to the outside of the memory device 10 so that the number of programming loops of the memory cell MC can be determined based on the BER. Therefore, the BER of the memory cell MC generated during the read operation can be received from the memory device 10. The BER can be received according to multiple reset read voltages. The memory controller 20 can refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the multiple reset read voltages, wherein the lookup table LUT can indicate the correlation between the BER and the number of programming loops.

[0100] In operation S1422, the memory controller 20 may determine the number of program loops of the memory device 10 based on the BER according to a plurality of reset write currents provided in the memory device 10. Fig.12As described, the memory device 10 can program the memory cell MC to reset data (e.g., program the memory cell to a high resistance state) by applying a plurality of current levels of reset write currents Irst1, Irst2, and Irst3 to the memory cell MC (wherein the plurality of reset write currents include a minimum reset write current required for the memory cell MC to become a high resistance state (e.g., Irst3)), and then read the memory cell MC according to a voltage level of a specific reset read voltage (e.g., VR1). The control circuit 13 of the memory device 10 can compare the number of programmed reset data bits with the number of read reset data bits, and provide the difference as a BER to the memory controller 20. The memory controller 20 can refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the plurality of reset write currents.

[0101] In operation S1424, the memory controller 20 may determine the number of programming loops of the memory device 10 based on the BER according to the multiple reset read voltages and the BER according to the multiple reset write currents provided in the memory device 10. After applying the multiple reset write current levels to the memory cells MC and programming the memory cells MC to the reset data, the memory device 10 may read the memory cells MC according to the multiple reset read voltage levels. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops, the number of programming loops corresponding to the BER according to the specific reset write current level among the multiple reset write current levels and the BER according to the specific reset read voltage level among the multiple reset read voltage levels.

[0102] In operation S1430, the memory controller 20 may detect the degree of degradation of the memory cell MC based on the number of programming loops determined in operation S1420, S1422, or S1424. When it is determined that the number of programming loops corresponding to the BER is high, the memory controller 20 may replace the memory block of the memory cell array 11 with another memory block (wherein the high degree of degradation of the memory cell MC may be determined based on the determination that the number of programming loops corresponding to the BER is high), thereby preventing errors caused by degradation of the memory device 10 in advance. Therefore, as described herein, operating the memory controller to determine the number of programming loops of the memory cell MC of the memory device 10 based on the BET may enable the improvement of the functions of a computing device, an electronic device, etc., including the memory controller 20 and the memory device 10, based on avoiding performance degradation of the memory device 10, wherein the avoiding may include: determining that degradation of at least a memory block of the memory cell array 11 increases and quickly replacing a memory block of the memory cell array 11 with another memory block of the memory cell array 11. Therefore, the performance of computing devices, electronic devices, etc. can be improved based on switching to a storage block with a low degree of degradation, and thus have a retention time and an endurance level, during which data can be retained and at which normal operations can be performed without being exhausted when writing data, thereby, the sensing of reset data can become more certain or faster, and the possibility of multiple bit errors in device operation can be reduced.

[0103] Fig.15 It is used to indicate the state of the set data. Fig. 7A A graph showing the threshold voltage distribution of memory cells MC.

[0104] Reference Fig.15 , which shows: the threshold voltage distribution of the set data according to the programming operation after applying multiple set write currents Iset1, Iset2 and Iset3 to the memory cell MC to perform the programming operation. In the initial programming operation, the threshold voltage distribution of the set data of the programmed memory cell MC according to the multiple set write currents Iset1, Iset2 and Iset3 can have almost the same shape. Thereafter, when the number of programming loops increases to M times, it can be seen that the shape of the threshold voltage distribution of the set data is changed and widened (B).

[0105] For example, assuming that the highest current among the plurality of set write currents Iset1, Iset2, and Iset3 is the first set write current Iset1, and the lowest current is the third set write current Iset3. It can be seen that the threshold voltage distribution of the set data of the memory cell MC programmed to the lowest third reset write current Irst3 is shifted to the right (i.e., toward the high resistance state of the reset data), and the threshold voltage distribution is greatly widened due to the stress according to the M programming cycles.

[0106] When the memory cell MC is read using the read voltage Vread to read the memory cell MC programmed to the third reset write current Irst3, the memory cell MC belonging to the shaded portion may be programmed to the set data but may be determined as reset data due to the reduction in the threshold voltage. That is, it can be expected that the BER of the memory cell MC belonging to the shaded portion may be large, and the BER of the set data according to the third reset write current Irst3 will further increase as the number of programming loops increases. Therefore, the BER of the set data according to the lowest third reset write current Irst3 may be a reference for detecting the degradation of the memory cell MC according to the number of programming loops. Here, when the BER of the set data is monitored by using the minimum set write current required for the phase change film 51 of the memory cell MC to phase change to the set state, the BER may be an optimal reference for detecting the degree of degradation of the memory cell MC and / or the degradation level of the memory device 10.

[0107] Fig.16 , Fig.17 , Fig.18 and Fig.19 is a diagram illustrating a method of detecting degradation of a memory device 10 according to some example embodiments of the inventive concept. Figures 16 to 19, a method for detecting degradation of a memory device 10 using set data of a memory cell MC is described. Under the control of a memory controller 20, the memory device 10 may apply a first set write current to a third set write current Iset1, Iset2, and Iset3 to the memory cell MC to perform a write operation, so that the memory cell MC is programmed to the set data. Thereafter, in order to determine the programming state of the memory cell MC, the memory device 10 may perform a read operation using a first set read voltage to a third set read voltage VS1, VS2, and VS3. Among the first set write current to the third set write current Iset1, Iset2, and Iset3, the first set write current Iset1 may be the highest, and the third set write current Iset3 may be the lowest, and the third set write current Iset3 may be set to the minimum current required for the phase change film 51 of the memory cell MC to phase change to the set state. Therefore, the third set write current Iset3 may be the minimum set write current required for the memory cell MC to change to a low resistance state. The reading direction among the first to third set read voltages VS1 , VS2 , and VS3 may be set to a direction in which a voltage level increases from the first set read voltage VS1 to the third set read voltage VS3 .

[0108] Reference Fig.16 , which shows the set data threshold voltage distribution when a programming operation of applying each of the first to third set write currents Iset1, Iset2, and Iset3 to the memory cell MC is performed, and in the initial programming operation, after N programming loops and M (M>N) programming loops thereafter, the data of the memory cell MC is read. It can be seen that the threshold voltage distribution shape in the initial programming operation is shifted to the right and widens as the number of programming loops increases.

[0109] The threshold voltage distribution of the set data shown in some example embodiments may correspond to Fig. 7A The distribution of the low resistance state LRS or Figure 8 Any one of the distributions of the first resistance state to the third resistance state RS1, RS2 and RS3. Figure 8 In the MLC of FIG. 1 , the threshold voltage distribution of the set data shown in some example embodiments may correspond to the threshold voltage distribution of the first resistance state RS1 which is the lowest resistance state.

[0110] According to some example embodiments, the memory controller 20 may read the memory cell MC after programming the memory cell MC to a specific set write current to detect the degree of degradation of the memory cell MC. For example, when reading the memory cell MC programmed to the third set write current Iset3 (e.g. Fig.17), the BER may vary according to the voltage levels of the first to third set read voltages VS1, VS2, and VS3. As the number of program loops increases, the BER according to the first to third set read voltages VS1, VS2, and VS3 may increase. In some example embodiments, the number of the set read voltages VR1, VR2, and VR3 is three, but the inventive concept is not limited thereto, and the number of the set read voltage levels may be variously changed.

[0111] The BER according to the first to third set read voltages VS1, VS2, and VS3 may be provided to the memory controller 20. The memory controller 20 may determine the BER according to the voltage levels of the first to third set read voltages VS1, VS2, and VS3, and detect the degree of degradation of the memory cell MC. The memory controller 20 may refer to the lookup table LUT when determining the BER. The lookup table LUT may show the correlation between the number of programming loops and the BER according to a plurality of set read voltage levels, and the lookup table LUT may be stored in the memory controller 20. The memory controller 20 may determine the number of programming loops corresponding to the BER according to the voltage levels of the first to third set read voltages VS1, VS2, and VS3.

[0112] According to some example embodiments, the memory controller 20 may program the memory cell MC to a plurality of set write currents and then read the memory cell MC to a specific set read level to detect the degree of degradation of the memory cell MC. For example, when the memory cell MC programmed to the first set write current to the third set write current Iset1, Iset2, and Iset3 is read with the first set read voltage VR1 (e.g., Fig.18 ), the BER may vary according to the current levels of the first to third set write currents Irst1, Irst2, and Irst3. As the number of programming loops increases, the BER according to the first to third set write currents Iset1, Iset2, and Iset3 may increase. In some example embodiments, the number of the set write currents Iset1, Iset2, and Iset3 is three, but the inventive concept is not limited thereto, and the number of the set write current levels may be variously changed.

[0113] The BER according to the first set write current to the third set write current Iset1, Iset2, and Iset3 may be provided to the memory controller 20. The memory controller 20 may determine the BER according to the current level of the first set write current to the third set write current Iset1, Iset2, and Iset3, and detect the degree of degradation of the memory cell MC. The memory controller 20 may refer to the lookup table LUT when determining the BER. The lookup table LUT may show the relationship between the number of programming loops and the BER according to a plurality of set write current levels, and the lookup table LUT may be stored in the memory controller 20. The memory controller 20 may determine the number of programming loops corresponding to the BER according to the first set write current to the third set write current Iset1, Iset2, and Iset3.

[0114] In such Fig.19 In the lookup table LUT shown, the horizontal axis may represent the BER according to a plurality of set read voltages VS, and the vertical axis may represent the BER according to a plurality of set write currents Iset. The intersection of the horizontal axis and the vertical axis may be the number of programming loops NPC. The lookup table LUT may be determined when the memory controller 20 is manufactured, and may be updated in real time.

[0115] The memory controller 20 may refer to the lookup table LUT to determine the number of program loops corresponding to the BER provided from the memory device 10, the BER being the BER according to a specific set read voltage level and / or the BER according to a specific set write current level. The memory controller 20 may determine the number of program loops corresponding to the BER and detect the degree of degradation of the memory device 10.

[0116] Fig. 20 is a flowchart illustrating a method of detecting degradation of the memory device 10 according to some example embodiments of the inventive concepts.

[0117] Combination Figure 1 and Figure 2 refer to Fig. 20, in operation S2010, a write operation may be performed to program the memory cell MC to the set data. Under the control of the memory controller 20, the memory device 10 may perform a set data write operation. The control circuit 13 of the memory device 10 may program the set data to the memory cells MC in all or some of the memory blocks in the memory cell array 11. At this time, the control circuit 13 may store the number of programmed set data bits in the memory block. The control at S2010 may include controlling the memory device 10 to program the memory cells MC in all or some of the memory blocks in the memory cell array 11 to a resistance state. The resistance state may be one of a plurality of resistance states. In some example embodiments, the resistance state may be a first resistance state RS1. In some example embodiments, the resistance state may be a fourth resistance state RS4. In some example embodiments, the resistance state is a low resistance state among a plurality of resistance states (e.g., resistance states RS1 to RS4). Programming may include repeatedly programming the memory cell MC to a resistance state.

[0118] In operation S2020, the memory controller 20 may determine the number of programming loops of the memory device 10 based on the BER according to the plurality of set read voltages provided in the memory device 10. The memory device 10 may program the memory cell Mc to the set data by applying a specific set write current (e.g., Iset3) to the memory cell MC, and then control the memory device 10 to read the programmed memory cell MC according to the levels of the plurality of set read voltages (e.g., VS1, VS2, and VS3). The control circuit 13 of the memory device 10 may compare the number of programmed set data bits with the number of read set data bits, and provide the difference as the BER to the memory controller 20. Therefore, the BER of the memory cell MC generated during the read operation may be received from the memory device 10. The BER may be received according to the plurality of set read voltages. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the plurality of set read voltages, wherein the lookup table LUT may indicate the correlation between the BER and the number of programming loops.

[0119] In operation S2022, the memory controller 20 may determine the number of programming loops of the memory device 10 based on the BER according to the multiple set write currents provided in the memory device 10. The memory device 10 may program the memory cell MC to the set data (e.g., program the memory cell to a low resistance state) by applying the levels of the multiple set write currents (e.g., Iset1, Iset2, and Iset3) to the memory cell MC, wherein the multiple set write currents include the minimum set write current required for the memory cell MC to become a low resistance state (e.g., Iset3), and then read the memory cell MC according to the level of a specific set read voltage (e.g., VS1). The control circuit 13 of the memory device 10 may compare the number of programmed set data bits with the number of read set data bits, and provide the difference as the BER to the memory controller 20. The memory controller 20 may refer to the lookup table LUT to determine the number of programming loops corresponding to the BER according to the multiple set write currents.

[0120] In operation S2024, the memory controller 20 may determine the number of programming loops of the memory device 10 based on the BER according to the plurality of set read voltages and the BER according to the plurality of set write currents provided in the memory device 10. After applying the plurality of levels of the set write currents to the memory cells MC and programming the memory cells MC to the set data, the memory device 10 may read the memory cells MC according to the plurality of levels of the set read voltages. The memory controller 20 may determine the number of programming loops with reference to the lookup table LUT, the number of programming loops corresponding to the BER according to a specific set write current level among the plurality of set write current levels and the BER according to a specific set read voltage level among the plurality of set read voltage levels.

[0121] In operation S2030, the memory controller 20 may detect the degree of degradation of the memory cell MC based on the number of programming loops determined in operation S2020, S2022, or S2024. When it is determined that the number of programming loops corresponding to the BER is high, the memory controller 20 may replace the memory block of the memory cell array 11 with another memory block of the memory cell array 11, thereby preventing errors caused by degradation of the memory device 10 in advance. Therefore, as described herein, operating the memory controller to determine the number of programming loops of the memory cell MC of the memory device 10 based on the BET may enable the improvement of the functions of a computing device, an electronic device, etc., which includes the memory controller 20 and the memory device 10, based on avoiding performance degradation of the memory device 10, wherein the avoiding may include: determining that degradation of at least a memory block of the memory cell array 11 increases and quickly replacing the memory block of the memory cell array 11 with another memory block of the memory cell array 11. Therefore, the performance of computing devices, electronic devices, etc. can be improved based on switching to a storage block with a low degree of degradation, and thus have a retention time and an endurance level, during which data can be retained and at which normal operations can be performed without being exhausted when writing data, thereby, the sensing of set data can become more certain or faster, and the possibility of multiple bit errors in device operation can be reduced.

[0122] Fig.21 2 is a block diagram showing a schematic configuration of a memory system 2100 according to some example embodiments of the inventive concept, the memory system employing a method performed by a memory controller 2110 for detecting degradation of a memory device. Such a memory system 2100 may be referred to herein as a computing device, an electronic device, or the like.

[0123] refer to Fig.21 , the memory system 2100 may include a memory controller 2110, a plurality of nonvolatile memory devices 2120 to 212n, and a volatile memory device 2130. The memory controller 2110 may control write operations and / or read operations of the plurality of nonvolatile memory devices 2120 to 212n in response to a request from a host HOST connected to the memory system 2100.

[0124] According to some example embodiments, the host HOST may be any computing system, such as a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, etc.

[0125] A plurality of nonvolatile memory devices 2120 to 212n (n is an integer greater than or equal to 0) may be used as storage media of the memory system 2100. Each of the nonvolatile memory devices 2120 to 212n may be, for example, a resistive memory device. A plurality of nonvolatile memory devices 2120 to 212n (including a nonvolatile memory device 2121, where n is greater than zero) may be connected to a memory controller 2110 via a channel. Each of the nonvolatile memory devices 2120 to 212n may perform a write operation and / or a read operation in response to a request from a host HOST provided via a channel.

[0126] The volatile memory device 2130 may temporarily store write data provided from the host HOST, or read data from the nonvolatile memory devices 2120 to 212n. The volatile memory device 2130 may store metadata or cache data to be stored in the nonvolatile memory devices 2120 to 212n. The volatile memory device 2130 may include DRAM, SRAM, etc.

[0127] Each of the nonvolatile memory devices 2120 to 212n may be a Figures 1 to 20 Each of the nonvolatile memory devices 2120 to 212n may include: a memory cell array 310 including memory cells; a write / read circuit 320 that programs the memory cells to a first resistance state and reads the programmed memory cells; and a control circuit 330 that outputs the BER of the memory cells generated during the read operation to the memory controller 2110. The BER may be referenced to determine the number of programming cycles of the memory cells.

[0128] The memory controller 2110 may detect degradation of each of the nonvolatile memory devices 2120 to 212n. The memory controller 2110 may perform: an operation of controlling a memory cell of each of the nonvolatile memory devices 2120 to 212n to be in a first resistance state; an operation of controlling reading of a programmed memory cell; an operation of receiving a BER of a memory cell generated during a read operation from a resistance memory device; and an operation of determining the number of programming loops of a memory cell corresponding to the BER by referring to a lookup table LUT.

[0129] Fig. 22 2 is a block diagram illustrating a system 2200 according to some example embodiments of the inventive concept, to which a method performed by a memory controller for detecting degradation of a memory device is applied. Such a system 2200 may be referred to herein as a computing device, an electronic device, etc.

[0130] refer to Fig. 22, the system 2200 may include a processing unit 2210 (also referred to herein as a processor, an instance of a processing circuit, etc.), a volatile memory unit 2220 (also referred to herein as a memory, a memory device, a memory device, etc.), a resistive memory unit 2230 (also referred to herein as a resistive memory device, a resistive memory device, a memory device, etc.), and a mass storage unit 2240 (also referred to herein as a mass storage device). The system 2200 may be a general-purpose or special-purpose computer system, such as a mobile device, a personal computer, a server computer, a programmable consumer electronic device, a mainframe computer, etc.

[0131] The functional units described in some example embodiments may be categorized as modules for implementing independent functions. For example, a module may be implemented as a hardware circuit including a custom VLSI circuit or an off-the-shelf semiconductor (e.g., a gate array, a logic chip, a transistor, or other discrete components). The module may be implemented as a programmable hardware device, such as a programmable gate array, a programmable gate logic, a programmable gate device, etc. The module may also be implemented as software configured as an executable code, an object, a process, or a function.

[0132] The processing unit 2210 may execute an operating system and a plurality of software systems and perform specific calculations or tasks. The processing unit 2210 may be a microprocessor or a central processing unit (CPU).

[0133] The volatile memory unit 2220 may refer to a medium that stores data for a short time or temporarily, as an operation memory of the system 2200 or as a cache memory. The volatile memory unit 2220 may include one or more memory devices, for example, DRAM.

[0134] The resistive memory cell 2230 may be used as a cache for the large-capacity memory cell 2240. The resistive memory cell 2230 may be frequently accessed, or the resistive memory cell 2230 may store some data of an application or an operating system. The resistive memory cell 2230 may include at least one memory device, such as a PRAM. The resistive memory cell 2230 may be beneficial as a cache because access to the resistive memory cell 2230 is much faster than accessing data through the large-capacity storage unit 2240, such as a hard disk drive (HDD). Figures 1 to 20 The resistive memory cell 2230 is implemented in the example embodiment shown in FIG.

[0135] The resistance memory cell 2230 may include: a memory cell array including memory cells; a write / read circuit 320 that programs the memory cells to a first resistance state and reads the programmed memory cells; and a control circuit that outputs the BER of the memory cells generated during the read operation to a memory controller. The memory controller may refer to a lookup table to determine the number of programming loops for the memory cells corresponding to the BER.

[0136] The mass storage unit 2240 may be implemented as a HDD, a solid state drive (SDD), a peripheral component interconnect (PCIe) memory module, a non-volatile memory express (NVMe), etc. Optionally, one or more layers of the mass storage unit 2240 may be implemented as one or more network accessible devices and / or services, such as NVMe (NVMe-oF) and / or remote direct memory access (RDMA) via Fabric, a server cluster, an application server, or a message server. The mass storage unit 2240 may refer to a storage medium on which the system 2200 will store user data for a long period of time. The mass storage unit 2240 may store applications, program data, etc.

[0137] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a memory controller, the memory controller being configured to control a resistive memory device, the resistive memory device comprising a plurality of memory cells, the method comprising: controlling the resistive memory device to program the plurality of memory cells to a first resistance state to establish the plurality of memory cells programmed; controlling the resistive memory device to read the programmed plurality of memory cells; receiving a bit error rate "BER" of the memory cell generated during a read operation from the resistive memory device; as well as determining a number of programming cycles for the memory cell based on the BER, The BER is generated based on controlling the resistive memory device to perform the following operations: applying a plurality of write currents to the plurality of memory cells to program the plurality of memory cells to the first resistance state, and reading the programmed plurality of memory cells by using a read voltage, the plurality of write currents including a minimum write current required for the plurality of memory cells to become the first resistance state, wherein the BER includes a BER according to the plurality of write currents, or A write current is applied to the plurality of memory cells to program the plurality of memory cells to the first resistance state, and the programmed plurality of memory cells are read by using a plurality of read voltages, the write current comprising a minimum write current required for the plurality of memory cells to become the first resistance state, wherein the BER comprises a BER according to the plurality of read voltages.

2. The method according to claim 1, wherein: Determining a number of programming loops for the memory cell based on the BER includes referencing a lookup table indicating a correlation between the BER and the number of programming loops.

3. The method according to claim 2, wherein: The lookup table is stored in a read only memory "ROM" or a non-volatile memory.

4. The method according to claim 1, wherein: Controlling the resistance memory device to program the plurality of memory cells to a first resistance state includes repeatedly programming the memory cells to the first resistance state.

5. The method according to claim 1, wherein: The first resistance state is a high resistance state among a plurality of resistance states.

6. The method according to claim 5, wherein: A reset write current is applied to the memory cell to program the memory cell to reset data in the high resistance state, and The reset write current is a minimum reset write current required for the memory cell to change to the high resistance state.

7. The method according to claim 6, wherein: Controlling the resistance memory device to read the programmed plurality of memory cells includes reading the programmed plurality of memory cells according to a plurality of reset read voltages.

8. The method according to claim 5, wherein: A plurality of reset write currents are applied to the memory cells to program the memory cells to reset data in the high resistance state, and The plurality of reset write currents include a minimum reset write current required for the memory cell to change to the high resistance state.

9. The method according to claim 8, wherein: Controlling the resistance memory device to read the programmed plurality of memory cells includes reading the programmed plurality of memory cells by using a reset read voltage.

10. The method according to claim 1, wherein: The first resistance state is a low resistance state among a plurality of resistance states.

11. The method according to claim 10, wherein: A set write current is applied to the memory cell to program the memory cell to the set data in the low resistance state, and The set write current is a minimum set write current required for the memory cell to change to the low resistance state.

12. The method according to claim 11, wherein: Controlling the resistance memory device to read the programmed plurality of memory cells includes reading the programmed plurality of memory cells according to a plurality of set read voltages.

13. The method according to claim 10, wherein: A plurality of set write currents are applied to the memory cells to program the memory cells to set data in the low resistance state, and The plurality of set write currents include a minimum set write current required for the memory cell to change to the low resistance state.

14. The method according to claim 13, wherein: Controlling the resistance memory device to read the programmed plurality of memory cells includes reading the programmed plurality of memory cells by using a set read voltage.

15. A resistive memory device, comprising: a memory cell array comprising a plurality of memory cells; a write circuit configured to program the plurality of memory cells to a first resistance state to establish the plurality of memory cells as programmed; a read circuit configured to read the programmed plurality of memory cells; as well as a control circuit configured to output a bit error rate (BER) of the memory cell generated during a read operation to the outside of the resistive memory device so that the number of programming loops of the plurality of memory cells can be determined based on the BER, Wherein, the control circuit is configured to generate the BER based on the following operations: controlling the write circuit to apply a plurality of write currents to the plurality of memory cells to program the plurality of memory cells to the first resistance state, and controlling the read circuit to read the programmed plurality of memory cells by using a read voltage, the plurality of write currents including a minimum write current required for the plurality of memory cells to become the first resistance state, wherein the BER includes a BER according to the plurality of write currents, or The write circuit is controlled to apply a write current to the plurality of memory cells to program the plurality of memory cells to the first resistance state, and the read circuit is controlled to read the programmed plurality of memory cells by using a plurality of read voltages, the write current including a minimum write current required for the plurality of memory cells to become the first resistance state, wherein the BER includes a BER according to the plurality of read voltages.

16. The resistive memory device according to claim 15, wherein: The correlation between the BER and the number of programming loops is stored in a lookup table, and The lookup table is stored in a memory controller configured to control the resistive memory device.

17. The resistive memory device according to claim 15, wherein: The first resistance state is: as a low resistance state for set data, or High resistance state as reset data.

18. The resistive memory device according to claim 15, wherein: The first resistance state is one resistance state among a plurality of resistance states.

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