Semiconductor device and semiconductor package including the same

Abstract

This application provides a semiconductor device and a semiconductor package. The semiconductor device has a semiconductor chip region and a dicing region. The semiconductor chip region includes a semiconductor chip and a first portion of a passivation film covering the semiconductor chip. The dicing region includes a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a portion of a first wiring. The first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, the second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0091643, filed on August 7, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices and semiconductor packages including the semiconductor devices. Background Art

[0004] Semiconductor devices are constantly being improved to reduce their size and increase their performance levels. In this regard, the use of low-dielectric-constant insulating films has been used as one improvement for semiconductor devices.

[0005] Semiconductor devices can be manufactured at the wafer level, where multiple devices are formed on a substrate at once, and the substrate can then be diced to separate the devices from each other. The individual semiconductor devices can then be packaged as chips. However, physical stress can be applied to the semiconductor devices when the substrate is diced. When a low-dielectric-constant insulating film is used in the semiconductor device, this stress can cause delamination, potentially resulting in the stripping of wiring disposed beneath the low-dielectric-constant insulating film. Summary of the Invention

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor chip region including a first portion of the semiconductor chip and a passivation film covering the semiconductor chip; a dicing region including a second portion of the passivation film adjacent to the first portion of the passivation film, a portion of a first insulating film that, when viewed in a plan view of the semiconductor device, laterally protrudes beyond the distal end of the second portion of the passivation film, and a first wiring. The portion of the first insulating film includes: a first portion disposed alongside the distal end of the second portion of the passivation film when viewed in a plan view of the semiconductor device, and a second portion protruding laterally outward from the first portion of the first insulating film. Furthermore, when viewed in a plan view of the semiconductor device, the first wiring protrudes laterally outward from the second portion of the first insulating film.

[0007] According to another aspect of the present invention, a semiconductor device is provided having a semiconductor chip region and a dicing line region, and the semiconductor device includes: a substrate constituting a semiconductor chip disposed in the semiconductor chip region and having semiconductor chip wiring, and the substrate extending into the dicing line region; a first insulating film disposed in the semiconductor chip region and the dicing line region; a first wiring in the dicing line region at an upper portion of the first insulating film; a second insulating film disposed on the first insulating film, the second insulating film having a first region defining a first opening exposing a substrate and a second region defining a second opening exposing the first wiring; and a passivation film disposed on the second insulating film. The passivation film exposes both the first region and the second region of the second insulating film, and the width of the first region of the second insulating film is smaller than the width of the second region of the second insulating film.

[0008] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; an integrated circuit assembly in the substrate; a lower wiring structure disposed on the substrate; an upper wiring structure disposed on the lower wiring structure; a passivation layer disposed on the upper wiring structure; and a connection terminal disposed on the upper surface of the passivation layer and electrically connected to redistribution wiring of the upper wiring structure. The lower wiring structure includes a lower insulating layer and wiring extending through the lower insulating layer and electrically connected to the integrated circuit assembly, the wiring including conductive wiring elements disposed at an outer peripheral portion of the upper surface of the lower insulating layer. The upper wiring structure includes: an upper insulating layer having a first region on one side and having a protrusion extending from the first region only on a portion of the conductive wiring element; and redistribution wiring extending through the upper insulating layer and electrically connected to the lower wiring structure.

[0009] In other aspects of the invention, a semiconductor package is provided having a semiconductor device according to any of the foregoing aspects, the semiconductor device being mounted on and electrically connected to the semiconductor package substrate. Attached Figure Description

[0010] The above and other aspects and features of the inventive concept will become more apparent from the following detailed description of examples of the inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1A It is a plan view of a substrate on which a semiconductor device according to the present invention is integrated;

[0012] Figure 1B This is a cross-sectional view of a portion of an example of a semiconductor package according to the present invention;

[0013] Figure 2 yes Figure 1BA bottom view of a portion of a semiconductor device in a semiconductor package, as shown;

[0014] Figure 3 yes Figure 2 A magnified view of region K;

[0015] Figure 4 It is along Figure 2 A cross-sectional view taken by line A-A';

[0016] Figure 5 It is along Figure 2 A cross-sectional view taken by line B-B';

[0017] Figure 6 It is a plan view of another substrate on which a semiconductor device according to the present invention is integrated;

[0018] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 These are multiple cross-sectional views of a semiconductor device during its manufacturing process, and together they illustrate an example of a method for manufacturing a semiconductor device according to the concept of the present invention;

[0019] Figure 12 It is being executed Figures 7 to 11 Following the method of manufacturing semiconductor devices Figure 6 A magnified view of region J in the image; and

[0020] Figure 13 yes Figure 12 A magnified view of region M. Detailed Implementation

[0021] In the following text, reference will be made to Figure 1A , Figure 1B as well as Figures 2 to 5 Examples of semiconductor devices conceived according to the present invention and semiconductor packages including the thereof are described.

[0022] Figure 1A A substrate 100 is shown, on which semiconductor devices 1100 are integrated, i.e., before the substrate 100 is cut to separate the semiconductor devices 1100 from each other. Figure 1B A semiconductor package 1000 comprising one of semiconductor devices 1100, according to the present invention, is shown. Specifically, Figure 1B It is cut along the cutting line SL Figure 1A The substrate 100 is used to separate the semiconductor devices from each other, and one of the semiconductor devices is mounted on the semiconductor packaging substrate 1200. Figure 1A A magnified view of region N. Figure 1BFor clarity, molding materials are not shown in the text. Figure 2 yes Figure 1B The image shows a bottom view of the semiconductor device 1100, but for descriptive purposes, it is shown when the semiconductor package 1000 is relative to... Figure 1B The orientation reversal shown (e.g.) Figure 4 Features in the planar diagram (as shown). In Figure 2 For clarity, only the passivation film 117, the third insulating film 115, and the first wiring element 124 are shown. Figure 3 yes Figure 2 A magnified view of region K. Figure 4 It is along Figure 2 A cross-sectional view taken by line A-A'. Figure 5 It is along Figure 2 A cross-sectional view taken from line B-B'.

[0023] Additionally, note that the ordinal numbers “first,” “second,” etc., are used simply to distinguish similar elements or features (e.g., insulating films) from one another in the order of mention and are not restrictive. Therefore, an insulating film referred to as a “third” insulating film in one place in this disclosure may otherwise be referred to as a “first” or “second” insulating film in another place in this disclosure (e.g., in the claims).

[0024] refer to Figure 1A The substrate 100 may include a semiconductor chip region I and a dicing line region II. Multiple semiconductor chip regions I may be disposed on the substrate 100. Each of the multiple semiconductor chip regions I may be spaced apart from each other by the dicing line region II.

[0025] Semiconductor chip region I may include semiconductor chip wiring ( Figure 4 105), bottom wiring structure ( Figure 4 121), upper wiring structure ( Figure 4 122) and redistribution layer ( Figure 4 (123).

[0026] The dicing region II may include a dicing line SL. The dicing line SL may be a virtual line along which the substrate 100 is diced to individual devices, one of which is a reference device. Figure 1B and Figure 2 The semiconductor device 1100 is described.

[0027] The semiconductor device 1100 formed by cutting the substrate 100 along the cutting line SL may include a portion of the semiconductor chip region I and a portion of the cutting line region II.

[0028] refer to Figure 1BThe semiconductor package 1000 according to the present invention may include a semiconductor package substrate 1200 and a semiconductor device 1100.

[0029] The semiconductor packaging substrate 1200 can be, for example, a printed circuit board (PCB) or a ceramic substrate. The semiconductor packaging substrate 1200 may include a first surface 1200a and a second surface 1200b. The first surface 1200a and the second surface 1200b of the semiconductor packaging substrate 1200 may face each other. A semiconductor device 1100 may be mounted on the first surface 1200a of the semiconductor packaging substrate 1200. A plurality of external connection terminals 1210 may be attached to the second surface 1200b of the semiconductor packaging substrate 1200.

[0030] The semiconductor packaging substrate 1200 and the semiconductor device 1100 can be electrically connected to each other via a connection terminal 101. The connection terminal 101 can be inserted between the first surface 1200a of the semiconductor packaging substrate 1200 and the semiconductor device 1100. A plurality of connection terminals 101 can electrically connect the semiconductor packaging substrate 1200 and the semiconductor device 1100.

[0031] External connection terminal 1210 can electrically connect semiconductor package 1000 to external devices.

[0032] The connection terminal 101 and the external connection terminal 1210 can be conductive balls or solder balls, but the inventive concept is not limited thereto. The connection terminal 101 and the external connection terminal 1210 can be, for example, conductive bumps, conductive pads, or pins. Therefore, the plurality of connection terminals 101 or the plurality of external connection terminals 1210 can be ball grid arrays (BGAs) or pin grid arrays (PGAs).

[0033] Each external connection terminal 1210 and its corresponding connection terminal 101 can be electrically connected to each other via a first pad 1213, a connection wiring 1215, and a second pad 1217.

[0034] A first pad 1213 may be disposed on a second surface 1200b of the semiconductor package substrate 1200. A second pad 1217 may be disposed on a first surface 1200a of the semiconductor package substrate 1200. Although the lower surface of the first pad 1213 is shown as being in the same plane as the second surface 1200b of the semiconductor package substrate 1200, the inventive concept is not limited thereto. Similarly, although the upper surface of the second pad 1217 is shown as being in the same plane as the first surface 1200a of the semiconductor package substrate 1200, the inventive concept is not limited thereto. For example, at least a portion of the first pad 1213 may protrude from the bottom surface of the body (insulator) of the semiconductor package substrate 1200 and / or at least a portion of the second pad 1217 may protrude from the upper surface of the body (insulator) of the semiconductor package substrate 1200.

[0035] The first pad 1213 and the second pad 1217 can be electrically connected to each other via the connecting wire 1215.

[0036] The first pad 1213, the second pad 1217, and the connection wiring 1215 may include conductive material.

[0037] refer to Figures 2 to 5 The semiconductor device 1100 according to the present invention may have a semiconductor chip region I and a dicing line region II. The semiconductor chip region I and the dicing line region II may be related to the above-mentioned reference. Figure 1A and Figure 1B The corresponding portions of semiconductor chip region I and dicing line region II are described.

[0038] Semiconductor chip region I may include a semiconductor chip. Furthermore, semiconductor chip region I may include a first portion 117a of a passivation film 117. The first portion 117a of the passivation film 117 may cover the semiconductor chip. In addition to the integrated circuit of the semiconductor chip formed on the substrate 100, the semiconductor chip may also include semiconductor chip wiring 105, lower wiring 121, upper wiring 122, and redistribution wiring 123.

[0039] Semiconductor chips can be memory chips, logic chips, etc. When the semiconductor chip is a logic chip, various types of logic circuits can be used, considering packaging applications, etc. When the semiconductor chip is a memory chip, the memory chip can be a non-volatile memory chip. For example, the memory chip can be a flash memory chip, such as a NAND flash memory chip or a NOR flash memory chip. However, the inventive concept is not limited to this. The memory chip can be a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), or a resistive random access memory (RRAM).

[0040] The dicing region II may be a region disposed along the outer periphery of the semiconductor chip region I. The dicing region II may include a second portion 117b of the passivation film 117, a first portion 115a of the third insulating film 115, a second portion 115b of the third insulating film 115, and a first wiring element 124.

[0041] Substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but the present invention is not limited thereto. Substrate 100 may include a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate, etc., and may be an SOI (silicon-on-insulator or semiconductor) substrate. In the following, a silicon substrate will be used as an example.

[0042] As described above, substrate 100 may include semiconductor chip wiring 105 in semiconductor chip region I. Here, semiconductor chip wiring 105 is shown and described as metal wiring, such as conductive traces, but the inventive concept is not limited thereto. Semiconductor chip wiring 105 may be a portion of an integrated circuit, such as a transistor or diode, formed in substrate 100, or simply a part of such an integrated circuit. For example, semiconductor chip wiring 105 may be the gate electrode of a transistor or the source / drain electrode of a transistor.

[0043] A first insulating film 111 can be disposed on the substrate 100. The first insulating film 111 can be disposed within the semiconductor chip region I and the dicing line region II. For example, the first insulating film 111 can cover the entire surface of the substrate 100.

[0044] The first insulating film 111 may include a low-k dielectric material with a dielectric constant lower than that of the silicon oxide film. The first insulating film 111 may have a dielectric constant of about 1.0 to 3.0 and may include at least one of organic materials, inorganic materials, and organic-inorganic hybrid materials. Furthermore, the first insulating film 111 may be porous or non-porous. The first insulating film 111 may be formed from, for example, an oxide film-based material doped with impurities or an organic polymer having a low dielectric constant (low k).

[0045] The oxide film-based materials doped with impurities can be, for example, fluorine-doped oxides (FSG), carbon-doped oxides, silicon oxide, HSQ (hydrogen silsesquioxane; SiO:H), MSQ (methyl silsesquioxane; SiO:CH3), a-SiOC (SiOC:H), etc. For example, organic polymers with low dielectric constants can be, for example, polyallyl ether resins, cyclic fluoropolymers, siloxane copolymers, fluorinated polyallyl ether resins, polypentafluorostyrene, polytetrafluorostyrene resins, fluorinated polyimide resins, fluorinated polynaphthalene fluorides, polyamide resins, etc.

[0046] In the accompanying drawings, the first insulating film 111 is shown as a single film, but the inventive concept is not limited thereto. For example, the first insulating film 111 may include insulating films stacked in a vertical direction and barrier films disposed between the vertically stacked insulating films. The barrier films may include insulating materials, such as SiN, SiON, SiC, SiCN, SiOCH films, SiOC, or SiOF.

[0047] The lower wiring 121 can be disposed in the first insulating film 111. The lower wiring 121 can be disposed in the semiconductor chip region I. The lower wiring 121 comprises a conductive material.

[0048] The lower wiring 121 can be electrically connected to the semiconductor chip wiring 105. The lower wiring 121 may include a lower wiring layer and a lower via inserted between the lower wiring layer and the semiconductor chip wiring 105. In the figures, the side of the lower via is shown to have a vertical orientation, but the inventive concept is not limited thereto. Rather, the side of the lower via can, of course, extend from the semiconductor chip wiring 105 toward the lower wiring layer at any angle.

[0049] The second insulating film 113 can be disposed on the first insulating film 111. The second insulating film 113 can be disposed within the semiconductor chip region I and the dicing line region II.

[0050] The second insulating film 113 can be, for example, a high-density plasma (HDP) oxide film.

[0051] The upper wiring 122 can be disposed in the second insulating film 113. The upper wiring 122 can be disposed in the semiconductor chip region I.

[0052] The upper wiring 122 can electrically connect the redistribution wiring 123 and the lower wiring 121. The upper wiring 122 may include an upper wiring layer and an upper via inserted between the upper wiring layer and the lower wiring 121. In the drawings, the side of the upper via is shown to have a vertical orientation, but the inventive concept is not limited thereto. Rather, the side of the upper via may extend from the lower wiring 121 toward the upper wiring layer at any angle.

[0053] The first wiring element 124 includes a conductive material. The first wiring element 124 may be disposed within the second insulating film 113 and may be part of the same metallization layer as the upper wiring layer. The first wiring element 124 may be disposed within the cleaved wire region II. At least a portion of the first wiring element 124 may be exposed by the third insulating film 115 and the insertion film 131. The first wiring element 124 may be configured to protrude from a second portion 115b of the third insulating film 115, i.e., in... Figures 2 to 5When viewed in the plan view of the device shown, the first wiring element 124 can extend laterally outward from the second portion 115b. Here, and in the following description, when one element is described as “exposing” another element, it should be understood that such a description means that, when viewed in the plan view, the former element does not cover or does not completely cover the latter.

[0054] The upper wiring 122 includes conductive material. The first insulating film 111, the second insulating film 113, the lower wiring 121, the upper wiring 122 and the first wiring element 124 can together form the lower wiring (connection) structure.

[0055] An insertion film 131 may be disposed on the second insulating film 113. The insertion film 131 may be disposed within the semiconductor chip region I and the dicing line region II. The insertion film 131 may expose at least a portion of the upper wiring 122. The insertion film 131 may expose at least a portion of the first wiring element 124.

[0056] The insertion film 131 may include an insulating material that has etch selectivity relative to the second insulating film 113 and the third insulating film 115. The insertion film 131 may be, for example, a silicon nitride film or a silicon oxynitride film.

[0057] A third insulating film 115 may be disposed on the insertion film 131. The third insulating film 115 may be disposed within the semiconductor chip region I and the dicing line region II. The third insulating film 115 has a first region 115_1 defining a first opening OP1 and a second region 115_2 defining a second opening OP2. Furthermore, the third insulating film 115 may include a first portion 115a, a second portion 115b, and a third portion 115c. The first region 115_1 of the third insulating film 115 may include only the first portion 115a. The second region 115_2 of the third insulating film 115 may include a portion of the first portion 115a and the second portion 115b.

[0058] The first portion 115a of the third insulating film 115 can be disposed in the cutting line region II. When viewed in a plan view, the first portion 115a of the third insulating film 115 can protrude from the distal end 117e of the passivation film 117. The first portion 115a of the third insulating film 115 can be disposed alongside the distal end 117e of the passivation film 117. That is, the first portion 115a of the third insulating film 115 can be the portion of the third insulating film 115 disposed along the periphery of the passivation film 117. The first portion 115a of the third insulating film 115 can be the portion of the third insulating film 115 that does not overlap with the passivation film 117, that is, no part of the first portion 115a of the third insulating film 115 is vertically juxtaposed with a portion of the passivation film 117. Therefore, the first portion 115a of the third insulating film 115 can be exposed by the passivation film 117.

[0059] The second portion 115b of the third insulating film 115 may be in the form of a tab protruding from the first portion 115a in the cutting line region II. The second portion 115b of the third insulating film 115 may protrude from the first portion 115a of the third insulating film 115. The second portion 115b of the third insulating film 115 may be exposed by the passivation film 117. The second portion 115b of the third insulating film 115 may also be a portion of the third insulating film 115 that does not overlap with the passivation film 117. The second portion 115b of the third insulating film 115 may expose the first wiring element 124.

[0060] In some examples, there is no alignment key on the second portion 115b of the third insulating film 115.

[0061] The third portion 115c of the third insulating film 115 can be disposed within the semiconductor chip region I and the dicing line region II. The third portion 115c of the third insulating film 115 can be the portion of the third insulating film 115 that is vertically juxtaposed with the passivation film 117.

[0062] The third insulating film 115 may include an insulating material different from the insulating material of the second insulating film 113. For example, the third insulating film 115 may include TEOS (tetraethyl orthosilicate).

[0063] The redistribution wiring 123 can be arranged in the semiconductor chip region I. A portion of the redistribution wiring 123 can extend into the third portion 115c of the third insulating film 115 and the insertion film 131. The remaining portion of the redistribution wiring 123 can be disposed on the third portion 115c of the third insulating film 115. The redistribution wiring 123 can be electrically connected to the upper wiring 122. The redistribution wiring 123 can be disposed between the upper wiring 122 and the connection terminal 101.

[0064] The third insulating film 115 and the redistribution wiring 123 can together form a redistribution wiring layer and can be referred to as the upper wiring (connection) structure.

[0065] The sides of the redistribution wiring 123 extending to the third portion 115c of the third insulating film 115 and the portion of the insertion film 131 are shown to have a vertical orientation, but the inventive concept is not limited thereto. Rather, the sides may have any angle of inclination as they extend from the upper wiring 122 toward the passivation film 117.

[0066] The redistribution wiring 123 may be formed of at least one metal or metal alloy selected from the group consisting of: copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C).

[0067] The protective film 133 can be disposed within the semiconductor chip region I and the dicing line region II. The protective film 133 can be disposed on the third portion 115c of the third insulating film 115 and the redistribution wiring 123. The protective film 133 may not extend to the second portion 115b of the third insulating film 115. Therefore, the protective film 133 can expose the first portion 115a and the second portion 115b of the third insulating film 115. The protective film 133 can expose a portion of the redistribution wiring 123.

[0068] The protective film 133 can be, for example, a silicon nitride film or a silicon oxynitride film.

[0069] The passivation film 117 can be disposed within the semiconductor chip region I and the dicing line region II. The passivation film 117 can also be disposed on the protective film 133.

[0070] The passivation film 117 may include a first portion 117a and a second portion 117b. The first portion 117a of the passivation film 117 is the portion of the passivation film 117 disposed in the semiconductor chip region I. The second portion 117b of the passivation film 117 is the portion of the passivation film 117 disposed in the dicing line region II. The second portion 117b of the passivation film 117 may be adjacent to the first portion 117a of the passivation film 117. The second portion 117b of the passivation film 117 may expose the first portion 115a and the second portion 115b of the third insulating film 115.

[0071] The distal end 117e of the passivation film 117 may be located on the third insulating film 115. In the figures, the distal end 117e of the passivation film 117 is shown to have a vertical orientation, that is, to extend vertically from the upper surface 115U of the third insulating film 115, but the inventive concept is not limited thereto. Rather, the distal end 117e of the passivation film 117 may have any angle of inclination.

[0072] The passivation film 117 may include a polyimide-based material, such as photosensitive polyimide (PSPI).

[0073] The upper surface 117U of the passivation film 117 can be located at a level higher than the level of the upper surface 115U of the third insulating film 115. In addition, the upper surface 115U of the third insulating film 115 can be set at a level higher than the level of the upper surface 124U of the first wiring element 124.

[0074] The first opening OP1 can be formed in the cutting line region II. The first opening OP1 can be formed in the first region 115_1 of the third insulating film 115.

[0075] For example, the side of the first opening OP1 may be defined by the surface of the first portion 115a of the third insulating film 115, the insertion film 131, the second insulating film 113, and the first insulating film 111. The bottom of the first opening OP1 may be defined by the upper surface of the substrate 100. Therefore, the first opening OP1 can open to the substrate 100.

[0076] In the accompanying drawings, the side of the first opening OP1 is shown as vertical relative to the substrate 100, but the inventive concept is not limited thereto. Rather, the side of the first opening OP1 can have any angle of inclination.

[0077] The second opening OP2 can be formed in the cutting line region II. The second opening OP2 can be defined by the second region 115_2 of the third insulating film 115.

[0078] The side of the second opening OP2 can be defined by the second portion 115b of the third insulating film 115 and the surface of the insertion film 131. The bottom of the second opening OP2 can be defined by the upper surface 124U of the first wiring element 124. Therefore, the second opening OP2 can lead to the first wiring element 124.

[0079] In the accompanying drawings, the side of the second opening OP2 is shown as vertical relative to the substrate 100, but the inventive concept is not limited thereto. Rather, the side of the second opening OP2 can have any angle of inclination.

[0080] exist Figure 4 and Figure 5 In this configuration, the bottom of the first opening OP1 may be located at a lower level than the bottom of the second opening OP2. In this respect, the side of the protrusion (second portion 115b) and the end surface of the first region 115_1 of the third insulating film 115 define a recess in the side of the upper insulating layer, and the recess is the upper portion of the opening OP1 that exposes (i.e. leads to) the upper surface of the substrate 100. The end surface of the protrusion (second portion 115b) defines the side of the second opening OP2 that exposes (i.e. leads to) a portion of the first wiring element 124.

[0081] The width W1 of the first region 115_1 of the third insulating film 115 may be smaller than the width W2 of the second region 115_2 of the third insulating film 115. Width W1 may be the size of the first opening OP1 measured from the distal end 117e of the passivation film 117 to the side of the first opening OP1. Width W2 may be the size of the second opening OP2 measured from the distal end 117e of the passivation film 117 to the side of the second opening OP2.

[0082] Because the second width W2 is greater than the first width W1, a portion of the first wiring element 124 is covered by the second portion 115b of the third insulating film 115. In the semiconductor device and semiconductor package including the semiconductor device according to the present invention, the width of the portion of the third insulating film 115 where the first wiring element 124 is disposed (i.e., the second region 115_2 of the third insulating film 115) is set to be greater than the width of the portion of the third insulating film 115 where the first wiring element 124 is not disposed (i.e., the first region 115_1 of the third insulating film 115). Therefore, the phenomenon of the first wiring element 124 peeling off from the second insulating film 113 can be prevented. Therefore, the yield of the semiconductor device can be improved.

[0083] Connection terminal 101 can be disposed in semiconductor chip region I. A portion of connection terminal 101 can extend into passivation film 117, protective film 133, and redistribution wiring 123. Connection terminal 101 can protrude from the upper surface 117U of passivation film 117.

[0084] The semiconductor chip wiring 105 can be electrically connected to the semiconductor packaging substrate 1200 through the connection terminal 101.

[0085] In the description above, such as Figure 1A and Figure 1B As shown and referenced Figure 2 The structure and features of region N of the device described in detail can be applied to another side or more than one side of the semiconductor device 1100. For example, the second portion 115b of the third insulating film 115 can not only be formed on such... Figure 1A The region N on the side of the device shown can also be formed on the other side of the device facing the cutting line SL or at least on one other side.

[0086] In the following text, reference will be made to Figures 6 to 13 A method for manufacturing a semiconductor device according to the present invention is described. For the sake of brevity and because the semiconductor device according to the present invention that can be manufactured by this method has already been described in detail above, the description of some features of the semiconductor device will be simplified or omitted. However, for clarity, the same reference numerals are used to indicate the same features of the semiconductor device according to the present invention.

[0087] Figure 6 A substrate 100 is shown, on which semiconductor devices 1100, some examples of the concept according to the present invention, are integrated. Figures 7 to 11 An intermediate step in a method for manufacturing a semiconductor device according to a concept conceived in this invention is shown. Figures 7 to 11 Is along with Figure 6 Cross-sectional views taken in the directions corresponding to lines D-D', E-E', and F-F'.

[0088] refer to Figure 6 and 7 A substrate 100 on which semiconductor chip wiring 105 is formed can be provided. Furthermore, a first insulating film 111, a second insulating film 113, an insertion film 131, and a third insulating film 115 can be sequentially stacked on the substrate 100. The first insulating film 111, the second insulating film 113, the insertion film 131, and the third insulating film 115 can be formed within the semiconductor chip region I and the dicing line region II.

[0089] The lower wiring 121 can be formed on the first insulating film 111. The upper wiring 122 and the first wiring element 124 can be formed on the second insulating film 113.

[0090] The lower wiring 121 and the upper wiring 122 can be formed in the semiconductor chip region I. The first wiring element 124 can be formed in the dicing region II.

[0091] refer to Figure 8 A first trench T1 can be formed in the semiconductor chip region I. For example, a portion of the third insulating film 115 and a portion of the insertion film 131 formed in the semiconductor chip region I can be removed. The upper wiring 122 can be exposed through the first trench T1.

[0092] refer to Figure 9 This can form redistribution wiring 123 and protective film 133.

[0093] Redistribution wiring 123 can be formed to fill the first trench T1. Alternatively, redistribution wiring 123 can also be formed on the upper surface of the third insulating film 115. Redistribution wiring 123 can be formed in the semiconductor chip region I.

[0094] A protective film 133 may be formed on a third insulating film 115 to cover the redistribution wiring 123. The protective film 133 may be formed within semiconductor chip region I and dicing line region II.

[0095] refer to Figure 10 A first opening OP1 and a second opening OP2 can be formed in the cutting line region II.

[0096] A first opening OP1 can be formed when a portion of the protective film 133, a portion of the third insulating film 115, a portion of the insertion film 131, a portion of the second insulating film 113, and a portion of the first insulating film 111 formed in the dicing region II are removed. The first opening OP1 can be formed in the portion of the dicing region II where the first wiring element 124 is not present. The substrate 100 can be exposed through the first opening OP1.

[0097] When a portion of the protective film 133, a portion of the third insulating film 115, and a portion of the insertion film 131 formed in the cutting line region II are removed, a second opening OP2 can be formed. The second opening OP2 can be formed in the portion of the cutting line region II where the first wiring element 124 is formed. The first wiring element 124 can be exposed through the second opening OP2.

[0098] The width W3 of the upper part of the first opening OP1 can be greater than the width W4 of the upper part of the second opening OP2. The width W3 of the upper part of the first opening OP1 and the width W4 of the upper part of the second opening OP2 can be dimensions measured between the relative boundaries of the structure formed by the protective film 133 and the third insulating film 115.

[0099] refer to Figure 11 A passivation film 117 can be formed on the protective film 133. The passivation film 117 may include a first portion 117a and a second portion 117b.

[0100] The second trench T2 can be formed by removing a portion of the first portion 117a of the passivation film 117, a portion of the protective film 133, and a portion of the redistribution wiring 123 from semiconductor chip region I. The second trench T2 can accommodate connection terminals in subsequent processes. Figure 4 (101 in the middle).

[0101] During the formation of the second portion 117b of the passivation film 117, a portion of the protective film 133 may be removed. During the formation of the second portion 117b of the passivation film 117, the first portion 115a, the second portion 115b, and the third portion 115c of the third insulating film 115 may be defined.

[0102] For example, refer to Figure 10 The protective film 133 formed in the dicing region II covers the entire upper surface of the third insulating film 115. During the formation of the second portion 117b of the passivation film 117, a portion of the protective film 133 in the dicing region II is removed, and a portion of the third insulating film 115 may be exposed.

[0103] When a portion of the protective film 133 is removed from the cutting line region II where the first opening OP1 is formed, the first portion 115a of the third insulating film 115 can be exposed.

[0104] When a portion of the protective film 133 is removed in the cutting line region II where the second opening OP2 is formed, the first portion 115a and the second portion 115b of the third insulating film 115 can be exposed.

[0105] The portion of the third insulating film 115 that overlaps with the first portion 117a of the passivation film 117 can be defined as the third portion 115c of the third insulating film 115.

[0106] Figure 12 It is being executed Figure 11 Following the method of manufacturing semiconductor devices Figure 6 A magnified view of region J. Figure 13 yes Figure 12 A magnified view of region M.

[0107] refer to Figure 12 and Figure 13 The first opening OP1 can be formed in the first region 115_1 of the third insulating film 115. The second opening OP2 can be formed in the second region 115_2 of the third insulating film 115.

[0108] The first width W1 of the first region 115_1 of the third insulating film 115 can be smaller than the second width W2 of the second region 115_2 of the third insulating film 115. The width W3 of the upper part of the first opening OP1 can be larger than the width W4 of the upper part of the second opening OP2.

[0109] The first wiring element 124 may overlap with the second portion 115b of the third insulating film 115.

[0110] When the substrate 100 is cut along the cutting line SL, a reference can be formed. Figure 2 An example of the semiconductor device 1100 described.

[0111] Although the inventive concept has been specifically shown and described with reference to various examples thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, it should be understood that the present examples are to be considered illustrative rather than restrictive in all respects, and the scope of the inventive concept should be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A semiconductor device, comprising: The semiconductor chip region includes the semiconductor chip and a first portion of the passivation film covering the semiconductor chip; The dicing region includes a second portion of the passivation film adjacent to the first portion of the passivation film, a portion of the first insulating film that laterally protrudes beyond the distal end of the second portion of the passivation film when viewed in a plan view of the semiconductor device, and a first wiring. The portion of the first insulating film includes: a first portion disposed beside the distal end of the second portion of the passivation film when viewed in a plan view of the semiconductor device; and a second portion protruding laterally outward from the first portion of the first insulating film, the second portion being located on a portion of the upper surface of the first wiring. When viewed in a plan view of the semiconductor device, the first wiring protrudes laterally outward from the second portion of the first insulating film.

2. The semiconductor device according to claim 1, further comprising: The substrate, in the semiconductor chip region and the dicing line region, The first insulating film has: a first region defining a first opening that exposes the substrate; and a second region defining a second opening that exposes the first wiring.

3. The semiconductor device according to claim 2, wherein, The first region has a width measured from the distal end of the second portion of the passivation film to the proximal side of the surface defining the first opening, and The second region has a width measured from the distal end of the second portion of the passivation film to the proximal side of the surface defining the second opening, and The width of the first region is smaller than the width of the second region.

4. The semiconductor device according to claim 1, wherein, The first wiring, the first insulating film, and the passivation film are stacked sequentially.

5. The semiconductor device according to claim 4, wherein, The upper surface of the first wiring is located lower than the upper surface of the first insulating film, and The upper surface of the first insulating film is located at a lower position than the upper surface of the passivation film.

6. The semiconductor device according to claim 1, wherein, The first insulating film has a third portion, which is disposed in the semiconductor chip region and vertically juxtaposed with the first portion of the passivation film. The semiconductor chip region further includes: A redistribution layer, at least a portion of which is disposed within the third portion of the first insulating film; and A connection terminal electrically connected to the redistribution layer, at least a portion of which is disposed in the passivation film.

7. The semiconductor device according to claim 1, further comprising: A substrate is located in the semiconductor chip region and the dicing line region; and A second insulating film is located on the substrate, and the first wiring is disposed on the upper surface of the second insulating film. The passivation film is disposed on the first insulating film. The first insulating film is disposed on the second insulating film, and The first insulating film has: The first region defines the first opening exposing the substrate, and The second region defines a second opening that exposes the portion of the first wiring.

8. The semiconductor device according to claim 1, wherein, The first insulating film comprises tetraethyl orthosilicate.

9. The semiconductor device according to claim 1, wherein, There are no alignment keys in the second portion of the first insulating film.

10. The semiconductor device according to claim 1, wherein, The passivation film comprises a polyimide-based material.

11. A semiconductor device having a semiconductor chip region and a dicing line region, and said semiconductor device comprising: A substrate constituting a semiconductor chip, the semiconductor chip being disposed in the semiconductor chip region and having semiconductor chip wiring, and the substrate extending into the dicing line region; A first insulating film is disposed in the semiconductor chip region and the dicing line region; The first wiring is located in the cut line region at the upper part of the first insulating film; A second insulating film is disposed on the first insulating film. The second insulating film has a first region defining a first opening that exposes the substrate and a second region defining a second opening that exposes the first wiring. The second region is located on a portion of the upper surface of the first wiring. as well as A passivation film is disposed on the second insulating film. The passivation film exposes both the first region of the second insulating film and the second region of the second insulating film. The width of the first region of the second insulating film is smaller than the width of the second region of the second insulating film.

12. The semiconductor device according to claim 11, wherein, The distal end of the passivation film is disposed on the second insulating film.

13. The semiconductor device according to claim 12, wherein, The width of the first region of the second insulating film is the distance between the distal end of the passivation film and the proximal side of the first opening in a direction parallel to the upper surface of the substrate. The width of the second region of the second insulating film is the distance between the distal end of the passivation film and the surface of the second region of the second insulating film defining the second opening in the direction parallel to the upper surface of the substrate.

14. The semiconductor device according to claim 13, wherein, The proximal side of the first opening is defined by the surface of the first region of the second insulating film, and The proximal side of the second opening is defined by the surface of the second region of the second insulating film.

15. The semiconductor device according to claim 11, wherein, When viewed in a plan view of the semiconductor device, the first wiring extends laterally outward beyond the second region of the second insulating film.

16. The semiconductor device according to claim 11, wherein, The semiconductor chip region further includes: A redistribution layer, wherein the redistribution layer is disposed on the first insulating film and at least a portion thereof is disposed in the second insulating film; and A connection terminal is electrically connected to the redistribution layer, and at least a portion of the connection terminal is disposed in the passivation film.

17. The semiconductor device according to claim 11, wherein, The first opening and the second opening are confined within the cutting line region.

18. The semiconductor device according to claim 11, wherein, The second insulating film comprises tetraethyl orthosilicate.

19. A semiconductor package comprising a semiconductor device according to claim 1 and a semiconductor package substrate on which the semiconductor device is mounted.

20. The semiconductor package of claim 19, wherein, The semiconductor packaging substrate has conductive pads on its surface. The first insulating film of the semiconductor device has a third portion, which is disposed in the semiconductor chip region and vertically juxtaposed with the first portion of the passivation film. The semiconductor chip region of the semiconductor device further includes: A redistribution layer, at least a portion of which is disposed within the third portion of the first insulating film; and A connection terminal is electrically connected to the conductive pads of the redistribution layer and the semiconductor packaging substrate, and at least a portion of the connection terminal is disposed in the passivation film.

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