Semiconductor device including resistor structure

Abstract

A semiconductor device is provided, comprising a substrate, the substrate comprising a resistor region, a plurality of lower patterns located in the resistor region, and a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region. The plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern extends in the second direction. The resistor line pattern located on the lower pattern has an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0092292 filed on August 8, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices including resistor structures. Background Art

[0004] The semiconductor device includes a main unit region and a peripheral region for driving the main unit. In the peripheral region, various devices such as transistors, resistor structures, capacitors and / or inductors are arranged to form a peripheral circuit. However, in order to obtain the desired resistance of the resistor structure included in the peripheral circuit, the resistor structure may occupy a relatively large area. Using a large area for the resistor structure may increase the cost of the semiconductor device, limit the degree to which the device can be integrated with other components, or increase the manufacturing cost. Summary of the invention

[0005] According to an example embodiment of the present invention, a semiconductor device may include a substrate including a resistor region, a plurality of lower patterns located in the resistor region, and a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region. The plurality of lower patterns may extend in a first direction parallel to a surface of the substrate, and may be arranged to be spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern may extend in the second direction. The resistor line pattern located on the lower pattern may have an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate.

[0006] According to an example embodiment of the present invention, a semiconductor device may include: a substrate including a cell region and a resistor region; a plurality of lower patterns, the plurality of lower patterns being located in the resistor region; a resistor line pattern, the resistor line pattern being located on the plurality of lower patterns and on the substrate in the resistor region; and a cell pattern, the cell pattern being located in the cell region. The plurality of lower patterns may extend in a first direction parallel to the surface of the substrate, and may be arranged to be spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern may extend in the second direction. The resistor line pattern located on the lower pattern may have an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate. The cell pattern may include the same material and the same stacking structure as each of the plurality of lower patterns.

[0007] According to an example embodiment of the present invention, a semiconductor device may include: a substrate including a cell region, a transistor region, and a resistor region; a plurality of lower patterns located in the resistor region; a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region; a cell pattern located in the cell region; and a gate structure located in the transistor region. The plurality of lower patterns may extend in a first direction parallel to a surface of the substrate, and may be arranged to be spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern may extend in the second direction. The resistor line pattern located on the lower pattern may have an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate. The unit pattern may include the same material and the same structure as each of the plurality of lower patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a top plan view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0009] Figure 2 , Figure 3 and Figure 4 is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0010] Figures 5 to 12 is a cross-sectional view illustrating a method of forming a resistor structure of a semiconductor device according to example embodiments.

[0011] Fig.13is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0012] Fig.14 is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0013] Fig.15 is a cross-sectional view illustrating a method of forming a resistor structure of a semiconductor device according to example embodiments.

[0014] Fig.16 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0015] Figures 17 to 25 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0016] Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The inventive concept may, however, be embodied in many alternate forms and should not be construed as limited to only the example embodiments set forth herein.

[0017] The present disclosure describes an embodiment of a semiconductor device that can achieve resistance levels with relatively small resistor structures. This can reduce the overall size of the device or make it more highly integrated. Example embodiments include resistor structures with wave-like shapes as described below and in the accompanying drawings.

[0018] Figure 1 is a top plan view illustrating a resistor structure of a semiconductor device according to example embodiments. Figure 2 , Figure 3 and Figure 4 is a cross-sectional view showing a resistor structure of a semiconductor device according to an example embodiment. Specifically, Figure 2 is along Figure 1 A cross-sectional view taken along line AA′. Figure 3 is along Figure 1 A cross-sectional view taken along line BB′. Figure 4 is along Figure 1 A cross-sectional view taken along line CC′.

[0019] Hereinafter, "first direction" refers to a direction parallel to the surface of the substrate, "second direction" refers to a direction parallel to the surface of the substrate and perpendicular to the first direction, and "third direction" refers to a direction perpendicular to the surface of the substrate. In some examples, the first direction may be an extension direction of the lower pattern of the resistor structure, and may be perpendicular to an extension direction of one or more resistor lines.

[0020] Reference Figures 1 to 4, the resistor structure of the semiconductor device may be disposed on a portion of the substrate 100 corresponding to the resistor region. The resistor structure may include a lower pattern 106 and a resistor line pattern 116 located on the lower pattern 106. Each resistor line pattern 116 may be disposed on the isolation pattern 104, and the lower pattern 106 may have an uneven upper surface and lower surface. A mask pattern 114 may be disposed on each resistor line pattern 116. An interlayer insulating layer 120 may be disposed to cover the mask pattern 114, the resistor line pattern 116, the lower pattern 106, and the isolation pattern 104. A contact plug 124 may be disposed to penetrate the mask pattern 114 and the interlayer insulating layer 120, and be electrically connected to the resistor line pattern 116.

[0021] The substrate 100 may be, for example, a semiconductor substrate, such as a silicon substrate, a gallium arsenide substrate, or a silicon germanium substrate. The substrate 100 may be a silicon-on-insulator (SOI) substrate.

[0022] The substrate 100 may include a cell region and a core / peripheral region. The resistor structure may be formed in the core / peripheral region. That is, the resistor structure may be formed in the resistor region, and the resistor region may be substantially located in the core / peripheral region.

[0023] The trench 102 may be formed in a portion of the substrate 100 corresponding to the resistor region. An isolation pattern 104 may be provided in the trench 102. The isolation pattern 104 may include an insulating material, such as silicon oxide. The isolation pattern 104 may have a substantially flat upper surface. The isolation pattern 104 may be provided as a field region. An upper portion of the substrate 100 where the isolation pattern 104 is not formed may be provided as an active region.

[0024] In some embodiments, the lower structure and the interlayer insulating layer covering the lower structure may be disposed on the substrate 100, and the resistor structure may be formed on the interlayer insulating layer. In this case, the resistor region may include an interlayer insulating layer located on the substrate 100. In addition, the resistor structure may be spaced apart from the upper surface of the substrate 100.

[0025] In some embodiments, a guard ring 118 may be provided on the active area 103 contacting the resistor area. The guard ring 118 may be provided to define the resistor area. The guard ring 118 may surround the boundary of the resistor area. The material included in the guard ring 118 may be the same as the material included in the resistor line pattern 116. In some embodiments, the guard ring 118 may not be included.

[0026] The lower pattern 106 may be arranged in the resistor region and may extend in the first direction. The lower patterns 106 may be spaced apart from each other in the second direction. The lower pattern 106 may include an insulating material, such as silicon nitride and / or silicon oxide. Each lower pattern 106 may be formed of a single layer or may have a multilayer stacked structure. As an example, each lower pattern 106 may be formed of a silicon nitride pattern. As another example, each lower pattern 106 may have a stacked structure of a silicon nitride pattern and a silicon oxide pattern. As another example, each lower pattern 106 may have a stacked structure of a first silicon oxide pattern, a silicon nitride pattern, and a second silicon oxide pattern.

[0027] Each lower pattern 106 may have a first height from its lower surface to its upper surface and a first width in the second direction. The lower patterns 106 may be spaced apart from each other by a first distance in the second direction. The opposite sidewalls of each lower pattern 106 in the second direction may be inclined relative to the surface of the substrate 100. That is, the cross section of each lower pattern 106 may have a trapezoidal shape. In some examples, the opposite sides of each lower pattern 106 may have equal but opposite slopes. In other examples, the opposite sides of each lower pattern 106 may have different slopes.

[0028] The closer the slope of the sidewall of each lower pattern 106 is to 90 degrees, the longer the resistor line pattern 116 will be, so the resistance of the resistor structure will increase. As an example, the inclination angle of the sidewall of each lower pattern 106 can be in the range of 30 degrees to 90 degrees, but is not limited thereto.

[0029] The lower pattern 106 may determine the shape of each resistor line pattern 116 thereon. For example, if the first height of each lower pattern 106 increases, the height of the protruding portion of each resistor line pattern 116 relative to the surface of the substrate 100 may increase accordingly. In other words, the protruding portion of each resistor line pattern 116 may be isolated from the substrate (and / or the isolation pattern 104) by one of the lower patterns 106.

[0030] If the first width of each lower pattern 106 increases, the width of the protruding portion of each resistor line pattern 116 increases accordingly. Similarly, if the first distance between the lower patterns 106 increases, the width of the lower portion of each resistor line pattern 116 between adjacent protruding portions of each resistor line pattern 116 increases accordingly. In addition, the slope of the protruding portion of each resistor line pattern 116 may vary according to the slope of the opposite sidewalls of each lower pattern 106 in the second direction.

[0031] The resistor line pattern 116 may be disposed in the resistor region and may extend in the second direction. In addition, the resistor line pattern 116 may be arranged to be spaced apart from each other in the first direction. Therefore, the resistor line pattern 116 may be arranged in a manner of alternately arranging lines and spaces.

[0032] In each resistor line pattern 116, a portion above each lower pattern 106 may protrude from the substrate 100 (and / or the isolation pattern 104) in a third direction relative to a portion of the resistor line pattern 116 that is not directly above the lower pattern 106. In addition, in each resistor line pattern 116, a bottom surface of a portion of the resistor line pattern 116 formed on the isolation pattern 104 between the lower patterns 106 may be lower than a bottom surface of a portion of the resistor line pattern 116 formed on the lower pattern 106. In addition, an upper surface of a portion of the resistor line pattern 116 formed on the isolation pattern 104 between the lower patterns 106 may be lower than an upper surface of a portion of the resistor line pattern 116 formed on the lower pattern 106.

[0033] Each resistor line pattern 116 may include a first portion 'a', a third portion 'c' (i.e., a protruding or elevated portion), and a second portion 'b' connecting the first portion 'a' and the third portion 'c', with reference to the upper surface of the substrate 100, the upper surface and the lower surface of the first portion 'a' having a relatively low height, with reference to the upper surface of the substrate 100, the upper surface and the lower surface of the third portion 'c' having a relatively high height, and the second portion 'b' having an inclined upper surface and a lower surface. In other words, with reference to the upper surface of the substrate 100, the upper surface and the lower surface of the first portion 'a' are respectively lower than the upper surface and the lower surface of the third portion 'c'. Since the upper surface and the lower surface of each resistor line pattern 116 are not flat, the length of the upper surface of each resistor line pattern 116 in the second direction can be longer than the case where the upper surface of each resistor line pattern 116 is flat. The increase in the surface length of the resistor line pattern 116 can increase the resistance of the resistor structure in the resistor region. Furthermore, the area of ​​the resistor region required to form a resistor structure having a desired resistance may be reduced, so that a semiconductor device including the resistor structure may be more highly integrated (ie, more highly integrated with other semiconductor devices or with other components).

[0034] Therefore, the semiconductor device may include a plurality of lower patterns 106 located in the resistor region, wherein the plurality of lower patterns 106 extend in a first direction parallel to the surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate, and wherein each of the plurality of lower patterns 106 includes inclined side walls relative to each other in the second direction.

[0035] In addition, a plurality of resistor line patterns 116 can form a resistor structure, wherein each resistor line pattern extends in a second direction and includes a plurality of high portions disposed on a plurality of lower patterns 106 and a plurality of low portions disposed between the plurality of lower patterns 106, and wherein the high portions and the low portions of each resistor line pattern 116 are connected to form a wavy shape, which is configured to increase the resistance of the resistor structure (i.e., compared to a resistor line pattern that does not have a wavy shape).

[0036] In some embodiments, the resistor line pattern 116 may include a resistor material, such as a metal, a metal silicide, a metal nitride, or a semiconductor material. For example, the resistor line pattern 116 may include tungsten, tungsten silicide, tungsten nitride, titanium, titanium silicide, titanium nitride, tantalum, tantalum silicide, tantalum nitride, and / or polysilicon. Each resistor line pattern 116 may be formed by one layer, or two or more stacked layers.

[0037] As shown, each resistor line pattern 116 may have a stack structure of a lower resistor pattern and an upper resistor pattern. For example, each resistor line pattern 116 may have a stack structure of a polysilicon pattern 108a and a tungsten silicide pattern 110a.

[0038] In the resistor region, a region adjacent to an end of each resistor line pattern 116 in the second direction may be provided as a contact region P for forming a contact plug 124 .

[0039] In some embodiments, in the contact region P, the ends of adjacent resistor line patterns 116 may be merged to form a merged resistor line 116a having an increased width in the first direction. For example, when it is difficult to form a contact plug 124 on each resistor line pattern 116 (e.g., due to the narrow width of each resistor line pattern 116), a merged resistor line 116a may be provided. Therefore, in some cases, the contact plug 124 may be disposed on the merged resistor line 116a.

[0040] In some embodiments, the merged resistor line 116 a may be omitted. For example, the resistor line pattern 116 may extend to a region close to a boundary of the resistor region. In this case, the contact plug 124 may be disposed on the resistor line pattern 116 .

[0041] The mask pattern 114 on each resistor line pattern 116 may include an insulating material.

[0042] The interlayer insulating layer 120 may cover the mask pattern 114, the resistor line pattern 116, the lower pattern 106, the isolation pattern 104, and the guard ring 118. The upper surface of the interlayer insulating layer 120 may be higher than the upper surface of the resistor line pattern 116 relative to the upper surface of the isolation pattern 104. In some examples, the interlayer insulating layer 120 may have a flat upper surface. The interlayer insulating layer 120 may include silicon oxide.

[0043] The contact plug 124 may contact an upper surface of the merged resistor line 116 a or an upper surface of the resistor line pattern 116 located in the contact region P. Hereinafter, the contact plug 124 may be disposed on the merged resistor line 116 a in the contact region P will be described.

[0044] In some embodiments, the lower pattern 106 may be disposed below the merged resistor line 116a. In this case, the merged resistor line 116a may have an uneven upper surface and an uneven lower surface.

[0045] In some embodiments, the merged resistor line 116a may include a first portion A, a third portion C, and a second portion B connecting the first portion A and the third portion C, the upper and lower surfaces of the first portion A having a relatively low height with reference to the upper surface of the substrate 100, the upper and lower surfaces of the third portion C having a relatively high height with reference to the upper surface of the substrate 100, and the second portion B having an inclined upper and lower surface. In other words, with reference to the upper surface of the substrate 100, the upper and lower surfaces of the first portion 'A' are lower than the upper and lower surfaces of the third portion 'C', respectively.

[0046] In some embodiments, the contact plug 124 may contact the second portion B of the merged resistor line 116a. Because the lower surface of the contact plug 124 contacts the inclined surface of the merged resistor line 116a, the lower surface of the contact plug 124 may be inclined (as opposed to flat or planarized). Therefore, the area of ​​the lower surface of the contact plug 124 may be increased. In this way, as the area of ​​the lower surface of the contact plug 124 increases, the contact resistance of the contact plug 124 may be reduced.

[0047] When the inclination angle of the second portion B of the merged resistor line 116a is 90 degrees, it may be difficult to form a contact plug 124 contacting the second portion B of the merged resistor line 116a. Therefore, the inclination angle of the second portion B of the merged resistor line 116a may be less than 90 degrees, for example, between 30 degrees and 90 degrees.

[0048] In some embodiments, at least one contact plug 124 may contact the first portion A or the third portion C of the merged resistor line 116 a. For example, at least one contact plug 124 may contact a flat portion of the merged resistor line 116 a.

[0049] Figures 5 to 12 is a cross-sectional view showing a method of forming a resistor structure of a semiconductor device according to an example embodiment. Specifically, Figure 5 , Figure 7 , Fig. 9 and Fig.11 It is along Figure 1 A cross-sectional view taken along line AA′. Figure 6 , Figure 8 , Fig.10 and Fig.12 is along Figure 1 A cross-sectional view taken along line BB′.

[0050] Reference Figure 5 and Figure 6 , an isolation process may be performed on the substrate 100 to define an isolation region and an active region. The isolation process may include a shallow trench isolation (STI) process. For example, a trench 102 may be formed in the substrate 100 of the isolation region, and then an isolation pattern 104 may be formed in the trench 102.

[0051] In some embodiments, the isolation pattern 104 may be formed in a resistor region for forming a resistor structure. For example, the resistor structure may be formed on the isolation pattern 104. The isolation pattern 104 may include an insulating material, such as silicon oxide. In some embodiments, the isolation pattern 104 may have a flat upper surface.

[0052] In some embodiments, a lower structure and an interlayer insulating layer covering the lower structure may be provided, and a resistor structure may be formed on the interlayer insulating layer. In this case, the same process as described later may be performed on the interlayer insulating layer to form the resistor structure.

[0053] A lower layer may be formed on the substrate 100 and the isolation pattern 104 , and then the lower layer may be patterned to form a lower pattern 106 on the isolation pattern 104 in the resistor region.

[0054] The lower layer may include an insulating material, such as silicon nitride and / or silicon oxide. The lower layer may be formed of one layer or multiple layers. Therefore, the lower patterns 106 may each have a single pattern or a multi-layer stacked structure.

[0055] The lower patterns 106 may extend in the first direction, and may be spaced apart from each other in the second direction.

[0056] The lower pattern 106 may be provided to form a resistor line pattern (eg, Fig. 9 Therefore, the height, width, interval and sidewall slope of the lower pattern 106 may vary according to the desired shape of the resistor line pattern.

[0057] In some embodiments, each lower pattern 106 may have an inclined sidewall in the second direction. The inclined opposite sidewalls of each lower pattern 106 may be symmetrical to each other with respect to a vertical center line of each lower pattern 106 extending in the third direction.

[0058] The closer the inclination angle of the sidewall of each lower pattern 106 can be to 90 degrees, the longer the resistor line pattern can be (eg, Fig. 9 The resistor line pattern 116 of the lower pattern 106 can increase the resistance of the resistor structure. As an example, the inclination angle of the sidewall of each lower pattern 106 can be in the range of 30 degrees to 90 degrees (measured from the plane where the upper surface of the substrate 100 and / or the isolation pattern 104 is located), but is not limited thereto.

[0059] In some embodiments, the lower pattern 106 may also be formed in the contact region P included in the resistor region. In this case, referring to Figures 1 to 4 The described semiconductor device can be formed by the following process.

[0060] Reference Figure 7 and Figure 8 , a resistor layer 112 may be formed on the isolation pattern 104 , the lower pattern 106 , and the substrate 100 .

[0061] In the resistor region, the resistor layer 112 may be conformally formed along the surfaces of the isolation pattern 104 and the lower pattern 106. Therefore, the upper and lower surfaces of some portions of the resistor layer 112 located on the lower pattern 106 may have a shape protruding in the third direction (i.e., further separated from the substrate 100 and / or the isolation pattern 104), and the upper and lower surfaces of other portions of the resistor layer 112 located between the lower patterns 106 on the isolation pattern 104 may have a relatively concave shape (i.e., in contact with the substrate 100 and / or the isolation pattern 104 or less separated from the substrate 100 and / or the isolation pattern 104). Therefore, the upper surface (and / or lower surface) of the resistor layer 112 may be uneven.

[0062] In some embodiments, the resistor layer 112 may include a material configured to obtain a desired resistance, such as a metal, a metal silicide, a metal nitride, or a semiconductor material. The resistor layer 112 may be formed of one layer or multiple layers. For example, the resistor layer 112 may be formed by stacking a polysilicon layer 108 and a tungsten silicide layer 110.

[0063] Fig. 9 and Fig.10An example of a mask pattern 114 that may be formed on the resistor layer 112 is shown. The resistor layer 112 may be patterned using the mask pattern 114 as an etching mask to form a resistor line pattern 116 extending along the second direction. A portion of the resistor layer 112 located on the active region of the substrate 100 and adjacent to the resistor region may be patterned to form a guard ring 118 surrounding the resistor region. Thus, the resistor line pattern 116 and the guard ring 118 may include the same material and / or may have the same stacked structure.

[0064] In some embodiments, the resistor line pattern 116 and the guard ring 118 may have a stack structure of the polysilicon pattern 108 a and the tungsten silicide pattern 110 a .

[0065] In the resistor region, a plurality of resistor line patterns 116 may be formed. The plurality of resistor line patterns 116 may be spaced apart from each other in the first direction. Therefore, the resistor line patterns 116 may be arranged in a manner of alternately arranging lines and spaces.

[0066] Each resistor line pattern 116 may include: a first portion 'a', whose upper and lower surfaces extending in the second direction have a relatively low height with reference to the upper surface of the substrate 100; a third portion 'c', whose upper and lower surfaces extending in the second direction have a relatively high height with reference to the upper surface of the substrate 100; and a second portion 'b', which connects the first portion 'a' and the third portion 'c', is located between the first portion 'a' and the third portion 'c', and whose upper and lower surfaces are inclined.

[0067] In some embodiments, Figure 1 As shown, the ends of adjacent resistor line patterns 116 may be merged near the contact region P to form a merged resistor line having an increased width in the first direction (eg, Figure 1 In some embodiments, the merged resistor line may be omitted, and the resistor line pattern 116 may extend to a region close to a boundary of the resistor region.

[0068] Reference Fig.11 and Fig.12 , an interlayer insulating layer 120 may be formed to cover the resistor line pattern 116 , the lower pattern 106 , the isolation pattern 104 , and the guard ring (eg, Figure 1 and Figure 3 The contact plug 124 may penetrate the interlayer insulating layer 120 and the mask pattern 114 to be electrically connected to the resistor line pattern 116.

[0069] The interlayer insulating layer 120 may be formed by depositing a silicon oxide layer and then planarizing an upper surface of the silicon oxide layer. The planarization may be performed by a chemical mechanical polishing process and / or an etch-back process.

[0070] To form the contact plug 124, a portion of the interlayer insulating layer 120 may be etched to form a contact hole. In some embodiments, a lower portion of the contact hole may expose a second portion (eg, Figure 2 The second portion B) of the inclined upper surface or the second portion of the resistor line pattern 116 (eg, Fig. 9 In the case where the inclination angle of the upper surface of the second portion of the merged resistor line 116a (or the resistor line pattern 116) is 90 degrees, it may be difficult to form a contact hole exposing the second portion of the merged resistor line 116a (or the resistor line pattern 116). Therefore, the inclination angle of the upper surface of the second portion of the merged resistor line 116a (or the resistor line pattern 116) may be less than 90 degrees, for example, in the range of 30 to 80 degrees.

[0071] The contact plug 124 may include a metal. For example, the contact plug 124 may include a barrier metal pattern and a metal pattern.

[0072] Since the lower surface of the contact plug 124 may contact the inclined upper surface of the resistor line pattern 116 (or the merged resistor line 116a), the contact area between the lower surface of the contact plug 124 and the underlying layer may increase. Therefore, the contact resistance of the contact plug 124 may be reduced.

[0073] In some embodiments, the resistor structure of the semiconductor device may have various structures depending on the shape of the lower pattern. Hereinafter, a resistor structure (which may vary according to the shape of the lower pattern) will be described.

[0074] Fig.13 is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0075] In addition to the contact area, Fig.13 The semiconductor device shown can be compared with the reference Figures 1 to 4 The semiconductor devices described are the same.

[0076] Reference Fig.13 , the lower pattern 106 may not be disposed in the contact region P. The merged resistor line 116 b may be formed on the flat upper surface of the isolation pattern 104 within the contact region P. The upper and lower surfaces of the merged resistor line 116 b may be flat (i.e., having no uneven portion due to being disposed above the lower pattern 106). The contact plug 124 may contact the upper surface of the flat merged resistor line 116 b.

[0077] Fig.13 The resistor structure shown can be compared with the reference Figures 5 to 12 However, when performing the same process as described in Figure 5 and Figure 6 During the described process, a lower pattern may not be formed in the contact region P in the resistor region. Therefore, the merged resistor line 116 b having a flat lower surface and a flat upper surface may be formed, and the contact plug 124 having a flat lower surface may be formed.

[0078] Fig.14 is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0079] In addition to the shape of the lower pattern (and therefore the shape of the resistor line pattern), Fig.14 The semiconductor device shown can be compared with the reference Figures 1 to 4 The semiconductor devices described are the same.

[0080] Reference Fig.14 , the first lower pattern 106a may be disposed in the resistor region but not in the contact region P, and the second lower pattern 106b may be disposed in the contact region P. The first lower pattern 106a and the second lower pattern 106b may include the same material. However, the first lower pattern 106a and the second lower pattern 106b may have different shapes (and may also have different intervals from each other).

[0081] For example, the sidewall of each first lower pattern 106a in the second direction may have a first slope, and the sidewall of each second lower pattern 106b may have a second slope that is gentler than the first slope (i.e., having a smaller angle measured relative to the plane of the upper surface of the substrate 100 and / or the isolation pattern 104).

[0082] The resistor line pattern 116 located on the first lower pattern 106a may have a protruding portion. The protruding portion may have a first slope substantially the same as a sidewall of the first lower pattern 106a.

[0083] In some embodiments, the combined resistor line 116c may be disposed on the second lower pattern 106b. The combined resistor line 116c may further include a protruding portion. The protruding portion may have a second slope substantially the same as the sidewall of the second lower pattern 106b. In other words, the protruding portion of the combined resistor line 116c may have a more gentle slope than the slope of the resistor line pattern 116.

[0084] In some embodiments, the merged resistor line 116 c may not be disposed on the second lower pattern 106 b, and the resistor line pattern 116 may extend to the contact region P. In this case, the protruding portion of the resistor line pattern 116 in the contact region P may have a relatively gentle slope (compared to the slope of the same resistor line pattern 116 outside the contact region P).

[0085] In this way, the slope of the protruding portion of the resistor line pattern 116 in the contact region P or the slope of the protruding portion of the merged resistor line 116 c may be different from the slope of the protruding portion of the resistor line pattern 116 in the resistor region outside the contact region P.

[0086] In some embodiments, a distance between the first lower patterns 106 a may be different from a distance between the second lower patterns 106 b .

[0087] The interlayer insulating layer 120 may be disposed to cover the mask pattern 114, the first lower pattern 106a, the second lower pattern 106b, the isolation pattern 104, the resistor line pattern 116, the merged resistor line 116c, and the guard ring (eg, Figure 3 The contact plug 124 may be disposed to penetrate the interlayer insulating layer 120 and the mask pattern 114 and contact the inclined surface of the merged resistor line 116c.

[0088] Since the first lower pattern 106a has the first slope, the length of the upper surface of the resistor line pattern 116 in the second direction can be increased. In addition, since the second lower pattern 106b has a second slope that is gentler than the first slope, the contact plug 124 can be more easily formed on the inclined upper surface of the merged resistor line 116c.

[0089] Fig.15 is a cross-sectional view showing a method of forming a resistor structure of a semiconductor device according to an example embodiment. Specifically, Fig.15 The illustrated method may include forming first and second lower patterns 106 a and 106 b having different shapes (and, in some cases, different pitches).

[0090] Reference Fig.15 , an isolation process may be performed on the substrate 100 to define an isolation region and an active region. A trench may be formed in the substrate 100 in the isolation region, and then an isolation pattern 104 may be formed in the trench. The isolation process may be similar to the reference Figure 5 and Figure 6 Same as described.

[0091] A lower layer may be formed on the substrate 100. The lower layer may be patterned to form a first lower pattern 106a and a second lower pattern 106b in the resistor region of the substrate 100. For example, the second lower pattern 106b may be formed in the contact region P of the resistor region, and the first lower pattern 106a may be formed in the resistor region outside the contact region.

[0092] In some embodiments, a portion of the lower layer in the resistor region may be etched to form a preliminary lower pattern (not shown), and then a sidewall of the preliminary lower pattern in the contact region P may be further etched to form first and second lower patterns 106a and 106b.

[0093] After that, you can execute and refer to Figures 7 to 12 The same process as described, thus forming Fig.14 The resistor structure of the semiconductor device shown.

[0094] Fig.16 is a cross-sectional view illustrating a resistor structure of a semiconductor device according to example embodiments.

[0095] Reference Fig.16 , a semiconductor device may be formed on a substrate 200 including a first region C and a second region PCR. The first region C may be a cell region, and the second region PCR may be a peripheral circuit region PCR. The second region PCR may include a high voltage transistor region HV, a low voltage transistor region LV, and a resistor region R.

[0096] A cell pattern 226 a constituting a portion of a memory cell may be disposed in the cell region C. As shown in FIG.

[0097] The first gate insulating layer 202 and the first gate structure 240 located on the first gate insulating layer 202 may be disposed in the high voltage transistor region HV. The first gate structure 240 may have a stacked structure of a first gate pattern and a mask pattern 236a. The second gate insulating layer 204 and the second gate structure 242 located on the second gate insulating layer 204 may be disposed in the low voltage transistor region LV. The second gate structure 242 may have a stacked structure of a second gate pattern and a mask pattern 236a.

[0098] The lower pattern 226b and the resistor line pattern 244 may be disposed in the resistor region R. The mask pattern 236a may be disposed on each resistor line pattern 244. The resistor line pattern 244 may be disposed on the substrate 200 and the lower pattern 226b, and the upper and lower surfaces of the resistor line pattern 244 may be uneven (i.e., the wavy shape described herein). The interlayer insulating layer 250 may be disposed to cover the mask pattern 236a, the lower pattern 226b, the cell pattern 226a, and the first and second gate structures 240 and 242. The contact plug 252 may be disposed to penetrate the interlayer insulating layer 250 and the mask pattern 236a and be electrically connected to the resistor line pattern 244.

[0099] An isolation trench 212 may be provided in the substrate 200. An isolation pattern 214 may be provided in the isolation trench 212. The substrate 200 may be divided into an isolation region and an active region by the isolation pattern 214. In each of the first region C and the second region PCR, the isolation pattern 214 may be formed in the isolation region. An upper portion of the substrate 200 where the isolation pattern 214 is not formed may be provided as an active region.

[0100] In some embodiments, upper surfaces of the first region C and the active region in the high voltage transistor region HV may be lower than an upper surface of the active region in the low voltage transistor region LV.

[0101] In some embodiments, the first gate structure 240 and the second gate structure 242 may be formed on the active region in the second region PCR. The resistor region R may include an isolation pattern 214 .

[0102] In some embodiments, the lower pattern 226b and the resistor line pattern 244 in the resistor region R may be the same as the reference pattern 226b. Figures 1 to 4 The lower pattern and the resistor line pattern described above are the same or similar. In some embodiments, the lower pattern 226b and each resistor line pattern 244 in the resistor region R may be the same as described in reference Fig.13 The lower pattern and the resistor line pattern described above are the same or similar. In some embodiments, the lower pattern 226b and each resistor line pattern 244 in the resistor region R may be the same as described in reference Fig.14 The lower pattern described is the same or similar to the resistor line pattern.

[0103] The lower pattern 226b may be disposed in the resistor region R. The lower patterns 226b may extend in the first direction and may be spaced apart from each other in the second direction. The lower pattern 226b may include the same material as the insulating layer or insulating pattern included in the unit pattern 226a. In some embodiments, the lower pattern 226b may have the same stacked structure as the unit pattern 226a.

[0104] In some embodiments, the lower pattern 226b may include an insulating material, such as silicon nitride and / or silicon oxide. Each lower pattern 226b may have a single-layer structure or a multi-layer stacked structure. For example, each lower pattern 226b may include a lower oxide pattern 220a, a nitride pattern 222a, and an upper oxide pattern 224a.

[0105] The resistor line pattern 244 may be disposed on the isolation pattern 214 and the lower pattern 226b in the resistor region R. The resistor line pattern 244 may extend in the second direction and may be spaced apart from each other in the first direction. In each resistor line pattern 244, a portion on the lower pattern 226b may protrude in the third direction (i.e., relative to the substrate 200), while another portion (i.e., a portion disposed on the isolation pattern 214 and located between the lower patterns 226b) may have a relatively low upper surface and lower surface.

[0106] The resistor line pattern 244 may include a material forming a resistor structure having a desired resistance, such as a metal, a metal silicide, a metal nitride, or a semiconductor material. Each resistor line pattern 244 may have a stacked structure of a lower resistor pattern and an upper resistor pattern. For example, each resistor line pattern 244 may have a structure in which a polysilicon pattern 230a and a tungsten silicide pattern 232a are stacked.

[0107] The width of the first gate structure 240 may be greater than the width of the second gate structure 242 .

[0108] The thickness of the first gate insulating layer 202 may be greater than the thickness of the second gate insulating layer 204. The first gate pattern and the second gate pattern may have the same stacked structure. In some embodiments, the first gate pattern and the second gate pattern may include the same material as the material included in the resistor line pattern 244. As an example, the first gate pattern and the second gate pattern may have a structure in which the material pattern included in each resistor line pattern 244 may be stacked on the lower polysilicon pattern 208a. Therefore, when each resistor line pattern 244 has a stacked structure including a polysilicon pattern 230a and a tungsten silicide pattern 232a, the first gate pattern and the second gate pattern may each have a stacked structure of the lower polysilicon pattern 208a, the polysilicon pattern 230a, and the tungsten silicide pattern 232a.

[0109] The mask pattern 236 a included in the first gate structure 240 and the second gate structure 242 may include the same material as the mask pattern 236 a located on the resistor line pattern 244 .

[0110] In the second region PCR, the same structure as the lower pattern 226 b may not be provided in the remaining regions except the resistor region R. For example, the same structure as the lower pattern 226 b may not be provided in the high voltage transistor region HV and the low voltage transistor region LV.

[0111] The semiconductor device may include a memory device, such as a vertical NAND flash memory device, a planar flash memory device, a DRAM device, or an SRAM device. Depending on the type, structure, or configuration of the semiconductor device, the stacking structure of the cell pattern 226a in the first region C (i.e., the cell region) may be changed. Therefore, the stacking structure of each lower pattern 226b may be changed.

[0112] Figures 17 to 25 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0113] Reference Fig.17 , portions of the substrate 200 corresponding to the first region C and the high voltage transistor region HV may be etched so that an upper surface of the substrate 200 of the first region C and the high voltage transistor region HV may be lower than an upper surface of the substrate 200 of the low voltage transistor LV and the resistor region R.

[0114] The insulating layer may be formed on the substrate 200 with different thicknesses in different regions (e.g., in the high voltage transistor region HV and the low voltage transistor region LV). For example, a first gate insulating layer 202 having a first thickness may be formed in the high voltage transistor region HV. A second gate insulating layer 204, which may be thinner than the first gate insulating layer 202, may be formed in the low voltage transistor region LV and the resistor region R. A third insulating layer 206, which may also be thinner than the first gate insulating layer 202, may be formed in the first region C.

[0115] The first gate insulating layer 202 in the high voltage transistor region HV and the second gate insulating layer 204 in the low voltage transistor region LV may be provided as gate insulating layers of transistors through the following process.

[0116] The stacked structure may be formed on an insulating layer (i.e., a first gate insulating layer 202, a second gate insulating layer 204, and a third insulating layer 206) where the first polysilicon pattern 208 and the capping pattern 210 are stacked. The capping pattern 210 may include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first polysilicon pattern 208 and the capping pattern 210 may be used as a mask pattern for forming an isolation trench. Therefore, the first polysilicon pattern 208 and the capping pattern 210 may be formed to cover the active area. Because the resistor region R corresponds to the isolation region, the first polysilicon pattern 208 and the capping pattern 210 may not be formed in the resistor region R. In some embodiments, the first polysilicon pattern 208 may be set as a portion of the gate of each of the high voltage transistor and the low voltage transistor.

[0117] Reference Fig.18 , the insulating layer (i.e., the first gate insulating layer 202 and the second gate insulating layer 204) and the substrate 200 may be etched using the stack structure of the first polysilicon pattern 208 and the capping pattern 210 as an etching mask, so that an isolation trench 212 may be formed. The isolation trench 212 may be formed in the resistor region R. During the etching process, the capping pattern 210 may be partially etched.

[0118] Reference Fig.19 An insulating layer may be formed on the capping pattern 210 to fill the isolation trench 212 , and then the insulating layer may be planarized until the first polysilicon pattern 208 is exposed, so that an isolation pattern 214 may be formed in the isolation trench 212 .

[0119] The planarization process may include a chemical mechanical polishing process. After the planarization process is performed, the upper surface of the isolation pattern 214 may be substantially coplanar with the upper surface of the exposed first polysilicon pattern 208 .

[0120] The capping pattern 210 in the second region PCR may be removed in the planarization process. In some embodiments, the capping pattern 210 and the insulating pattern 214a may remain on the substrate 200 in the first region C because the upper surface of the substrate 200 in the first region C is relatively low.

[0121] Reference Fig. 20 A cell pattern insulating layer 226 may be formed on the isolation pattern 214, the first polysilicon pattern 208, the capping pattern 210, and the insulating pattern 214a. The cell pattern insulating layer 226 may cover the entire upper surface of the resultant structure formed in the first region C and the second region PCR.

[0122] The cell pattern insulating layer 226 may be an insulating layer for forming cells in the first region C. Therefore, the cell pattern insulating layer 226 may be changed according to a desired structure of a cell pattern. The cell pattern insulating layer 226 may include an oxide layer and / or a nitride layer.

[0123] In some embodiments, the unit pattern insulating layer 226 may have a stacked structure of a lower oxide layer 220, a nitride layer 222, and an upper oxide layer 224. The lower oxide layer 220 may be provided as a pad oxide layer between the nitride layer 222 and the layer below. The nitride layer 222 may be used as an etch stop layer, a sacrificial layer, or a hard mask layer. The upper oxide layer 224 may be used as an interlayer insulating layer or a buffer layer for covering the nitride layer 222.

[0124] Reference Fig.21 , a first etching mask 228 may be formed on the cell pattern insulating layer 226, and then the cell pattern insulating layer 226 may be patterned using the first etching mask 228. Thus, a cell pattern 226a may be formed in the first region C, and a lower pattern 226b may be formed in the resistor region R. The first etching mask 228 may include a photoresist pattern.

[0125] In some embodiments, in order to leave the unit pattern insulating layer 226 in the first region C, the first etching mask 228 may cover the entire first region C. However, the unit pattern insulating layer 226 may not be formed in the second region PCR outside the resistor region R. That is, the first etching mask 228 may expose the entire second region PCR except the resistor region R. For example, since the high voltage transistor and the low voltage transistor may not include the unit pattern insulating layer 226, the first etching mask 228 may expose the high voltage transistor region HV and the low voltage transistor region LV. In addition, in order to form the lower pattern 226b in the resistor region R, the first etching mask 228 may have a structure of a plurality of lines extending in the first direction and spaced apart from each other in the second direction.

[0126] When the cell pattern insulating layer 226 is patterned using the first etching mask 228, the cell pattern insulating layer 226 may be completely removed in the second region PCR except the resistor region R. Therefore, the upper surfaces of the isolation pattern 214 and the first polysilicon pattern 208 may be exposed in the high voltage transistor region HV and the low voltage transistor region LV. At this time, a portion of the upper surface of the isolation pattern 214 may be removed.

[0127] However, the lower pattern 226b extending in the first direction may be formed in the resistor region R. The lower patterns 226b may be arranged to be spaced apart from each other in the second direction. In this way, the lower pattern 226b may be formed in a single process together with the unit pattern 226a (ie, without performing a separate etching process for each pattern).

[0128] The shape of the lower pattern 226b may be similar to that of the reference Figures 1 to 4 In some embodiments, the shape of the lower pattern 226b may be the same as that of the lower pattern 226b described in the reference Fig.13 In some embodiments, the shape of the lower pattern 226b may be the same as that of the lower pattern 226b described in the reference Fig.14 The shape of the lower pattern described is the same.

[0129] After performing an etching process, which may be a single process to form the lower pattern 226 b and the unit pattern 226 a together using the first etching mask 228 , the first etching mask 228 may be removed.

[0130] Reference Fig. 22 , a resistor layer 234 may be conformally formed on the lower pattern 226b, the isolation pattern 214, and the cell pattern 226a. The resistor layer 234 may cover the entire upper surface of the resulting structure in the first region C and the second region PCR.

[0131] A portion of the resistor layer 234 located on the lower pattern 226b may have upper and lower surfaces protruding along the third direction, and another portion of the resistor layer 234 located between the lower patterns 226b may have relatively low upper and lower surfaces (i.e., lower than the corresponding surfaces of the protruding portion).

[0132] In some embodiments, the resistor layer 234 may include a material for forming a desired resistor structure, such as a metal, a metal silicide, a metal nitride, or a semiconductor material. For example, the resistor layer 234 may be formed by stacking a polysilicon layer 230 and a tungsten silicide layer 232 .

[0133] Reference Fig.23 , a mask layer 236 may be formed to cover the resistor layer 234. A second etch mask 238 may be formed on the mask layer 236. The second etch mask 238 may be provided to form a resistor line pattern and the first and second gate structures.

[0134] In some embodiments, the mask layer 236 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The second etch mask 238 may include a photoresist.

[0135] The second etching mask 238 may expose the mask layer 236 in the first region C. The second etching mask 238 may cover a portion of the resulting structure in each of the high voltage transistor region HV and the low voltage transistor region LV. The second etching mask 238 in the resistor region R may have a structure of a plurality of lines extending in the second direction and spaced apart from each other in the first direction.

[0136] Reference Fig.24 The mask layer 236 may be etched using the second etch mask 238 to form a mask pattern 236a. The resistor layer 234 and the first polysilicon pattern 208 may be etched using the mask pattern 236a as an etch mask.

[0137] Through the above-described etching process, the resistor layer 234 in the first region C may be removed, and thus the unit pattern 226 a may be exposed.

[0138] The first polysilicon pattern 208 and the resistor layer 234 in the high voltage transistor region HV may be patterned to form a first gate structure 240, in which a lower polysilicon pattern 208a, a resistor layer pattern, and a mask pattern 236a are stacked on the first gate insulating layer 202. For example, in the case where the resistor layer 234 includes a polysilicon layer and a tungsten silicide layer, the first gate structure 240 may have a structure in which the lower polysilicon pattern 208a, the polysilicon pattern 230a, the tungsten silicide pattern 232a, and the mask pattern 236a are stacked.

[0139] The first polysilicon pattern 208 and the resistor layer 234 in the low voltage transistor region LV may be patterned to form a second gate structure 242, wherein the lower polysilicon pattern 208a, the resistor layer pattern, and the mask pattern 236a are stacked on the second gate insulating layer 204. In some embodiments, the first gate structure 240 and the second gate structure 242 may include the same material as the resistor line pattern 244.

[0140] In the resistor region R, a resistor line pattern 244 extending along the second direction may be formed. In some embodiments, the guard ring (which may be Figure 1 and Figure 3 A guard ring 118 (same or similar to that shown) may be formed on the active area of ​​the contact resistor region R.

[0141] The shape of the resistor line pattern 244 may be similar to that of the reference Figures 1 to 4 In some embodiments, the shape of the resistor line pattern 244 may be the same as that of the reference Fig.13 In some embodiments, the shape of the resistor line pattern 244 may be the same as that of the reference Fig.14 The mask pattern 236 a may be disposed on the resistor line pattern 244 .

[0142] Reference Fig.25 , an interlayer insulating layer 250 may be formed to cover the cell pattern 226 a , the first gate structure 240 , the second gate structure 242 , the isolation pattern 214 , the mask pattern 236 a , the lower pattern 226 b , and the guard ring.

[0143] The interlayer insulating layer 250 may be formed by depositing silicon oxide to form a silicon oxide layer and then planarizing the silicon oxide layer. The planarization process may include a chemical mechanical polishing process and / or an etch-back process.

[0144] A portion of the interlayer insulating layer 250 and a portion of the mask pattern 236a may be etched to form a contact hole exposing the upper surface of the resistor line pattern 244, and then a conductive material layer may be formed in the contact hole to form a contact plug 252. The contact plug 252 may include a metal. For example, the contact plug 252 may include a barrier metal pattern and a metal pattern.

[0145] In some embodiments, the contact plug 252 may contact the inclined upper surface of the resistor line pattern 244 (eg, it may contact a second portion of the resistor line pattern 244 having a shape similar to that of the resistor line pattern 244). Figure 2 The shape of the second portion B of the merged resistor line 116a is shown to be the same).

[0146] In some embodiments, the contact plug 252 may contact the flat upper surface of the resistor line pattern 244 (eg, it may contact the first portion or the third portion of the resistor line pattern 244 having a shape similar to that of the resistor line pattern 244). Figure 2 The shapes of the first portion A or the third portion C of the merged resistor line 116a are shown to be the same).

[0147] In some embodiments, the lower pattern 226 b may not be formed in the contact region P. In this case, the resistor line pattern 244 in the contact region P may have a flat upper surface, and the contact plug 252 may be formed on the flat upper surface of the resistor line pattern 244 .

[0148] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a substrate including a resistor region; a plurality of lower patterns, the plurality of lower patterns extending in a first direction parallel to a surface of the substrate and spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate; and a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region, wherein the resistor line pattern extends in the second direction and the resistor line pattern located on the lower patterns has a raised portion in a third direction perpendicular to the surface of the substrate to form a wavy shape, The plurality of lower patterns include an insulating material, and a lower surface of the elevated portion of the resistor line pattern contacts the insulating material of the plurality of lower patterns.

2. The semiconductor device according to claim 1, wherein The resistor region includes an isolation pattern in the substrate or an interlayer insulating layer on the substrate.

3. The semiconductor device according to claim 1, wherein Each of the plurality of lower patterns has a flat upper surface and a sidewall inclined in the second direction.

4. The semiconductor device according to claim 1, wherein: The resistor line pattern includes a plurality of resistor line patterns, Wherein, the plurality of resistor line patterns are spaced apart from each other in the first direction.

5. The semiconductor device according to claim 4, wherein: Ends of adjacent resistor line patterns among the plurality of resistor line patterns are merged into a merged portion, the merged portion having an increased width in the first direction.

6. The semiconductor device according to claim 1, wherein The resistor line pattern includes a first portion, a third portion, and a second portion connecting the first portion and the third portion, wherein the upper surface and the lower surface of the first portion have a high height with reference to the surface of the substrate, the upper surface and the lower surface of the third portion have a low height with reference to the surface of the substrate, and the second portion has an inclined upper surface and a lower surface.

7. The semiconductor device according to claim 6, further comprising: An interlayer insulating layer is located on the resistor line pattern.

8. The semiconductor device according to claim 7, further comprising: A contact plug penetrates the interlayer insulating layer to contact the resistor line pattern.

9. The semiconductor device according to claim 1, wherein: The substrate further includes a unit region, The semiconductor device further includes a unit pattern located in the unit region, and the unit pattern has the same stacking structure and the same material as each of the plurality of lower patterns.

10. The semiconductor device according to claim 1, wherein The plurality of lower patterns have the same shape or different shapes depending on positions in the resistor region.

11. The semiconductor device according to claim 1, wherein The plurality of lower patterns are disposed in a portion of the resistor region.

12. A semiconductor device, comprising: a substrate comprising a cell region and a resistor region; a plurality of lower patterns, the plurality of lower patterns being located in the resistor region, wherein the plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate; a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region, wherein the resistor line pattern extends in the second direction, and the resistor line pattern located on the lower patterns has an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate; and a unit pattern, the unit pattern being located in the unit region, wherein the unit pattern comprises the same material and the same stacking structure as each of the plurality of lower patterns, The plurality of lower patterns include an insulating material, and the lower surface of the resistor line pattern contacts the insulating material of the plurality of lower patterns.

13. The semiconductor device according to claim 12, wherein: Each of the plurality of lower patterns has a flat upper surface and a sidewall inclined in the second direction.

14. The semiconductor device according to claim 12, further comprising: an interlayer insulating layer, the interlayer insulating layer being located on the resistor line pattern; as well as A contact plug penetrates the interlayer insulating layer to contact the upper surface of the resistor line pattern.

15. The semiconductor device according to claim 14, wherein: The resistor line pattern on the sidewall of each of the plurality of lower patterns has an inclined upper surface, wherein the contact plug contacts the inclined upper surface of the resistor line pattern.

16. A semiconductor device, comprising: A substrate, the substrate comprising a cell region, a transistor region and a resistor region; a plurality of lower patterns, the plurality of lower patterns being located in the resistor region, wherein the plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate; a resistor line pattern located on the plurality of lower patterns and on the substrate in the resistor region, wherein the resistor line pattern extends in the second direction, and the resistor line pattern located on the lower patterns has an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate; a unit pattern located in the unit region, wherein the unit pattern includes the same material and the same structure as each of the plurality of lower patterns; and a gate structure, the gate structure being located in the transistor region, The plurality of lower patterns include an insulating material, and the lower surface of the resistor line pattern contacts the insulating material of the plurality of lower patterns.

17. The semiconductor device according to claim 16, wherein: The gate structure includes the same material as a material included in the resistor line pattern.

18. The semiconductor device according to claim 16, further comprising: Interlayer insulation layer; as well as A contact plug penetrates the interlayer insulating layer to contact the upper surface of the resistor line pattern.

19. The semiconductor device according to claim 18, wherein: The resistor line pattern on the sidewall of each of the plurality of lower patterns has an inclined upper surface, wherein the contact plug contacts the inclined upper surface of the resistor line pattern.

20. A semiconductor device, comprising: a substrate including a resistor structure in a resistor region; a plurality of lower patterns located in the resistor region, wherein the plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate, wherein each of the plurality of lower patterns includes inclined sidewalls opposite to each other in the second direction; and a plurality of resistor line patterns forming the resistor structure, wherein each of the resistor line patterns extends in the second direction and includes a plurality of high portions disposed on the plurality of lower patterns and a plurality of low portions disposed between the plurality of lower patterns, wherein the high portion and the low portion of each of the resistor line patterns are connected to form a wavy shape configured to increase the resistance of the resistor structure, The plurality of lower patterns include an insulating material, and a lower surface of the high portion of each resistor line pattern contacts the insulating material of a corresponding lower pattern among the plurality of lower patterns.

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