Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. According to an example embodiment, the semiconductor device includes: a substrate having an active region; a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, the gate electrode layer having a rounded upper corner; and a gate spacer layer on a side surface of the gate structure, the upper surface of the gate spacer layer being at a height lower than the upper surface of the gate electrode layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0094973, entitled “Semiconductor Device and Method of Manufacturing the Same,” filed on August 14, 2018 in the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As the demand for high performance, high speed, multifunctionality, etc. of semiconductor devices increases, the integration of semiconductor devices also increases. Therefore, when manufacturing semiconductor devices, it is necessary to realize a pattern with a fine width or fine pitch corresponding to the high integration of semiconductor devices. In addition, in order to overcome the limitations of the operating characteristics of planar metal oxide semiconductor field effect transistors (MOSFETs) due to their reduced size, efforts are being made to develop semiconductor devices including FinFETs having a three-dimensional structure channel. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor device may include: a substrate having an active region; a gate structure disposed on the active region and including a gate dielectric layer and a gate electrode layer; and a gate spacer disposed on both side surfaces of the gate structure, the upper surface of which is located at a height lower than the height of the upper surface of the gate electrode layer. The gate electrode layer has a shape with rounded upper corners.

[0006] According to one aspect of the present disclosure, a semiconductor device may include: a substrate having an active region and having a first region and a second region; a first gate electrode layer disposed on the first region, extending in a first direction and having a first length in a second direction perpendicular to the first direction; and a second gate electrode layer disposed on the second region, extending in the first direction and having a second length greater than the first length in the second direction. The first gate electrode layer and the second gate electrode layer have a first thickness in an edge region in the second direction, and have a second thickness greater than the first thickness in a region inward of the edge region.

[0007] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device may include: forming a gate electrode layer and a gate spacer layer facing the sidewalls of the gate electrode layer on a substrate having an active area, partially removing the gate spacer layer from the upper surface to expose a portion of the side surface of the gate electrode layer, partially removing the gate electrode layer from the upper surface and the side surface exposed by the gate spacer layer, and forming a gate cap layer covering the upper surfaces of the gate spacer layer and the gate electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a plan view of a semiconductor device according to an example embodiment;

[0010] Figure 2A and Figure 2B shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0011] Figure 3 A partially exploded perspective view showing a portion of a semiconductor device according to an example embodiment;

[0012] Figure 4A and Figure 4B shows a partial enlarged view of a portion of a semiconductor device according to an example embodiment;

[0013] Figure 5 and Figure 6 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0014] Figure 7 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 8 A flowchart showing a method of manufacturing a semiconductor device according to an example embodiment is shown;

[0016] FIG. 9A to FIG. 9J cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an example embodiment;

[0017] Fig.10 A block diagram showing an electronic device including a semiconductor device according to example embodiments; and

[0018] Fig.11 A schematic diagram of a system including a semiconductor device according to example embodiments is shown. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0020] Figure 1 is a plan view of a semiconductor device according to an example embodiment. For ease of explanation, Figure 1 Only the main components of the semiconductor device are shown.

[0021] Figure 2A and Figure 2B is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 2A Shown along Figure 1The cross-sectional view of the lines I-I' and II-II' in FIG. Figure 2B Shown along Figure 1 Cross-sectional view along lines III-III' and IV-IV'.

[0022] refer to Figures 1 to 2B The semiconductor device 100 may include a substrate 101 having a first region R1 and a second region R2, an active fin 105, a first gate dielectric layer 112 and a second gate dielectric layer 114, a gate electrode layer 120, a gate spacer layer 130, a gate cap layer 140, a source / drain region 150, and a contact plug 160. The semiconductor device 100 may also include a device isolation layer 107 and a first interlayer insulating layer 192 and a second interlayer insulating layer 194.

[0023] The semiconductor device 100 may include a FinFET device, i.e., a transistor having an active fin 105 with a fin structure. The FinFET device may include a first transistor TR1 and a second transistor TR2, which are positioned based on the active fin 105 intersecting each other and the first and second gate structures GS1 and GS2. The first transistor TR1 and the second transistor TR2 may be n-type or p-type metal oxide semiconductor field effect transistors (MOSFETs). The first transistor TR1 and the second transistor TR2 may have different threshold voltages to have different operating voltages. For example, when the first transistor TR1 and the second transistor TR2 are transistors of the same conductivity type, the first transistor TR1 may have a threshold voltage and an operating voltage lower than the second transistor TR2. According to example embodiments, the magnitudes of the threshold voltage and the operating voltage may be compared using their absolute values. The first transistor TR1 and the second transistor TR2 may constitute the same or different circuits in the semiconductor device 100.

[0024] The substrate 101 may have different first and second regions R1 and R2, and the first and second regions R1 and R2 may be regions where the first and second transistors TR1 and TR2 are disposed, respectively. The first and second regions R1 and R2 may be disposed to be spaced apart from or adjacent to each other in the semiconductor device 100.

[0025] The substrate 101 may have an upper surface extending in the X and Y directions. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided in the form of a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0026] The device isolation layer 107 may define active fins 105 in the substrate 101, such as Figure 2BAs shown. The device isolation layer 107 may be formed, for example, by a shallow trench isolation (STI) process. According to example embodiments, the device isolation layer 107 may include a region extending into the lower portion of the substrate 101 between adjacent active fins 105, thereby being relatively deeper in the region. According to example embodiments, the device isolation layer 107 may also have a curved upper surface whose height in the height direction increases toward the active fin 105, and the form of the upper and lower surfaces of the device isolation layer 107 is not limited to the illustrations of the accompanying drawings. The device isolation layer 107 may be formed of an insulating material. The device isolation layer 107 may be formed of, for example, an oxide, a nitride, or a combination thereof.

[0027] The active fin 105 may be defined in the substrate 101 by the device isolation layer 107 and may be arranged to extend in one direction (eg, the X direction). The active fin 105 may have a linear or bar shape, for example, having a longitudinal direction extending in the X direction, and protruding from the substrate 101 to extend between the device isolation layers 107. Figure 1 It is shown that three active fins 105 are spaced apart from each other in the Y direction in each of the first region R1 and the second region R2, but the arrangement and number of the active fins 105 are not limited thereto. In addition, in example embodiments, the number of active fins 105 constituting each of the first transistor TR1 and the second transistor TR2 may be variously changed.

[0028] The active fin 105 may be formed of a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The active fin 105 may be partially recessed on both sides of the first gate structure GS1 and the second gate structure GS2 and the gate spacer layer 130, and the source / drain region 150 may be formed on the recessed active fin 105. Figure 2A As shown, the active fin 105 under the first gate structure GS1 and the second gate structure GS2 may have a relatively high height. In example embodiments, the active fin 105 may include impurities.

[0029] The first gate structure GS1 and the second gate structure GS2 may be arranged to extend in a certain direction (e.g., Y direction) on the active fin 105 while crossing the active fin 105. The first gate structure GS1 and the second gate structure GS2 may each include a first gate dielectric layer 112 and a second gate dielectric layer 114 and a gate electrode layer 120. The first gate structure GS1 and the second gate structure GS2 may have the same structure or may have different structures. For example, in the first gate structure GS1 and the second gate structure GS2, the first gate dielectric layer 112 and the second gate dielectric layer 114 may have different compositions and / or thicknesses, and the configurations of the gate electrode layer 120 may be different from each other.

[0030] The first gate dielectric layer 112 and the second gate dielectric layer 114 may be disposed between the active fin 105 and the gate electrode layer 120. Figure 2A As shown in , the first gate dielectric layer 112 may be disposed on the lower surface of the gate electrode layer 120, and the second gate dielectric layer 114 may be disposed to cover the lower surface and side surfaces of the gate electrode layer 120, for example, the first gate dielectric layer 112 may be only between the lower surface of the second gate dielectric layer 114 and the active fin 105. In another example, the second gate dielectric layer 114 may also be only disposed on the lower surface of the gate electrode layer 120.

[0031] On the side surface of the gate electrode layer 120, the upper end of the second gate dielectric layer 114 may be located at a height that is the same as or lower than the height of the upper surface of the gate electrode layer 120. The upper end of the second gate dielectric layer 114 may be closer to the upper surface of the gate spacer layer 130 than to the highest portion of the gate electrode layer 120 whose maximum height is in the central region thereof. The upper end of the second gate dielectric layer 114 may have a profile that is continuous with the upper surface of the gate electrode layer 120. For example, in a cross-sectional view, the upper surface of the second gate dielectric layer 114 may form a substantially continuous curve with the upper surface of the gate electrode layer 120 without an inflection point. At the upper end of the second gate dielectric layer 114, the height of the inner side surface of the second gate dielectric layer 114 in contact with the gate electrode layer 120 may be higher than the height of the outer side surface thereof in contact with the gate spacer layer 130.

[0032] The first gate dielectric layer 112 and the second gate dielectric layer 114 may include different materials. The first gate dielectric layer 112 may be formed of a dielectric material such as silicon oxide, silicon oxynitride, or a combination thereof. The second gate dielectric layer 114 may include a material having a dielectric constant higher than that of the first gate dielectric layer 112, and may include, for example, an oxide, a nitride, or a high-k material. However, example embodiments are not limited thereto. The high-k material may refer to a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material. The high-k material may be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl xO y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ). In example embodiments, the second gate dielectric layer 114 may further include an element for increasing the threshold voltage of the transistor, such as a rare earth element such as lanthanum (La), gadolinium (Gd), ruthenium (Ru), yttrium (Y), or scandium (Sc). These elements may increase the threshold voltage by forming, for example, an electric dipole.

[0033] The channel regions of the first transistor TR1 and the second transistor TR2 may be formed in the active fin 105 intersecting the gate electrode layer 120. The gate electrode layer 120 may have a first length L1 and a second length L2 in the channel direction (e.g., in the X direction) in the first region R1 and the second region R2, respectively. The first length L1 and the second length L2 may be equal to or correspond to the channel lengths of the first transistor TR1 and the second transistor TR2, respectively. The second length L2 may be greater than the first length L1. For example, the first length L1 may be in the range of about 3 nm to about 100 nm, and the second length L2 may be in the range of about 150 nm to about 1000 nm. The gate electrode layer 120 may have a first maximum height H1 and a second maximum height H2 along the Z direction in the first region R1 and the second region R2, respectively. The first maximum height H1 and the second maximum height H2 may be substantially equal to each other, but are not limited thereto.

[0034] The gate electrode layer 120 may have a rounded upper corner TC. Figure 2A As shown, the gate electrode layer 120 may have a shape in which the corners on both sides in the X direction are rounded, for example, the top corners of each gate electrode layer 120 may be spaced apart from each other in the X direction and may be rounded. Therefore, the gate electrode layer 120 may have a minimum thickness in the edge region in its extension direction (for example, in the Y direction). For example, the top corner TC of each gate electrode layer 120 may be rounded (for example, bent), for example, continuously along the entire length of the corresponding gate electrode layer 120 in the Y direction, so that the width at the top edge region of the corresponding gate electrode layer 120, for example, measured along the X direction, is reduced.

[0035] Since the gate electrode layer 120 has such a shape that the width in the X direction is reduced at the top edge region, the gate electrode layer 120 can ensure the separation distance L3 in the X direction. The separation distance L3 refers to the distance from the outer side surface of the gate electrode layer 120 adjacent to the contact plug 160 to the outer side surface of the adjacent contact plug 160 along the X direction. Therefore, even in the case where the contact plug 160 is misaligned and / or the height deviation of the gate electrode layer 120 occurs, the occurrence of an electrical short circuit between the gate electrode layer 120 and the contact plug 160 can be suppressed or even prevented.

[0036] The upper surface of the gate electrode layer 120 may have an upward convex shape as a whole. The upper surface of the gate electrode layer 120 may have different profiles in the first gate structure GS1 and the second gate structure GS2. However, in example embodiments, the gate electrode layer 120 may have various shapes within the range that the two upper corners TC are not sharp corners but their angles are reduced. Figure 3 The shape of the gate electrode layer 120 is described in more detail.

[0037] According to example embodiments, the gate electrode layer 120 may be formed of a single layer, or may have a form in which a plurality of layers are stacked. The gate electrode layer 120 may include, for example, TiN, TaN, W, WCN, TiAl, TiAlC, TiAlN, or a combination thereof, but is not necessarily formed of a metal material. In another example, according to example embodiments, the gate electrode layer 120 may be formed of a semiconductor material such as polysilicon.

[0038] The gate spacer layer 130 may be disposed on both sides of the first gate structure GS1 and the second gate structure GS2. The gate spacer layer 130 may isolate the source / drain region 150 from the gate electrode layer 120. In the case of the gate spacer layer 130, its inner side surface facing the first gate structure GS1 and the second gate structure GS2 may contact the second gate dielectric layer 114, and its outer side surface may contact the source / drain region 150 and the first interlayer insulating layer 192. The thickness (e.g., the height along the Z direction) of the gate spacer layer 130 may be less than the thickness of the gate electrode layer 120 relative to the bottom surface of the substrate 101. Therefore, the height of the upper surface of the gate spacer layer 130 may be equal to or lower than the height of the upper surface of the gate electrode layer 120, and may be lower than the height of the highest part of the gate electrode layer 120. The upper surface of the gate spacer layer 130 may have a convex shape. Therefore, the gate spacer layer 130 may have a minimum thickness in its central region in the X direction and may have a maximum thickness in its edge region.

[0039] According to example embodiments, the gate spacer layer 130 may also be formed of a plurality of layers. The gate spacer layer 130 may be formed of a low dielectric constant material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0040] The gate capping layer 140 may be provided to cover the upper surfaces of the gate electrode layer 120 and the gate spacer layer 130. Therefore, the profile of the lower surface of the gate capping layer 140 may be along the upper surfaces of the gate electrode layer 120 and the gate spacer layer 130. The lower surface of the gate capping layer 140 may have a recessed area in the center region in the X direction, and may have a downwardly protruding area in the edge region thereof. The upper surface of the gate capping layer 140 may be a flat surface, and the gate capping layer 140 may have a horseshoe shape as a whole, for example, surrounding the upper surface and side surfaces ( Figure 3 ). The side surface of the gate cap layer 140 in the X direction may be coplanar with the outer surface of the gate spacer layer 130. The gate cap layer 140 may be formed of, for example, silicon nitride, and in the case where the composition of the gate cap layer 140 is different from that of the gate spacer layer 130, the interface therebetween may be clearly identified. Alternatively, even in the case where the composition of the gate cap layer 140 is similar to that of the gate spacer layer 130, the gate cap layer 140 and the gate spacer layer 130 may be formed by different processes, and their physical properties may therefore be different, so that the interface therebetween may be distinct.

[0041] The source / drain region 150 may be disposed on the active fin 105 at both sides of each of the first gate structure GS1 and the second gate structure GS2, for example, having the corresponding gate spacer layer 130. The source / drain region 150 may serve as a source region or a drain region of the first transistor TR1 and the second transistor TR2. The source / drain region 150 may have an elevated source / drain structure, the upper surface of which is higher than the lower surface of the gate electrode layer 120, but is not limited thereto. The source / drain region 150 may be connected to each other or merged with each other on two or more active fins 105 to form a single source / drain region 150, but example embodiments are not limited thereto.

[0042] The source / drain region 150 may be formed of an epitaxial layer and may include impurities. For example, when the first transistor TR1 and the second transistor TR2 are p-type transistors, the source / drain region 150 may include p-type doped silicon germanium (SiGe). In another example, when the first transistor TR1 and the second transistor TR2 are n-type transistors, the source / drain region 150 may include n-type doped silicon (Si). In example embodiments, the source / drain region 150 may include a plurality of regions including different element concentrations and / or different doping elements.

[0043] The contact plug 160 may penetrate the first interlayer insulating layer 192 and the second interlayer insulating layer 194 to be connected to the source / drain region 150. The contact plug 160 may be electrically connected to other components (e.g., wiring) so that a signal may be applied to the source / drain region 150. The contact plug 160 may be formed to recess a portion of the source / drain region 150 to be connected to the source / drain region 150, but example embodiments are not limited thereto. The contact plug 160 may have an elongated shape extending in an extension direction of the first gate structure GS1 and the second gate structure GS2 (e.g., in the Y direction), and may have a shape such as a rectangle, an ellipse, or the like.

[0044] The contact plug 160 may include a plug conductive layer 165 and a diffusion barrier layer 162 disposed on the lower surface and the side surface of the plug conductive layer 165 in contact with the source / drain region 150. The diffusion barrier layer 162 may be a layer that is formed as a part of the material constituting the plug conductive layer 165 and is silicided by the source / drain region 150. The contact plug 160 may include a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), etc.

[0045] The first interlayer insulating layer 192 and the second interlayer insulating layer 194 may be provided to cover the upper surfaces of the device isolation layer 107, the source / drain region 150, and the gate capping layer 140. The height of the upper surface of the first interlayer insulating layer 192 may be substantially the same as the height of the upper surface of the gate capping layer 140. The first interlayer insulating layer 192 and the second interlayer insulating layer 194 may be layers distinguished from each other in the process, and the relative heights and the positions of the interfaces thereof are not limited to the examples shown in the drawings. In another exemplary embodiment, the first interlayer insulating layer 192 and the second interlayer insulating layer 194 may be formed of a single layer. The first interlayer insulating layer 192 and the second interlayer insulating layer 194 may include, for example, at least one of an oxide, a nitride, and an oxynitride, and may include a low dielectric constant material.

[0046] Figure 3 is a partially exploded perspective view illustrating a portion of a semiconductor device according to example embodiments.

[0047] refer to Figure 3 , showing Figures 1 to 2B The semiconductor device 100 includes a first gate structure GS1, a gate spacer layer 130, and a gate cap layer 140. The first gate structure GS1 may extend in one direction (eg, in the Y direction), and the gate spacer layer 130 and the gate cap layer 140 may also extend in the Y direction along the first gate structure GS1.

[0048] In the first gate structure GS1, the gate electrode layer 120 may have a shape in which two upper corners TC spaced apart from each other in the X direction are rounded. The gate electrode layer 120 may be formed such that its thickness (i.e., height in the Z direction) is greater than the thickness of the gate spacer layer 130 on both sides of the gate electrode layer 120, so that, for example, the center of the gate electrode layer 120 protrudes above the gate spacer layer 130 by a predetermined length D1. For example, as Figure 3 As shown in FIG. 1 , the highest point (eg, the center thereof) of the gate electrode layer 120 protrudes above the highest point of the gate spacer layer 130 by a length D1 .

[0049] Specifically, the gate electrode layer 120 may have a first height H1 (i.e., a maximum height along the Z direction) in a central region thereof, and may have a third height H3 (i.e., a minimum height along the Z direction) at an edge region in contact with the gate spacer layer 130. The gate electrode layer 120 may have an area with a flat upper surface in at least a portion including the central region, but example embodiments are not limited thereto. The first gate structure GS1 may extend a predetermined length D2 in the Y direction, and the extension length D2 may be variously changed according to example embodiments and the structure of the first transistor TR1.

[0050] The gate spacer layer 130 may be arranged to have a fourth height H4 (i.e., a maximum height) on both sides of the first gate structure GS1. The fourth height H4 may be less than the first height H1 (i.e., a maximum height of the gate electrode layer 120), and may be substantially the same as or less than the third height H3 (i.e., a minimum height of the gate electrode layer 120).

[0051] The gate capping layer 140 may be disposed on the first gate structure GS1 and the gate spacer layer 130. The gate capping layer 140 may have a flat upper surface, and may have a curved lower surface that is curved along the first gate structure GS1 and the gate spacer layer 130. The gate capping layer 140 may have a first thickness T1 (i.e., a minimum thickness) corresponding to a central region of the gate capping layer 140 on the gate electrode layer 120, and may have a second thickness T2 (i.e., a maximum thickness) corresponding to a peripheral region thereof on the gate spacer layer 130.

[0052] Figure 4A and 4B is a partially enlarged view illustrating a portion of a semiconductor device according to other example embodiments. Figure 4A and Figure 4B Shown with Figure 2A The area corresponding to area "A".

[0053] refer to Figure 4A, the upper end 114E of the second gate dielectric layer 114 in the first gate structure GS1 may have a flat upper surface between the gate electrode layer 120 and the gate spacer layer 130. Therefore, unlike Figure 2A and Figure 3 In an exemplary embodiment of the present invention, the upper end 114E of the second gate dielectric layer 114 may not have a profile continuous with the gate electrode layer 120. The upper end 114E of the second gate dielectric layer 114 may have a profile discontinuous with the gate electrode layer 120, so that a step may be formed at the interface between the upper end 114E and the gate electrode layer 120. In addition, the upper end 114E of the second gate dielectric layer 114 may have a profile discontinuous with the gate spacer layer 130, and a step may be formed at the interface therebetween.

[0054] refer to Figure 4B ,and Figure 2A and 3 Unlike the exemplary embodiment of FIG. 1 , the upper end 114E of the second gate dielectric layer 114 in the first gate structure GS1 may not have a profile continuous with the gate electrode layer 120 , and may have a profile continuous with the gate spacer layer 130 .

[0055] As referenced above Figure 4A and 4B As described above, according to example embodiments, various modifications may be made to the shape of the upper end of the second gate dielectric layer 114 in the first gate structure GS1 and the second gate structure GS2. Figure 9H The etching process is controlled by the process conditions in the process described in the specification, the materials of the second gate dielectric layer 114 and the gate electrode layer 120, the etching rate of the gate dielectric layer 114, the relative etching rate of the gate dielectric layer 114 with respect to the gate electrode layer 120, etc.

[0056] Figure 5 and Figure 6 is a cross-sectional view illustrating a semiconductor device according to other example embodiments. Figure 5 and 6 Shows the corresponding Figure 2A cross section.

[0057] refer to Figure 5 In the semiconductor device 100a, the upper surfaces of the gate electrode layers 120a constituting the second gate structure GS2a may have two or more curved surfaces. The maximum height H5 of each of the gate electrode layers 120a of the second gate structure GS2a may be higher than the maximum height H1 of each of the gate electrode layers 120 of the first gate structure GS1.

[0058] Depending on the range of the length in the X direction, the shape of the upper surface of the gate electrode layer 120a may have two or more curved surfaces. This shape may be obtained by removing a portion of the gate electrode layer 120a in a process (which will be referred to below). Figure 9H In this case, the upper corner TC of the gate electrode layer 120a may also have an upward convex shape, and the gate electrode layer 120a may have a minimum thickness in a region in contact with the gate spacer layer 130.

[0059] In example embodiments, the maximum height H5 of the gate electrode layer 120a in the second gate structure GS2a may be different from the maximum height H1 of the gate electrode layer 120 in the first gate structure GS1. The gate electrode layer 120a of the second gate structure GS2a may have a relatively large length, and thus the degree to which it is affected by the etchant from the side during the removal process of the gate electrode layer 120a may be different from the degree affected in the first gate structure GS1. The maximum height H5 of the gate electrode layer 120a in the second gate structure GS2a may be higher than the maximum height H1 of the gate electrode layer 120 in the first gate structure GS1. The difference in height may be variously changed according to the lengths of the gate electrode layers 120 and 120a, the height of the gate spacer layer 130, process conditions, etc. In addition, the height difference and the shape of the upper surface of the gate electrode layer 120a are not necessarily related to each other and may be independently applied to the above reference. Figure 2A 4 to describe example embodiments.

[0060] refer to Figure 6 In the semiconductor device 100b, the gate spacer layer 130a may have a flat upper surface, and the gate electrode layer 120b of the first gate structure GS1b and the second gate structure GS2b may have a thickness greater than 1. Figure 2A The shape of the upper surface of the semiconductor device 100 is more convex.

[0061] Depending on the width, height, process conditions, etc. in the X direction, the gate spacer layer 130a may be formed to have a flat upper surface. In this case, the gate spacer layer 130a may also be set lower than the gate electrode layer 120b. In addition, the upper surface of the gate electrode layer 120b may have an upward convex shape to have a maximum height only in its central area without a flat area. However, the shape of the gate spacer layer 130a and the upper surface of the gate electrode layer 120b are not related to each other and may be applied to the above reference 1 and 2, respectively. Figures 2A to 5 Example embodiments are described.

[0062] Figure 7 is a cross-sectional view illustrating a semiconductor device according to other example embodiments.

[0063] refer to Figure 7In the semiconductor device 100c, in addition to the first region R1 and the second region R2, the substrate 101 may further have a third region R3. A third transistor TR3 including a third gate structure GS3 may be disposed in the third region R3. In addition, in the first gate structure GS1c and the second gate structure GS2c, the gate electrode layer 120c may include a first conductive layer 123c and a second conductive layer 125c. In the first to third transistors TR1, TR2, and TR3, upper corners TC of the gate electrode layers 120c and 120d may have a curved shape.

[0064] The third transistor TR3 may have the same channel length as the first transistor TR1 and may have a different threshold voltage or operating voltage. For example, the first transistor TR1 may be an n-type transistor and the third transistor TR3 may be a p-type transistor. In this case, in the first region R1 and the third region R3, the active fin 105 may include impurities of different conductivity types.

[0065] In the first gate structure GS1c and the second gate structure GS2c, the first conductive layer 123c and the second conductive layer 125c of the gate electrode layer 120c may include different materials. For example, the first conductive layer 123c may be used to control the work function and may include, for example, TiN, Ta, TaN, TiAl, TiAlC, TiAlN, or a combination thereof. The second conductive layer 125c may include, for example, TiN, W, WCN, or a combination thereof.

[0066] In the third gate structure GS3, the gate electrode layer 120d may include a first conductive layer 123d and a second conductive layer 126d. For example, the first conductive layer 123d may be formed of the same material as the first conductive layer 123c of the first gate structure GS1c and the second gate structure GS2c, and the second conductive layer 126d may be formed of a material different from the material of the second conductive layer 125c of the first gate structure GS1c and the second gate structure GS2c. In addition, the second conductive layer 126d may have a shape having a relatively wide width at the upper portion and a relatively thin and elongated extension at the lower portion. Fig.9F In the described process of forming the gate electrode layer 120d, such a structure may be obtained depending on the relative thicknesses of the first conductive layer 123d and the second conductive layer 126d, the size of the third gate structure GS3, and the like.

[0067] As described above, in example embodiments, the semiconductor device 100c may include a plurality of transistors TR1, TR2, and TR3 having different threshold voltages. In each of the transistors TR1, TR2, and TR3, the number, material, structure, and the like of the conductive layers 123c, 123d, 125c, and 126d constituting the gate electrode layers 120c and 120d may be variously changed. Although the example embodiments illustrate as examples that the gate electrode layers 120c and 120d have rounded upper corners TC, the example embodiments are not limited thereto. For example, a portion of the gate electrode layers 120c and 120d of the first to third transistors TR1, TR2, and TR3 may also have substantially right-angled upper corners, and the other portions may have rounded upper corners TC.

[0068] Figure 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 9A to FIG. 9J are cross-sectional views illustrating some stages in a method of fabricating a semiconductor device according to example embodiments. Figures 9A to 9J Shows the corresponding Figure 2A area.

[0069] refer to Figure 8 and Fig.9A In operation S110, active fins 105 may be formed by patterning the substrate 101 having the first region R1 and the second region R2, and a sacrificial gate structure 180 and source / drain regions 150 may be formed. In addition, in this operation, a gate spacer layer 130P and a first interlayer insulating layer 192 may also be formed.

[0070] The first region R1 and the second region R2 may be transistor regions, respectively, and the substrate 101 may include a conductive region, such as a well structure doped with impurities. The active fin 105 may be formed by forming a device isolation layer 107 (see Figure 2B ) and may have a shape protruding from the substrate 101. The active fin 105 may include an impurity region.

[0071] The sacrificial gate structure 180 may be formed in Figure 2AAs shown in the figure, the first gate dielectric layer 112 and the second gate dielectric layer 114, the gate electrode layer 120 and the gate capping layer 140 are arranged in the region by subsequent processes. Each sacrificial gate structure 180 may include a sacrificial gate insulating layer 182 and a sacrificial gate electrode layer 185. The sacrificial gate structure 180 may be formed to also include a sacrificial gate capping layer arranged on the sacrificial gate electrode layer 185. The sacrificial gate capping layer may be removed by a planarization process performed when forming the first interlayer insulating layer 192, so there may be no left. The sacrificial gate insulating layer 182 may be an insulating layer, and the sacrificial gate electrode layer 185 may be a conductive layer, but is not limited thereto. For example, the sacrificial gate insulating layer 182 may include, for example, silicon oxide, and the sacrificial gate electrode layer 185 may include, for example, polysilicon.

[0072] The gate spacer layer 130P may be formed on both sidewalls of the sacrificial gate structure 180. The gate spacer layer 130P is located in a region where the gate spacer layer 130 has a Figure 2A The gate spacer layer 130P is a state before the final shape shown in the figure, and is therefore denoted by a reference numeral 130P different from the reference numeral 130. The gate spacer layer 130P may be formed to have a narrowed top when it is formed, and then the top may be removed in a planarization process performed when forming the first interlayer insulating layer 192. Therefore, the gate spacer layer 130P may have a flat upper surface as shown in the figure.

[0073] The source / drain region 150 may be formed on the active fin 105 recessed after removing a portion of the active fin 105 on both sides of the gate spacer layer 130. The source / drain region 150 may be formed using, for example, a selective epitaxial growth (SEG) process. The source / drain region 150 may include a semiconductor material doped with impurities, such as Si, SiGe, or SiC. Specifically, the source / drain region 150 may include n-type or p-type impurities. The impurities may be in-situ doped during the formation of the source / drain region 150, or may be implanted separately after the source / drain region is grown. The source / drain region 150 may grow along a crystallographically stable plane during the growth process, thereby having a cross-section in the Y direction, for example, a pentagon, a hexagon, or a similar shape, but example embodiments are not limited thereto.

[0074] The first interlayer insulating layer 192 may be formed by depositing an insulating material to cover the sacrificial gate structure 180 and the source / drain region 150, and then exposing the upper surface of the sacrificial gate electrode layer 185 through a planarization process. The first interlayer insulating layer 192 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric constant material.

[0075] refer to Figure 8 and Fig. 9B In operation S120 , the sacrificial gate structure 180 may be removed to form an opening OP.

[0076] The sacrificial gate structure 180 may be selectively removed relative to the device isolation layer 107, the active fin 105, and the gate spacer layer 130P to form an opening OP exposing the device isolation layer 107, the active fin 105, and the gate spacer layer 130P. The removal process of the sacrificial gate structure 180 may be performed using at least one of a dry etching process and a wet etching process.

[0077] refer to Figure 8 and Fig. 9C In operation S130 , a first gate dielectric layer 112 and a second gate dielectric layer 114 may be formed in the opening OP.

[0078] The first gate dielectric layer 112 and the second gate dielectric layer 114 may be formed to have substantially the same thickness in the first region R1 and the second region R2. The first gate dielectric layer 112 may be formed on the upper surface of the active fin 105, exposed to the lower surface of the opening OP. According to example embodiments, the first gate dielectric layer 112 may also be formed by oxidizing a portion of the active fin 105. The second gate dielectric layer 114 may be substantially conformally formed along the sidewalls and lower surface of the opening OP. The formation process of the first gate dielectric layer 112 and the formation process of the second gate dielectric layer 114 may be performed separately. The first gate dielectric layer 112 and the second gate dielectric layer 114 may be formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. The first gate dielectric layer 112 and the second gate dielectric layer 114 may include, for example, oxides, nitrides, or high-k materials.

[0079] Next, we will refer to Figure 8 and 9D 9F describe forming the gate electrode layer 120P in operation S140. As an example, Figures 9D to 9F The gate electrode layer 120P (see Fig.9F ) is a manufacturing method in which a plurality of conductive layers are formed.

[0080] refer to Fig.9D , a first layer 122 constituting a gate electrode layer 120P may be formed in the opening OP.

[0081] The first layer 122 may be a layer that forms a part of the gate electrode layer 120P through a subsequent process. For example, when the gate electrode layer 120P includes a plurality of conductive layers, the first layer 122 may include at least one layer formed at a lower portion among the plurality of conductive layers. Figure 7 In the case of the semiconductor device 100c of FIG. 1 , the first conductive layer 123d may be formed in this operation. The first layer 122 may be conformally formed on the second gate dielectric layer 114 in the opening OP.

[0082] refer to Fig.9E, the first layer 122 may be partially removed in the opening OP.

[0083] First, a coating layer CL may be formed on the first layer 122 to fill the lower portion of the opening OP to a predetermined height. The coating layer CL may include a carbon-containing material and may be formed of, for example, an amorphous carbon layer (ACL) or a carbon-based spin-on hard mask (C-SOH) layer.

[0084] Next, the first layer 122 on the coating layer CL in the opening OP may be removed to a predetermined depth. The depth may be, for example, in the range of about 20% to about 70% of the total depth of the opening OP. The lower portion of the first layer 122 covered by the coating layer CL may not be removed. By removing the upper region of the first layer 122, it is possible to ensure that the second layer 124 (see FIG. 1 ) to be subsequently formed is sufficient. Fig.9F ) gap-filling space.

[0085] During the process of removing a portion of the first layer 122, the first gate dielectric layer 112 and the second gate dielectric layer 114 may remain without being removed, but example embodiments are not limited thereto. According to example embodiments, in this operation, the second gate dielectric layer 114 above the coating layer CL may also be removed together. In this case, in the final structure, the second gate dielectric layer 114 may be provided to have a relatively low height at the side of the gate electrode layer 120.

[0086] The coating layer CL may be removed after the removal process of removing a portion of the first layer 122. The coating layer CL may be removed, for example, by an ashing or stripping process.

[0087] refer to Fig.9F , a second layer 124 may be formed in the opening OP to constitute a gate electrode layer 120P.

[0088] The second layer 124 may be a layer constituting a portion of the gate electrode layer 120P. For example, when the gate electrode layer 120P includes a plurality of conductive layers, the second layer 124 may be a layer other than the layers described above. Fig.9D Layers other than those formed during the operations described. Figure 7 In the case of the semiconductor device 100c, the second conductive layer 126d may be formed in this operation. The second layer 124 may be formed to completely fill the opening OP. The second layer 124 may be formed of the same material as that of the first layer 122 or a different material, and in the case where the second layer 124 is formed of the same material as that of the first layer 122, the interface between the first layer and the second layer may be indistinguishable.

[0089] After the material forming the second layer 124 is deposited, the material forming the second layer 124 may be removed from the upper surface of the first interlayer insulating layer 192. The removal process may be performed using a planarization process such as chemical mechanical polishing (CMP). Thus, a gate electrode layer 120P including the first layer 122 and the second layer 124 may be formed. Figure 2A In the state before the final form is obtained as shown, the gate electrode layer 120P is composed of Figure 2A The reference numeral 120 is denoted by a different reference numeral 120P. Hereinafter, the gate electrode layer 120P may be illustrated as a single layer.

[0090] In example embodiments, for example, when the gate electrode layer 120P is formed of a single layer, Fig.9D In the described operation, the gate electrode layer 120P is formed by depositing a conductive material to fill the opening OP. In addition, even when the gate electrode layer 120P is formed of multiple layers, in the case where the multiple layers are sequentially stacked, the gate electrode layer 120P may be formed by depositing a conductive material to fill the opening OP. Fig.9D The described operation sequentially deposits a conductive material to fill the opening OP, thereby forming the gate electrode layer 120P.

[0091] refer to Figure 8 and Figure 9G , a portion of the gate spacer layer 130P may be removed in operation S150.

[0092] The gate spacer layer 130P may be selectively removed relative to the first interlayer insulating layer 192 and the gate electrode layer 120P. The gate spacer layer 130P may be recessed from the exposed upper portion to a predetermined depth D3 using a dry etching or wet etching process. In consideration of the final height of the desired gate electrode layer 120, the depth D3 may be determined as a depth at which the gate spacer layer 130 remains at the same height as or lower than the final height of the desired gate electrode layer 120. A tunnel portion ST may be formed in the region from which the gate spacer layer 130P has been removed. The tunnel portion ST may have a shape extending in the Y direction. For example, when a portion of the gate spacer layer 130P is removed, in the case where a relatively large amount of etching is performed in the central region of the gate spacer layer 130P, the gate spacer layer 130 may have a recessed region on the upper surface, but example embodiments are not limited thereto.

[0093] In this operation, the second gate dielectric layer 114 on the side of the gate electrode layer 120P may be removed together, or may remain without being removed. Figure 4B The case of the example embodiment may correspond to a structure in which the second gate dielectric layer 114 is removed together with a portion of the gate spacer layer 130P in this operation.

[0094] refer to Figure 8 and Figure 9H, a portion of the gate electrode layer 120P may be removed in operation S160.

[0095] The gate electrode layer 120P may be selectively recessed relative to the first interlayer insulating layer 192 and the gate spacer layer 130. A recessed region GR may be formed in a region where the gate electrode layer 120P has been removed. The gate electrode layer 120P may be etched from the exposed upper surface and the exposed side surface. In the etching process, as shown in FIG. Figure 9H As shown by the arrows in the enlarged view of , since the etchant is supplied (e.g., introduced) from the side surface and from the upper surface through the tunnel portion ST, the etching amount in the corner region can be relatively large. Therefore, when the gate electrode layer 120P is removed under appropriate conditions, such as by isotropic etching process conditions without applying a bias or by applying a significantly reduced bias thereto, the gate electrode layer 120 can be formed to have a rounded corner TC.

[0096] In this operation, the second gate dielectric layer 114 on the side of the gate electrode layer 120P may be removed together with a portion of the gate electrode layer 120P. Fig.9E If the first layer 122 is left in the described process but is not completely removed, etching may be performed from the side surface in this operation, thereby removing the entire upper portion of the first layer 122 .

[0097] Through this operation, first and second gate structures GS1 and GS2 including first and second gate dielectric layers 112 and 114 and gate electrode layer 120 may be formed. Finally, gate electrode layer 120 may be formed to protrude upward from gate spacer layer 130 by a predetermined length.

[0098] refer to Figure 8 and Fig.9I In operation S170 , a gate capping layer 140 may be formed on the gate electrode layer 120 .

[0099] The gate capping layer 140 may be formed to fill the recessed region GR while covering the upper surfaces of the gate electrode layer 120 and the gate spacer layer 130. After depositing the material forming the gate capping layer 140, a planarization process may be performed. Therefore, the gate capping layer 140 may be formed to fill the space between the adjacent first interlayer insulating layers 192 and have a flat upper surface. The gate capping layer 140 may be formed of, for example, SiN. Since the gate capping layer 140 may have a different process from the gate spacer layer 130, even when their compositions are similar, the interface between the gate capping layer 140 and the gate spacer layer 130 may be distinct.

[0100] refer to Figure 8 and Figure 9J In operation S180 , a contact hole PH may be formed to expose the source / drain region 150 .

[0101] First, a second interlayer insulating layer 194 may be formed on the gate capping layer 140 and the first interlayer insulating layer 192. The contact hole PH may be formed by removing the first interlayer insulating layer 192 and the second interlayer insulating layer 194 to expose the source / drain region 150. The contact hole PH may have an inclined side surface on the upper surface of the substrate 101 according to the aspect ratio. Figure 2A , a conductive material may be sequentially deposited in the contact hole PH to form a contact plug 160 including a diffusion barrier layer 162 and a plug conductive layer 165 .

[0102] If the contact plug 160 is formed adjacent to the first gate structure GS1 and the second gate structure GS2, the contact plug 160 may contact the side surface of the gate electrode layer 120 adjacent thereto in the event of misalignment. In this case, defects such as electrical short circuits may occur. However, in example embodiments, since the upper portion of the gate electrode layer 120 has rounded corners, such defects may be suppressed or even prevented.

[0103] Fig.10 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments.

[0104] refer to Fig.10 , an electronic device 1000 according to an example embodiment may include a communication unit 1010 , an input unit 1020 , an output unit 1030 , a memory 1040 , and a processor 1050 .

[0105] The communication unit 1010 may include a wired / wireless communication module, and may include a wireless Internet module, a near field communication module, a global positioning system (GPS) module, a mobile communication module, etc. The wired / wireless communication module included in the communication unit 1010 may be connected to an external communication network through various communication protocols to transmit and receive data.

[0106] The input unit 1020 may include a mechanical switch, a touch screen, a voice recognition module, etc. as a module that allows the user to control the operation of the electronic device 1000. In addition, the input unit 1020 may also include a mouse operated using a trackball, a laser pointer solution, etc., or may include a finger mouse device. In addition, the input unit 1020 may also include various sensor modules through which the user inputs data.

[0107] The output unit 1030 may output information processed by the electronic device 1000 in the form of voice or image, and the memory 1040 may store programs, data, etc. for processing and control of the processor 1050. The processor 1050 may transmit a command to the memory 1040 according to necessary operations, thereby storing data or retrieving data therefrom.

[0108] The memory 1040 may communicate with the processor 1050 through an interface embedded in the electronic device 1000 or through a separate interface. For example, when the memory 1040 communicates with the processor 1050 through a separate interface, the processor 1050 may store data in the memory 1040 or retrieve data from the memory 1040 through various interface standards such as secure digital (SD), secure digital high capacity (SDHC), secure digital extended capacity (SDXC), MICRO SD, universal serial bus (USB), etc.

[0109] The processor 1050 may control the operation of each component included in the electronic device 1000. The processor 1050 may perform control and data processing related to voice communication, video phone, data communication, etc. or related to multimedia reproduction and management. In addition, the processor 1050 may process an input made by a user through the input unit 1020, and may output the processed result through the output unit 1030. In addition, the processor 1050 may store data necessary for controlling the operation of the electronic device 1000 in the memory 1040, or may retrieve data from the memory 1040. At least one of the processor 1050 and the memory 1040 may include a processor according to the above reference. Figures 1 to 7 Various exemplary embodiments of semiconductor devices are described.

[0110] Fig.11 is a schematic diagram illustrating a system including a semiconductor device according to example embodiments.

[0111] refer to Fig.11 , the system 2000 may include a controller 2100, an input / output device 2200, a memory 2300, and an interface 2400. The system 2000 may be a mobile system or a system for sending or receiving information. The mobile system may be, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

[0112] The controller 2100 may execute a program and may be used to control the system 2000. For example, the controller 2100 may be a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0113] The input / output device 2200 may be used to input or output data of the system 2000. The system 2000 may be connected to an external device (e.g., a personal computer or a network) using the input / output device 2200 to exchange data with the external device. The input / output device 2200 may be, for example, a keypad, a keyboard, or a display.

[0114] The memory 2300 may store therein codes and / or data used for the operation of the controller 2100 , or may store therein data processed by the controller 2100 .

[0115] The interface 2400 may be used as a data transmission path between the system 2000 and external different devices. The controller 2100 , the input / output device 2200 , the memory 2300 , and the interface 2400 may communicate with each other via the bus 2500 .

[0116] At least one of the controller 2100 or the memory 2300 may include a Figures 1 to 7 Various exemplary embodiments of semiconductor devices are described.

[0117] As described above, according to example embodiments, by controlling the shape of the gate electrode, a semiconductor device with improved reliability can be provided. In addition, by first recessing the gate spacer layer and then recessing the gate electrode layer, a method for manufacturing a semiconductor device with improved reliability can be provided. That is, the gate spacer layer can be first recessed in the manufacturing process, and then the gate electrode layer is etched from the side surface and the upper surface to have a rounded corner, thereby minimizing the width of the gate electrode and increasing the distance between the gate electrode and the adjacent contact plug.

[0118] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general and descriptive sense, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly noted otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having an active region; A gate structure on the active area, the gate structure comprising a gate dielectric layer and a gate electrode layer, the gate electrode layer having a rounded upper corner; as well as A gate spacer layer on a side surface of the gate structure, an upper surface of the gate spacer layer is at a height lower than an upper surface of the gate electrode layer, and an upper surface of the gate spacer layer has a downward convex shape, Each of the gate spacer layers has a minimum thickness in a central region thereof and a maximum thickness in an edge region thereof in the second direction.

2. The semiconductor device according to claim 1, wherein The gate electrode layer extends in a first direction perpendicular to the second direction to cross the active region, and the gate electrode layer has rounded corners on both sides in the second direction.

3. The semiconductor device according to claim 1, wherein The upper surface of the gate electrode layer has an upward convex shape.

4. The semiconductor device according to claim 1, further comprising: A gate cap layer covers the upper surfaces of the gate electrode layer and the gate spacer layer.

5. The semiconductor device according to claim 4, wherein: An outer surface of the gate spacer layer that is not in contact with the gate structure is coplanar with a side surface of the gate cap layer.

6. The semiconductor device according to claim 1, wherein The gate dielectric layer covers the lower surface and side surfaces of the gate electrode layer, and on the side surfaces of the gate electrode layer, the upper end of the gate dielectric layer is at the same height as the upper surface of the gate electrode layer, or at a height lower than the upper surface of the gate electrode layer.

7. The semiconductor device according to claim 6, wherein: On the side surface of the gate electrode layer, when the upper end of the gate dielectric layer is at a height lower than the upper surface of the gate electrode layer, the upper end of the gate dielectric layer is at a height closer to the upper surface of the gate spacer layer than to the highest part of the gate electrode layer.

8. The semiconductor device according to claim 6, wherein: The gate dielectric layer includes a first gate dielectric layer on the substrate and a second gate dielectric layer on the first gate dielectric layer and extending to a side surface of the gate electrode layer, and The upper end of the gate dielectric layer is the upper end of the second gate dielectric layer.

9. The semiconductor device according to claim 1, wherein: An upper end of the gate dielectric layer has a profile continuous with an upper surface of the gate electrode layer.

10. The semiconductor device according to claim 1, wherein The upper end of the gate dielectric layer has a profile continuous with the upper surface of the gate spacer layer.

11. The semiconductor device according to claim 1, wherein The gate electrode layer extends in a first direction perpendicular to the second direction, and a thickness of the gate electrode layer at a central region is greater than a thickness at an edge region, the thickness being measured along the second direction.

12. The semiconductor device according to claim 1, wherein The upper surface of the gate electrode layer has two or more curved surfaces.

13. The semiconductor device according to claim 1, wherein The gate electrode layer comprises: a first conductive layer extending onto a side surface of the gate spacer layer, and A second conductive layer is provided between portions of the first conductive layer on the side surfaces of the gate spacer layer.

14. The semiconductor device according to claim 1, further comprising: Source / drain regions, located in the active region on both sides of the gate structure; as well as A contact plug is connected to the source / drain region.

15. A semiconductor device comprising: a substrate having an active region and having a first region and a second region; A first gate electrode layer on the first region extends in a first direction, the first gate electrode layer having a first length in a second direction perpendicular to the first direction; a second gate electrode layer on the second region extending in the first direction, wherein a second length of the second gate electrode layer in the second direction is greater than the first length, and a gate spacer layer located on the side surfaces of the first gate electrode layer and the second gate electrode layer, respectively, wherein the upper surface of the gate spacer layer is at a height lower than the upper surfaces of the first gate electrode layer and the second gate electrode layer, and the upper surface of the gate spacer layer has a downward convex shape, wherein the first gate electrode layer and the second gate electrode layer have a first thickness at an edge region in the second direction, and have a second thickness greater than the first thickness in a region inward of the edge region, wherein the maximum thickness of the first gate electrode layer is less than the maximum thickness of the second gate electrode layer, and Each of the gate spacer layers has a minimum thickness in a central region thereof and a maximum thickness in an edge region thereof in the second direction.

16. The semiconductor device according to claim 15, wherein: The first gate electrode layer and the second gate electrode layer have rounded upper corners.

17. The semiconductor device according to claim 15, wherein: An upper surface of the first gate electrode layer has an upward convex shape, and an upper surface of the second gate electrode layer has a profile different from a profile of an upper surface of the first gate electrode layer.

18. The semiconductor device according to claim 15, wherein: An operating voltage of a first transistor including the first gate electrode layer is lower than an operating voltage of a second transistor including the second gate electrode layer.

19. A semiconductor device comprising: a substrate having an active region; A gate structure on the active area, the gate structure comprising a gate dielectric layer and a gate electrode layer, the gate electrode layer having a rounded upper corner; A gate spacer layer on a side surface of the gate structure, wherein an upper surface of the gate spacer layer is at a height lower than an upper surface of the gate electrode layer, and the upper surface of the gate spacer layer has a downward convex shape; as well as a gate cap layer, covering the upper surfaces of the gate electrode layer and the gate partition wall layer, The outer surface of the gate partition layer not in contact with the gate structure is coplanar with the side surface of the gate cap layer, and Each of the gate spacer layers has a minimum thickness in a central region thereof and a maximum thickness in an edge region thereof in a first direction.

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