Semiconductor Devices

Abstract

The present disclosure relates to a semiconductor device, which includes a composite pn junction structure in a semiconductor substrate, wherein the composite pn junction structure is arranged to have a predetermined first junction gradation coefficient m1, wherein m1≥0.50. The composite pn junction structure includes a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure is arranged to have a predetermined first structure partial junction gradation coefficient m1. 11 , and wherein the second portion pn junction structure is arranged to have a predetermined second portion junction grading coefficient m 12 The first part of the predetermined ramp coefficient m 11 The second part of the predetermined ramp coefficient m 12 Different, among which m 11 ≠m 12 The first part of the predetermined ramp coefficient m 11 and the second part of the slow-changing coefficient m 12 At least one of them is greater than 0.50, where m 11 and / or m 12 >0.50. The predetermined first junction grading coefficient m1 of the composite pn junction structure is based on the first part of the junction grading coefficient m 11 and the second part of the slow-changing coefficient m 12 The predetermined combination.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly to semiconductor devices. Background Art

[0002] Typically, discrete ESD protection devices (ESD = Electrostatic Discharge) and TVS devices (TVS = Transient Voltage Suppressor) have nonlinear electrical properties that can cause harmonic distortion of RF signals (RF = Radio Frequency) present on signal lines connected to the ESD protection device or TVS device, such as on PCB lines (PCB = Printed Circuit Board). This harmonic generation can produce spurious and undesirable harmonic signals that can interfere with other functions or functional blocks of the electronic system if these functions or functional blocks use frequency bands that are integer multiples of the distorted RF signal.

[0003] For example, the third harmonic (H3) frequency of certain frequency bands in the 800 MHz to 900 MHz range used in mobile telecommunication standards interferes with RF signals in the 2.4 GHz - WiFi band (ie, in the frequency range between 2.412 and 2.472 GHz).

[0004] In order to avoid such undesirable interference between the frequency bands exemplarily described above, electronic devices such as TVS devices should minimize their harmonic generation to a sufficiently low level.

[0005] In known implementations, the generation of even harmonics is minimized, for example, by utilizing a strictly symmetrical design and highly symmetrical behavior of electronic components for the positive and negative half-waves of the RF signal. By ensuring symmetry, even harmonics can be effectively suppressed, however, this approach does not affect or support the generation of odd harmonics.

[0006] Generally, there is a need in the art for a method for implementing a semiconductor device, eg, for a discrete ESD protection device or TVS device, with reduced or minimized generation of odd harmonics, eg, third harmonic generation, which further has an adjustable, eg, lowered or tuned, breakdown voltage. Summary of the Invention

[0007] According to one embodiment, a semiconductor device includes: a composite pn junction structure in a semiconductor substrate, wherein the composite pn junction structure is arranged to have a predetermined first junction grading coefficient m1, wherein m1 ≥ 0.50, wherein the composite pn junction structure includes a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure is arranged to have a predetermined first partial junction grading coefficient m1. 11 , and wherein the second portion pn junction structure is arranged to have a predetermined second portion junction grading coefficient m 12, wherein the predetermined first part of the ramp coefficient m 11 Different from the predetermined second part of the junction ramp coefficient m 12 , where m 11 ≠m 12 , and wherein the predetermined first part of the ramp coefficient m 11 and the second part of the gradual change coefficient m 12 At least one of them is greater than 0.50, where m 11 and / or m 12 >0.50, and wherein the predetermined effective first junction grading coefficient m1 of the composite pn junction structure is based on the first partial junction grading coefficient m 11 and the second part of the gradual change coefficient m 12 The predetermined combination.

[0008] Some embodiments relate to a semiconductor device comprising a composite pn junction structure (also referred to herein as a diode structure) in a semiconductor substrate, wherein the composite pn junction structure is arranged to have a predetermined first junction gradation coefficient m1, for example, where m1 ≥ 0.50. The composite pn junction structure includes, for example, a first partial pn junction structure and a second partial pn junction structure. The first partial pn junction structure is, for example, arranged to have a predetermined first partial junction gradation coefficient m1. 11 , and the second partial pn junction structure is, for example, arranged to have a predetermined second partial junction grading coefficient m 12 For example, the predetermined first part of the ramp coefficient m 11 The second part of the predetermined ramp coefficient m 12 Different, where m 11 ≠m 12 , and for example, the predetermined first part of the ramp coefficient m 11 and the second part of the gradual change coefficient m 12 At least one of them is greater than 0.50, where m 11 and / or m 12 >0.50. The predetermined first junction grading coefficient m1 of the composite pn junction structure (J1) is, for example, based on the first partial junction grading coefficient m 11 and the second part of the gradual change coefficient m 12 The predetermined combination.

[0009] Other embodiments relate to a semiconductor device having at least one composite pn junction structure (also referred to herein as a diode structure), the at least one composite pn junction structure including an adjustable junction grading coefficient m1 (preferably adjustable in design and technology, and typically not adjustable in operation), wherein the composite pn junction structure includes a first partial pn junction structure and a second partial pn junction structure, wherein each partial pn junction structure may include an adjustable partial junction grading coefficient m1. 11 、m 12 (also known as the diode power law index) (preferably adjustable in design and technology, and usually not adjustable in operation), the partially adjustable ramping coefficient m 11 、m 12 . BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present concept are described herein with reference to the accompanying drawings, in which

[0011] Figure 1 shows an exemplary circuit diagram of a semiconductor device consisting of a pair of pn junction structures connected in anti-series according to an embodiment,

[0012] Figure 2a shows a schematic cross-sectional view of a semiconductor device according to an embodiment,

[0013] Figure 2b Shown Figure 2a Schematic simulation diagram of an exemplary doping distribution of a pn junction structure of a semiconductor device,

[0014] Figure 3a Shown based on Figure 2b Schematic simulation diagram of the junction gradation coefficient m1 obtained for different implantation doses of the doping profile of the shallow pn junction as a function of the doping concentration,

[0015] Figure 3b Shown based on Figure 2b Schematic simulation diagram of the breakdown voltage obtained as a function of doping concentration for different implantation doses of the doping profile of a shallow pn junction,

[0016] Figure 4 shows a schematic equivalent circuit diagram according to an embodiment, wherein the composite pn junction structure J1 is equivalent to the first partial pn junction structure J11 and the second partial pn junction structure J12, and wherein the further composite structure pn junction structure J2 is equivalent to the further first partial pn junction structure J21 and the second partial pn junction structure J22,

[0017] Figure 5 Shown based on the Figure 2b The two adjusted partial junction grading coefficients m for the two doping profiles shown in11 、m 12 , the resulting combined junction grading coefficient of the composite pn junction structure as a function of the area ratio between the areas of the first partial pn junction structure and the second partial pn junction structure,

[0018] Figures 6a to 6d shows schematic cross-sectional views of different implementations of semiconductor devices having a composite pn junction structure J1 according to embodiments,

[0019] Figure 7a 、 Figure 7b further schematic cross-sectional views showing different implementations of semiconductor devices with a composite pn junction structure J1 according to further embodiments, and

[0020] Figures 8a to 8d Schematic cross-sectional views of different implementations of a semiconductor device having two composite pn junction structures J1 , J2 according to embodiments are shown.

[0021] Before discussing the embodiments of the present invention in further detail using the drawings, it is pointed out that in the drawings and the description, the same elements and elements having the same functionality and / or the same technical or physical effects are generally given the same reference numerals or identified with the same names, so that the descriptions of these elements and their functionality illustrated in different embodiments are interchangeable, or they can be applied to each other in different embodiments. DETAILED DESCRIPTION

[0022] In the following description, embodiments of the present invention are discussed in detail. However, it should be understood that the present invention provides many applicable concepts that can be implemented in a variety of semiconductor devices. The specific embodiments discussed only illustrate specific ways to make and use the present invention and do not limit the scope of the invention. In the following description of the embodiments, the same or similar elements having the same function are associated with the same reference numerals or the same names, and the description of these elements will not be repeated for each embodiment. In addition, unless otherwise specifically stated, the features of the different embodiments described below may be combined with each other.

[0023] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly," "connected" or "coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0024] Figure 1FIG2 shows a circuit diagram of a semiconductor device 100 that can be used as an ESD (electrostatic discharge) device. The semiconductor device 100 includes a pair 102 of pn junction structures (diode structures) J1 and J2 connected in anti-series connection, i.e., a pair of a pn junction structure J1 and another pn junction structure J2. The pn junction structure J1 and the other pn junction structure J2 are arranged to have a first effective junction gradation coefficient m1 and a second effective junction gradation coefficient m2, respectively. In addition, the pn junction structure J1 is arranged to have a first zero-bias junction capacitance C J01 and the first junction voltage potential V J1 , and the other pn junction J2 structure is arranged to have a second bias junction capacitance C J02 and a predetermined second junction voltage potential V J2 .

[0025] The pn junction structures J1 and J2 are connected between the first terminal 107 and the second terminal 108 .

[0026] In the commonly used pn junction structure model, based on the reverse bias voltage V for the pn junction structure i The voltage-dependent capacitance characteristic C of the depletion region of the pn junction structure i (V i ) to determine the ramp coefficient m of the i-th (i=1,2) junction i ,in

[0027]

[0028] The C(V) characteristic described by equation A1 also applies to small forward bias voltages. In other words, the expression also applies to the applied voltage range where the reverse bias voltage is negative, i.e., the applied voltage is a forward bias voltage. In this specification, the wording "having a ramp coefficient m i The pn junction (or diode structure)” is used to express that the C(V) characteristics of the pn junction or diode structure can be represented by a ramp coefficient or power law index m i is described by equation A1.

[0029] From the perspective of suppressing the generation of high-order harmonics (such as the second harmonic and the third harmonic), for example, for use in a simple topology of an electronic RF signal switching device or a varactor diode or a tuning diode or an ESD device, the pn junction structures J1 and J2 can preferably be arranged to be equal and have a junction gradient coefficient m1 = m2 = 0.50. In other topologies, such as the topology of an ESD device, it may be preferred to have specially adjusted but different zero-bias capacitances C of the pn junction structures J1, J2 connected in anti-series. J01 、C J02 And the junction ramp coefficients are equal, where m1=m2 and m1>0.50.

[0030] According to an embodiment, the semiconductor device 100 forms a discrete ESD device (ESD=Electrostatic Discharge), for example with TVS functionality. In other embodiments, the device 100 forms an electronic RF signal switching device or a varactor diode or a tuner diode.

[0031] Some examples of ramp coefficients are:

[0032] m = 0.5 indicates the behavior of an abrupt pn junction with uniform dopant (= doping concentration) in the n- and p-regions (1), or the behavior of a one-sided junction with a very abrupt pn junction between a highly doped region and a uniformly doped low-doped region (2). Realizing such an idealized junction with conventional semiconductor technology can be difficult or expensive.

[0033] m = 0.33 indicates linearly graded junction behavior. In this case, the dopant concentration around the metallurgical junction varies linearly with depth. This pn junction type is very similar to conventional semiconductor technology, as, for example, p-doped species diffuse into the n-doped region.

[0034] - The term "hyperabrupt junction" is used in the case of m>0.5. It can be considered as a one-sided junction, where the lower doped region does not have a constant doping profile, but rather the doping concentration decreases with distance from the metallurgical junction.

[0035] Figure 2a A schematic cross-sectional view of a semiconductor device 100 is shown, as a semiconductor substrate 120 implementing the Figure 1 An example of a circuit diagram.

[0036] like Figure 2a As shown in , the semiconductor device 100 includes a semiconductor substrate 120 having a first main surface portion 120 a and a second main surface portion 120 b on opposite main sides of the semiconductor substrate 120 .

[0037] The following exemplary description of different layers and regions of the semiconductor substrate 120 extends substantially from the second main surface portion 120b to the first main surface portion 120a of the semiconductor substrate 120. The different regions and structures in the semiconductor substrate 120 may, for example, be manufactured during a so-called front-end of line (FEOL) process phase of semiconductor integrated circuit manufacturing.

[0038] The semiconductor substrate 120 may include a low-ohmic n-type substrate 120-1. A p-type semiconductor layer 120-2 is disposed on the n-type substrate 120-1. The p-type semiconductor layer 120-2 (e.g., p-epitaxial layer 120-2) may be epitaxially applied to the n-type substrate 120-1. The p-type semiconductor layer 120-2 includes a buried p-type semiconductor layer 120-3 (P-buried layer 120-3). The buried p-type semiconductor layer 120-3 may be formed, for example, by blanket (unmasked) implantation of a p-type dopant in the semiconductor layer 120-2.

[0039] Another p-type layer 120-4 (e.g., p-epitaxial layer 120-4) is arranged on p-type semiconductor layer 120-2 together with buried p-type layer 120-3. P-type semiconductor layer 120-4 can be epitaxially applied on p-type semiconductor layer 120-2. Alternatively, layer 120-4 can also be implemented as an i-type (i.e., intrinsic or non-intentionally doped) layer.

[0040] A p-type well region 120-5 (p-well 120-5) may be arranged in the second epitaxial layer 120-4. The p-type well region 120-5 may be formed by performing a blanket implantation step after LOCOS oxidation has been performed on the main surface region 120a of the p-type layer 120-4 of the semiconductor substrate 120. Based on this method, a photolithographic resist mask is not required on the surface region 120a of the p-type layer 120-4. However, due to the LOCOS oxidation on the surface 120a, a self-aligned implantation process can be performed. The LOCOS process (LOCOS = Local Oxidation of Silicon) is a microfabrication process in which silicon dioxide is formed in selected areas on a silicon wafer (i.e., semiconductor substrate 120), with a Si-SiO2 interface at a point or plane lower than the rest of the silicon main surface region 120a. Of course, the p-well 102-5 may also be formed using a photolithographic structured photoresist mask method known in the art.

[0041] like Figure 2a As shown in FIG, pn junction structures J1 and J2 can be arranged in a semiconductor region 122 of a semiconductor substrate 120, which can be separated from other regions of the semiconductor substrate 120 by means of so-called deep isolation trenches 130, wherein the deep isolation trenches 130 laterally confine and / or laterally surround the semiconductor region 122 with the pn junction structures J1, J2. The deep isolation trenches 130 can be formed, for example, by means of an RIE process step (RIE=reactive ion etching) in the semiconductor substrate 120, wherein the resulting trenches 130 can be lined with an oxide material 134, for example a SiO2 liner, by means of a trench liner oxidation process and filled with a semiconductor material 132, for example polysilicon.

[0042] Semiconductor device 100 also includes a highly doped n-type contact region 120-7 in the form of an implanted region adjacent to the surface region of p-type well 120-5. In some embodiments, n-type contact region 120-7 may also be simply referred to as a shallow n-region 120-7 or emitter region. N-type contact region 120-7 may be formed using an n-contact implantation process step, such as a blanket implant, which may be self-aligned using the LOCOS process (described above), thus eliminating the need for a photolithographic resist mask.

[0043] As a further (e.g. final) process step of a front-end production line process for processing the semiconductor substrate 120, an oxide material 128 may be deposited on the first main surface area 120a of the semiconductor substrate 120. The semiconductor device 100 may further include a contact and metallization layer stack 140 (BEOL stack, BEOL=back-end production line) on the first main surface area 120a of the semiconductor substrate 120 for providing interconnects 110 (e.g. contact plugs or vias) and the interconnect layer 107. The terminal 108 ( Figure 2a Not shown but in Figure 1 The semiconductor substrate 120 (shown in FIG) may be formed by backside metallization of the semiconductor substrate 120 or on another region of the semiconductor substrate 120. The contact structures and (structured) metallization layers of the metallization stack 140 may be formed by means of BEOL process steps. Finally, if a plurality of semiconductor devices 100 are manufactured in a semiconductor substrate 120 such as a semiconductor wafer 120, one or more semiconductor devices 100 may be separated (diced). For example, a chip-scale packaging process may include, for example, the formation of electrodes (or pads) as the top layer of the metallization stack 140 and a dicing process.

[0044] like Figure 2a As shown in FIG, n-type contact region 120-7 (=cathode region) and p-type well region 120-5 (=anode region) form a pn junction structure J1. Furthermore, buried p-type layer 120-3 (=anode region) and n-type substrate 120-1 (=cathode region) form another pn junction structure J2.

[0045] Figure 2b Shown Figure 2a FIG. 1 is a schematic calculated graph of exemplary doping profiles of the semiconductor device 100 , wherein different doping concentrations in the p-type well 120 - 5 can be achieved by different implantation doses, which are indicated by “ 36 ” to “ 42 ”. Figure 2b The graph also contains Figure 2a1. The metallurgical junction between n-type region 120-7 and p-type region 120-5 falls within the descending slope of the p-type implant profile of region 120-5. With a sufficiently steep slope of the n-type implant profile of n-type region 120-7, the C(V) properties of the pn junction formed by regions 120-5 and 120-7 can exhibit hyperabrupt characteristics and, therefore, can have a gradation coefficient m1 > 0.5.

[0046] From the pair Figure 2a and Figure 2b Further analysis of the various doping profiles shown in

[15] reveals that, in conventional semiconductor technology, it is difficult to achieve (hyper)abrupt junctions with a controllable gradation coefficient m ≥ 0.5 and a low breakdown voltage below 25 V, or even below 16 V or 12 V. This is due to the fact that processing steps conventionally used in semiconductor technology, such as implantation and diffusion, produce dopant profiles that exhibit some gradation in a narrow region surrounding the metallurgical junction. The space charge region, which determines the capacitance-voltage behavior and breakdown voltage of the pn junction, extends around the metallurgical junction. At low breakdown voltages, the doping concentration is high and the extension of the space charge region is small. As the breakdown voltage increases, the doping concentration on one or both sides of the metallurgical junction decreases, and the width of the space charge region increases. Due to the unavoidable gradation near the metallurgical junction, junctions with low breakdown voltages will, in practice, exhibit a more or less gradual profile, rather than the desired abrupt or hyperabrupt doping profile. Therefore, the combination of low breakdown voltage and a gradation coefficient m ≥ 0.5 is difficult to achieve using the semiconductor processes conventionally used in the large-scale production of semiconductor devices and circuits.

[0047] In summary, a higher doping level results in a less extended space charge region (=depletion region) and thus a lower (lower) breakdown voltage V bd Furthermore, the resulting more linearly graded junction behavior leads to a small (smaller) graded coefficient m.

[0048] High (higher) grading factors m ≥ 0.5 require a more (or hyper) abrupt doping profile. In case of a lower doping level on one side of the metallurgical junction, the depletion layer will extend further into this lower doping region. Therefore, the depletion layer is not limited to a narrow region around the metallurgical junction, as in the case of higher doping levels, where usually the doping profile shows a more or less linear grading. Because in the case of lower doping levels the depletion region extends beyond this grading region close to the metallurgical junction, the C(V) characteristics of the lower doped junction can be more easily adapted to a grading factor m ≥ 0.5. At the same time, low (lower) doping levels result in a higher breakdown voltage V bd .

[0049] Therefore, it is difficult to achieve a combination of low breakdown voltage and ramp coefficient m≥0.5 using conventional technology.

[0050] Figure 3a Shown based on Figure 2b Schematic diagram of simulated junction gradation coefficient m1 as a function of doping concentration in region 120-4 including the pn junction between regions 120-7 and 120-5 for different implantation doses of a portion of the doping profile. More specifically, Figure 2b The doping profile shown in FIG (described in more detail above) is for semiconductor region 120-4 including regions 120-7 and 120-5 (see, e.g., FIG. Figure 2a ),exist Figure 3a Figure 3 shows the simulated capacitance-voltage characteristics of the pn junction between a highly n-doped shallow contact region and a p-doped well region, with the corresponding doping profiles labeled (36-42). This figure demonstrates that a low-implantation implantation dose can be achieved for a p-well hyperabrupt junction with m > 0.5.

[0051] Figure 3b Shown based on Figure 3a and Figure 2b Schematic diagram of the simulated breakdown voltage of the pn junction between regions 120-7 and 120-5 as a function of doping concentration for different implant doses and doping profiles indicated by the same reference numerals in FIG. However, as discussed above, the junction with the lower p-well dose, which tends to have the highest grading coefficient, tends to have a high breakdown voltage, such as Figure 3b In the case of this simulation example it is shown that if a gradation factor of about 0.5 is required for minimum third harmonic generation, the junction will have a breakdown voltage of 40 V or higher without using a composite pn junction structure as explained above.

[0052] Some embodiments provide the semiconductor device 100 with the desired properties of a low breakdown voltage and an adjustable grading factor of at least 0.50.

[0053] According to the following reference Figure 4 In a more detailed embodiment, a semiconductor device 100 may be provided, comprising a composite pn junction structure 102-1 in a semiconductor substrate 120, wherein the composite pn junction structure 102-1 may be arranged to have a predetermined first junction gradation coefficient m1, wherein m1 ≥ 0.50. The composite pn junction structure 102-1 may include a first partial pn junction structure J11 and a second partial pn junction structure J12. The first partial pn junction structure J11 may be arranged to have a predetermined first partial junction gradation coefficient m1. 11 The second partial pn junction structure J12 may be arranged to have a predetermined second partial junction grading coefficient m 12The first part of the predetermined ramp coefficient m 11 The second part can be combined with the predetermined ramp coefficient m 12 Different, where m 11 ≠m 12 The first part of the predetermined ramp coefficient m 11 and the second part of the gradual change coefficient m 12 At least one of can be greater than 0.50, where m 11 and / or m 12 >0.50. In addition, the predetermined first junction grading coefficient m1 of the composite pn junction structure 102-1 may be based on the first partial junction grading coefficient m 11 and the second part node slow-changing coefficient m 12 The predetermined combination.

[0054] According to the following reference will also be made Figure 4 Another embodiment described in more detail may provide a semiconductor device 100 that includes another composite pn junction structure 102-2 in a semiconductor substrate 120. The composite pn junction structure 102-1 and the other composite pn junction structure 102-2 may be monolithically integrated. In other words, the composite pn junction structure 102-1 and the other composite pn junction structure 102-2 may be integrated within the same semiconductor substrate 120. Alternatively, the composite pn junction structure 102-1 and the other composite pn junction structure 102-2 may not be monolithically integrated, but may be formed as separate discrete components. In other words, alternative embodiments may also be implemented by electrically connecting separate chips having the composite pn junction structure 102-1 and the other composite pn junction structure 102-2, for example, using bonding wires or any other technique. The other composite pn junction structure 102-2 may be arranged to have a predetermined second junction gradation coefficient m2, where m2 ≥ 0.50. Another composite pn junction structure 102-2 may include another first partial pn junction structure J21 and another second partial pn junction structure J22. Another first partial pn junction structure J21 may be arranged to have a predetermined another first partial junction grading coefficient m 21 , and the other second partial pn junction structure J22 may be arranged to have a predetermined other second partial junction grading coefficient m 22 The predetermined first part of the gradual change coefficient m 21 The ramp coefficient m can be combined with another predetermined second part 22 Different, where m 21 ≠m 22 The predetermined first part of the gradual change coefficient m 21 and a predetermined second part of the ramp coefficient m 21 、m 22 At least one of can be greater than 0.50, where m 21and / or m 22 >0.50. In addition, the predetermined second junction grading coefficient m2 of another composite pn junction structure 102-2 may be based on another predetermined first partial junction grading coefficient m 21 and a predetermined second part of the ramp coefficient m 21 、m 22 The predetermined combination.

[0055] Figure 4 An example of a pn junction structure pair 102 is shown, formed as a pair of two composite pn junction structures 102-1 and 102-2. The first composite pn junction structure 102-1 may also be sometimes denoted by reference numeral J1, and the second composite pn junction structure 102-2 may also be sometimes denoted by reference numeral J2. The first composite pn junction structure 102-1 includes a first partial pn junction structure J11 and a second partial pn junction structure J12, and the second composite pn junction structure 102-2 (also referred to as another pn junction structure) includes another first partial pn junction structure J21 and another second partial pn junction structure J22. In other words, the pair 102 is formed by a pair of composite pn junction structures 102-1 and 102-2 connected in anti-series, each composite pn junction structure having a parallel connection of first partial pn junction structures J11, J21 and second partial pn junction structures J12, J22. The first partial pn junction structure J11 of the first composite pn junction structure 102 - 1 has a first partial junction grading coefficient m 11 , the first part of the junction voltage potential V J11 and the first part zero bias capacitor C J011 , wherein the second partial pn junction structure J12 of the first composite pn junction structure 102-1 has a second partial junction grading coefficient m 12 , the second part junction voltage potential V J12 And the second part zero bias capacitor C J012 , which may be different from the first part of the junction ramp coefficient m 11 , the first part of the junction voltage potential V J11 and the first part zero bias capacitor C J011 At least one of the first part of the gradual change coefficient m 11 and the second part of the gradual change coefficient m 12 The first effective junction grading coefficient m1 of the composite pn junction structure 102-1 is obtained. In other words, the composite pn junction structure 102-1 exhibits an effective junction grading coefficient m1 and an effective junction potential V J1 and the effective zero-bias junction capacitance C J01 The effective behavior of the composite pn junction structure 102-1 as a simple pn junction structure is Figure 4In the equation, the corresponding relationship between the composite pn junction structure 102-1 and the pn junction structure J1 is indicated. Accordingly, in many cases, the voltage-dependent capacitance characteristic of the composite pn junction structure J1 can be satisfactorily described or modeled by the above expression A1, where m i as the effective (combined) junction grading coefficient and similarly for the junction potential V Ji and the zero-bias junction capacitance C J0i Additionally, for another composite pn junction structure 102 - 2 , another first partial pn junction structure J21 has a first partial junction grading coefficient m . 21 , another first part junction voltage potential V J21 and another first part zero bias capacitor C J021 , wherein another second partial pn junction structure J22 has another second partial junction gradient coefficient m 22 , another second part junction voltage potential V J22 and another second part zero bias capacitor C J022 , which may be different from another first part junction ramping coefficient m 21 , another first part junction voltage potential V J21 and another first part zero bias capacitor C J021 At least one of the first part of the junction ramp coefficient m 21 and the second part of the gradual change coefficient m 22 The combination of the effective junction grading coefficient m2 of the other composite pn junction structure 102-2 is obtained. That is, the other composite pn junction structure 102-2 exhibits an effective junction grading coefficient m2 and an effective junction potential V J2 and the effective zero-bias junction capacitance C J02 As for the composite pn junction structure 102-1, the effective behavior of the other composite pn junction structure 102-2 as a simple pn junction structure is Figure 4 In the embodiment, the voltage-dependent capacitance characteristic of the composite pn junction structure J2 can be satisfactorily described or modeled by the above expression A1, where m is the corresponding relation from the other composite pn junction structure 102-2 to the other pn junction structure J2. i as the effective (combined) junction grading coefficient and similarly for the junction potential V Ji and zero-bias junction capacitance C J0i .

[0056] In other words, according to the embodiment Figure 4The semiconductor device 100 shown in FIG. 1 includes a first parallel circuit 102-1 of a first partial pn junction structure J11 and a second partial pn junction structure J12, and a second parallel circuit 102-2 of another first partial pn junction structure J21 and another second partial pn junction structure J22, wherein the first parallel circuit 102-1 and the second parallel circuit 102-2 are anti-series connected. The anti-series connected first parallel circuit 102-1 and the second parallel circuit 102-2 form Figure 1 and Figure 4 The pair 102 of pn junction structures J1, J2 is shown in FIG.

[0057] As from especially including Figure 4 As can be appreciated from the above, a semiconductor device 100 having a pn junction structure with the resulting junction grading coefficients m1 and m2 can be implemented with great freedom. In particular, a pn junction structure with great freedom in tuning the breakdown voltage with a grading coefficient m≥0.5 can be implemented as a composite pn junction structure and used in the semiconductor device 100 of some embodiments, or can be employed individually in various topologies in other embodiments.

[0058] In other words, Figure 4 The embodiment shown in introduces the concept of obtaining a junction (pn junction structure) having two desired properties, namely a predetermined low breakdown voltage of not more than 25 V and a predetermined grading coefficient equal to or greater than 0.5, by subdividing the junction into two regions, namely into partial pn junction structures J11, J12; J21, J22 that together form the respective composite pn junction structures 102-1, 102-2:

[0059] (1) An active region with a higher well implantation dose, which results in a portion of the pn junction J11, J21 having a low predetermined breakdown voltage, wherein in some embodiments, the pn junction J11, J21 may have a grading coefficient m 11 <0.50,m 21 <0.50, and

[0060] (2) Another active region with a lower well implantation dose, which results in a breakdown voltage and a ramping coefficient m higher than the predetermined breakdown voltage. 12 >0.50m 22 >0.50 of the pn junction J12 and J22.

[0061] The overall behavior of the composite pn junctions 102-1 and 102-2 respectively represents a breakdown voltage determined by higher well doping, and the gradual variation coefficient of the capacitance and voltage characteristics is determined by the parallel connection in the two branches of the first partial pn junction structure J11, J12 and the second partial pn junction structure J21, J22.

[0062] By adjusting (1) the grading coefficient m in the two regions of the first and second partial pn junction structures J11, J12 (and J21, J22) 11 、m 12 (and m 21 、m 22 )(by well implantation dose and energy, and by further diffusion steps) and by adjusting (2) the area ratio of the two regions of the first and second partial pn junction structures J11, J12 (and J21, J22) with different well implantations, the resulting effective grading coefficient m1 of the resulting composite junction structure 102-1 (and m2 of 102-2) can be adjusted.

[0063] In some embodiments, from the perspective of forming a symmetrical device 100 for suppressing even (e.g., second) harmonic generation, the zero-bias capacitance (C J0 ) are arranged to be equal. Similar considerations apply to the junction voltage potentials (V J0 ) and the area ratio of the partial pn junctions in each of composite structures 102-1 and 102-2 forming composite pn junction structure pair 102. In these embodiments, from the perspective of suppressing the generation of stray odd harmonics (e.g., third harmonics), it may be further advantageous to adjust the effective ramp coefficients m1 and m2 to m1=m2=0.50. In other embodiments, to suppress the generation of stray odd harmonics, the effective ramp coefficients are adjusted to m1=m2>0.50.

[0064] In the above concept, a pair of composite pn junctions 102 - 1 and 102 - 2 is realized, wherein both the breakdown voltage and the net gradation coefficient can be controlled within a much larger parameter range through technical and physical design or layout adjustments.

[0065] Figure 5 shows the partial junction ramp coefficient m based on two adjustments 11 (or m 21 ) and m 12 (or m 22 ), the resulting combined junction grading coefficient m1 (or m2) of the composite pn junction structure 102-1 (102-2) as a function of the area ratio between the active areas of the first and second partial pn junction structures J11 and J12 (or J21 and J22). In this case, the doping profiles of the first and second partial pn junction structures correspond to Figure 2b 37 and 41 shown in FIG (see also Figure 3a and Figure 3b As discussed above, the breakdown voltage of the junction with the lowest p-well dose and the highest grading coefficient tends to have a high breakdown voltage, such as Figure 5 The relative area contribution can be easily controlled by the physical design (layout) of the device.

[0066] According to an embodiment, the first partial pn junction structure J11 is arranged to have a first partial junction grading coefficient m 11 >0.50, and wherein the second partial pn junction structure J12 is arranged to have a second partial junction grading coefficient m 12 <m 11 , for example m 11 It can be between 0.30 and 0.50.

[0067] According to an embodiment, the first partial pn junction structures J11, J21 and the second partial pn junction structures J12, J22 are arranged in the semiconductor substrate 120, wherein the combination is proportionally determined by the area ratio between the active areas of the first and second partial pn junction structures J11 and J12 of the composite pn junction structure 102-1 and J21 and J22 of the further composite pn junction structure 102-2, which are parallel to the first main surface area 120a of the semiconductor substrate 120. According to one embodiment, the first partial pn junction structure J11 and the second partial pn junction structure J12 of the composite pn junction structure 102-1 and the first partial pn junction structure J21 and the second partial pn junction structure J22 of the further composite pn junction structure 102-2 may be arranged in a laterally isolated common area of ​​the semiconductor substrate 120. According to one embodiment, the first partial pn junction structures J11 , J12 and the second partial pn junction structures J21 , J22 extend vertically into the semiconductor substrate 120 in a depth direction relative to the first main surface region 120 a of the semiconductor substrate 120 .

[0068] Therefore, embodiments relate to a semiconductor device 100 having a "composite" pn junction structure J1 (102-1) having at least two partial pn junction structures J11, J12 to adjust and obtain a desired behavior with respect to its breakdown voltage and / or junction grading coefficient.

[0069] According to one embodiment, Figure 6a The semiconductor device 100 shown in FIG. 1 includes a composite pn junction structure J1 ( 102 - 1 ) in a semiconductor substrate 120 , wherein the composite pn junction structure J1 is arranged to have a predetermined first junction grading coefficient m1 , where m1 ≥ 0.5, and wherein the composite pn junction structure J1 includes a first partial pn junction structure J11 and a second partial pn junction structure J12 .

[0070] The first partial pn junction structure J11 is arranged to have a predetermined first partial junction grading coefficient m 11 , wherein the second partial pn junction structure J12 is arranged to have a predetermined second partial junction grading coefficient m 12 The first part of the predetermined ramp coefficient m 11 The second part of the predetermined ramp coefficient m 12 Different, where m 11 ≠m 12 , where the predetermined first part of the ramp coefficient m 11 and the predetermined second part of the ramp coefficient m 12 At least one of them is greater than 0.5, where m 11 and / or m 12 >0.5. The predetermined first junction grading coefficient m1 of the composite pn junction structure J1 is based on the first partial junction grading coefficient m 11 and the second part of the gradual change coefficient m 12 The predetermined combination.

[0071] Figure 6a Shown with Figure 4 Schematic cross-sectional view of a semiconductor device 100 having a “composite” pn junction (diode) structure J1 as shown in FIG. Figure 6a As shown in , the semiconductor device 100 includes a semiconductor substrate 120 having a first main surface portion 120 a and a second main surface portion 120 b on opposite main sides of the semiconductor substrate 120 .

[0072] The following exemplary description of different layers and regions of the semiconductor substrate 120 extends substantially from the second main surface portion 120b to the first main surface portion 120a of the semiconductor substrate 120. The different regions and structures in the semiconductor substrate 120 are, for example, manufactured during a so-called front-end-of-line (FEOL) process stage.

[0073] Semiconductor substrate 120 may include a p-type semiconductor layer 120-3 (P-substrate 120-3). Disposed on p-type layer 120-3 is another p-type layer 120-4 (e.g., a P-epitaxial layer). P-type semiconductor layer 120-4 may be epitaxially applied to p-type layer 120-3. In other embodiments, p-type layer 120-4 may be an integral part of p-substrate 120-3, rather than an additional epitaxial layer. In other words, the epitaxial layer described herein may be considered optional.

[0074] In epitaxial p-type layer 120-4, a p-type well region 120-5 (P-well 120-5) and another p-type well region 120-6 (P-well 120-6) may be arranged. Semiconductor device 100 also includes a highly doped n-type contact region 120-7 in the form of an implanted region adjacent to the surface regions of p-type wells 120-5 and 120-6.

[0075] The semiconductor device 100 may further comprise a contact and metallization layer stack 140 (BEOL stack, BEOL=backend of line) on the first main surface area 120a of the semiconductor substrate 120 for providing circuit elements for the semiconductor device 100 and optionally for further circuit elements in the semiconductor substrate 120 ( Figure 6a The interconnects 110 (e.g., contact plugs or vias) and contact regions 107 (not shown) are formed. The contact structures and (structured) metallization layers of the metallization stack 140 can be formed using BEOL process steps. Finally, if multiple semiconductor devices 100 are manufactured in a semiconductor substrate 120 such as a semiconductor wafer 120, the semiconductor devices 100 can be separated (diced). For example, a chip-scale packaging process for pad deposition (electrode formation) can be performed, followed by a dicing process.

[0076] like Figure 6a As shown in , a first composite pn junction structure J1 can be realized by using two different implant regions 120-5 and 120-6 in substrate region 120-4. Thus, an n-type contact region 120-7 in substrate region 120-4 is embedded in adjacent (contiguous) implant regions 120-5 and 120-6. Implant region 120-6 and n-type contact region 120-7 in substrate region 120-4 form a first partial pn junction structure J11, while implant region 120-5 and n-type contact region 120-7 in substrate region 122 form a second partial pn junction structure J12 (in this embodiment, adjacent partial pn junction structures J11 and J12). The partial pn junction structure of the second composite pn junction structure J2 can be formed in a manner similar to that described above for the first composite pn junction structure J1.

[0077] like Figure 6bAs shown in FIG, a p-type well region 120-5 (P-well 120-5) is arranged in the second epitaxial p-type layer 120-4 in the semiconductor region 120-4, wherein the p-type well 120-5 only partially surrounds the highly doped n-type contact region 120-7 in the p-type layer 120-4 of the semiconductor substrate 120. Therefore, in the semiconductor region 120-4, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a first partial pn junction structure J11, wherein the p-type well region 120-5 and the highly doped n-type contact region 120-7 form a second partial pn junction structure J12 (in this embodiment, the adjacent partial pn junction structures J11 and J12). A p-type well region 120-5 (P-well 120-5) may be arranged in the epitaxial p-type layer 120-4, for example by forming a desired doping profile in the p-type semiconductor layer 120-4, for example during epitaxial application of the p-type well region 120-5 on the p-type well 120-3 or by performing an implantation step.

[0078] Alternatively, by gradually adjusting the doping level during the epitaxial growth of the layer 120-4, the doping profile in the layer 120-4 may be adjusted to obtain a predetermined grading coefficient m in the portion of the pn junction structure J11, respectively. 12 In other words, by controlling the gas flow of the dopant source gas during epitaxial layer growth, a hyperabrupt junction behavior can be achieved in the portion of the pn junction J11 by creating a depth dependence of the doping level in the epitaxial layer.

[0079] As shown in FIG6C , a first partial pn junction structure J11 can be implemented using an implant region 120-5 in the substrate region 120-4, wherein an n-type contact region 120-7 is embedded in the implant region 120-5. A second partial pn junction structure J12, laterally spaced apart from the first partial pn junction structure J11, can be implemented using an implant region 120-6 in the substrate region 120-4, wherein another n-type contact region 120-7 is embedded in the implant region 120-6. Thus, in this embodiment, the partial pn junction structures J11 and J12 are non-contiguous.

[0080] like Figure 6d As shown in FIG, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a first partial pn junction structure J11, wherein the p-type well region 120-5 and the highly doped n-type contact region 120-7 form a second partial pn junction structure J12, which is laterally spaced apart from the first partial pn junction structure J11. Therefore, in this embodiment, the partial pn junction structures J11 and J12 are non-contiguous.

[0081] Also in Figure 6dAlternatively, by gradually adjusting the doping level during the epitaxial growth of the layer 120-4, the doping profile in the layer 120-4 can be adjusted to obtain a predetermined grading coefficient m in the partial pn junction structure J11. 12 In other words, by controlling the gas flow of the dopant source gas during epitaxial layer growth, a hyperabrupt junction behavior can be achieved in the portion of the pn junction J11 by creating a depth dependence of the doping level in the epitaxial layer.

[0082] According to one embodiment, a predetermined partial junction ramping coefficient m is smaller. 11 or m 12 The partial pn junction structure J11 or J12 of the first partial pn junction structure J11 and the second partial pn junction structure J12 is arranged to provide a predetermined breakdown voltage of the semiconductor device 100 .

[0083] As described in detail above, higher doping levels lead to a less extended space charge region (=depletion region) and thus to a lower (lower) breakdown voltage V bd . In addition, the resulting more linear graded junction behavior leads to a small (smaller) grading coefficient. A high (higher) grading coefficient requires a more hyperabrupt doping profile. However, since an "ideal" abrupt profile cannot be created, a wide (wider) space charge region with low (lower) doping levels results. Low (lower) doping levels lead to a higher breakdown voltage V bd .

[0084] Therefore, the desired (eg, low) breakdown voltage of the semiconductor device 100 can be achieved by having a smaller predetermined partial junction grading coefficient m. 11 or m 12 The first partial pn junction structure J11 and the second partial pn junction structure J12 are adjusted by the partial pn junction structure J11 or J12.

[0085] According to one embodiment, the first partial pn junction structure J11 is arranged to have a first partial junction grading coefficient m greater than 0.50. 11 , where m 11 >0.50, and wherein the second partial pn junction structure J12 is arranged to have a second partial junction grading coefficient m greater than 0.25 12 , where m 12 >0.25.

[0086] According to one embodiment, the first partial pn junction structure J11 is arranged to have a first partial junction grading coefficient m greater than 0.50. 11 , where m 11 >0.50, and wherein the second partial pn junction structure J12 is arranged to have a second partial junction grading coefficient m less than 0.5012 , where m 12 <0.50.

[0087] The predetermined first junction grading coefficient m1 of the composite pn junction structure J1 (102-1) is based on the first partial junction grading coefficient m 11 and the second part of the gradual change coefficient m 12 Therefore, according to the present concept, the first part of the gradual change coefficient m 11 The first part of the pn junction structure J11 can be formed as a hyperabrupt junction, wherein the second part of the junction gradient coefficient m 12 The second part of the pn junction structure J12 can be formed as a linear graded junction (m 12 =0.33±0.10).

[0088] According to one embodiment, the first part of the junction ramp coefficient m 11 and the second part of the gradual change coefficient m 12 The predetermined combination of the first and second partial pn junction structures J11 and J12 is proportionally determined by the area ratio between the active regions 120-5 and 120-6 of the first and second partial pn junction structures J11 and J12, which are parallel to the first main surface region 120a of the semiconductor substrate 120. Therefore, the resulting predetermined first junction grading coefficient m1 can be adjusted through circuit design, that is, by adjusting the ratio of the active regions of the first and second partial pn junction structures J11 and J12.

[0089] According to one embodiment, the first partial pn junction structure J11 and the second partial pn junction structure J12 of the composite pn junction structure J1 (102-1) are electrically connected in parallel. Figures 6a to 6d Furthermore, the first partial pn junction structure J11 and the second partial pn junction structure J12 may extend vertically into the semiconductor substrate 120 in a depth direction relative to the first main surface region 120 a of the semiconductor substrate 120 .

[0090] Those skilled in the art will understand that in all of the above embodiments, the boundary region of the pn junction between 120-7 and 120-4, 120-5, 120-6 may have different electrical properties than the planar junction formed between 120-7 and 120-4, 120-5, 120-6, such as a reduced breakdown voltage in the peripheral region compared to the breakdown voltage in the planar junction, which is parallel to the main surface 120a, and those skilled in the art will understand that additional features may be optionally added in any of the embodiments described herein to avoid undesirable properties in the peripheral region, which may include guard ring implants, edge termination structures, or overlap or underlap of the adjustment region 120-7 relative to 120-4, 120-5, 120-6.

[0091] It should be noted that the recombination junction does not necessarily need to be defined by different p-wells (e.g., Figure 6a to Figure 6d ). On the contrary, as an alternative, for example, a p-well (or a single p-well) and two different contact implants (e.g. 120-7) can also be used to realize two pn junctions having different (partial) junction grading coefficients and connected in parallel circuits. For example, a less steep N profile (or N doping profile) can be realized using phosphorus doping, and a steeper profile (or N doping profile) can be realized using arsenic doping. Therefore, when a p-well is introduced (or a single or common p-well is introduced), this less steep profile including phosphorus doping and the steeper profile including arsenic doping will result in two different (partial) junction grading coefficients. The steepness of the N profile is also adjustable by applying different annealing steps to one (of the two) profiles and the other (of the two) profiles.

[0092] In summary, it is not necessary to have different p-wells or different p-regions for realizing two pn junctions with different (partial) junction grading coefficients and connected in parallel circuit. Instead, a common p-well or two p-wells with the same doping can also be used, wherein different (partial) junction grading coefficients can be realized by adapting the doping profile of the n-doped region. Such adaptation can optionally be applied to, for example, Figures 6a to 6d The present invention is not limited to the embodiments shown in the drawings and may also be applied to other embodiments disclosed herein.

[0093] Figure 7a 1 shows a configuration of a composite pn junction structure 102-1 according to another embodiment. The composite pn junction structure 102-1 includes a pn junction between an n+ region 120-7 and a p-well region 120-5 and another adjacent voltage-dependent capacitor, which in this embodiment can be formed by an inversion charge layer 120-8 at a semiconductor / oxide interface 135 and a bulk or epitaxial layer 120-4 of semiconductor material. For example, the bulk semiconductor material or epitaxial layer 120-4 can be p-doped or intrinsic (i.e., not intentionally doped). One electrode of the voltage-dependent capacitor (corresponding to the cathode) is formed by an inversion charge layer 120-8, which is caused by the presence of fixed oxide charges 136 at or near the semiconductor / oxide interface 135. Directly adjacent to the inversion charge layer 120-8, the volume of the semiconductor material is depleted of mobile charges, such as Figure 7a The depletion region 120-9 in FIG is indicated, and the undepleted semiconductor material below the depletion region forms the other electrode (corresponding to the anode) of the voltage-dependent capacitor. Figure 7a This is indicated in FIG. 1 by means of a dashed line 137 which schematically represents the boundary of the depletion layer.

[0094] In some embodiments, the doping profile of the semiconductor / oxide interface 135 and the p-well 120-5 near the edge is adjusted so that the charge inversion layer 120-8 also exists in this region and an electrical connection is established between the n+ region 120-7 and the surrounding charge inversion layer 120-8.

[0095] The characteristics of the voltage-dependent capacitance formed by the electron inversion charge layer 120-8 can be modeled according to the above formula (A1), which defines the ramp coefficient, zero-bias capacitance, and junction potential for this type of voltage-dependent capacitance. In this regard, the voltage-dependent capacitance formed by the presence of the electron inversion charge layer 120-8 as described above is also considered to be a partial pn junction structure J11, J12; J21, J22 in the context of the composite pn junction structure J1 (102-1), J2 (102-2).

[0096] The effective grading coefficient of the composite pn junction structure 102-1 according to this embodiment is a combination of the grading coefficient of the voltage-dependent capacitor formed due to the presence of the electron inversion charge layer 120-8 and the grading coefficient of the pn junction. The relative contributions of the two grading coefficients can be adjusted by (1) defining the doping profiles of the respective regions of the pn junction and the voltage-dependent capacitor 120-8 and (2) the relative regions of the pn junction and the voltage-dependent capacitor 120-8.

[0097] The voltage dependent capacitor 120 - 8 may be surrounded by a channel stop region 120 - 10 that prevents regions outside of the intended region where the voltage dependent capacitor 120 - 8 is formed from contributing to the voltage dependent capacitor.

[0098] The breakdown voltage of this structure is V bd It is determined by the pn junction structure between the n+ region 120-7 and the p-well region 120-5.

[0099] Figure 7b Another embodiment of the composite pn junction structure 102-1 is shown. The inversion layer 120-8V formed on the vertical sidewall of the deep isolation trench structure 130 is further extended. Figure 7a The voltage dependent capacitance of the embodiment shown in FIG. Other details are similar to those of FIG. Figure 7a those described above and are not repeated here.

[0100] According to another embodiment, an example of which can be referred to below Figures 8a to 8dDiscussed in detail, the semiconductor device 100 further comprises another (= second) composite pn junction structure J2 in the semiconductor substrate 120, wherein the another composite pn junction structure J2 is arranged to have a predetermined another first junction grading coefficient m2, wherein m2 ≥ 0.5, wherein the another composite pn junction structure J2 comprises another first partial pn junction structure J21 and another second partial pn junction structure J22, wherein the another first partial pn junction structure J21 is arranged to have a predetermined another first partial junction grading coefficient m2. 21 , and wherein the another second partial pn junction structure J22 is arranged to have a predetermined another second partial junction grading coefficient m 22 , wherein the predetermined first part of the ramp coefficient m 21 and a predetermined second part of the ramp coefficient m 22 Different, where m 21 ≠m 22 , and wherein the predetermined first part of the ramp coefficient m 21 and a predetermined second part of the ramp coefficient m 22 At least one of them is greater than 0.50, where m 21 and / or m 22 >0.50. The predetermined first junction grading coefficient m2 of the other composite pn junction structure J2 is based on the predetermined first partial junction grading coefficient m 21 and a predetermined second part of the ramp coefficient m 22 The predetermined combination.

[0101] Therefore, embodiments relate to a semiconductor device 100 having a first composite pn junction structure J1 and a second composite pn junction structure J2 to adjust and obtain a desired TVS behavior (TVS=Transient Voltage Suppressor) of the semiconductor device 100 with respect to its breakdown voltage and junction ramping coefficient (the latter, for example, with respect to suppressing the generation of stray harmonics).

[0102] like Figure 8aAs shown in FIG, a first composite pn junction structure J1 can be realized by using two different implant regions 120-5 and 120-6 in substrate region 120-4, wherein a second composite pn junction structure J2 can also be realized by using two different implant regions 120-5 and 120-6 in substrate region 120-4. Thus, an n-type contact region 120-7 in substrate region 120 is embedded in adjacent implant regions 120-5 and 120-6. The n-type contact region 120-7 and the implant region 120-6 form a first partial pn junction structure J11, wherein the n-type contact region 120-7 and the implant region 120-5 form a second partial pn junction structure J12 (in this embodiment, the adjacent partial pn junction structures J11 and J12). Furthermore, another n-type contact region 120-7 and another implantation region 120-6 form another first partial pn junction structure J21, wherein another n-type contact region 120-7 and another implantation region 120-5 form another second partial pn junction structure J22 (in this embodiment, adjacent partial pn junction structures J21, J22).

[0103] like Figure 8b As shown in FIG, in semiconductor region 120-4, highly doped n-type contact region 120-7 and second epitaxial p-type layer 120-4 form first partial pn junction structures J11 and J21, wherein p-type well region 120-5 and highly doped n-type contact region 120-7 form second partial pn junction structures J12 and J22. Therefore, in semiconductor pattern region 120-4, highly doped n-type contact region 120-7 and epitaxial p-type layer 120-4 form first partial pn junction structure J11, wherein p-type well region 120-5 and highly doped n-type contact region 120-7 form second partial pn junction structure J12 (in this embodiment, adjacent partial pn junction structures J11 and J12). In addition, in the semiconductor region 120-4, another highly doped n-type contact region 120-7 and the epitaxial p-type layer 120-4 form another first partial pn junction structure J21, wherein another p-type well region 120-5 and another highly doped n-type contact region 120-7 form another second partial pn junction structure J22 (in this embodiment, adjacent partial pn junction structures J21 and J22).

[0104] 8C , respective first partial pn junction structures J11 and J21 can be implemented by using an implant region 120-5 in the substrate region 120-4, wherein an n-type contact region 120-7 in the substrate region 120-4 is respectively embedded in the implant region 120-5. Respective second partial pn junction structures J12 and J22 can be implemented by using an implant region 120-6 in the substrate region 120-4, wherein another n-type contact region 120-7 in the substrate region 120-4 is embedded in the implant region 120-6.

[0105] More specifically, a first partial pn junction structure J11 of the first composite pn junction structure J1 can be implemented using an implant region 120-5 in the substrate region 120-4, wherein an n-type contact region 120-7 is embedded in the implant region 120-5. A second partial pn junction structure J12 of the first composite pn junction structure J1, laterally spaced apart from the first partial pn junction structure J11, can be implemented using an implant region 120-6 in the substrate region 120-4, wherein another n-type contact region 120-7 is embedded in the implant region 120-6. Therefore, in this embodiment, the partial pn junction structures J11 and J12 of the first composite pn junction structure J1 are non-contiguous.

[0106] Furthermore, another first partial pn junction structure J21 of another (i.e., second) composite pn junction structure J2 can be implemented by using another implant region 120-5 in substrate region 120-4, wherein another n-type contact region 120-7 is embedded in another implant region 120-5. Another second partial pn junction structure J22 of another (i.e., second) composite pn junction structure J2, laterally spaced apart from another first partial pn junction structure J21, can be implemented by using another implant region 120-6 in substrate region 120-4, wherein another n-type contact region 120-7 is embedded in another implant region 120-6. Therefore, in this embodiment, the partial pn junction structures J21 and J22 of another (i.e., second) composite pn junction structure J2 are non-contiguous.

[0107] like Figure 8d As shown in FIG, the highly doped n-type contact region 120-7 and the epitaxial p-type layer 120-4 form a first partial pn junction structure J11, J21, wherein the p-type well region 120-5 and another highly doped n-type contact region 120-7 form a second partial pn junction structure J12, J22.

[0108] More specifically, the highly doped n-type contact region 120-7 and the epitaxial p-type layer 120-4 form a first partial pn junction structure J11 of the first composite pn junction structure J1, wherein the p-type well region 120-5 and the highly doped n-type contact region 120-7 form a second partial pn junction structure J12 of the first composite pn junction structure J1. The second partial pn junction structure J12 is laterally spaced apart from the first partial pn junction structure J11. Therefore, in this embodiment, the partial pn junction structures J11 and J12 are non-contiguous.

[0109] Furthermore, another highly doped n-type contact region 120-7 and second epitaxial p-type layer 120-4 form another first partial pn junction structure J21 of another (i.e., second) composite pn junction structure J2, wherein another p-type well region 120-5 and another highly doped n-type contact region 120-7 form another second partial pn junction structure J22 of another (i.e., second) composite pn junction structure J2. Another second partial pn junction structure J22 is laterally spaced apart from another first partial pn junction structure J21. Therefore, in this embodiment, the partial pn junction structures J21 and J22 are non-contiguous.

[0110] According to one embodiment, the predetermined first partial ramp coefficient m 21 and the second part of the gradual change coefficient m 22 The predetermined combination of the first and second partial pn junction structures J21 and J22 proportionally depends on the area ratio between the active regions 120 - 5 , 120 - 6 parallel to the first main surface region 120 a of the semiconductor substrate 120 .

[0111] According to another embodiment, another first partial pn junction structure J21 and another second partial pn junction structure J22 of another composite pn junction structure J2 ( 102 - 2 ) may be electrically connected in parallel between the interconnection layer 140 and the semiconductor substrate 120 .

[0112] According to another embodiment, another first partial pn junction structure J21 and another second partial pn junction structure J22 of another composite pn junction structure J2 ( 102 - 2 ) may extend vertically from the first main surface region 120 a of the semiconductor substrate 120 into the semiconductor substrate 120 in the depth direction.

[0113] According to another embodiment, the composite pn junction structure J1 ( 102 - 1 ) and the further composite pn junction structure J2 ( 102 - 2 ) may be arranged to have substantially equal grading coefficients, where m1 = m2 .

[0114] According to another embodiment, the composite pn junction structure J1 (102-1) may be arranged to have a predetermined first junction grading coefficient m1, a predetermined first zero-bias junction capacitance C J01and a predetermined first junction voltage potential V J1 , wherein m1=0.5, and wherein the other composite pn junction structure J2 (102-2) can be arranged to have a predetermined second junction grading coefficient m2, a predetermined second zero-bias junction capacitance C J02 and a predetermined second junction voltage potential V J2 , where m2=0.5, and where the predetermined first zero-bias junction capacitance C of the composite pn junction structure J1 (102-1) J01 and a predetermined second zero-bias junction capacitance C of another composite pn junction structure J2 (102-2) J02 Basically equal.

[0115] According to another embodiment, the composite pn junction structure J1 (102-1) is anti-series connected to another composite pn junction structure J2 (102-2), wherein the first junction grading coefficient m1 and the second junction combined grading coefficient m2 are greater than 0.5, wherein m1 and m2>0.5 (hyperabrupt).

[0116] According to another embodiment, the composite pn junction structure J1 (102-1) may be arranged to have a predetermined first zero-bias junction capacitance C J01 and the predetermined first junction potential V J1 , and the other composite pn junction structure J2 (102-2) can be arranged to have a predetermined second zero-bias junction capacitance C J02 and a predetermined second junction voltage potential V J2 , wherein the predetermined first zero-bias junction capacitance C of the composite pn junction structure J1 (102-1) J01 and a predetermined second zero-bias junction capacitance C of another composite pn junction structure J2 (102-2) J02 They may be substantially equal, and wherein the first junction gradient coefficient m1 and the second junction gradient coefficient m2 may be substantially equal.

[0117] According to one embodiment, the predetermined junction voltage potential V of the composite pn junction structure J1 (102-1) is J1 and a predetermined second junction voltage potential V of another composite pn junction structure J2 (102-2) J2 Basically equal.

[0118] According to one embodiment, the semiconductor device forms an ESD protection device (ESD=Electrostatic Discharge).

[0119] about Figures 8a to 8d, an embodiment is described having a composite pn junction structure 102-1 (J1) and another composite pn junction structure 102-2 (J2) integrated within the same semiconductor substrate 120. Of course, the present invention is not limited to such a configuration and may also be implemented by electrically connecting separate chips having the composite pn junction structure 102-1 (J1) and another composite pn junction structure 102-2 (J2), for example, using bonding wires or any other technique known in the art.

[0120] Although some aspects have been described as features in the context of an apparatus, it is clear that such descriptions may also be considered as descriptions of corresponding features of a method. Although some aspects have been described as features in the context of a method, it is clear that such descriptions may also be considered as descriptions of corresponding features of the functionality of the apparatus.

[0121] In the foregoing detailed description, it can be seen that in order to simplify the disclosure, various features are grouped together in the examples. This method of disclosure should not be interpreted as reflecting an intention that the claimed examples require more features than expressly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention may lie in less than all the features of a single disclosed example. Therefore, the following claims are incorporated herein into the detailed description, where each claim may stand on its own as a separate example. Although each claim may stand on its own as a separate example, it should be noted that although a dependent claim may mention a specific combination with one or more other claims in a claim, other examples may also include the following combinations: a combination of a dependent claim with the subject matter of each other dependent claim or a combination of each feature with other dependent claims or independent claims. Unless it is stated that a specific combination is not intended, such a combination is proposed herein. In addition, it is intended that features of a claim will also be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0122] Although specific embodiments have been illustrated and described herein, it will be apparent to those skilled in the art that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

[0123] Reference Numbers List:

[0124] (If in doubt, the manual takes precedence)

[0125] 32-42 different injection doses

[0126] 100 semiconductor devices

[0127] 102 The first pair of pn junction structures

[0128] 102-1, 102-2 First and second parallel circuits / composite pn junction structure

[0129] 107 First Terminal

[0130] 108 Second terminal

[0131] 110 Interconnection

[0132] 120 semiconductor substrate

[0133] 120a, 120b first and second main surface portions

[0134] 120-1 n-type substrate

[0135] 120-2 p-type semiconductor layer

[0136] 120-3 buried p-type semiconductor layer or p-type substrate

[0137] 120-4 p-type semiconductor layer

[0138] 120-5 p-type well region

[0139] 120-6 p-type well region

[0140] 120-7 n-type contact area

[0141] 120-8 Charge Reversal Layer

[0142] 120-9 Depletion Region

[0143] 120-10 Channel stop area

[0144] 122 Separated semiconductor regions

[0145] 124 Separated semiconductor regions

[0146] 130 Deep Isolation Trench

[0147] 132 Semiconductor Filler

[0148] 134 Pad Oxide

[0149] 135 Semiconductor / Oxide Interface

[0150] 136 Fixed Oxide Charge

[0151] 137 Depletion Region Boundary

[0152] C J01 , C J02 First and second zero-bias capacitors

[0153] C J011 , C J012 The first and second parts of the zero-bias capacitor

[0154] J1, J2 composite pn junction structure

[0155] J11, J21 Type I partial pn junction structure

[0156] J12, J22 Type II partial pn junction structure

[0157] m1, m2 first and second junction ramp coefficients

[0158] m 11 , m 12 Partial junction ramp coefficient

[0159] V bd Breakdown voltage

[0160] V J1 , V J2 The first and second junction voltage potentials

[0161] V J11 , V J12 The voltage potential of the first and second junctions

[0162] PH3 Signal power level of the spurious third harmonic.

Claims

1. A semiconductor device (100), comprising: A composite pn junction structure (J1) in a semiconductor substrate (120), wherein the composite pn junction structure (J1) is arranged to have a predetermined first junction gradation coefficient m1, wherein m1≥0.50, The composite pn junction structure (J1) includes a first partial pn junction structure (J11) and a second partial pn junction structure (J12). The first partial pn junction structure (J11) is arranged to have a predetermined first partial junction gradient coefficient m 11 , and wherein the second partial pn junction structure (J12) is arranged to have a predetermined second partial junction gradient coefficient m 12 , Wherein, the predetermined first part of the junction ramp coefficient m 11 The second part of the predetermined ramp coefficient m 12 Different, among which m 11 ≠m 12 ,and Wherein, the predetermined first part of the junction ramp coefficient m 11 and the second part of the slow-changing coefficient m 12 At least one of them is greater than 0.50, where m 11 >0.50 and / or m 12 >0.50, The predetermined first junction grading coefficient m1 of the composite pn junction structure (J1) is based on the first partial junction grading coefficient m 11 and the second part of the gradual change coefficient m 12 The predetermined combination.

2. The semiconductor device (100) according to claim 1, wherein: The first partial pn junction structure (J11) and the second partial pn junction structure (J12) have a smaller predetermined partial junction gradient coefficient m 11 or m 12 The partial pn junction structure is arranged to provide a predetermined breakdown voltage (V) of the semiconductor device (100) equal to or less than 25V. bd ).

3. The semiconductor device (100) according to claim 1 or 2, wherein: The predetermined combination depends proportionally on the area ratio between active regions of the first partial pn junction structure (J11) and the second partial pn junction structure (J12) parallel to the first main surface region (120a) of the semiconductor substrate (120).

4. The semiconductor device (100) according to claim 1 or 2, wherein: The first partial pn junction structure (J11) and the second partial pn junction structure (J12) of the composite pn junction structure (J1) are electrically connected in parallel.

5. The semiconductor device (100) according to claim 1 or 2, wherein: The first partial pn junction structure (J11) is arranged to have a first partial junction grading coefficient m greater than 0.50 11 , where m 11 >0.50, and wherein the second partial pn junction structure (J12) is arranged to have a second partial junction grading coefficient m greater than 0.25 12 , where m 12 >0.

25.

6. The semiconductor device (100) according to claim 1 or 2, wherein: The first partial pn junction structure (J11) is arranged to have a first partial junction grading coefficient m greater than 0.50 11 , where m 11 >0.50, and wherein the second partial pn junction structure (J12) is arranged to have a second partial junction grading coefficient m less than 0.50 12 , where m 12 <0.

50.

7. The semiconductor device (100) according to claim 1 or 2, wherein: The first partial pn junction structure (J11) and the second partial pn junction structure (J12) extend vertically into the semiconductor substrate (120) in a depth direction relative to a first main surface region (120a) of the semiconductor substrate (120).

8. The semiconductor device (100) according to claim 1 or 2, further comprising: Another composite pn junction structure (J2) in the semiconductor substrate (120), wherein the another composite pn junction structure (J2) is arranged to have a predetermined second junction gradation coefficient m2, wherein m2≥0.50, The another composite pn junction structure (J2) includes another first partial pn junction structure (J21) and another second partial pn junction structure (J22), The first pn junction structure (J21) is arranged to have a predetermined first pn junction gradient coefficient m. 21 , and wherein the another second partial pn junction structure (J22) is arranged to have a predetermined another second partial junction grading coefficient m 22 , Among them, the predetermined first part of the gradual change coefficient m 21 The predetermined second part of the ramp coefficient m 22 Different, among which m 21 ≠m 22 ,and Among them, the predetermined first part of the gradual change coefficient m 21 and the predetermined second part of the ramp coefficient m 22 At least one of them is greater than 0.50, where m 21 >0.50 and / or m 22 >0.50, The predetermined second junction gradation coefficient m2 of the other composite pn junction structure (J2) is based on the predetermined other first part junction gradation coefficient m 21 and the predetermined second part of the ramp coefficient m 22 The predetermined combination.

9. The semiconductor device (100) according to claim 8, wherein: The predetermined first part of the ramp coefficient m 21 and the predetermined second part of the ramp coefficient m 22 The predetermined combination depends proportionally on: the area ratio between the active areas of the another first partial pn junction structure (J21) and the another second partial pn junction structure (J22) parallel to the first main surface area (120a) of the semiconductor substrate (120).

10. The semiconductor device (100) according to claim 8, wherein: The another first partial pn junction structure (J21) and the another second partial pn junction structure (J22) of the another composite pn junction structure (J2) are electrically connected in parallel in the semiconductor substrate (120).

11. The semiconductor device (100) according to claim 8, wherein: The another first partial pn junction structure (J21) and the another second partial pn junction structure (J22) extend vertically from a first main surface region (120a) of the semiconductor substrate (120) into the semiconductor substrate (120) in a depth direction.

12. The semiconductor device (100) according to claim 8, wherein: The composite pn junction structure (J1) and the further composite pn junction structure (J2) are arranged to have substantially equal grading coefficients, wherein m1=m2.

13. The semiconductor device (100) according to claim 8, wherein: The composite pn junction structure (J1) is connected in anti-series to the other composite pn junction structure (J2).

14. The semiconductor device (100) according to claim 13, in, The composite pn junction structure (J1) is arranged to have the predetermined first junction gradation coefficient m1, the predetermined first zero bias junction capacitance C J01 and the predetermined first junction potential V J1 , where m1 = 0.50, and The other composite pn junction structure (J2) is arranged to have a predetermined second junction gradient coefficient m2, a predetermined second zero bias junction capacitance C J02 and a predetermined second junction voltage potential V J2 , where m2 = 0.50, and Wherein, the predetermined first zero bias junction capacitance C of the composite pn junction structure (J1) J01 and the predetermined second zero bias junction capacitance C of the other composite pn junction structure (J2) J02 Basically equal.

15. The semiconductor device (100) according to claim 13, in, The first junction taper coefficient m1 and the second junction taper coefficient m2 are greater than 0.50, wherein m1>0.50 and m2>0.

50.

16. The semiconductor device (100) according to claim 15, in, The composite pn junction structure (J1) is arranged to have a predetermined first zero bias junction capacitance C J01 and the predetermined first junction potential V J1 ,as well as The other composite pn junction structure (J2) is arranged to have a predetermined second zero bias junction capacitance C J02 and a predetermined second junction voltage potential V J2 , Wherein, the predetermined first zero bias junction capacitance C of the composite pn junction structure (J1) J01 and the predetermined second zero bias junction capacitance C of the other composite pn junction structure (J2) J02 are substantially equal, and The first junction gradual change coefficient m1 and the second junction gradual change coefficient m2 are substantially equal.

17. The semiconductor device (100) according to claim 14 or 16, wherein: The predetermined first junction voltage potential V of the composite pn junction structure (J1) J1 and the predetermined second junction voltage potential V of the other composite pn junction structure (J2) J2 Basically equal.

18. The semiconductor device (100) according to claim 8, wherein: The semiconductor device (100) forms an electrostatic discharge (ESD) device.

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