Oxygen-inserted Si layers in vertical trench power devices

Abstract

Oxygen-inserted Si layer in vertical trench power device. The semiconductor device includes a gate trench extending into a Si substrate; a body region in the Si substrate adjacent to the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and filled with a conductive material, the conductive material contacting the source region at the sidewalls of the contact trench and a highly doped body contact region at the bottom of the contact trench; a diffusion barrier structure formed along the sidewalls of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and extending vertically along the sidewalls of the gate trench. A corresponding manufacturing method is also described.

Description

Background Art

[0001] As the size of trench-based transistors shrinks, the impact of highly doped source / body contacts on the net body doped near the channel region becomes more important. For a wider lateral distribution of source / body contact diffusion with a doping level 2-3 orders of magnitude higher than the body doping, the Vth (threshold voltage) and RonA (on-state resistance) of the device increase. Increasing the distance between the source / body contact and the channel region causes the body to be depleted at high drain voltages, which may lead to high DIBL (drain-induced barrier lowering). In addition, the process window variations of both trench width and contact width and contact misalignment must become smaller to avoid these adverse effects (higher Vth, higher RonA, and higher DIBL).

[0002] Therefore, better control of the lateral outdiffusion of source / body contact doping is desirable. Summary of the invention

[0003] According to an embodiment of a semiconductor device, the semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent to the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and filled with a conductive material, the conductive material contacting the source region at the sidewalls of the contact trench and a highly doped body contact region at the bottom of the contact trench; a diffusion barrier structure formed along the sidewalls of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and extending vertically along the sidewalls of the gate trench.

[0004] In an embodiment, the diffusion barrier structure may extend onto the front main surface of the Si substrate into which the gate trench and the contact trench are formed.

[0005] Alone or in combination, the diffusion barrier structure may extend along the front main surface of the Si substrate to the conductive material filling the contact trench.

[0006] Either alone or in combination, a Si capping layer of the diffusion barrier structure may be present along the bottom of the gate trench instead of alternating layers of Si and oxygen-doped Si.

[0007] Either alone or in combination, the gate trench may include: a gate dielectric lining the sidewalls and bottom of the gate trench; a gate electrode disposed in the upper portion of the gate trench; a field electrode embedded in the field dielectric in the lower portion of the gate trench below the gate electrode; an insulating spacer vertically separating the gate electrode from the field electrode; and a silicon nitride layer separating the insulating spacer and the field dielectric from the gate dielectric.

[0008] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming a gate trench extending into a Si substrate; forming a body region in the Si substrate adjacent to the gate trench; forming a source region in the Si substrate above the body region; forming a contact trench extending into the Si substrate and filled with a conductive material, the conductive material contacting the source region at the sidewalls of the contact trench and a highly doped body contact region at the bottom of the contact trench; forming a diffusion barrier structure along the sidewalls of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and forming a channel region in the Si capping layer, and the channel region extending vertically along the sidewalls of the gate trench.

[0009] In an embodiment, forming the diffusion barrier structure may include: epitaxially growing alternating layers of Si and oxygen-doped Si on sidewalls and a bottom of the gate trench; and epitaxially growing a Si capping layer on the alternating layers of Si and oxygen-doped Si.

[0010] Either alone or in combination, the method may further comprise epitaxially growing alternating layers of Si and oxygen-doped Si and a Si capping layer on the front main surface of a Si substrate into which the gate trench is formed.

[0011] Either alone or in combination, the method may further include, after forming the diffusion barrier structure, implanting a dopant species of opposite conductivity type into the Si substrate to form the body and source regions.

[0012] Alone or in combination, the method may further include: forming a gate dielectric on the Si capping layer.

[0013] The gate dielectric may be formed by a deposition process, a thermal oxidation process, or both a deposition process and a thermal oxidation process, alone or in combination.

[0014] Either alone or in combination, the method may further include: forming a silicon nitride layer on the gate dielectric; forming a field dielectric on the silicon nitride layer; after forming the field dielectric, filling the gate trench with a first conductive material; and recessing the first conductive material to a first depth in the gate trench to form a field electrode.

[0015] Alone or in combination, the method may further include: removing the field dielectric over the field electrode to expose the silicon nitride layer in a region of the gate trench over the field electrode; and covering the field electrode with an insulating spacer after removing the field dielectric over the field electrode.

[0016] Alone or in combination, covering the field electrode with the insulating spacer may include: filling the gate trench with a dielectric material after removing the field oxide over the field electrode; and recessing the dielectric material to a second depth in the gate trench over the field electrode.

[0017] Alone or in combination, filling the gate trench with the dielectric material may include depositing a high density plasma oxide in the gate trench by chemical vapor deposition.

[0018] Alone or in combination, covering the field electrode with the insulating spacer may include forming a thermal oxide on the field electrode by a thermal oxidation process.

[0019] Either alone or in combination, the method may further include: removing the silicon nitride layer above the insulating spacer; filling the gate trench with a second conductive material after removing the silicon nitride layer above the insulating spacer; and recessing the second conductive material to a third depth in the gate trench to form a gate electrode.

[0020] Either alone or in combination, the method may further include, after forming the gate electrode, implanting a dopant species of opposite conductivity type into the Si substrate to form a body region and a source region.

[0021] Either alone or in combination, the contact trenches may be formed after implanting dopant species of the opposite conductivity type into the Si substrate.

[0022] Either alone or in combination, the method may further include: removing the silicon nitride layer above the insulating spacer; filling the gate trench with a second conductive material after removing the silicon nitride layer above the insulating spacer; and recessing the second conductive material to a third depth in the gate trench to form a gate electrode.

[0023] Either alone or in combination, the method may further include: before forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, forming an insulating spacer in the lower portion of the gate trench, the insulating spacer covering the bottom and the lower portion of the sidewall of the gate trench to prevent the formation of the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure on the bottom and the lower portion of the sidewall of the gate trench; and after forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, removing the insulating spacer from the lower portion of the gate trench.

[0024] Either alone or in combination, the method may further include, after removing the insulating spacer from the lower portion of the gate trench, epitaxially growing a Si capping layer of the diffusion barrier structure on the alternating layers of Si and oxygen-doped Si and on the lower portion of the bottom and sidewalls of the gate trench.

[0025] Either alone or in combination, forming an insulating spacer in a lower portion of the gate trench may include: forming a high-density plasma oxide on the sidewalls and bottom of the gate trench, the high-density plasma oxide being thinner along the sidewalls and thicker on the bottom of the gate trench; and removing the high-density plasma oxide from the sidewalls of the gate trench.

[0026] Either alone or in combination, forming an insulating spacer in the lower portion of the gate trench may include: forming a silicon oxide layer on the sidewalls and bottom of the gate trench; forming a silicon nitride layer on the silicon oxide layer above the sidewalls and bottom of the gate trench; forming an opening in the silicon nitride layer at the bottom of the gate trench to expose the silicon oxide layer at the bottom of the gate trench; thermally oxidizing a region of the Si substrate below the exposed silicon oxide layer at the bottom of the gate trench; and removing the silicon nitride layer and the silicon oxide layer from the sidewalls of the gate trench.

[0027] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are detailed in the following description.

[0029] Figure 1 A partial cross-sectional view of an embodiment of a trench based semiconductor device having a diffusion barrier structure is illustrated.

[0030] Figures 2A to 2M The diagram shows the different stages of the manufacturing process. Figure 1 ] A corresponding cross-sectional view of a trench-based semiconductor device is shown in FIG.

[0031] Figure 3 A partial cross-sectional view of another embodiment of a trench-based semiconductor device having a diffusion barrier structure is illustrated.

[0032] Figure 4 A partial cross-sectional view of another embodiment of a trench-based semiconductor device having a diffusion barrier structure is illustrated.

[0033] FIG. 5A to FIG. 5F The diagram illustrates the various stages of the fabrication process used to form the diffusion barrier structure. Figure 4 ] A corresponding cross-sectional view of a trench-based semiconductor device is shown in FIG.

[0034] 6A to 6H illustrates during different stages of another fabrication process for forming a diffusion barrier structure Figure 4] A corresponding cross-sectional view of a trench-based semiconductor device is shown in FIG. DETAILED DESCRIPTION

[0035] The embodiments described herein control the lateral outdiffusion of source / body contact doping of trench-based transistors, thereby allowing narrower Vth, RonA and DIBL distributions for given geometric variations of highly doped source / body contacts and gate trenches, and / or allowing the lateral spacing between the source / body contact and the channel region of the device to be reduced for given Vth, RonA and DIBL windows. By inserting a diffusion barrier structure extending along at least a portion of the channel region of the device, the lateral outdiffusion of source / body contact doping can be better controlled. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si, which are arranged between the highly doped source / body contact and the channel region of the device. The oxygen-doped Si layer of the diffusion barrier structure limits the lateral outdiffusion of source / body contact doping, thereby controlling the lateral outdiffusion of source / body contact doping in the direction toward the channel region. The diffusion barrier structure enables, for example, a narrower Vth distribution of a narrow trench MOSFET, or enables a smaller distance between the contact trench and the gate trench for a predetermined Vth distribution width. By incorporating a diffusion barrier structure, the charge carrier mobility in the channel region can be increased, for example, by up to 80%. By incorporating a diffusion barrier structure, gate leakage can be reduced, for example, by up to 50%, and gate reliability can be improved, compared to gate oxides grown on conventional silicon epitaxial layers. Embodiments of semiconductor devices having such a diffusion barrier structure, and corresponding manufacturing methods are described in more detail below.

[0036] Figure 1 A partial cross-sectional view of an embodiment of a trench-based semiconductor device 100 is illustrated. The semiconductor device 100 includes one or more gate trenches 102 extending into a Si substrate 104. Figure 1A single gate trench 102 is shown in the figure, however, the semiconductor device 100 may include multiple gate trenches 102 having the same or similar configuration but outside the view. The Si substrate 104 may include one or more Si epitaxial layers grown on a base Si substrate. The gate electrode 106 disposed in each gate trench 102 is insulated from the surrounding semiconductor material by a gate dielectric 108. A field electrode 110 may be disposed in each gate trench 102 below the corresponding gate electrode 106 and insulated from the surrounding semiconductor material and the gate electrode 106 by a field dielectric 112. The gate dielectric 108 and the field dielectric 112 may include the same or different materials and may have the same or different thicknesses. Alternatively, the field electrode 110 may be formed in a different trench separate from the gate trench 102 or omitted entirely, depending on the type of semiconductor device. In one embodiment, an insulating spacer 111 such as a high density plasma oxide vertically separates the gate electrode 106 from the field electrode 110 , and a silicon nitride layer 113 separates the insulating spacer 111 and the field dielectric 112 from the gate dielectric 108 in the region of the gate trench 102 below the gate electrode 106 .

[0037] The trench-based semiconductor device 100 may be a power semiconductor device, such as a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), etc. The trench-based semiconductor device 100 further includes: a body region 114 formed in a Si substrate 104. The body region 114 includes a channel region 116 extending vertically along a sidewall 118 of a corresponding gate trench 102. The semiconductor device 100 also includes a source region 120 formed in the Si substrate 104 above the body region 114. A vertical current flowing through the channel region 116 is controlled by applying a gate potential to the gate electrode 106. A drain or collector region (not shown) is formed below a drift region 122 of the device 100. Depending on the type of device, additional structures may be formed in the drift region 122 and / or between the drift region 122 and the drain / collector region. For example, in the case of an IGBT type device, a charge compensation structure may be formed in the drift region 122 and / or a field stop layer may be formed between the drift region 122 and the drain / collector region. Again, any type of semiconductor device with a trench gate may utilize the diffusion barrier layer teachings described herein.

[0038] The trench-based semiconductor device 100 further includes a contact trench 124 extending into the Si substrate 104. The contact trench 124 is separated from each adjacent gate trench 102 by a portion of the source region 120 and a portion of the body region 114. The contact trench 124 is filled with a conductive material 126 (such as doped polysilicon, metal, etc.) that contacts the source region 120 at the sidewalls of the contact trench 124 and a highly doped body contact region 128 at the bottom of the contact trench.

[0039] The highly doped body contact region 128 at the bottom of the contact trench 124 has the same doping type as the body region 114, but at a higher concentration to provide a good ohmic contact with the conductive material 126 filling the contact trench 124. For example, in the case of an n-channel device, the source region 120 and the drift region 122 are n-type doped, and the body region 114, the channel region 116, and the highly doped body contact region 128 are p-type doped. Conversely, in the case of a p-channel device, the source region 120 and the drift region 122 are p-type doped, and the body region 114, the channel region 116, and the highly doped body contact region 128 are n-type doped. In either case, the gate and contact trenches 102, 124 extend from the same front surface 130 into the Si substrate 104.

[0040] The diffusion barrier structure 132 extends along the sidewalls 118 and the bottom of the gate trench 102 and is disposed between the channel region 116 and the adjacent highly doped body contact region 128. The diffusion barrier structure 132 includes alternating layers of Si 134 and oxygen-doped Si 136. The alternating layers of Si 134 and oxygen-doped Si 136 form oxygen-doped silicon regions grown by epitaxy. In an embodiment, the oxygen concentration of each oxygen-doped Si layer 136 is lower than 5e14cm-3. Each oxygen-doped Si layer 136 may have a thickness in the atomic range (e.g., one or several atomic thicknesses) or in the nanometer range to ensure sufficient crystal information for growing Si on the oxygen-doped Si layer 136. The alternating layers of Si 134 and oxygen-doped Si 136 may be achieved by epitaxially growing Si layers with oxygen layers adsorbed on the surfaces of the Si layers, respectively, for example, with a specific limited thickness for the oxygen-doped Si layer 136 to ensure sufficient Si growth.

[0041] Figure 1An exploded view of a diffusion barrier structure 132 is provided, which may also include a Si buffer layer 138 below the alternating layers of Si 134 and oxygen-doped Si 136, and a Si capping layer 140 epitaxially grown on the alternating layers of Si 134 and oxygen-doped Si 136. The Si buffer layer 138 may be relatively thin, for example, in the range of 2-5 nm thick. The Si buffer layer 138 may be grown after an implantation or etching step. The capping layer 140 provides high carrier mobility in this region of the device 100. The channel region 116 is formed in the Si capping layer 140 and extends vertically along the sidewalls 118 of the gate trench 102. The buffer layer 138 may be omitted. The oxygen-doped Si layer 136 of the diffusion barrier structure 132 limits the lateral outdiffusion of the source / body contact doping, thereby controlling the lateral outdiffusion from each highly doped body contact region 128 in the direction toward the channel region 116. The oxygen-doped Si layer 136 of the diffusion barrier structure 132 may also improve carrier mobility within the vertical channel region 116 of the device 100 .

[0042] The oxygen-doped Si layer 136 of the diffusion barrier structure 132 can be formed by introducing a partial monolayer of oxygen into the Si lattice. The oxygen atoms are placed intermittently to minimize damage to the Si lattice. The Si atomic layer 134 separates the adjacent oxygen partial monolayers 136. The alternating layers of Si 134 and oxygen-doped Si 136 can be formed by Si epitaxy with oxygen absorption at different steps. For example, the temperature and gas conditions can be controlled during the epitaxy process to form a partial oxygen monolayer 136. Oxygen can be introduced / incorporated between the epitaxial layers 134 of Si, for example, by controlling the introduction of an oxygen precursor into the epitaxial chamber. The resulting diffusion barrier structure 132 includes a monolayer 136 interlaced with a standard Si epitaxial layer 134 without oxygen, and the monolayer 136 mainly includes Si but has a certain doping level or concentration level of oxygen. The diffusion barrier structure 132 also includes a Si capping layer 140 epitaxially grown on the alternating layers of Si 134 and oxygen-doped Si 136, or the Si capping layer 140 can be omitted. The capping layer 140 of epitaxial Si is doped to form the channel region 116 of the device 100. Additionally or alternatively, a diffusion barrier structure 132 may extend over the upper side 115 of the body region 114 and be disposed between the source domain 120 and the body region 114 at the upper side of the body region 114.

[0043] By applying a gate potential (indicated by “-ve bias” in FIG. 2 ) to the gate electrode 106, current flows through the high mobility channel region 116 of the semiconductor device 100. The current path includes the source region 120, the channel region 116, and the drift region 122. As the current path progresses vertically into the drift region 122, the current expands outward from the channel region 116, as shown in FIG. Figure 1 Indicated by the dotted line in .

[0044] Figures 2A to 2M The diagram shows the different stages of the manufacturing process. Figure 1 A corresponding cross-sectional view of a trench-based semiconductor device 100 is shown in FIG.

[0045] Figure 2A The semiconductor device 100 is shown after forming the gate trench 102. The gate trench 102 can be etched into the Si substrate 104 using any common trench formation process, such as applying a mask / insulating material 200 on the front major surface 130 of the Si substrate 104 and etching the gate trench 102 into the Si substrate 104 through the opening 201 in the mask 200.

[0046] Figure 2B The semiconductor device 100 is shown after epitaxially growing alternating layers of Si 134 and oxygen-doped Si 136 of the diffusion barrier structure 132 on the sidewalls 118 and bottom of the gate trench 102. According to this embodiment, the alternating layers of Si 134 and oxygen-doped Si 136 are epitaxially grown on the sidewalls 118 and bottom of the gate trench 102 after the gate trench 102 is etched into the Si substrate 104, but before the gate electrode 106 and the gate dielectric 108 are formed in the gate trench 102.

[0047] Figure 2C The semiconductor device 100 is shown after epitaxially growing a capping layer 140 of Si on the alternating layers of Si 134 and oxygen-doped Si 136 to form the diffusion barrier structure 132. In one embodiment, the capping layer 140 of epitaxial Si has the same standard in-situ doping concentration as the alternating layers of Si 134 and oxygen-doped Si 136, and may then be doped with a different dopant species and concentration to form the channel region 116 of the semiconductor device 100. Alternatively, the capping layer 140 may have a different in-situ doping concentration compared to the alternating layers of Si 134 and oxygen-doped Si 136. In either case, the capping layer 140 may be used to implement the channel region 116 of the semiconductor device 100.

[0048] Figure 2D The semiconductor device 100 is shown after forming the gate dielectric 108 along the diffusion barrier structure 132. Any common semiconductor manufacturing process for forming the gate dielectric may be used, such as, for example, a deposition process, a thermal oxidation process, or both a deposition process and a thermal oxidation process.

[0049] Figure 2E The semiconductor device 100 is shown after forming a silicon nitride layer 113 on the gate dielectric 108. Any common semiconductor manufacturing process for forming the silicon nitride layer may be used, such as, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0050] Figure 2F The semiconductor device 100 is shown after the following process: a field dielectric 112 such as a field oxide is formed on the silicon nitride layer 113, and after the formation of the field dielectric 1121, the gate trench 102 is filled with a first conductive material 202 such as doped polysilicon, metal, etc.

[0051] Figure 2G The semiconductor device 100 is shown after the first conductive material 202 is recessed to a first depth D1 in the gate trench 102 to form the field electrode 110. Any common semiconductor manufacturing process for recessing the electrode material in the trench can be used, for example, such as plasma etching.

[0052] Figure 2H The semiconductor device 100 is shown after the field dielectric 112 is removed from the gate trench 102 above the field electrode 110 to expose the silicon nitride layer 113 in the region of the gate trench 102 above the field electrode 110. Any common semiconductor manufacturing process for removing the field dielectric from the trench can be used, for example, such as HF etching.

[0053] Fig.2I The semiconductor device 100 is shown after the gate trench 102 is filled with a dielectric material 204. In one embodiment, a high density plasma chemical vapor deposition (HDP CVD) process is used to fill the gate trench 102 with a silicon-based dielectric such as silicon oxide. Other processes can be used to produce a void-free gate trench 102, such as a multi-step deposition / etch process, a spin-on dielectric process, etc.

[0054] Figure 2J The semiconductor device 100 is shown after the dielectric material 204 is recessed to a second depth D2 in the gate trench 102 above the field electrode 110, where D2 < D1. Any common semiconductor manufacturing process for recessing the dielectric material in the trench can be used, for example, such as HF etching in the case of an oxide. The portion of the dielectric material 204 remaining in the gate trench 102 forms an insulating spacer 111 that covers the field electrode 110. Alternatively, in order to form the insulating spacer 111 from HDP oxide, the insulating spacer 111 can alternatively be a thermal oxide. In this case, by using a thermal oxidation temperature lower than the thermal oxidation temperature usually used to form a thermal oxide, the oxygen-doped Si layer 136 of the diffusion barrier structure 132 can be protected during the thermal oxidation process.

[0055] Figure 2KThe semiconductor device 110 is shown after removing the silicon nitride layer 113 from the gate trench 102 above the insulating spacer 111. Any common semiconductor manufacturing process for removing silicon nitride from a trench can be used, for example, wet etching, plasma etching, etc. After removing the silicon nitride layer 113 above the insulating spacer 111, the gate trench 102 is filled with a second conductive material 206 such as doped polysilicon, metal, etc.

[0056] Figure 2L The semiconductor device is shown after recessing the second conductive material 206 to a third depth D3 in the gate trench 102 to form the gate electrode 106, where D3 < D2. Any common semiconductor manufacturing process for recessing the gate electrode material in a trench can be used, for example, plasma etching, wet etching, etc.

[0057] Figure 2M The semiconductor device 100 is shown after injecting a dopant species of the opposite conductivity type into the Si substrate 104 and activating it by annealing to form the body 114 and the source region 120 of the device 100. In the case of an n-channel device, the source dopant can be phosphorus, arsenic, etc., and the body dopant can be boron, gallium, etc. In the case of a p-channel device, the source dopant can be boron, gallium, etc., and the body dopant can be phosphorus, arsenic, etc.

[0058] The contact trench 124 can be formed after injecting a dopant species of the opposite conductivity type into the Si substrate 104 to form the body 114 and the source region 120 of the device 100. For example, the contact trench 124 can be etched into the front main surface 130 of the Si substrate 104, a highly doped body contact region 128 can be formed at the bottom of the contact trench 124 by in-trench bottom implantation, and then filled with a conductive material 126 that contacts the source region 120 at the sidewalls of the contact trench 124 and the highly doped body contact region 128 at the bottom of the contact trench 124, as shown, for example, Figure 1 in.

[0059] Figure 3 A partial cross-sectional view of another embodiment of a trench-based semiconductor device 300 having a diffusion barrier structure 132 is illustrated. The diffusion barrier structure 132 includes alternating layers of Si 134 and oxygen-doped Si 136 and a Si capping layer 140 epitaxially grown on the alternating layers of Si 134 and oxygen-doped Si 136, where the channel region 116 of the device 300 is formed in the Si capping layer 140 and extends vertically along the sidewalls 118 of the gate trench 102. Figure 3 The embodiment shown in Figure 1 is similar to the embodiment shown in Figure 3The diffusion barrier structure 132 of the device 300 shown in FIG. 1 also extends onto the front major surface 130 of the Si substrate 104 in which the gate trench 102 and the contact trench 126 are formed. In one embodiment, the diffusion barrier structure 132 extends along the front major surface 130 of the Si substrate 104 to the conductive material 126 filling the contact trench 126. After etching the gate trench 102 into the Si substrate 104 and before forming the alternating layers of Si 134 and oxygen-doped Si 136, the diffusion barrier structure 132 is removed by removing the conductive material 126 filling the contact trench 126. Figure 2A The mask / insulating material 200 shown in FIG. 1 can be used to form the diffusion barrier structure 132 in this manner. In this way, the diffusion barrier structure 132 will also be epitaxially grown on the front major surface 130 of the Si substrate 104.

[0060] Figure 4 A partial cross-sectional view of another embodiment of a trench-based semiconductor device 400 having a diffusion barrier structure 132 comprising alternating layers of Si 134 and oxygen-doped Si 136 and a capping layer 140 epitaxially grown on the alternating layers of Si 134 and oxygen-doped Si 136 is illustrated, wherein a channel region 116 of the device 400 is formed in the Si capping layer 140 and extends vertically along the sidewalls of the gate trench 102. Figure 4 The embodiment shown in is similar to Figure 3 However, the difference is that the Si capping layer 140 of the diffusion barrier structure 132 is present along the bottom of the gate trench 102 instead of the alternating layers of Si 134 and oxygen-doped Si 136. Omitting the alternating layers of Si 134 and oxygen-doped Si 136 from the bottom of the gate trench 102 allows the current to spread near the bottom of the gate trench 102, as shown in FIG. Figure 4 Indicated by the dotted arrow in .

[0061] FIG. 5A to FIG. 5F An embodiment of a method of omitting the alternating layers of Si 134 and oxygen-doped Si 136 of the diffusion barrier structure 132 from the bottom of the gate trench 102 is illustrated.

[0062] Figure 5A The semiconductor device 400 is shown after forming the gate trench 102. The gate trench 102 can be etched into the Si substrate 104 using any common trench formation process, such as applying a mask / insulating material 200 on the front major surface 130 of the Si substrate 104 and etching the gate trench 102 into the Si substrate 104 through the opening 201 in the mask 200.

[0063] Figure 5BThe semiconductor device 400 is shown after forming an insulating material 500 such as HDP oxide on the sidewalls 118 and bottom of the gate trench 102. In the case of HDP oxide as the insulating material 500, the HDP oxide may be thinner along the sidewalls 118 (T1) and thicker on the bottom of the gate trench 102 (T2).

[0064] Figure 5C The semiconductor device 400 is shown after removing the insulating material 500 from the sidewalls 118 of the gate trench 102. In the case of a HDP oxide that is thinner along the sidewalls 118 and thicker on the bottom of the gate trench 102, the HDP oxide will be removed from the sidewalls 118 of the gate trench 102 before the HDP oxide is completely removed from the bottom of the trench. The portion of the HDP oxide that remains in the bottom of the gate trench 102 forms an insulating spacer 502 in the lower portion of the gate trench 102. The insulating spacer 502 covers the bottom of the gate trench 102 and the lower portion of the sidewalls 118 to prevent the alternating layers of Si 134 and oxygen-doped Si 136 of the diffusion barrier structure 132 from forming on the bottom of the gate trench 102 and the lower portion of the sidewalls 118.

[0065] Figure 5D The semiconductor device 400 is shown after epitaxial growth of alternating layers of Si 134 and oxygen-doped Si 136 on the exposed sidewalls 118 of the gate trench 102 .

[0066] Figure 5E The semiconductor process 400 is shown after the following process, which is to remove the insulating spacer 502 from the bottom of the gate trench 102, and remove the insulating material 500 and any remnants of the mask / insulating material 200 from the front main surface 130 of the Si substrate 104. The lower portion 504 of the sidewall 118 of the gate trench 102 and the bottom 506 of the gate trench 102 are exposed by removing the insulating spacer 502.

[0067] Fig. 5F The semiconductor device 400 is shown after epitaxially growing the Si capping layer 140 of the diffusion structure 132 on the front major surface 130 of the Si substrate 104, on the alternating layers of Si 134 and oxygen-doped Si 136, on the exposed lower portion 504 of the sidewall 118 of the gate trench 102, and on the exposed bottom 506 of the gate trench 102. Device processing continues (e.g., as Figures 2D to 2M and as previously described herein) to complete Figure 4 The device 400 shown in FIG.

[0068] 6A to 6H Another embodiment of a method of omitting the alternating layers of Si 134 and oxygen-doped Si 136 of the diffusion barrier structure 132 from the bottom of the gate trench 102 is illustrated.

[0069] Fig. 6A The semiconductor device 400 is shown after forming the gate trench 102. The gate trench 102 can be etched into the Si substrate 104 using any common trench formation process, such as applying a mask / insulating material 200 on the front major surface 130 of the Si substrate 104 and etching the gate trench 102 into the Si substrate 104 through the opening 201 in the mask 200.

[0070] Figure 6B The semiconductor device 400 is shown after forming an oxide layer 600 on the sidewalls 118 and bottom of the gate trench 102 , for example by deposition, thermal oxidation, or a combination of both, and forming a silicon nitride layer 602 on the oxide layer 600 over the sidewalls 118 and bottom of the gate trench 102 .

[0071] Figure 6C The semiconductor device 400 is shown after forming an opening 604 in the silicon nitride layer 602 at the bottom of the gate trench 102 , for example by anisotropic plasma etching, to expose the silicon oxide layer 600 at the bottom of the trench.

[0072] Fig.6D The semiconductor device 400 is shown after thermally oxidizing a region of the Si substrate 104 below the exposed silicon oxide layer 600 at the bottom of the gate trench 102. The thermal oxidation process produces an insulating spacer 606 in the lower portion of the gate trench 102. The insulating spacer 606 covers the bottom of the gate trench 102 and the lower portion of the sidewall 118 to prevent the alternating layers of Si 134 and oxygen-doped Si 136 of the diffusion barrier structure 132 from forming on the bottom of the gate trench 102 and the lower portion of the sidewall 118.

[0073] Fig. 6E The semiconductor device 400 is shown after the silicon nitride layer 602 and the silicon oxide layer 600 are removed from the sidewalls 118 of the gate trench 102 .

[0074] Fig. 6F The semiconductor device 400 is shown after epitaxial growth of alternating layers of Si and oxygen-doped Si on the exposed sidewalls 118 of the gate trench 102 .

[0075] Figure 6G The semiconductor device 400 is shown after removing the insulating spacer 606 from the bottom of the gate trench 102, and after removing any remnants of the mask / insulating material 200 from the front main surface 130 of the Si substrate 104. The lower portion 608 of the sidewall 118 of the gate trench 102 and the bottom 610 of the gate trench 102 are exposed by removing the insulating spacer 606.

[0076] Figure 6HThe semiconductor device 400 is shown after epitaxially growing the Si capping layer 140 of the diffusion structure 132 on the front major surface 130 of the Si substrate 104, on the alternating layers of Si 134 and oxygen-doped Si 136, on the exposed lower portion 608 of the sidewalls 118 of the gate trench 102, and on the exposed bottom 610 of the gate trench 102. Device processing continues (e.g., as Figures 2D to 2M and as previously described herein) to complete Figure 4 The device 400 shown in FIG.

[0077] For ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. In addition to orientations that are different from the orientations depicted in the figures, these terms are intended to cover different orientations of the device. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. The same terms refer to the same elements throughout the specification.

[0078] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0079] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor device, comprising: A gate trench extending into the Si substrate; a body region in the Si substrate adjacent to the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and filled with a conductive material, the conductive material contacting a source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench; a diffusion barrier structure formed along the sidewalls of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; as well as A channel region is formed in the Si capping layer and vertically extends along the sidewalls of the gate trench.

2. The semiconductor device according to claim 1, wherein The diffusion barrier structure extends onto the front main surface of the Si substrate into which the gate trench and the contact trench are formed.

3. The semiconductor device according to claim 2, wherein: The diffusion barrier structure extends along the front main surface of the Si substrate to the conductive material filling the contact trench. 4 . The semiconductor device according to claim 1 , wherein a Si capping layer of the diffusion barrier structure exists along the bottom of the gate trench instead of the alternating layers of Si and oxygen-doped Si.

5. The semiconductor device according to claim 1, wherein the gate trench comprises: a gate dielectric lining the sidewalls and bottom of the gate trench; a gate electrode disposed in an upper portion of the gate trench; a field electrode embedded in a field dielectric in a lower portion of the gate trench below the gate electrode; an insulating spacer vertically separating the gate electrode from the field electrode; and a silicon nitride layer separating the insulating spacers and the field dielectric from the gate dielectric.

6. A method for manufacturing a semiconductor device, the method comprising: forming a gate trench extending into the Si substrate; forming a body region in the Si substrate adjacent to the gate trench; forming a source region in the Si substrate above the body region; forming a contact trench extending into the Si substrate and filled with a conductive material, the conductive material contacting a source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench; forming a diffusion barrier structure along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; as well as A channel region is formed in the Si capping layer, and the channel region vertically extends along a sidewall of the gate trench.

7. The method according to claim 6, wherein: Forming the diffusion barrier structure includes: epitaxially growing alternating layers of Si and oxygen-doped Si on the sidewalls and bottom of the gate trench; and The Si capping layer is epitaxially grown on the alternating layers of Si and oxygen-doped Si.

8. The method according to claim 7, further comprising: The alternating layers of Si and oxygen-doped Si and the Si capping layer are epitaxially grown on the front main surface of the Si substrate into which the gate trench is formed.

9. The method according to claim 7, further comprising: A gate dielectric is formed on the Si capping layer. 10 . The method of claim 9 , wherein the gate dielectric is formed by a deposition process, a thermal oxidation process, or both the deposition process and the thermal oxidation process.

11. The method according to claim 9, further comprising: forming a silicon nitride layer on the gate dielectric; forming a field dielectric on the silicon nitride layer; After forming the field dielectric, filling the gate trench with a first conductive material; as well as The first conductive material is recessed to a first depth in the gate trench to form a field electrode.

12. The method according to claim 11, further comprising: removing a field dielectric over the field electrode to expose the silicon nitride layer in a region of the gate trench over the field electrode; as well as After removing the field dielectric over the field electrodes, the field electrodes are covered with insulating spacers.

13. The method of claim 12, wherein covering the field electrodes with the insulating spacers comprises: filling the gate trench with a dielectric material after removing the field oxide above the field electrode; as well as The dielectric material is recessed to a second depth in the gate trench over the field electrode.

14. The method according to claim 13, wherein filling the gate trench with the dielectric material comprises: A high density plasma oxide is deposited in the gate trench by chemical vapor deposition.

15. The method of claim 12, wherein covering the field electrodes with the insulating spacers comprises: A thermal oxide is formed on the field electrode through a thermal oxidation process.

16. The method according to claim 12, further comprising: removing the silicon nitride layer above the insulating spacer; After removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second conductive material; as well as The second conductive material is recessed to a third depth in the gate trench to form a gate electrode.

17. The method according to claim 16, further comprising: After forming the gate electrode, dopant species of opposite conductivity type are implanted into the Si substrate to form the body region and the source region.

18. The method according to claim 17, wherein: The contact trench is formed after implanting a dopant species of opposite conductivity type into the Si substrate.

19. The method according to claim 12, further comprising: removing the silicon nitride layer above the insulating spacer; After removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second conductive material; as well as The second conductive material is recessed to a third depth in the gate trench to form a gate electrode.

20. The method of claim 12, further comprising: Before forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, forming an insulating spacer in the lower portion of the gate trench, the insulating spacer covering the bottom and lower portion of the sidewall of the gate trench to prevent the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure from being formed on the bottom and lower portion of the sidewall of the gate trench; as well as After forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, the insulating spacer is removed from the lower portion of the gate trench.

21. The method according to claim 20, further comprising: After removing the insulating spacer from the lower portion of the gate trench, a Si capping layer of the diffusion barrier structure is epitaxially grown on the alternating layers of Si and oxygen-doped Si and on the bottom and lower portions of the sidewalls of the gate trench.

22. The method of claim 20, wherein forming the insulating spacer in the lower portion of the gate trench comprises: forming a high density plasma oxide on the sidewalls and the bottom of the gate trench, the high density plasma oxide being thinner along the sidewalls and thicker on the bottom of the gate trench; as well as The high density plasma oxide is removed from sidewalls of the gate trench.

23. The method of claim 20, wherein forming the insulating spacer in the lower portion of the gate trench comprises: forming a silicon oxide layer on the sidewalls and bottom of the gate trench; forming a silicon nitride layer on the silicon oxide layer on the sidewalls and the bottom of the gate trench; forming an opening in the silicon nitride layer at the bottom of the gate trench to expose the silicon oxide layer at the bottom of the gate trench; thermally oxidizing a region of the Si substrate below the exposed silicon oxide layer at the bottom of the gate trench; as well as The silicon nitride layer and the silicon oxide layer are removed from sidewalls of the gate trench.

24. The method according to claim 6, further comprising: After forming the diffusion barrier structure, dopant species of opposite conductivity type are implanted into the Si substrate to form the body and the source region.

25. A semiconductor device comprising: A gate trench extending into the Si substrate; a body region in the Si substrate adjacent to the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent to a sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; as well as A channel region is formed in the Si capping layer and vertically extends along the sidewalls of the gate trench.

26. The semiconductor device according to claim 25, wherein: The diffusion barrier structure extends onto the front main surface of the Si substrate into which the gate trench is formed. 27 . The semiconductor device of claim 25 , wherein a Si capping layer of the diffusion barrier structure exists along the bottom of the gate trench instead of the alternating layers of Si and oxygen-doped Si.

28. The semiconductor device according to claim 25, wherein the gate trench comprises: a gate dielectric lining the sidewalls and bottom of the gate trench; a gate electrode disposed in an upper portion of the gate trench; a field electrode embedded in a field dielectric in a lower portion of the gate trench below the gate electrode; an insulating spacer vertically separating the gate electrode from the field electrode; and a silicon nitride layer separating the insulating spacers and the field dielectric from the gate dielectric.

29. A method for manufacturing a semiconductor device, the method comprising: forming a gate trench extending into the Si substrate; forming a body region in the Si substrate adjacent to the gate trench; forming a source region in the Si substrate above the body region; forming a diffusion barrier structure along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; as well as A channel region is formed in the Si capping layer, and the channel region vertically extends along a sidewall of the gate trench.

30. The method of claim 29, wherein: Forming the diffusion barrier structure includes: epitaxially growing alternating layers of Si and oxygen-doped Si on the sidewalls and bottom of the gate trench; and The Si capping layer is epitaxially grown on the alternating layers of Si and oxygen-doped Si.

31. The method of claim 30, further comprising: The alternating layers of Si and oxygen-doped Si and the Si capping layer are epitaxially grown on the front main surface of the Si substrate into which the gate trench is formed.

32. The method of claim 30, further comprising: A gate dielectric is formed on the Si capping layer.

33. The method of claim 32, further comprising: forming a silicon nitride layer on the gate dielectric; forming a field dielectric on the silicon nitride layer; After forming the field dielectric, filling the gate trench with a first conductive material; as well as The first conductive material is recessed to a first depth in the gate trench to form a field electrode.

34. The method of claim 33, further comprising: removing a field dielectric over the field electrode to expose the silicon nitride layer in a region of the gate trench over the field electrode; as well as After removing the field dielectric over the field electrodes, the field electrodes are covered with insulating spacers.

35. The method of claim 34, wherein covering the field electrodes with the insulating spacers comprises: filling the gate trench with a dielectric material after removing the field oxide above the field electrode; as well as The dielectric material is recessed to a second depth in the gate trench over the field electrode.

36. The method of claim 35, wherein filling the gate trench with the dielectric material comprises: A high density plasma oxide is deposited in the gate trench by chemical vapor deposition.

37. The method of claim 35, wherein covering the field electrodes with the insulating spacers comprises: A thermal oxide is formed on the field electrode through a thermal oxidation process.

38. The method of claim 34, further comprising: removing the silicon nitride layer above the insulating spacer; After removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second conductive material; as well as The second conductive material is recessed to a third depth in the gate trench to form a gate electrode.

39. The method of claim 38, further comprising: After forming the gate electrode, dopant species of opposite conductivity type are implanted into the Si substrate to form the body region and the source region.

40. The method of claim 34, further comprising: removing the silicon nitride layer above the insulating spacer; After removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second conductive material; as well as The second conductive material is recessed to a third depth in the gate trench to form a gate electrode.

41. The method of claim 34, further comprising: Before forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, forming an insulating spacer in the lower portion of the gate trench, the insulating spacer covering the bottom and lower portion of the sidewall of the gate trench to prevent the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure from being formed on the bottom and lower portion of the sidewall of the gate trench; as well as After forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, the insulating spacer is removed from the lower portion of the gate trench.

42. The method of claim 41, further comprising: After removing the insulating spacer from the lower portion of the gate trench, a Si capping layer of the diffusion barrier structure is epitaxially grown on the alternating layers of Si and oxygen-doped Si and on the bottom and lower portions of the sidewalls of the gate trench.

43. The method of claim 41 , wherein forming the insulating spacer in the lower portion of the gate trench comprises: forming a high density plasma oxide on the sidewalls and the bottom of the gate trench, the high density plasma oxide being thinner along the sidewalls and thicker on the bottom of the gate trench; as well as The high density plasma oxide is removed from sidewalls of the gate trench.

44. The method of claim 41 , wherein forming the insulating spacer in the lower portion of the gate trench comprises: forming a silicon oxide layer on the sidewalls and bottom of the gate trench; forming a silicon nitride layer on the silicon oxide layer on the sidewalls and the bottom of the gate trench; forming an opening in the silicon nitride layer at the bottom of the gate trench to expose the silicon oxide layer at the bottom of the gate trench; thermally oxidizing a region of the Si substrate below the exposed silicon oxide layer at the bottom of the gate trench; as well as The silicon nitride layer and the silicon oxide layer are removed from sidewalls of the gate trench.

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