Display Panel

Abstract

A display panel includes: a substrate including a first non-display area surrounding a transmission area, a display area outside the first non-display area, and a second non-display area surrounding the display area; a driving thin film transistor and a display element located in the display area; a first power supply line located in the second non-display area and extending in a first direction; a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction crossing the first direction and spaced apart from each other by a transmission area located between the plurality of first driving voltage lines and the plurality of second driving voltage lines; and a power supply bus located in the first non-display area or the second non-display area, connected to the plurality of second driving voltage lines, the power supply bus extending in the first direction. The length of the power supply bus in the first direction is less than the length of the first power supply line in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0096131, titled “DISPLAY PANEL,” filed on August 17, 2018 in the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display panel and a display device including the display panel. Background Art

[0004] Display devices have been used for various purposes. Also, as the thickness and weight of display devices have been reduced, the scope of use of display devices has increased.

[0005] According to the purpose of the display device, different methods of designing its shape have been developed, and more functions have been embedded in or linked to the display device. Summary of the invention

[0006] The embodiment relates to a display panel, comprising: a substrate, comprising a first non-display area surrounding a transmission area, a display area outside the first non-display area, and a second non-display area surrounding the display area; a driving thin film transistor and a display element, located in the display area; a first power line, located in the second non-display area, the first power line extending in a first direction; a plurality of first driving voltage lines and a plurality of second driving voltage lines, extending in a second direction crossing the first direction and spaced apart from each other by a transmission area located between the plurality of first driving voltage lines and the plurality of second driving voltage lines; and a power bus, located in the first non-display area or the second non-display area, connected to the plurality of second driving voltage lines, the power bus extending in the first direction. The length of the power bus in the first direction is less than the length of the first power line in the first direction.

[0007] The power bus may be located in the second non-display area and may be integrated with the plurality of second driving voltage lines.

[0008] The display panel may further include: at least one third driving voltage line extending from the first power line in the second direction and connected to the power bus. The at least one third driving voltage line, the first power line and the power bus may be integrated with each other.

[0009] The display panel may further include: at least one fourth driving voltage line extending from the first power line in the second direction. An end of the at least one fourth driving voltage line may be spaced apart from the power bus line.

[0010] The display panel may further include: a plurality of electrode voltage lines arranged at a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, the plurality of electrode voltage lines extending in the first direction and crossing the plurality of first driving voltage lines and the plurality of second driving voltage lines. The plurality of electrode voltage lines may be connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via contact holes.

[0011] The specific resistance of the power bus may be smaller than the specific resistance of the plurality of electrode voltage lines.

[0012] At least some of the plurality of electrode voltage lines each include a raised portion connected to each other in a ring shape around the transmission area.

[0013] Each of the driving thin film transistors may include a semiconductor layer and a driving gate electrode. A plurality of electrode voltage lines may overlap the driving gate electrode to form a storage capacitor.

[0014] A width of the transmission area in the first direction may be greater than a width of the transmission area in the second direction.

[0015] The power bus may be located in the first non-display area, at a different layer from the plurality of second driving voltage lines, and may be connected to the plurality of second driving voltage lines via a contact hole.

[0016] The display panel may further include: a plurality of scan lines extending in the first direction and arching around a boundary of the transmission area. The power bus may overlap with the arched portions of the plurality of scan lines.

[0017] The display panel may further include: an additional power bus connected to the plurality of first driving voltage lines and extending in the first direction. The additional power bus may be arranged in the first non-display area.

[0018] The display panel may include a plurality of transmission areas. The first non-display area may surround the plurality of transmission areas.

[0019] An embodiment also relates to a display panel, comprising: a substrate, comprising a first non-display area surrounding a transmission area, a display area located outside the first non-display area, and a second non-display area surrounding the display area; a driving thin film transistor and a display element located in the display area; a first power line located in the second non-display area, the first power line extending in a first direction; a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction intersecting the first direction and spaced apart from each other by a transmission area located between the plurality of first driving voltage lines and the plurality of second driving voltage lines; a power bus connected to the plurality of second driving voltage lines, the power bus being located in the first non-display area or the second non-display area to extend in the first direction; and a plurality of electrode voltage lines, being located in a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, intersecting the plurality of first driving voltage lines and the plurality of second driving voltage lines, the plurality of electrode voltage lines being connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via contact holes.

[0020] The specific resistance of the power bus may be smaller than the specific resistance of the plurality of electrode voltage lines.

[0021] At least some of the plurality of electrode voltage lines may each include a domed portion connected to each other in a ring shape around the transmission area.

[0022] Each of the driving thin film transistors may include a semiconductor layer and a driving gate electrode. A plurality of electrode voltage lines may overlap the driving gate electrode to form a storage capacitor.

[0023] The power bus may be located in the second non-display area and may be integrated with the plurality of second driving voltage lines.

[0024] The power bus may be located in the first non-display area, and may be located at a different layer from the plurality of second driving voltage lines to be connected to the plurality of second driving voltage lines via the contact hole.

[0025] The display panel may further include: an additional power bus connected to the plurality of first driving voltage lines and extending in the first direction, wherein the additional power bus is located in the first non-display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 shows a perspective view of a display device according to an embodiment;

[0028] FIG. 2A to FIG. 2C shows a cross-sectional view of a display device according to an embodiment;

[0029] FIG. 3A to FIG. 3C shows a cross-sectional view of a display device according to an embodiment;

[0030] Figure 4 shows a plan view of a display panel according to an embodiment;

[0031] Figure 5 An equivalent circuit diagram of a pixel in a display panel according to an embodiment is shown;

[0032] Fig. 6A A plan view showing a pixel circuit of a pixel in a display panel according to an embodiment;

[0033] Figure 6B Shown along Fig. 6A A cross-sectional view of the organic light-emitting device taken along line II' and line II-II';

[0034] Figure 7 shows a plan view of wiring located around a transmissive area according to an embodiment;

[0035] Figure 8 Shown along Figure 7 A cross-sectional view taken along line XX';

[0036] Fig. 9 shows a plan view of wiring located around a transmissive area according to an embodiment;

[0037] Fig.10 Shown along Fig. 9 A cross-sectional view taken along line XI-XI';

[0038] Fig.11 A plan view showing wiring around a transmissive region according to an embodiment; and

[0039] Fig.12 A plan view of wirings around a transmissive area according to an embodiment is shown. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the exemplary embodiments to those skilled in the art.

[0041] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer. In addition, it is understood that when a layer is referred to as being "below" another layer, it can be directly below, or there can be one or more intermediate layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intermediate layers. Throughout the text, the same reference numerals indicate the same elements.

[0042] Although terms such as "first", "second", etc. may be used to describe various components, these components are not limited by the above terms. The above terms are only used to distinguish one component from another component.

[0043] Unless it has a clearly different meaning in the context, an expression used in the singular includes the expression in the plural form.

[0044] Figure 1 A perspective view of a display device 1 according to an embodiment is shown.

[0045] refer to Figure 1 The display device 1 may include a display area DA for emitting light and a non-display area NDA that does not emit light. The display device 1 may provide a predetermined image via light emitted from a plurality of pixels arranged in the display area DA.

[0046] The display device 1 may further include a transmission area TA. The transmission area TA may be at least partially surrounded by the display area DA. Figure 1 , the transmission area TA may be completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding the transmission area TA and a second non-display area NDA2 surrounding the outside of the display area DA. For example, the first non-display area NDA1 may completely surround the transmission area TA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0047] The transmission area TA may be an area where electronic components are arranged, as will be described later. Figure 2A The transmission area TA may be considered as an area through which light and / or sound output from the electronic component or advancing toward the electronic component from the outside may pass. In an embodiment, when light passes through the transmission area TA, the transmittance may be about 20% or more, for example, 50% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0048] In the following, according to the embodiment, it is considered that the display device 1 is an organic light emitting display device. In some embodiments, the display device 1 may be an inorganic light emitting display, a quantum dot light emitting display, or the like.

[0049] exist Figure 1 , it is shown that the transmission area TA is located in a part (upper right part) of the rectangular display area DA. In some embodiments, the display area DA may have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, etc. Various changes may be made to the size, shape, number, and position of the transmission area TA.

[0050] FIG. 2A to FIG. 2C Shown along Figure 1 A cross-sectional view of the display device 1 according to the embodiment taken along line AA′ in FIG.

[0051] refer to Figure 2A The display device 1 may include a display panel 10 and a component 20 , the display panel 10 includes a display element, and the component 20 corresponds to the transmission area TA.

[0052] The display panel 10 may include a substrate 100, an encapsulation substrate 300 as an encapsulation member facing the substrate 100, and a display element layer 200 located between the substrate 100 and the encapsulation substrate 300. A sealing material (sealant 350) for covering the side surface of the display element layer 200 may be provided between the substrate 100 and the encapsulation substrate 300. Figure 2A In the embodiment, the sealant 350 is provided on opposite sides of the transmission area TA, but when viewed from a direction perpendicular to the main surface of the substrate 100 , it can be seen that the transmission area TA may be completely surrounded by the sealant 350 .

[0053] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. The substrate 100 including the polymer resin may have flexible, rollable or bendable properties. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer. The encapsulation substrate 300 may include glass or a polymer resin.

[0054] The display element layer 200 may include a circuit layer including a thin film transistor TFT, an organic light emitting diode OLED as a display element connected to the thin film transistor TFT, and an insulating layer IL located between the thin film transistor TFT and the organic light emitting diode OLED. The thin film transistor TFT and the organic light emitting diode OLED connected to the thin film transistor TFT may be arranged in the display area DA. Some wirings WL in the display element layer 200 may be located in the first non-display area NDA1. The wirings WL may provide a predetermined signal or voltage to pixels spaced apart from each other with a transmission area TA provided therebetween. Figure 2A 2 shows that the wiring WL does not overlap with the sealant 350 in the first non-display area NDA1. In some embodiments, the sealant 350 may be partially disposed on the wiring WL.

[0055] The display panel 10 may include a through hole 10H corresponding to the transmission area TA. For example, the substrate 100 and the encapsulation substrate 300 may include through holes 100H and 300H corresponding to the transmission area TA, respectively. The display element layer 200 may also include a through hole corresponding to the transmission area TA.

[0056] Components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder or including a color filter and a black matrix, a transparent window, etc. may be further disposed on the display panel 10 .

[0057] The component 20 may be located in the transmission area TA. The component 20 may be an electronic component that uses light or sound. For example, the electronic component may include: a light receiving sensor such as an infrared (IR) sensor, a camera that captures an image by receiving light, a sensor for outputting light or sound and sensing light or sound to measure a distance or recognize a fingerprint, a small lamp that irradiates light, a speaker for outputting sound, etc. The electronic component that uses light may use light of various wavelengths such as visible light, IR, ultraviolet (UV) rays, etc. Figure 2A As shown, when the display panel 10 includes the through holes 10H corresponding to the transmission areas TA, light or sound output from or received through the electronic elements may be effectively utilized.

[0058] Although Figure 2A The display panel 10 is shown to include a through hole 10H corresponding to the transmissive area TA, but in some embodiments, some components of the display panel 10 may not include a through hole. Figure 2B As shown, the package substrate 300 may include a through hole 300H corresponding to the transmission area TA, but the substrate 100 may not include a through hole. Figure 2CAs shown, the substrate 100 and the encapsulation substrate 300 may not include a through hole corresponding to the transmission area TA. Figure 2B and Figure 2C When the through hole 100H is not included, the portion of the display element layer 200 corresponding to the transmission area TA may also be removed to ensure the light transmittance of the electronic element. Figure 2B and Figure 2C When the display panel 10 shown in FIG. 1 is used, it may be appropriate to use electronic components that utilize light.

[0059] FIG. 2A to FIG. 2C The member 20 shown in FIG. 1 may be located inside the through hole 10H so as to overlap with a side surface of the display panel 10 defining the through hole 10H.

[0060] The component 20 may be another member other than an electronic component. In an embodiment, when the display panel 10 is used in a smart watch or a dashboard of a vehicle, the component 20 may include a member having a clock hand or a hand for indicating predetermined information (e.g., vehicle speed, etc.). In some embodiments, the component 20 may include an element such as an accessory for enhancing the aesthetics of the display panel 10.

[0061] FIG. 3A to FIG. 3C Shown along Figure 1 A cross-sectional view of the display device 1 according to the embodiment taken along line AA′ in FIG.

[0062] refer to Figure 3A The display device 1 may include a display panel 10 and a component 20, similar to the above reference Figure 2A The display device 1 described above may further include an input sensing member, an anti-reflection member, a window, etc., disposed on the display panel 10 for sensing a touch input.

[0063] and Figure 2A Unlike the display panel 10 including the encapsulation substrate 300 and the sealant 350 as the encapsulation member in the embodiment, the display panel 10 according to another embodiment may include a thin film encapsulation layer 300' as the encapsulation member. In this case, the flexibility of the display panel 10 can be further improved. Hereinafter, for the convenience of description, the above differences will be described.

[0064] The thin film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3A The thin film encapsulation layer 300 ′ may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 , and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 .

[0065] The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may each include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ). The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, polyimide, polyethylene, and the like.

[0066] The display panel 10 may include a through hole 10H corresponding to the transmission area TA. For example, the substrate 100 and the thin film encapsulation layer 300' may include through holes 100H and 300'H corresponding to the transmission area TA, respectively. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 and the organic encapsulation layer 320 may each include a hole corresponding to the transmission area TA. The hole in the organic encapsulation layer 320 may be larger than the hole in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, so the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other around the transmission area TA.

[0067] In some embodiments, the display panel 10 may not include a through hole. Figure 3B As shown, the thin film encapsulation layer 300' may include a through hole 300'H corresponding to the transmission area TA, but the substrate 100 may not include a through hole. Figure 3C As shown, the substrate 100 and the thin film encapsulation layer 300' may not include a through hole corresponding to the transmission area TA. Figure 3B and Figure 3C When the through hole 100H is not included as shown, a portion of the display element layer 200 corresponding to the transmission area TA may also be removed to ensure the light transmittance of the electronic element (eg, component 20 ).

[0068] When Figure 3C When the thin film encapsulation layer 300' shown does not include a through hole, at least one inorganic encapsulation layer and at least one organic encapsulation layer may cover the substrate 100 in the transmission area TA. In this case, in the display element layer 200 between the substrate 100 and the thin film encapsulation layer 300', a portion corresponding to the transmission area TA may be removed. Figure 3AIn the embodiment, all corresponding portions of the insulating layer IL corresponding to the transmission area TA are removed. In some embodiments, only some of the plurality of layers in the insulating layer IL may be removed.

[0069] The component 20 may be located inside the through hole 10H, for example, Figure 3A As shown, the through hole 100H and the inner side of the through hole 200H of the display element layer 200 are overlapped with the side surface of the display panel 10 for defining the through hole 10H, or as shown in FIG. Figure 3B The illustrated structure is located inside the through hole 200H of the display element layer 200 .

[0070] Figure 4 A plan view of a display panel 10 according to an embodiment is shown.

[0071] refer to Figure 4 , the display panel 10 may include a plurality of pixels P arranged in a display area DA. The pixels P may each include a display element such as an organic light emitting diode. Each of the pixels P may emit light, for example, red light, green light, blue light, or white light, via an organic light emitting diode. In this specification, the pixel P may emit red light, green light, blue light, or white light as described above. The display area DA may be Figures 2A to 3C The described packaging member is covered so as to be protected from external air or moisture.

[0072] The transmission area TA may be arranged in the interior of the display area DA, and a plurality of pixels P may be arranged around the transmission area TA. The plurality of pixels P may be arranged to surround the transmission area TA. A first non-display area NDA1 in which the pixels P are not arranged may be located between the transmission area TA and the display area DA. Wiring for applying a predetermined signal or power to the pixels P spaced apart from each other based on the transmission area TA may be detoured in the first non-display area NDA1. In some embodiments, some wiring may be disconnected at the transmission area TA.

[0073] Each of the pixels P may be electrically connected to an external circuit disposed in a non-display area (e.g., a second non-display area NDA2). In the second non-display area NDA2, a first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power line 160, and a second power line 170 may be disposed.

[0074] The first scan driving circuit 110 may provide a scan signal to each pixel P via a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each pixel P via an emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110, and the display area DA is arranged between the second scan driving circuit 120 and the first scan driving circuit 110. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110. Other pixels P may be connected to the second scan driving circuit 120. In some embodiments, the second scan driving circuit 120 may be omitted.

[0075] The terminal 140 may be arranged on one side of the substrate 100. The terminal 140 may not be covered by the insulating layer but may be exposed. The terminal 140 may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB may transmit a signal or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120 respectively via the printed circuit board PCB. The controller may provide the driving voltage ELVDD and the common voltage ELVSS to the first power line 160 and the second power line 170 respectively via the first connection line 161 and the second connection line 171 (see Figure 5 ). The driving voltage ELVDD may be supplied to each pixel P via the driving voltage line PL connected to the first power line 160, and the common voltage ELVSS may be supplied to the counter electrode of each of the pixels P connected to the second power line 170. The second power line 170 may have a ring shape having an open side to partially surround the display area DA.

[0076] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each of the pixels P via the connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Figure 4 The data driving circuit 150 is shown to be disposed on the printed circuit board PCB, but in some embodiments, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0077] In an embodiment, the power bus 163 may be connected to some of the driving voltage lines PL and may extend in the first direction. Figure 4As shown, the power bus 163 may be arranged in the second non-display area NDA2 and may extend in parallel with the first power line 160 in the first direction, and the display area DA is provided between the power bus 163 and the first power line 160. In some embodiments, the power bus 163 may be arranged in the first non-display area NDA1 surrounding the transmissive area TA. In some embodiments, a plurality of power buses 163 may be provided, some of the plurality of power buses 163 may be arranged in the first non-display area NDA1, and other of the plurality of power buses 163 may be arranged in the second non-display area NDA2.

[0078] The first power line 160 may be connected to the first connection line 161 to be provided with a driving voltage ELVDD from a controller connected to the terminal 140. The power bus 163 may not be directly connected to the terminal 140 but may be connected to the first power line 160 via a driving voltage line PL to receive the same voltage as that of the first power line 160.

[0079] In an embodiment, one end portion of the driving voltage lines PL1 , PL2 , PL3 , and PL4 may be connected to the first power line 160 .

[0080] The plurality of first driving voltage lines PL1 may extend in the second direction from the first power line 160. One end of the plurality of first driving voltage lines PL1 may be arranged at one side (lower side) of the transmission area TA. For example, one end of the plurality of first driving voltage lines PL1 may be arranged in the first non-display area NDA1. In some embodiments, the plurality of first driving voltage lines PL1 and the first power line 160 may be provided as one body with each other.

[0081] The plurality of second driving voltage lines PL2 may extend in the second direction from the power bus 163. One end of the plurality of second driving voltage lines PL2 may be arranged on the opposite side (upper side) of the transmission area TA. For example, one end of the plurality of second driving voltage lines PL2 may be arranged in the first non-display area NDA1. In some embodiments, the plurality of second driving voltage lines PL2 and the power bus 163 may be provided as one body with each other. The plurality of first driving voltage lines PL1 and the plurality of second driving voltage lines PL2 may be spaced apart from each other with the transmission area TA provided therebetween.

[0082] The plurality of third driving voltage lines PL3 may extend in the second direction to be connected to the first power lines 160 and the power bus 163. In some embodiments, the plurality of third driving voltage lines PL3, the first power lines 160, and the power bus 163 may be provided as one body with each other.

[0083] A plurality of fourth driving voltage lines PL4 may extend in a second direction from the first power supply line 160. One end of the plurality of fourth driving voltage lines PL4 may be disposed in the second non-display area NDA2. In some embodiments, the plurality of fourth driving voltage lines PL4 and the first power supply line 160 may be provided integrally with each other.

[0084] In some embodiments, the length L2 of the power supply bus 163 in the first direction may be less than the length L1 of the first power supply line 160 in the first direction (L2 < L1). In some embodiments, the number of the plurality of driving voltage lines PL connected to the power supply bus 163 may be less than the number of the plurality of driving voltage lines PL connected to the first power supply line 160.

[0085] The first power supply line 160 may be arranged to correspond to all columns of the pixels P arranged in the first direction to transmit the driving voltage ELVDD to each column of the pixels P. On the other hand, the power supply bus 163 may be provided to prevent the IR drop of the second driving voltage line PL2. The power supply bus 163 may be arranged based on the transmission area TA. As described above, when the length of the power supply bus 163 is reduced, the utilization rate of the second non-display area NDA2 may be increased.

[0086] Figure 5 An equivalent circuit diagram of one pixel P in a display panel according to an embodiment is shown.

[0087] Reference Figure 5 , the pixel P includes a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. The thin film transistors and the storage capacitor may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0088] In Figure 5 , each pixel P may be connected to, for example, signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL. In some embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent pixels P.

[0089] The plurality of thin film transistors may include a driving TFT T1, a switching TFT T2, a compensating TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

[0090] The signal lines include a scan line SL transmitting a scan signal Sn, a previous scan line SL-1 transmitting a previous scan signal Sn-1 to a first initialization TFT T4 and a second initialization TFT T7, an emission control line EL transmitting an emission control signal En to an operation control TFT T5 and an emission control TFT T6, and a data line DL crossing the scan line SL and transmitting a data signal Dm. The driving voltage line PL may transmit a driving voltage ELVDD to the driving TFT T1. The initialization voltage line VL may transmit an initialization voltage Vint to initialize the driving TFT T1 and the pixel electrode of the organic light emitting diode OLED.

[0091] The driving gate electrode G1 of the driving TFT T1 may be connected to the first storage capacitor plate CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving TFT T1 may be connected to the driving voltage line PL via the operation control TFT T5. The driving drain electrode D1 of the driving TFT T1 may be electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 to switch the driving current I OLED Supply to organic light emitting diode OLED.

[0092] The switching gate electrode G2 of the switching TFT T2 may be connected to the scan line SL. The switching source electrode S2 of the switching TFT T2 may be connected to the data line DL. The switching drain electrode D2 of the switching TFT T2 may be connected to the driving source electrode S1 of the driving TFT T1, and at the same time may be connected to the driving voltage line PL located at the lower side via the operation control TFT T5. The switching TFT T2 may be turned on according to the scan signal Sn received through the scan line SL, and may perform a switching operation that transmits the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving TFT T1.

[0093] The compensation gate electrode G3 of the compensation TFT T3 may be connected to the scan line SL. The compensation source electrode S3 of the compensation TFT T3 may be connected to the driving drain electrode D1 of the driving TFT T1, and at the same time may be connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The compensation drain electrode D3 of the compensation TFT T3 may be connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 may be turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1 to each other and diode-connect the driving TFT T1.

[0094] The first initialization gate electrode G4 of the first initialization TFT T4 may be connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization TFT T4 may be connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL. The first initialization drain electrode D4 of the first initialization TFT T4 may be connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 may be turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1, and perform an initialization operation to initialize the voltage at the driving gate electrode G1 of the driving TFT T1.

[0095] The operation control gate electrode G5 of the operation control TFT T5 may be connected to the emission control line EL. The operation control source electrode S5 of the operation control TFT T5 may be connected to the driving voltage line PL located at the lower side. The operation control drain electrode D5 of the operation control TFT T5 may be connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0096] The emission control gate electrode G6 of the emission control TFT T6 may be connected to the emission control line EL. The emission control source electrode S6 of the emission control TFT T6 may be connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3. The emission control drain electrode D6 of the emission control TFT T6 may be electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0097] The operation control TFT T5 and the emission control TFT T6 may be simultaneously turned on according to the emission control signal En transmitted through the emission control line EL to transmit the driving voltage ELVDD to the organic light emitting diode OLED and allow the driving current I OLED Flows into the organic light emitting diode OLED.

[0098] The second initialization gate electrode G7 of the second initialization TFT T7 may be connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization TFT T7 may be connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED. The second initialization drain electrode D7 of the second initialization TFT T7 may be connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 may be turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0099] exist Figure 5 , the first initialization TFT T4 and the second initialization TFT T7 are shown to be connected to the previous scan line SL-1. In some embodiments, the first initialization TFT T4 may be connected to the previous scan line SL-1 to operate according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., a subsequent scan line) to operate according to a signal transmitted to the signal line.

[0100] The second storage capacitor plate CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The counter electrode of the organic light emitting diode OLED may be connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED may receive the driving current I from the driving TFT T1. OLED To emit light to display images.

[0101] exist Figure 5 , the compensation TFT T3 and the first initialization TFT T4 are shown to have dual gate electrodes. In some embodiments, the compensation TFT T3 and the first initialization TFT T4 may each have one gate electrode.

[0102] Fig. 6A A plan view showing a pixel circuit of one pixel in a display panel according to an embodiment.

[0103] refer to Fig. 6A , a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7 may be arranged along the semiconductor layer 1130. The semiconductor layer 1130 may be arranged on a substrate having a buffer layer including an inorganic insulating material arranged thereon.

[0104] Some areas of the semiconductor layer 1130 correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7. For example, the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 may be connected to each other and bent into various shapes.

[0105] The semiconductor layer 1130 may include a channel region and a source region and a drain region located on opposite sides of the channel region. The source region and the drain region may be identified as a source electrode and a drain electrode of a corresponding TFT, respectively. Hereinafter, for ease of description, the source region and the drain region will be referred to as a source electrode and a drain electrode.

[0106] The driving TFT T1 may include a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located at opposite sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 may have a curved shape (e.g., an Ω shape) to establish a long channel length in a narrow space. When the driving channel region has a long length, the driving range of the gate voltage increases, and therefore, the grayscale of the light emitted from the organic light emitting diode OLED can be finely controlled, and the quality of the displayed image can be improved.

[0107] The switching TFT T2 may include a switching gate electrode G2 overlapping the switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located at opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0108] The compensation TFT T3 may be a dual-gate TFT including a compensation gate electrode G3 respectively overlapping two compensation channel regions and a compensation source electrode S3 and a compensation drain electrode D3 located at opposite sides of the two compensation channel regions. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 via a node connection line 1174 to be described below.

[0109] The first initialization TFT T4 may be a dual-gate TFT including a first initialization gate electrode G4 respectively overlapping two first initialization channel regions and a first initialization source electrode S4 and a first initialization drain electrode D4 located at opposite sides of the two first initialization channel regions.

[0110] The operation control TFT T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 located at opposite sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0111] The emission control TFT T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and an emission control source electrode S6 and an emission control drain electrode D6 located at opposite sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0112] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 located at opposite sides of the second initialization channel region.

[0113] The above-mentioned TFTs may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0114] The scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1 may be arranged on the semiconductor layer 1130, and an insulating layer is provided between the semiconductor layer 1130 and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0115] The scan line SL may extend in the first direction. Some regions of the scan line SL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SL that overlap the channel regions of the switching TFT T2 and the compensation TFT T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0116] The previous scan line SL-1 may extend along the first direction. Some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, regions of the previous scan line SL-1 that overlap with the channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0117] The emission control line EL may extend along the first direction. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, regions of the emission control line EL that overlap the channel regions of the operation control TFT T5 and the emission control TFT T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0118] The driving gate electrode G1 may be a floating electrode connected to the compensation TFT T3 via a node connection line 1174 .

[0119] The electrode voltage line HL may be disposed on the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1, and an insulating layer is provided between the electrode voltage line HL and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0120] The electrode voltage line HL may extend in the first direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1, and may configure a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may become a first storage capacitor plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may become a second storage capacitor plate CE2 of the storage capacitor Cst.

[0121] The second storage capacitor plate CE2 of the storage capacitor Cst may be electrically connected to the driving voltage line PL. For example, the electrode voltage line HL may be connected to the driving voltage line PL on the electrode voltage line HL via the contact hole CNT. The electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL may have a constant voltage of +5V. The electrode voltage line HL may be identified as a driving voltage line in the lateral direction.

[0122] The driving voltage line PL may extend along the second direction. The electrode voltage line HL electrically connected to the driving voltage line PL may extend along the first direction crossing the second direction. The plurality of driving voltage lines PL and the electrode voltage lines HL in the display area DA may generate a mesh structure.

[0123] In this embodiment, the electrode voltage line HL may be arranged at a different layer from the driving voltage line PL. The specific resistance of the electrode voltage line HL may be greater than the specific resistance of the driving voltage line PL.

[0124] The data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may be disposed on the electrode voltage line HL, and an insulating layer is provided between the electrode voltage line HL and the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 .

[0125] The data line DL may extend in the second direction. The data line DL may be connected to the switching source electrode S2 of the switching TFT T2 via the contact hole 1154. A portion of the data line DL may be identified as the switching source electrode S2.

[0126] The driving voltage line PL may extend in the second direction. As described above, the driving voltage line PL may be connected to the electrode voltage line HL via the contact hole CNT. The driving voltage line PL may be connected to the operation control TFT T5 via the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 via the contact hole 1155.

[0127] One end of the initialization connection line 1173 may be connected to the first initialization TFT T4 and the second initialization TFT T7 via the contact hole 1152. The other end of the initialization connection line 1173 may be connected to an initialization voltage line VL (described below) via the contact hole 1151.

[0128] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 via the contact hole 1156. The other end of the node connection line 1174 may be connected to the driving gate electrode G1 via the contact hole 1157.

[0129] The initialization voltage line VL may be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 , and an insulating layer is provided between the initialization voltage line VL and the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 .

[0130] The initialization voltage line VL may extend in the first direction. The initialization voltage line VL may be connected to the first initialization TFT T4 and the second initialization TFT T7 via the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V, etc.).

[0131] The initialization voltage line VL can be connected to the organic light emitting diode OLED (see Figure 5 ) is arranged at the same layer. The initialization voltage line VL may include the same material as the pixel electrode 210. The pixel electrode 210 may be connected to the emission control TFT T6. The pixel electrode 210 may be connected to the connection metal 1175 via the contact hole 1163. The connection metal 1175 may be connected to the emission control drain electrode D6 via the contact hole 1153.

[0132] exist Fig. 6A , the initialization voltage line VL is shown to be arranged at the same layer as the layer of the pixel electrode 210. In some embodiments, the initialization voltage line VL may be arranged at the same layer as the electrode voltage line HL.

[0133] Moreover, in Figure 5 and Fig. 6A, the pixel circuit PC is shown to include seven TFTs and one storage capacitor. In some embodiments, the number of TFTs and the number of storage capacitors may vary depending on the design of the pixel circuit PC.

[0134] In the following, reference will be made to Figure 6B A stacked structure of components included in a display panel according to an embodiment will be described. Figure 6B Shown along Fig. 6A A cross-sectional view of the organic light emitting diode OLED taken along lines II' and II-II'.

[0135] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. The substrate 100 including the polymer resin may have flexible, rollable or bendable properties. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer.

[0136] The buffer layer 111 may be located on the substrate 100 to reduce or block the penetration of impurities, moisture or external air from the lower part of the substrate 100 and provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material, an organic material, or an inorganic-organic composite material such as an oxide material or a nitride material. The buffer layer 111 may have a single-layer or multi-layer structure including an inorganic material and an organic material. A barrier layer for preventing external air penetration may also be provided between the substrate 100 and the buffer layer 111.

[0137] The semiconductor layers A1 and A6 may each include amorphous silicon or polycrystalline silicon. In some embodiments, the semiconductor layers A1 and A6 may each include an oxide of at least one selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layers A1 and A6 may each include a channel region and a source region and a drain region doped with impurities.

[0138] The gate electrodes G1 and G6 may be disposed on the semiconductor layers A1 and A6, respectively, and a first gate insulating layer 112 is provided between the gate electrodes G1 and G6 and the semiconductor layers A1 and A6. The gate electrodes G1 and G6 may each include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single layer or a multilayer structure. As an example, the gate electrodes G1 and G6 may each have a single layer including Mo. The scan line SL (see Fig. 6A ), the previous scan line SL-1 and the emission control line EL may be provided at the same layer as the gate electrodes G1 and G6. For example, the gate electrodes G1 and G6, the scan line SL (see Fig. 6A ), the previous scan line SL-1 and the emission control line EL may be disposed on the first gate insulating layer 112.

[0139] The first gate insulating layer 112 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) of insulating material.

[0140] A second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) of insulating material.

[0141] The first storage capacitor plate CE1 of the storage capacitor Cst may be provided integrally with the gate electrode G1 of the driving TFT T1. For example, the gate electrode G1 of the driving TFT T1 may serve as the first storage capacitor plate CE1 of the storage capacitor Cst.

[0142] The second storage capacitor plate CE2 of the storage capacitor Cst may overlap with the first storage capacitor plate CE1, and the second gate insulating layer 113 is arranged between the second storage capacitor plate CE2 and the first storage capacitor plate CE1. In this case, the second gate insulating layer 113 may be used as a dielectric layer of the storage capacitor Cst. The second storage capacitor plate CE2 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. As an example, the second storage capacitor plate CE2 may be in the form of a single layer including Mo, or may be a multi-layer structure including Mo / Al / Mo.

[0143] In the drawings, the storage capacitor Cst is shown to overlap with the driving TFT T1. In some embodiments, various modifications may be made to the storage capacitor Cst. For example, the storage capacitor Cst may be arranged not to overlap with the driving TFT T1.

[0144] The second storage capacitor plate CE2 may serve as the electrode voltage line HL. For example, a portion of the electrode voltage line HL may serve as the second storage capacitor plate CE2 of the storage capacitor Cst.

[0145] An interlayer insulating layer 115 may be provided to cover the second storage capacitor plate CE2. The interlayer insulating layer 115 may include a silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) of insulating material.

[0146] The data line DL, the driving voltage line PL, and the connection metal 1175 may be disposed on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the connection metal 1175 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure including the above materials. For example, each of the data line DL, the driving voltage line PL, and the connection metal 1175 may have a multi-layer structure including Ti / Al / Ti.

[0147] The data lines DL and the driving voltage lines PL may be arranged throughout the display area DA to transmit signals or voltages to the plurality of pixels P. The data lines DL and the driving voltage lines PL may have a specific resistance less than that of the second storage capacitor plate CE2 or the electrode voltage line HL. In some embodiments, the data lines DL and the driving voltage lines PL may have a specific resistance of about 1 / 10 of that of the second storage capacitor plate CE2 or the electrode voltage line HL.

[0148] The second storage capacitor plate CE2 of the storage capacitor Cst may be connected to the driving voltage line PL via a contact hole CNT defined in the interlayer insulating layer 115. The electrode voltage line HL may be connected to the driving voltage line PL via the contact hole CNT. The electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL.

[0149] The connection metal 1175 may be connected to the semiconductor layer A6 of the emission control TFT T6 via a contact hole 1153 that penetrates the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control TFT T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED via the connection metal 1175.

[0150] The planarization layer 117 may be located on the data line DL, the driving voltage line PL, and the connection metal 1175. The organic light emitting diode OLED may be located on the planarization layer 117.

[0151] The planarization layer 117 may have a flat upper surface so that the pixel electrode 210 formed thereon will be flat. The planarization layer 117 may include a single layer or a multilayer structure including an organic material. The planarization layer 117 may include a general polymer (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative with a phenol group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof. The planarization layer 117 may include an inorganic material. The planarization layer 117 may include a silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ) insulating material. When the planarization layer 117 includes an inorganic material, chemical planarization polishing can be performed as needed. In some embodiments, the planarization layer 117 may include an organic material and an inorganic material.

[0152] The planarization layer 117 may include a contact hole 1163 to expose the connection metal 1175. The pixel electrode 210 may be connected to the connection metal 1175 via the contact hole 1163.

[0153] The pixel electrode 210 may be a (semi) transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective layer including at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and compounds thereof, and a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may include a stack structure including ITO / Ag / ITO.

[0154] The pixel defining layer 119 may be located on the planarization layer 117. The pixel defining layer 119 may include an opening 119OP exposing a central portion of the pixel electrode 210 to define the light emitting area of ​​the pixel. The pixel defining layer 119 may increase the distance between the edge of the pixel electrode 210 and the counter electrode 230 located on the pixel electrode 210 to prevent arcing at the edge of the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin. The pixel defining layer 119 may be obtained by spin coating, etc.

[0155] The intermediate layer 220 of the organic light emitting diode OLED may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent or phosphor material emitting red, green, blue or white light. The organic light emitting layer may include a low molecular organic material or a polymer organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be selectively arranged below and above the organic light emitting layer. The intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210. In some embodiments, the intermediate layer 220 may be changed differently. For example, the intermediate layer 220 may be arranged throughout the plurality of pixel electrodes 210.

[0156] The counter electrode 230 may be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may be provided as a metal film including at least one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg and compounds thereof having a small work function. A substrate such as ITO, IZO, ZnO or In may also be provided over the metal film. 2 O 3The counter electrode 230 may be disposed throughout the display area DA and the non-display area NDA, and disposed on the intermediate layer 220 and the pixel defining layer 119. The counter electrode 230 may be provided as one body with respect to the plurality of organic light emitting diodes OLED to correspond to the plurality of pixel electrodes 210.

[0157] When the pixel electrode 210 is a reflective electrode and the counter electrode 230 is a transmissive electrode, light emitted from the intermediate layer 220 may be emitted toward the counter electrode 230. For example, the display device 1 may be a top emission type. When the pixel electrode 210 is a transparent or semi-transparent electrode and the counter electrode 230 is a reflective electrode, light emitted from the intermediate layer 220 may be emitted toward the substrate 100, and the display device 1 may be a bottom emission type. In some embodiments, the display device 1 may be a dual emission type in which light is emitted to the top and bottom surfaces.

[0158] Figure 7 A plan view for illustrating arrangement of wirings around the transmission area TA according to an embodiment is illustrated.

[0159] refer to Figure 7 , the scan lines SL0 to SL5 may extend in the first direction, and the data lines DL0 to DL7 may extend in the second direction and cross the scan lines SL0 to SL5.

[0160] Some of the scan lines SL1 to SL4 may be detoured around the transmission area TA. For example, the first scan line SL1 and the second scan line SL2 may be bent along the upper edge of the transmission area TA, and the third scan line SL3 and the fourth scan line SL4 may be bent along the lower edge of the transmission area TA. Each of the scan lines SL1 to SL4 may include a portion extending along the first direction in the display area DA and an arched portion (or a curved portion) around the edge of the transmission area TA in the first non-display area NDA1. The pixels P located on the left and right sides of the transmission area TA may be electrically connected to the scan lines SL1 to SL4 having the arched portion around the transmission area TA.

[0161] Some of the data lines DL1 to DL6 may be arched around the transmission area TA. For example, each of the data lines DL1 to DL6 may include a portion extending in the second direction and an arched portion around an edge of the transmission area TA. The arched portion in each of the data lines DL1 to DL6 may be located in the first non-display area NDA1.

[0162] The pixels P above and below the transmission area TA may be electrically connected to the data lines DL1 to DL6 that are arched around the transmission area TA. The pixels P may receive signals from corresponding data lines among the data lines DL1 to DL6. Among the data lines DL1 to DL6, the first to third data lines DL1 to DL3 may be bent along the left edge of the transmission area TA, and the fourth to sixth data lines DL4 to DL6 may be bent around the right edge of the transmission area TA.

[0163] The driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1 and PL3_2 may be arranged at the same layer as the data lines DL0 to DL7 to be spaced apart from each other. The driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1 and PL3_2 may extend in the second direction to cross the scan lines SL0 to SL5. Some of the driving voltage lines PL3_1 and PL3_2 may extend continuously to pass through the display area DA. The driving voltage lines PL1_1 to PL1_7 and PL2_1 to PL2_7 around the transmission area TA may be disconnected at the transmission area TA. For example, a plurality of first driving voltage lines PL1_1 to PL1_7 and a plurality of second driving voltage lines PL2_1 to PL2_7 may be spaced apart from each other with the transmission area TA therebetween.

[0164] A plurality of first driving voltage lines PL1_1 to PL1_7 may be connected to the above reference Figure 4 The first power line 160 is described. The plurality of second driving voltage lines PL2_1 to PL2_7 may be connected to the power bus 163 .

[0165] The electrode voltage lines HL0 to HL4 may extend in the first direction, crossing the driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1, and PL3_2. Some of the electrode voltage lines HL1 to HL3 may be arranged around the transmission area TA. For example, the first electrode voltage line HL1 may include a portion extending in the first direction and a portion arched around the upper portion of the transmission area TA. The third electrode voltage line HL3 may include a portion extending in the first direction and a portion arched around the lower portion of the transmission area TA. The second electrode voltage line HL2 may include a portion extending in the first direction and portions arched around the upper and lower portions of the transmission area TA, respectively. The arched portions in the second electrode voltage line HL2 may be connected to each other to provide a ring shape.

[0166] For each pixel circuit PC, the driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1 and PL3_2 and the electrode voltage lines HL0 to HL4 may be connected via the contact hole CNT. The driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, and PL3_1 and PL3_2 may extend in the second direction. The electrode voltage lines HL electrically connected to the driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1 and PL3_2 may extend in the first direction intersecting the second direction. Therefore, the plurality of driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1 and PL3_2 and the electrode voltage lines HL0 to HL4 may form a mesh structure in the display area DA.

[0167] In an embodiment, the power bus 163 may be provided to prevent an IR drop of the driving voltage ELVDD around the transmission area TA In this case, a width Wx of the transmission area TA in the first direction may be greater than a width Wy of the transmission area TA in the second direction.

[0168] For example, the width Wx of the transmission area TA in the first direction may be about 15 mm to about 20 mm, and the width Wy of the transmission area TA in the second direction may be about 1 mm to about 5 mm.

[0169] The plurality of second driving voltage lines PL2_1 to PL2_7 and the electrode voltage line HL0 may provide a mesh structure even when the power bus 163 is not provided. Therefore, the driving voltage ELVDD may be supplied to pixels arranged at an upper portion of the transmission area TA to operate the pixels.

[0170] As above reference Fig. 6A and Figure 6B As described above, the electrode voltage lines HL0 to HL4 may be obtained by connecting the second storage capacitor plate CE2 of the storage capacitor Cst included in each pixel. Therefore, the specific resistance of the electrode voltage lines HL0 to HL4 may be greater than the specific resistance of the driving voltage lines PL1_1 to PL1_7, PL2_1 to PL2_7, PL3_1, and PL3_2.

[0171] If the power bus 163 is not provided, the driving voltage ELVDD can be supplied to the second driving voltage lines PL2_1 to PL2_7 only through the electrode voltage line HL0 having a larger specific resistance. Therefore, IR drop may occur. When the width Wx of the transmission area TA in the first direction increases, the degree of IR drop may be greater.

[0172] In an embodiment, a power bus 163 having a relatively small specific resistance and disposed in a second non-display area NDA2 is connected to a plurality of second driving voltage lines PL2_1 to PL2_7. Accordingly, IR drops that may occur on the driving voltage lines PL1_1 to PL1_7 and PL2_1 to PL2_7, which are disconnected based on the transmissive area TA, can be reduced.

[0173] The power bus 163 may include a conductive material containing Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. As an example, the power bus 163 may have a multi-layer structure including Ti / Al / Ti.

[0174] In an embodiment, the power bus 163 may be provided integrally with a plurality of second driving voltage lines PL2_1 to PL2_7. For example, the power bus 163 may be provided on the same layer as the plurality of second driving voltage lines PL2_1 to PL2_7 by using the same material. The plurality of second driving voltage lines PL2_1 to PL2_7 may extend in a second direction from the power bus 163 extending in a first direction.

[0175] The power bus 163 may be connected to a plurality of third driving voltage lines PL3_1 and PL3_2 extending from a first power line 160. For example, the first power line 160 (see Figure 4 ), the power bus 163, and the third driving voltage lines PL3_1 and PL3_2 may be provided integrally with each other. In this case, the power bus 163 may receive a driving voltage ELVDD provided from the first power line 160 via the plurality of third driving voltage lines PL3_1 and PL3_2, and the uniform driving voltage ELVDD may be supplied to the plurality of second driving voltage lines PL2_1 to PL2_7.

[0176] The width W1 of the power bus 163 in the second direction may be greater than the width W2 of one of the second driving voltage lines PL2_1 to PL2_7 to reduce the resistance value. For example, the width W1 of the power bus 163 in the second direction may be about 10 μm to about 30 μm, and the width W2 of one of the second driving voltage lines PL2_1 to PL2_7 may be about 1 μm to about 5 μm.

[0177] Moreover, as Figure 4 shown, the length L2 of the power bus 163 in the first direction may be less than the length L1 of the first power line 160 in the first direction (L2 < L1). The power bus 163 may be connected to the second driving voltage lines PL2_1 to PL2_7 that are disconnected around the transmissive area TA to prevent IR drops. When the length L2 of the power bus 163 in the first direction is reduced, the utilization rate of the second non-display area NDA2 can be improved.

[0178] Figure 8 Shown along Figure 7 A cross-sectional view taken along the line X-X' in FIG. Figure 8 In the drawings, the same reference numerals denote Figure 6B The elements are the same as the elements of , and their detailed description will not be repeated.

[0179] refer to Figure 8 , the data line DL6 , the scan lines SL0 and SL1 , and the electrode voltage lines HL0 and HL1 are arranged in different layers from each other, and the data line DL6 , the driving voltage line PL2_7 , and the power bus line 163 may be arranged in the same layer as each other.

[0180] The scan lines SL0 and SL1 may be located on the first gate insulating layer 112, and the electrode voltage lines HL0 and HL1 may be located on the second gate insulating layer 113. The data line DL6, the driving voltage line PL2_7, and the power bus line 163 may be disposed on the interlayer insulating layer 115.

[0181] refer to Figure 7 and Figure 8 , the data line DL6 , the scan line SL1 , and the electrode voltage line HL1 arched in the first non-display area NDA1 are shown not to overlap with each other. In some embodiments, wirings arranged in different layers in the first non-display area NDA1 may overlap with each other.

[0182] Fig. 9 A plan view illustrating the arrangement of wirings around a transmissive area TA of a display panel according to an embodiment. Fig.10 Shown along Fig. 9 A cross-sectional view of a portion of the pixel area taken along line XI-XI' in FIG. Fig. 9 and Fig.10 In, with Figure 6B , Figure 7 and Figure 8 The same reference numerals as those in the accompanying drawings denote the same elements, and a detailed description thereof will not be repeated.

[0183] refer to Fig. 9 The display panel may include a plurality of first driving voltage lines PL1_1 to PL1_7 and a plurality of second driving voltage lines PL2_1 to PL2_7 spaced apart from each other with the transmissive area TA therebetween. The plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 extend in the second direction.

[0184] The data lines DL1 to DL6 arranged around the transmission area TA may not be disconnected, but may be arranged to be arranged around the boundary of the transmission area TA. When the data lines DL1 to DL6 and the driving voltage lines PL are arranged at the same layer, the driving voltage lines PL may be spaced apart from each other to ensure space for arching the data lines DL1 to DL6.

[0185] The plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may be connected to the electrode voltage lines HL0 to HL4 via the contact holes CNT1, and the electrode voltage lines HL0 to HL4 are arranged at different layers to cross the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7. Therefore, the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may have a mesh structure with the electrode voltage lines HL0 to HL4.

[0186] In this embodiment, the power bus 164 connected to the plurality of second driving voltage lines PL2_1 to PL2_7 may be disposed in the first non-display area NDA1 to correspond to an upper portion of the transmission area TA.

[0187] The power bus 164 may be arranged at a different layer from the plurality of second driving voltage lines PL2_1 to PL2_7. For example, the power bus 164 may be located on the planarization layer 117 for covering the plurality of second driving voltage lines PL2_1 to PL2_7 to be connected to the plurality of second driving voltage lines PL2_1 to PL2_7 via the contact hole CNT2. When the power bus 164 is arranged at a different layer from the layer of the plurality of second driving voltage lines PL2_1 to PL2_7, the power bus 164 may be arranged to overlap the plurality of second driving voltage lines PL2_1 to PL2_7 and the data lines DL2 to DL6.

[0188] In addition, the power bus 164 may overlap the scan lines SL1 and SL2 that are arched around the edge of the transmission area TA.

[0189] The power bus 164 may extend in the first direction. In some embodiments, the length L2' of the power bus 164 in the first direction may be less than the length L1 of the first power line 160 in the first direction, as described above with reference to Figure 4 In some embodiments, the number of driving voltage lines PL connected to the power bus 164 may be less than the number of driving voltage lines PL connected to the first power line 160. In some embodiments, the length L2' of the power bus 164 in the first direction may be equal to or greater than the width Wx of the transmission area TA in the first direction.

[0190] In addition, the specific resistance of the power bus 164 may be smaller than that of the electrode voltage lines HL0 to HL4. Therefore, an IR drop that may occur in the second driving voltage lines PL2_1 to PL2_7 may be reduced.

[0191] refer to Fig.10 The display panel according to the embodiment may further include an upper planarization layer 118 on the planarization layer 117. The additional wiring PL′, the intermediate wiring CM, and the power bus 164 may be arranged on the planarization layer 117.

[0192] The upper planarization layer 118 may include an organic material and / or an inorganic material. For example, the organic material may include a general polymer (BCB, polyimide, HMDSO, PMMA, or PS), a polymer derivative having a phenol group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof. The inorganic material may include a silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 The upper planarization layer 118 may include a single layer or a multi-layer structure.

[0193] The additional wiring PL' disposed on the planarization layer 117 may be used as a driving voltage line for transmitting a driving voltage or a data line for transmitting a data signal. The additional wiring PL' may be connected to the data line DL or the driving voltage line PL via a contact hole defined in the planarization layer 117. Also, the pixel electrode 210 of the organic light emitting diode OLED may be connected to the emission control TFT T6 via the intermediate wiring CM on the planarization layer 117. The pixel electrode 210 may be located on the upper planarization layer 118 and may be connected to the intermediate wiring CM via a contact hole defined in the upper planarization layer 118.

[0194] The power bus 164 may be located on the planarization layer 117 , and may be connected to the second driving voltage line PL2_7 via a contact hole CNT2 defined in the planarization layer 117 .

[0195] The power bus 164, the additional wiring PL' and the intermediate wiring CM may each include Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. As an example, the power bus 164 may have a multi-layer structure including Ti / Al / Ti. The specific resistance of the power bus 164 may be smaller than the specific resistance of the electrode voltage lines HL0 to HL4. Therefore, a uniform driving voltage ELVDD may be transmitted to the plurality of second driving voltage lines PL2_1 to PL2_7, and IR drop may be reduced.

[0196] exist Fig. 9 , the power bus 164 is shown as being connected only to the plurality of second driving voltage lines PL2_1 to PL2_7. In some embodiments, the power bus 164 may be connected to the first power line 160 (see Figure 4 ) at least one third driving voltage line among a plurality of third driving voltage lines PL3_1 and PL3_2 extending from the first driving voltage line PL3_1.

[0197] Fig.11 FIG. 1 is a plan view showing the arrangement of wirings around the transmissive area TA of the display panel according to an embodiment. Fig.11 In the drawings, the same reference numerals denote Fig. 9 The same elements as those of the components of FIG. 1 and their detailed description will not be repeated.

[0198] refer to Fig.11 , the display panel according to this embodiment includes a plurality of first driving voltage lines PL1_1 to PL1_7 extending in a second direction from a first power line 160 and a plurality of second driving voltage lines PL2_1 to PL2_7 spaced apart from the plurality of first driving voltage lines PL1_1 to PL1_7 with transmission areas TA therebetween.

[0199] The data lines DL1 to DL6 arranged around the transmission area TA may not be disconnected, but may be arranged to be arranged around the boundary of the transmission area TA. When the data lines DL1 to DL6 are arranged at the same layer as the layer of the driving voltage lines PL, the driving voltage lines PL may be spaced apart from each other so as to ensure space for arching the data lines DL1 to DL6.

[0200] The plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may be connected to the electrode voltage lines HL0 to HL4 via the contact holes CNT1, and the electrode voltage lines HL0 to HL4 are arranged at different layers to cross the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7. Therefore, the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may have a mesh structure with the electrode voltage lines HL0 to HL4.

[0201] In the display panel according to the embodiment, the power bus 164 may be disposed in the transmission area TA, and the additional power bus 165 may be disposed at a lower portion of the transmission area TA.

[0202] The power bus 164 may be arranged in the first non-display area NDA1 to correspond to the upper portion of the transmission area TA. The power bus 164 may extend in the first direction. In some embodiments, the length L2' of the power bus 164 in the first direction may be equal to or greater than the width Wx of the transmission area TA in the first direction.

[0203] The power bus 164 may be formed by a planarization layer 117 (see Fig.10 ) is provided between the power bus 164 and the plurality of second driving voltage lines PL2_1 to PL2_7 and is arranged. The power bus 164 may be connected to the ends of the plurality of second driving voltage lines PL2_1 to PL2_7 via the contact hole CNT2. In some embodiments, the power bus 164 may be connected to at least one third driving voltage line of the plurality of third driving voltage lines PL3_1 and PL3_2 via the contact hole CNT2.

[0204] The additional power bus 165 may be arranged in the first non-display area NDA1 to correspond to the lower portion of the transmission area TA. The additional power bus 165 may extend in the first direction. In some embodiments, the length L3 of the additional power bus 165 in the first direction may be equal to or greater than the width Wx of the transmission area TA in the first direction. The additional power bus 165 may be formed with the planarization layer 117 (see Fig.10 ) is provided between the additional power bus 165 and the plurality of first driving voltage lines PL1_1 to PL1_7 and is arranged. The additional power bus 165 may be connected to the ends of the plurality of first driving voltage lines PL1_1 to PL1_7 via the contact hole CNT3. In some embodiments, the additional power bus 165 may be connected to at least one of the plurality of third driving voltage lines PL3_1 and PL3_2 via the contact hole CNT3.

[0205] The power bus 164 and the additional power bus 165 may each include Mo, Al, Cu, Ti, etc., and may have a single layer or multilayer structure. As an example, the power bus 164 and the additional power bus 165 may each have a multilayer structure including Ti / Al / Ti.

[0206] The specific resistance of the power bus 164 and the additional power bus 165 may be smaller than the specific resistance of the electrode voltage lines HL0 to HL4. Therefore, a constant driving voltage ELVDD may be transmitted to the plurality of first driving voltage lines PL1_1 to PL1_7, the plurality of second driving voltage lines PL2_1 to PL2_7, and the plurality of third driving voltage lines PL3_1 and PL3_2 arranged around the transmission area TA, and IR drop may be reduced.

[0207] Fig.12 FIG. 1 is a plan view showing the arrangement of wirings around the transmissive area TA of the display panel according to an embodiment. Fig.12 In the drawings, the same reference numerals denote Figure 7 The same elements as those of the components of FIG. 1 and their detailed description will not be repeated.

[0208] refer to Fig.12 The display panel may include a plurality of first driving voltage lines PL1_1 to PL1_7 and a plurality of second driving voltage lines PL2_1 to PL2_7 spaced apart from each other with the transmissive area TA therebetween. The plurality of first driving voltage lines PL1_1 to PL1_7 and a plurality of second driving voltage lines PL2_1 to PL2_7 may extend in the second direction.

[0209] The plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may be connected to the electrode voltage lines HL0 to HL4 via the contact holes CNT1, and the electrode voltage lines HL0 to HL4 are arranged at different layers to cross the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7. Therefore, the plurality of first driving voltage lines PL1_1 to PL1_7 and the plurality of second driving voltage lines PL2_1 to PL2_7 may have a mesh structure with the electrode voltage lines HL0 to HL4.

[0210] The data lines DL1 to DL6 arranged around the transmission area TA may not be disconnected, but may be arranged to be arranged around the boundary of the transmission area TA. When the data lines DL1 to DL6 are arranged at the same layer as the layer of the driving voltage lines PL, the driving voltage lines PL may be spaced apart from each other so as to ensure space for arching the data lines DL1 to DL6.

[0211] A plurality of second driving voltage lines PL2_1 to PL2_7 may be arranged in the second non-display area NDA2 and may be connected to a power bus 163 extending in the first direction. When the power bus 163 has a lower specific resistance than the electrode voltage lines HL0 to HL4, an IR drop that may occur in the second driving voltage lines PL2_1 to PL2_7 may be reduced.

[0212] In this embodiment, there may be a plurality of transmission areas TA1, TA2, and TA3. The first non-display area NDA1 may be arranged to surround the plurality of transmission areas TA1, TA2, and TA3. A component for sensing light or sound may be arranged in each of the plurality of transmission areas TA1, TA2, and TA3. Fig.12 , three transmission areas TA1, TA2 and TA3 are shown. In some embodiments, there may be one or two transmission areas or more than three transmission areas.

[0213] In addition, when the plurality of transmission areas TA1, TA2 and TA3 are surrounded by the first non-display area NDA1, the width Wx of the plurality of transmission areas TA1, TA2 and TA3 in the first direction may be identified as the length of a line connecting the rightmost point to the leftmost point of the plurality of transmission areas TA1, TA2 and TA3.

[0214] In this embodiment, a power bus 163 may be provided to prevent an IR drop of the driving voltage ELVDD around the plurality of transmission areas TA1, TA2, and TA3. A width Wx of the transmission area TA in the first direction may be greater than a width Wy of the transmission area TA in the second direction. In this embodiment, a width Wx of the plurality of transmission areas TA1, TA2, and TA3 in the first direction may be about 15 mm to about 20 mm.

[0215] According to some embodiments, it is possible to reduce IR drop that may occur in wiring around a transmission area corresponding to electronic components such as a sensor, a camera, etc. Therefore, it is possible to improve display quality.

[0216] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted only in a general and descriptive sense and not for limiting purposes. In some cases, as will be apparent to those of ordinary skill in the art from the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly stated. Therefore, it will be understood by those skilled in the art that various modifications may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display panel, comprising: A substrate comprising a first non-display area surrounding a transmission area, a display area outside the first non-display area, and a second non-display area surrounding the display area; A driving thin film transistor and a display element are located in the display area; A first power line, located in the second non-display area, the first power line extending in a first direction; a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction crossing the first direction and spaced apart from each other with the transmission area located between the plurality of first driving voltage lines and the plurality of second driving voltage lines; as well as A power bus connected to the plurality of second driving voltage lines is located in the first non-display area or the second non-display area, and the power bus extends in the first direction. Wherein, the length of the power bus in the first direction is smaller than the length of the first power line in the first direction.

2. The display panel according to claim 1, wherein: The power bus is located in the second non-display area and is integrated with the plurality of second driving voltage lines.

3. The display panel according to claim 1, further comprising: at least one third driving voltage line extending from the first power line in the second direction and connected to the power bus, Wherein, the at least one third driving voltage line, the first power line and the power bus are integrated with each other.

4. The display panel according to claim 1, further comprising: at least one fourth driving voltage line extending from the first power line in the second direction, Wherein, an end portion of the at least one fourth driving voltage line is spaced apart from the power bus.

5. The display panel according to claim 1, further comprising: a plurality of electrode voltage lines, arranged at a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, the plurality of electrode voltage lines extending in the first direction and crossing the plurality of first driving voltage lines and the plurality of second driving voltage lines, The plurality of electrode voltage lines are connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via contact holes.

6. The display panel according to claim 5, wherein: The specific resistance of the power bus is smaller than the specific resistance of the plurality of electrode voltage lines.

7. The display panel according to claim 5, wherein: At least some of the plurality of electrode voltage lines each include a raised portion connected to each other in a ring shape around the transmission area.

8. The display panel according to claim 5, wherein: Each of the driving thin film transistors includes a semiconductor layer and a driving gate electrode, and The plurality of electrode voltage lines overlap the driving gate electrode to form a storage capacitor.

9. The display panel according to claim 1, wherein: A width of the transmission area in the first direction is greater than a width of the transmission area in the second direction.

10. The display panel according to claim 1, wherein: The power bus is located in the first non-display area, is located at a different layer from the plurality of second driving voltage lines, and is connected to the plurality of second driving voltage lines via contact holes.

11. The display panel according to claim 10, further comprising: a plurality of scanning lines extending in the first direction and arching around the boundary of the transmission area, Wherein, the power bus overlaps with the arched parts of the plurality of scan lines.

12. The display panel according to claim 1, further comprising: an additional power bus connected to the plurality of first driving voltage lines and extending in the first direction, Wherein, the additional power bus is arranged in the first non-display area.

13. The display panel according to claim 1, wherein: The transmission area includes a plurality of transmission areas, and the first non-display area surrounds the plurality of transmission areas.

14. A display panel, comprising: A substrate comprising a first non-display area surrounding a transmission area, a display area outside the first non-display area, and a second non-display area surrounding the display area; A driving thin film transistor and a display element are located in the display area; A first power line, located in the second non-display area, the first power line extending in a first direction; a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction crossing the first direction and spaced apart from each other with the transmission area located between the plurality of first driving voltage lines and the plurality of second driving voltage lines; as well as a power bus connected to the plurality of second driving voltage lines, the power bus being located in the first non-display area or the second non-display area to extend in the first direction; as well as a plurality of electrode voltage lines crossing the plurality of first driving voltage lines and the plurality of second driving voltage lines, being located at a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, and the plurality of electrode voltage lines being connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via contact holes, Wherein, the specific resistance of the power bus is smaller than the specific resistance of the plurality of electrode voltage lines.

15. The display panel according to claim 14, wherein: At least some of the plurality of electrode voltage lines each include a raised portion connected to each other in a ring shape around the transmission area.

16. The display panel according to claim 14, wherein: Each of the driving thin film transistors includes a semiconductor layer and a driving gate electrode, and The plurality of electrode voltage lines overlap the driving gate electrode to form a storage capacitor.

17. The display panel according to claim 14, wherein: The power bus is located in the second non-display area and is integrated with the plurality of second driving voltage lines.

18. The display panel according to claim 14, wherein: The power bus is located in the first non-display area and is located at a different layer from the plurality of second driving voltage lines to be connected to the plurality of second driving voltage lines through contact holes.

19. The display panel according to claim 14, further comprising: an additional power bus connected to the plurality of first driving voltage lines and extending in the first direction, Wherein, the additional power bus is located in the first non-display area.

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