Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The method includes providing a semiconductor substrate; forming a redistribution line on a top surface of the semiconductor substrate; and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. Forming the redistribution line includes a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line. The average grain size of the second segment of the redistribution line is smaller than the average grain size of the first segment of the redistribution line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This nonprovisional application claims priority from Korean Patent Application No. 10-2018-0096751 filed on August 20, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device and / or a method of manufacturing the same, and more particularly, to a semiconductor device including a redistribution layer and / or a method of manufacturing the same. Background Art

[0004] Semiconductor devices are beneficial in the electronics industry due to their small size, multifunctionality, and / or low manufacturing cost.As the electronics industry develops, semiconductor devices become highly integrated.

[0005] To achieve higher integration densities, the line width of semiconductor device patterns is being reduced. However, new and / or inexpensive exposure techniques are required to define finer patterns. Consequently, it is difficult to highly integrate semiconductor devices. Consequently, various research efforts have been conducted into new integration technologies.

[0006] As performance and integration in semiconductor devices have advanced, technologies for manufacturing semiconductor devices or packages with higher signal transmission rates and compact sizes have been developed. For example, redistribution lines are used to reduce the size and increase the electrical characteristics of semiconductor devices. Summary of the Invention

[0007] Some example embodiments of the inventive concepts provide a semiconductor device having improved structural stability and / or a method of manufacturing the same.

[0008] Some example embodiments of the inventive concepts provide methods of manufacturing semiconductor devices, which facilitate processes.

[0009] According to example embodiments of the present inventive concepts, a method for manufacturing a semiconductor device may include providing a semiconductor substrate, forming a redistribution line on a top surface of the semiconductor substrate, and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. Forming the redistribution line may include forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and forming a second segment of the redistribution line on the first segment of the redistribution line. The average grain size of the second segment of the redistribution line may be smaller than the average grain size of the first segment of the redistribution line.

[0010] According to example embodiments of the present inventive concepts, a semiconductor device may include: a semiconductor substrate; a redistribution line located on a top surface of the semiconductor substrate, the redistribution line including a first segment on the top surface of the semiconductor substrate and a second segment on a top surface of the first segment; a passivation layer covering the redistribution line on the top surface of the semiconductor substrate; and a pad located on the passivation layer, the pad penetrating the passivation layer and contacting the redistribution line. An average grain size of the second segment of the redistribution line may be smaller than an average grain size of the first segment of the redistribution line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concepts is shown.

[0012] Figure 2 Shown Shown Figure 1 Magnified view of part II.

[0013] Figure 3 A photograph capturing the top surface of the first section is shown according to an example embodiment.

[0014] Figure 4 A photograph capturing the top surface of the second section is shown according to an example embodiment.

[0015] Figures 5 to 14 Cross-sectional views illustrating a method of fabricating a semiconductor device according to example embodiments of the inventive concepts are shown.

[0016] Figure 15 A graph showing the relationship between current density and grain density while forming grains using a step plating process is shown. DETAILED DESCRIPTION

[0017] Although the term "same" is used in the description of the exemplary embodiments, it should be understood that some errors may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that one element is the same as the other element within an expected manufacturing tolerance range (e.g., ±10%).

[0018] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the precise geometric shape is not required, but rather that a tolerance for the shape is within the scope of the present disclosure.

[0019] Hereinafter, a semiconductor device according to the inventive concept will be described with reference to the accompanying drawings. Figure 1A cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concepts is shown. Figure 2 Shown Shown Figure 1 Magnified view of part II.

[0020] refer to Figure 1 The semiconductor device may include: a semiconductor substrate 100 having one or more metal lines 120 disposed on a first surface 100a thereof, an interlayer dielectric layer 200 covering the first surface 100a of the semiconductor substrate 100, a through-electrode 110 penetrating the semiconductor substrate 100, a redistribution line 300 electrically connected to the through-electrode 110, and a passivation layer 500 covering the redistribution line 300. The through-electrode 110 may further penetrate at least a portion of the interlayer dielectric layer 200.

[0021] A semiconductor substrate 100 may be provided. The semiconductor substrate 100 may have a second surface 100b facing the first surface 100a. The semiconductor substrate 100 may be a semiconductor wafer (e.g., a silicon wafer) including various semiconductor components. For example, the first surface 100a may be an active surface of the semiconductor substrate 100. The first surface 100a may be an active surface on which a circuit pattern (not shown) electrically connected to the metal line 120 is provided, and the second surface 100b may be an inactive surface of the semiconductor substrate 100. The circuit pattern (not shown) may include a memory circuit, a logic circuit, or a combination thereof. Although not shown, a passive device (e.g., a capacitor or a resistor) may be provided on the first surface 100a of the semiconductor substrate 100.

[0022] The through electrode 110 may penetrate the semiconductor substrate 100 and may be electrically connected to the metal line 120. The through electrode 110 may include a conductor (e.g., copper (Cu), tungsten (W), or polysilicon). Although not shown, a via dielectric layer and a via barrier layer may be further provided around the through electrode 110. The through electrode 110 may be electrically insulated from the semiconductor substrate 100 by the via dielectric layer. The via barrier layer may inhibit the material of the through electrode 110 (e.g., copper) from migrating into the semiconductor substrate 100 through the gap between the through electrode 110 and the via dielectric layer. The via barrier layer may include, for example, titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The via dielectric layer may include, for example, silicon oxide (SiOx) or silicon nitride (SiNx).

[0023] The metal lines 120 may be disposed on the first surface 100 a of the semiconductor substrate 100 . The metal lines 120 may be arranged in one or more columns at the center or edge of the first surface 100 a of the semiconductor substrate 100 . The metal lines 120 may be coupled to internal circuits including circuit patterns and / or passive devices. The metal lines 120 may electrically connect the circuit patterns and / or passive devices to the through electrodes 110 .

[0024] An interlayer dielectric layer 200 may be disposed on the first surface 100a of the semiconductor substrate 100. The interlayer dielectric layer 200 may cover the circuit pattern and / or passive devices disposed on the first surface 100a of the semiconductor substrate 100. The interlayer dielectric layer 200 may protect the circuit pattern and / or passive devices. The interlayer dielectric layer 200 may include an oxide or a nitride. For example, the interlayer dielectric layer 200 may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0025] In the case where the second surface 100b is the active surface of the semiconductor substrate 100, a protective layer (also referred to as a passivation layer) or a dielectric layer may be provided on the second surface 100b of the semiconductor substrate 100. The protective layer or dielectric layer may protect the circuit pattern provided on the second surface 100b of the semiconductor substrate 100. For example, the protective layer or dielectric layer may include silicon oxide (SiOx) or silicon nitride (SiNx). An example in which the first surface 100a is the active surface of the semiconductor substrate 100 will be described below.

[0026] The redistribution line 300 may be disposed on the second surface 100b of the semiconductor substrate 100. The redistribution line 300 may be electrically connected to the through-electrode 110 in the semiconductor substrate 100. The redistribution line 300 may have a thickness of about 15 μm or less, and more narrowly a thickness from about 10 μm to about 15 μm. The redistribution line 300 may include a metal material. For example, the redistribution line 300 may be formed of copper (Cu). A barrier layer 410 and a seed layer 420 may be provided between the redistribution line 300 and the semiconductor substrate 100. The barrier layer 410 may include, for example, titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The seed layer 420 may include, for example, copper (Cu), ruthenium (Ru), nickel (Ni), or tungsten (W). According to some example embodiments, the barrier layer 410 may not be provided.

[0027] refer to Figure 2, the redistribution line 300 may include a first segment 310 and a second segment 320 sequentially stacked on the second surface 100b of the semiconductor substrate 100. The second segment 320 of the redistribution line 300 may have a thickness of approximately 0.01 times or 0.5 times the thickness of the first segment 310. The first segment 310 and the second segment 320 of the redistribution line 300 may be formed of the same material. For example, the first segment 310 and the second segment 320 of the redistribution line 300 may include copper (Cu). In this case, the interface between the first segment 310 and the second segment 320 of the redistribution line 300 may not be visible, and the first segment 310 and the second segment 320 may have a continuous configuration at the interface therebetween. In some example embodiments, the interface between the first segment 310 and the second segment 320 of the redistribution line 300 may be visible.

[0028] The average grain size of the second section 320 may be smaller than the average grain size of the first section 310. In this specification, the average grain area may be defined by dividing a specific area by the number of grains included in the specific area, and the diameter of a circle having the average grain area may be defined as the average grain size. In some example embodiments, the average grain size may be determined by diameter measurement, the American Society for Testing and Materials (ASTM) grain size number, etc. For ease of description, Figure 2 The grain size is exaggerated, and the size ratio between the grains and the material of the semiconductor device may be different from the actual ratio. In the redistribution line 300, the average grain size GS2 of the second section 320 may be less than about 70% of the average grain size GS1 of the first section 310. For example, in the redistribution line 300, the average grain size GS2 of the second section 320 may be about 10% to about 30% of the average grain size GS1 of the first section 310.

[0029] The difference in average grain size may cause the surface roughness of the second segment 320 of the redistribution line 300 to be less than the surface roughness of the first segment 310 of the redistribution line 300. For example, the surface roughness of the top surface 320a of the second segment 320 may be less than the surface roughness of the top surface 310a or the bottom surface 310b of the first segment 310. The top surface 320a of the second segment 320 may correspond to the top surface of the redistribution line 300, and thus, the top surface 320a of the second segment 320 and the top surface of the redistribution line 300 may be denoted by the same reference numeral 320a.

[0030] Figure 3 A photograph of the first section 310 or a photograph of the top surface 310 a of the first section 310 is shown. Figure 4 A photograph of the second section 320 or a photograph of the top surface 320a of the second section 320 is shown. Figure 3, the top surface 310 a of the first section 310 of the redistribution line 300 may have a high color variation. Figure 3 It can be indicated that the top surface 310a of the first section 310 has a relatively high roughness. Figure 4 , the top surface 320 a of the second section 320 of the redistribution line 300 may have low color variation. Figure 4 This indicates that the top surface 320a of the second section 320 has a relatively low roughness. In other words, the top surface 310a of the first section 310 of the redistribution line 300 has a higher roughness than the top surface 320a of the second section 320. Therefore, the redistribution line 300 may have increased adhesion to the passivation layer 500 and / or the redistribution pad 600.

[0031] In some example embodiments, a metal conductive line (e.g., a pad, another redistribution line, or a metal filler) may be provided on the redistribution line 300, thereby increasing adhesion between the redistribution line 300 and the metal conductive line. Since the top surface 320a of the redistribution line 300 has a relatively low surface roughness and a relatively high flatness, the gap between the redistribution line 300 and the passivation layer 500 or between the redistribution line 300 and the metal conductive line may be reduced. As a result, the semiconductor device may have improved structural stability.

[0032] In some example embodiments, Figure 2 As shown, the redistribution line 300 may further include a third segment 330 between the first segment 310 and the semiconductor substrate 100. For example, the redistribution line 300 may include the third segment 330, the first segment 310, and the second segment 320 sequentially stacked on the second surface 100b of the semiconductor substrate 100. In the redistribution line 300, the third segment 330 may have an average grain size GS3 that is smaller than the average grain size GS1 of the first segment 310. In the redistribution line 300, the average grain size GS3 of the third segment 330 may be less than approximately 70% of the average grain size GS1 of the first segment 310. For example, the surface roughness of the bottom surface 330a of the third segment 330 may be smaller than the surface roughness of the bottom surface 310b of the first segment 310. The bottom surface 330a of the third section 330 may correspond to the bottom surface of the redistribution line 300. Therefore, the bottom surface 330a of the third section 330 and the bottom surface of the redistribution line 300 may be represented by the same reference numeral 330a. Therefore, the redistribution line 300 may have increased adhesion to the semiconductor substrate 100, the barrier layer 410, or the seed layer 420, thereby improving the structural stability of the semiconductor device.

[0033] Return Reference Figure 1, a passivation layer 500 may be disposed on the second surface 100b of the semiconductor substrate 100. The passivation layer 500 may cover the redistribution line 300. The passivation layer 500 may include an inorganic dielectric layer or an organic dielectric layer. For example, the passivation layer 500 may include an organic dielectric layer (e.g., photosensitive polyimide (PSPI) or polybenzoxazole (PBO)). The passivation layer 500 may have a thickness of about 3 μm to about 5 μm.

[0034] The oxide layer 510 may be provided between the redistribution line 300 and the passivation layer 500. The oxide layer 510 may contact the second segment 320 of the redistribution line 300. The oxide layer 510 may include the oxide material included in the redistribution line 310. The oxide layer 510 may have a thickness of about 50 nm to about 200 nm, more narrowly about 100 nm. The oxide layer 510 may prevent material (e.g., copper (Cu)) from migrating from the redistribution line 300. In some example embodiments, the oxide layer 510 may not be provided, and the passivation layer 500 may contact the second segment 320 of the redistribution line 300.

[0035] The redistribution pad 600 may be provided to be electrically connected to the redistribution line 300. The redistribution pad 600 may contact the redistribution line 300 while penetrating the passivation layer 500 and the oxide layer 510. When viewed in a plan view, the redistribution pad 600 may be provided spaced apart from the through-electrode 110. The redistribution pad 600 may include a conductive material. The redistribution pad 600 may include a metal (e.g., copper (Cu), ruthenium (Ru), nickel (Ni), or tungsten (W)).

[0036] The external terminal 700 may be provided on the redistribution pad 600. The external terminal 700 may be shaped like a solder ball. In some example embodiments, the external terminal 700 may be a solder bump.

[0037] Figures 5 to 14 Cross-sectional views illustrating a method of fabricating a semiconductor device according to example embodiments of the inventive concepts are shown. Figure 15 A graph showing the relationship between current density and grain density obtained from three different experiments conducted while forming grains using a stepwise electroplating process is shown.

[0038] refer to Figure 5 , a semiconductor substrate 100 may be provided having a first surface 100a and a third surface 100c facing each other. The semiconductor substrate 100 may be a semiconductor wafer including various components of a semiconductor device. The semiconductor substrate 100 may include a circuit pattern (e.g., a memory circuit, a logic circuit, or a combination thereof). For example, a transistor may be formed on the first surface 100a of the semiconductor substrate 100. Passive devices (e.g., capacitors or resistors) may also be formed on the first surface 100a of the semiconductor substrate 100.

[0039] An interlayer dielectric layer 200, a through-electrode 110, and / or a metal line 120 may be formed on the first surface 100a of the semiconductor substrate 100. For example, an oxide or nitride covering the circuit pattern and passive devices may be coated on the first surface 100a of the semiconductor substrate 100 to form a portion of the interlayer dielectric layer 200. Thereafter, the through-electrode 110 may be formed. For example, a hole may be formed by etching a portion of the semiconductor substrate 100 and the interlayer dielectric layer 200, and then the hole may be filled with a conductive material to form the through-electrode 110. The through-electrode 110 may have a length sufficient to penetrate the semiconductor substrate 100 but insufficient to reach the third surface 100c of the semiconductor substrate 100. The through-electrode 110 may be formed by electroplating or depositing a conductor (e.g., copper (Cu), tungsten (W), or polysilicon). Although not shown, a via barrier layer and a via dielectric layer may be formed to surround the side and top surfaces of the through-electrode 110. An oxide or nitride may be applied to cover the through-electrode 110 to form an interlayer dielectric layer 200. The interlayer dielectric layer 200 may be formed as a single layer composed of a single material or as a multilayer composed of a plurality of different materials. The metal line 120 may be formed on the bottom surface of the interlayer dielectric layer 200. The metal line 120 may be formed by depositing a metal (e.g., copper (Cu), aluminum (Al), or tungsten (W)) on the interlayer dielectric layer 200 and then patterning the metal.

[0040] refer to Figure 6 , the third surface 100c of the semiconductor substrate 100 may be polished. A planarization process (e.g., chemical mechanical polishing (CMP) or etch back) may be performed on the third surface 100c of the semiconductor substrate 100. The planarization process may expose the second surface 100b of the semiconductor substrate 100. The semiconductor substrate 100 may be planarized. When the planarization process is performed, the through-electrode 110 may also be polished. The second surface 100b of the semiconductor substrate 100 may expose the top surface of the through-electrode 110.

[0041] The first mask pattern MP1 may be formed on the second surface 100b of the semiconductor substrate 100. The first mask pattern MP1 may have a groove GR exposing the through electrode 110. The first mask pattern MP1 may include an organic material (eg, photoresist) or an inorganic material (eg, silicon oxide (SiOx) or silicon nitride (SiNx)).

[0042] refer to Figure 7A barrier layer 410, a seed layer 420, and a sacrificial layer 800 may be formed on the second surface 100b of the semiconductor substrate 100. The barrier layer 410 may be formed by coating, for example, titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN) to conformally cover the groove GR and the top surface of the first mask pattern MP1. The seed layer 420 may be formed by coating, for example, copper (Cu), ruthenium (Ru), nickel (Ni), or tungsten (W) to cover the barrier layer 410. The sacrificial layer 800 may fill the groove GR. The sacrificial layer 800 may include an organic material (e.g., a photoresist) or an inorganic material (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)).

[0043] refer to Figure 8 , the seed layer 420 may be partially removed. A wet etching process may be performed to partially remove the seed layer 420. When the wet etching process is performed, a portion of the seed layer 420 may remain in the groove GR. Therefore, the seed layer 420 may be confined in the groove GR and between the sacrificial layer 800 and the barrier layer 410 to form a seed layer pattern 420'. In some example embodiments, the seed layer 420 may be confined in the groove GR while extending from the gap between the sacrificial layer 800 and the barrier layer 410 along the side surface of the sacrificial layer 800.

[0044] like Figure 11 As shown, after removing the sacrificial layer 800, a redistribution line 300 may be formed in the groove GR. The redistribution line 300 may include a metal (eg, copper (Cu)). Figures 9 to 12 The formation of the redistribution line 300 is described in detail.

[0045] refer to Figure 9 , the sacrificial layer 800 may be removed so that the seed layer pattern 420' may be exposed in the groove GR. A first stage may be performed to form the third segment 330 of the redistribution line 300 in the groove GR. The first stage may include an electroplating process in which the exposed seed layer pattern 420' is used as a seed. For example, in the electroplating process, about 10 mA / cm 2 to about 50mA / cm 2 A current density of 10 ...

[0046] refer to Figure 10, a second stage may be performed to form the first segment 310 of the redistribution line 300 in the groove GR. The second stage may include an electroplating process, in which the third segment 330 of the redistribution line 300 is used as a seed. The first segment 310 of the redistribution line 300 may be formed to have a thickness of about 6 μm to about 15 μm. The electroplating process of the first stage and the electroplating process of the second stage may be collectively referred to as a stepped electroplating process in which the first electroplating process and the second electroplating process are performed continuously. For example, the first stage and the second stage may be performed continuously in the same bath. The same electroplating solution may be used for the first stage and the second stage.

[0047] The first section 310 of the redistribution line 300 may be formed to have an average grain size larger than an average grain size of the third section 330 of the redistribution line 300. The current density applied in the first stage of the electroplating process may be greater than the current density applied in the second stage of the electroplating process. For example, in the second stage, about 50 mA / cm may be applied. 2 to about 120mA / cm 2 A current density of 1000000 is applied to the seed layer 420 or the electroplating solution. Figure 15 As shown in FIG. 1 , as the current density applied during the electroplating process increases, the grain density may decrease. This trend may indicate that the higher the current density of the electroplating process, the smaller the average grain size. When the voltage applied in the second stage is set to be higher than the voltage applied in the first stage, the first section 310 of the redistribution line 300 may be formed to have an average grain size larger than the average grain size of the third section 330 of the redistribution line 300.

[0048] In another example, the plating solution used in the second stage of the plating process may have a higher concentration than the plating solution used in the first stage of the plating process. Therefore, when the second stage is performed, the grains of the first section 310 may grow at a high rate. Consequently, the first section 310 of the redistribution line 300 may be formed to have an average grain size larger than the average grain size of the third section 330 of the redistribution line 300.

[0049] refer to Figure 11, a third stage may be performed to form the second segment 320 of the redistribution line 300 in the groove GR. The third stage may include an electroplating process in which the first segment 310 of the redistribution line 300 is used as a seed. The second segment 320 of the redistribution line 300 may be formed to have a top surface that is the same as or lower than the horizontal plane of the top surface of the first mask pattern MP1. The second segment 320 of the redistribution line 300 may be formed to have a thickness of approximately 0.1 μm to approximately 2 μm. The electroplating process of the second stage and the electroplating process of the third stage may be collectively referred to as a stepped electroplating process in which the second electroplating process and the third electroplating process are performed continuously. For example, the second stage and the third stage may be performed continuously in the same plating solution. In this case, the second stage and the third stage may use the same electroplating solution.

[0050] The second section 320 of the redistribution line 300 may be formed to have an average grain size smaller than that of the first section 310 of the redistribution line 300. The current density applied in the third stage of the electroplating process may be smaller than the current density applied in the second stage of the electroplating process. For example, in the third stage, about 10 mA / cm 2 to about 50mA / cm 2 When the voltage applied in the third stage is set to be smaller than the voltage applied in the second stage, the second section 320 of the redistribution line 300 may be formed to have an average grain size smaller than that of the first section 310 of the redistribution line 300.

[0051] In another example, the plating solution used in the third stage of the plating process may have a lower concentration than the plating solution used in the second stage of the plating process. Therefore, the grains of the second section 320 may grow at a lower rate in the third stage. As a result, the second section 320 of the redistribution line 300 may be formed to have an average grain size smaller than the average grain size of the first section 310 of the redistribution line 300.

[0052] As another example, a grain refiner may be added to the plating solution used in the third stage of the plating process. Consequently, the grains of the second segment 320 may grow at a lower rate in the third stage. Consequently, the second segment 320 of the redistribution line 300 may have an average grain size that is smaller than the average grain size of the first segment 310 of the redistribution line 300.

[0053] According to some example embodiments of the present inventive concepts, the redistribution line 300 may be formed to have a relatively smaller average grain size on a surface portion thereof (e.g., the third segment 330 corresponding to the lower portion of the redistribution line 300 and / or the second segment 320 corresponding to the upper portion of the redistribution line 300) than the first segment 310 of the redistribution line 300. To this end, a relatively high current density may be applied in the second-stage electroplating process for forming the first segment 310. Therefore, the first segment 310 may be formed at a higher rate, and the redistribution line 300 may be formed in a shortened time.

[0054] refer to Figure 12 , a portion of the barrier layer 410 may be removed to form a barrier layer pattern 410'. For example, a portion of the barrier layer 410 exposed by the redistribution line 300 or on the side surface of the redistribution line 300 may be removed. A wet etching process may be used to remove a portion of the barrier layer 410. The remaining portion of the barrier layer 410 may remain in the groove GR as the barrier layer pattern 410'. In the groove GR, the barrier layer pattern 410' may be placed between the seed layer 420 and the second surface 100b of the semiconductor substrate 100. The redistribution line 300 may be formed by the above process.

[0055] refer to Figure 13 , the first mask pattern MP1 may be removed, and then a passivation layer 500 may be formed on the second surface 100b of the semiconductor substrate 100. The passivation layer 500 may be formed to cover the redistribution line 300 and the second surface 100b of the semiconductor substrate 100. The passivation layer 500 may include an inorganic dielectric layer (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)) or an organic dielectric layer (e.g., polyimide (PI) or polybenzoxazole (PBO)). For example, the passivation layer 500 may be formed by coating polybenzoxazole (PBO) on the second surface 100b of the semiconductor substrate 100 and curing the polybenzoxazole (PBO). The passivation layer 500 may have a thickness of about 3 μm to about 5 μm.

[0056] refer to Figure 14 , the passivation layer 500 may be patterned to form an opening OP that partially exposes the redistribution line 300. For example, a second mask pattern MP2 may be formed on the passivation layer 500, and then an etching process may be performed in which the second mask pattern MP2 is used as an etching mask. The second mask pattern MP2 may include an organic material (e.g., a photoresist) or an inorganic material (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)).

[0057] Return Reference Figure 1, the second mask pattern MP2 may be removed, and then the redistribution pads 600 may be formed in the openings OP. For example, a conductive material may be coated on the passivation layer 500, and then the conductive material may be patterned to form the redistribution pads 600. The redistribution pads 600 may be formed by various techniques. External terminals 700 may be formed on the redistribution pads 600 to manufacture a semiconductor device.

[0058] In some example embodiments, after forming the redistribution pad 600, due to heat generated in subsequent processes (e.g., deposition, plating, reflow, and / or curing), an oxide layer 510 may be formed between the redistribution line 300 and the passivation layer 500. For example, during subsequent processes, heat associated with the subsequent processes may cause oxygen in the passivation layer 500 to react with the material (e.g., copper (Cu)) of the redistribution line 300. This reaction may automatically form a native metal oxide layer, or oxide layer 510.

[0059] According to some example embodiments of the present inventive concepts, a semiconductor device may include a redistribution line having increased adhesion to a passivation layer and / or a redistribution pad. Furthermore, because the top surface of the redistribution line has relatively low surface roughness and relatively high flatness, the gap between the redistribution line and the passivation layer, or between the redistribution line and the metal conductive line, may be reduced. Consequently, a semiconductor device having improved structural stability may be achieved.

[0060] In addition, the redistribution line can be formed to have a relatively small average grain size in its surface portion. The redistribution line can be formed to have a relatively large average grain size in other portions. To this end, when performing the electroplating process for forming the other portions of the redistribution line, a relatively high current density can be applied. As a result, the first section can be formed at a higher rate, and the redistribution line can be formed in a reduced time.

[0061] Although the present invention has been described in conjunction with some example embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made in the present invention without departing from the spirit and essential characteristics of the present invention. Therefore, the example embodiments disclosed above should be considered as illustrative rather than restrictive.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; forming redistribution lines on a top surface of the semiconductor substrate; as well as forming a passivation layer to cover the redistribution lines on the top surface of the semiconductor substrate, Wherein forming the redistribution line comprises: In the first stage, a first section of the redistribution line is formed on the top surface of the semiconductor substrate. In the second stage, a second section of the redistribution line is formed on the first section of the redistribution line, and a third stage of forming a third segment of the redistribution line on the top surface of the semiconductor substrate before performing the first stage, so that performing the first stage forms the first segment on the third segment; wherein an average grain size of the second section of the redistribution line is smaller than an average grain size of the first section of the redistribution line, and The average grain size of the third section of the redistribution line is smaller than the average grain size of the first section of the redistribution line.

2. The method according to claim 1, wherein The first phase and the second phase are performed continuously.

3. The method according to claim 2, wherein Each of the first stage and the second stage includes an electroplating process, and The voltage applied in the first phase is greater than the voltage applied in the second phase.

4. The method according to claim 2, wherein Each of the first stage and the second stage includes an electroplating process, and The concentration of the electroplating solution used in the first stage is greater than the concentration of the electroplating solution used in the second stage.

5. The method according to claim 2, wherein: An electroplating solution is used in the second stage and includes a grain refiner.

6. The method according to claim 2, wherein: The first stage and the second stage are performed in the same plating bath.

7. The method according to claim 1, wherein The roughness of the bottom surface of the first section is greater than the roughness of the top surface of the second section.

8. The method according to claim 1, wherein The average grain size of the second section of the redistribution line is less than 70% of the average grain size of the first section of the redistribution line.

9. The method according to claim 1, further comprising: etching the passivation layer to expose portions of the redistribution lines; and A pad is formed on the portion of the redistribution line exposed by the passivation layer.

10. The method according to claim 1, further comprising: Before forming the redistribution line, a seed layer is formed on the top surface of the semiconductor substrate.

11. A semiconductor device comprising: semiconductor substrates; a redistribution line located on a top surface of the semiconductor substrate, the redistribution line comprising a first segment on the top surface of the semiconductor substrate, a second segment on a top surface of the first segment, and a third segment located between the first segment and the semiconductor substrate, an average grain size of the second segment of the redistribution line being smaller than an average grain size of the first segment of the redistribution line, and an average grain size of the third segment being smaller than the average grain size of the second segment; a passivation layer covering the redistribution lines on the top surface of the semiconductor substrate; as well as A pad is located on the passivation layer, and the pad penetrates the passivation layer and contacts the redistribution line.

12. The semiconductor device according to claim 11, wherein The surface roughness of the first section of the redistribution line is greater than the surface roughness of the second section of the redistribution line.

13. The semiconductor device according to claim 11, wherein The average grain size of the second section of the redistribution line is less than 70% of the average grain size of the first section of the redistribution line.

14. The semiconductor device according to claim 11, wherein The second section of the redistribution line contacts the top surface of the first section and a bottom surface of the passivation layer.

15. The semiconductor device according to claim 11, wherein The first section and the second section include the same material.

16. The semiconductor device according to claim 11, further comprising: A seed layer is located between the redistribution line and the semiconductor substrate.

17. The semiconductor device according to claim 11, further comprising: The connecting terminal is located on the pad.

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