Perc cell and method of manufacturing the same

Abstract

This application provides a PERC cell and its fabrication method, belonging to the field of photovoltaic cell technology. The fabrication method includes texturing, diffusion, etching, back-side polishing, annealing, back-side coating, and front-side coating. The back-side coating step includes: introducing ozone gas into a device containing an annealed silicon wafer for oxidation treatment, forming a back-side silicon dioxide layer on the back of the silicon wafer. Then, ozone is continuously introduced into the same device as an oxygen source, and an aluminum source is added to deposit a back-side aluminum oxide layer on the back-side silicon dioxide layer. A back-side silicon nitride layer is then deposited on the back-side aluminum oxide layer. This fabrication method forms a back-side silicon oxide layer by introducing ozone, and using ozone as an oxygen source, a back-side aluminum oxide layer can be deposited in the ozone-introducing device. Both the back-side silicon dioxide layer and the back-side aluminum oxide layer can be formed in the same device, eliminating the need for additional ozone oxidation equipment, maintaining the cleanliness of the film layer contact interface, and improving the PID performance of the PERC cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell technology, and more specifically, to a PERC cell and its preparation method. Background Technology

[0002] PERC (Passivated Emitter and Rear Cell) cells have garnered widespread attention in the industry due to their high conversion efficiency. The core of this technology is to cover the back of the silicon wafer with a thin film of aluminum oxide or silicon oxide to passivate the back surface and improve long-wavelength response, thereby enhancing the cell's conversion efficiency.

[0003] A thin film of aluminum oxide is deposited on the back of the silicon wafer to passivate the silicon. However, the matching between the aluminum oxide film and the silicon is not good. Even after passivation with the aluminum oxide film, there are still significant defects on the back side, and the passivation effect is generally poor.

[0004] To enhance the chemical passivation effect on the back of the silicon wafer, CN106992229A discloses a passivation process for the back of a PERC cell. A silicon dioxide layer is formed on the back of the silicon wafer using an ozone generator, an aluminum oxide thin film is deposited on the silicon dioxide layer using an ALD device, and then a silicon nitride layer is deposited on the aluminum oxide thin film using plasma-enhanced chemical vapor deposition. Summary of the Invention

[0005] The purpose of this application is to provide a PERC battery and its preparation method, which has stronger process compatibility, reduces battery production costs, and can improve battery conversion efficiency and reliability.

[0006] This application provides a method for fabricating a PERC cell, including texturing, diffusion, etching, back-side polishing, annealing, back-side coating, and front-side coating. The back-side coating step includes: introducing ozone gas into a device containing an annealed silicon wafer to perform oxidation treatment, forming a back-side silicon dioxide layer on the back of the silicon wafer. Then, ozone is continuously introduced as an oxygen source into the same device, and an aluminum source is added to deposit a back-side aluminum oxide layer on the back-side silicon dioxide layer. Finally, a back-side silicon nitride layer is deposited on the back-side aluminum oxide layer.

[0007] The inventors discovered that the PID performance of PERC cells obtained through a back passivation process disclosed in CN106992229A was poor. Therefore, the inventors conducted careful research and found that the formation of the silicon dioxide layer was carried out in an ozone generator, while the deposition of the alumina film was carried out in an ALD (Alternating Current Deposition) device. Since the two processes need to be performed in two separate devices, the cleanliness of the film interface is affected during the transfer of the silicon wafer from the ozone generator to the ALD device. Furthermore, in existing technologies, oxygen is used as the oxygen source in the ALD device during the preparation of the back alumina layer. Therefore, CN106992229A separates the preparation of the back silicon dioxide layer and the back alumina layer into two separate devices.

[0008] The beneficial effects of the PERC battery fabrication method provided in this application include: by introducing ozone into the equipment to deposit a back silica layer, the resulting silica layer can be made more dense. Then, using ozone as an oxygen source in the same equipment, a back alumina layer can be deposited. This allows two processes to be performed in the same equipment without the need for additional ozone oxidation equipment, and it can maintain the cleanliness of the film contact interface, thereby improving the reliability and conversion efficiency of the battery. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort and also fall within the protection scope of this application.

[0010] Figure 1 This is a schematic diagram of the structure of a single-sided PERC cell provided in an embodiment of this application;

[0011] Figure 2 This is a schematic diagram of the structure of a bifacial PERC battery provided in an embodiment of this application;

[0012] Icons: 10 - P-type silicon substrate; 20 - N+ emitter junction layer; 30 - N++ silicon layer; 40 - front silicon dioxide layer; 50 - back silicon dioxide layer; 60 - back aluminum oxide layer; 70 - back silicon nitride layer; 80 - front antireflection layer; 90 - front electrode; 91 - aluminum back field; 92 - aluminum gate line. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0014] Figure 1 This is a schematic diagram of the structure of a single-sided PERC cell provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a bifacial PERC cell provided in an embodiment of this application. Please refer to [link / reference]. Figure 1 and Figure 2 In this embodiment of the application, the method for preparing a PERC battery includes the following steps:

[0015] S10, Texturing: The silicon wafer is cleaned and texturized to remove the damaged layer on the surface of the silicon wafer. Simultaneously, texturing is performed on the front side of the silicon wafer to form a pyramidal textured surface with a height of 0.5-5 μm. Optionally, the height of the textured surface is 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm. Optionally, in this embodiment, the silicon wafer provided is a monocrystalline silicon wafer, and texturing is performed using an alkaline solution (e.g., a strong alkali, NaOH, or KOH). In other embodiments, the silicon wafer is a polycrystalline silicon wafer, and texturing is performed using an acidic solution (e.g., a strong acid, nitric acid, or / and hydrofluoric acid).

[0016] S20, Diffusion: Phosphorus is doped onto the texturized silicon wafer to form a phosphorus-doped N+ emitter junction layer 20. Optionally, the silicon wafer is placed in a diffusion furnace and diffused at a diffusion temperature of 750-850℃ for 30-60 min, depositing a dopant source on the front side of the silicon wafer and performing thermal diffusion to prepare the phosphorus-doped N+ emitter junction 20, thereby forming a PN junction. The dopant source is a phosphorus oxychloride (POCl3) solution, and the diffusion temperature can be 750℃, 780℃, 800℃, 820℃, or 850℃; the diffusion time can be 30 min, 40 min, 50 min, or 60 min. The thickness of the formed phosphorus-doped N+ emitter junction layer 20 is 0.2-0.4 μm. For example, the thickness of the phosphorus-doped N+ emitter junction layer 20 can be 0.2 μm, 0.3 μm, or 0.4 μm.

[0017] S30, Heavy Doping: Localized doping diffusion is performed on the phosphorus-doped N+ emitter junction layer 20, forming a phosphorus-doped N++ silicon layer 30 between the N+ emitter junction layer 20 and the silicon wafer (i.e., the P-type silicon substrate 10). High-concentration doping (phosphorus-doped N++ silicon layer 30) is applied at and near the contact area between the metal gate and the silicon wafer, while low-concentration doping (phosphorus-doped N+ emitter junction layer 20) is applied in the area outside the front electrode 90. This reduces the contact resistance between the silicon wafer and the electrode, reduces surface recombination, and improves minority carrier lifetime. This reduces series resistance, increases the fill factor, reduces carrier recombination, improves surface passivation, enhances the short-wavelength spectral response of the battery, and increases short-circuit current and open-circuit voltage.

[0018] Optionally, a phosphorus-doped N++ silicon layer 30 (heavily doped silicon layer) is formed using laser doping. In the laser doping process, the thermal effect of the laser melts the surface of the silicon wafer, and phosphorus atoms in the phosphosilicate glass covering the top of the emitter enter the surface layer of the silicon wafer for localized doping diffusion. The diffusion coefficient of phosphorus atoms in liquid silicon is higher than that in solid silicon. After solidification, the doped phosphorus atoms replace the positions of silicon atoms to form a heavily doped silicon layer. The laser power is 20-40W. For example, the laser power can be 20W, 25W, 30W, 35W, or 40W. S40, Etching and Back Polishing: The laser-doped silicon wafer is cleaned and the back is polished. Since an N-type layer is formed on the front, back, and edges of the silicon wafer after the diffusion process, and the surface has phosphosilicate glass, the N-type layer on the edges and back of the silicon wafer is removed by wet etching, the phosphosilicate glass on the front is removed, and the back of the silicon wafer is polished. The etching solution used in the wet etching is a mixed solution of HNO3 and HF.

[0019] S50, Annealing: The silicon wafer is placed in an annealing furnace, and a certain amount of oxygen is introduced during annealing to grow a front-side silicon dioxide layer 40 (SiO2) on the phosphorus-doped N+ emitter junction layer. The annealing temperature is 750-850℃. For example, annealing temperatures of 750℃, 770℃, 790℃, 810℃, 830℃, or 850℃. The thickness of the formed front-side silicon dioxide layer 40 is 2-5nm. For example, the thickness of the front-side silicon dioxide layer 40 is 2nm, 3nm, 4nm, or 5nm.

[0020] S60, Backside Coating: A backside silicon dioxide layer 50 (SiO2), a backside aluminum oxide layer 60 (AlOx), and a backside silicon nitride layer 70 (SiNx) are sequentially deposited on the backside of a silicon wafer. Optionally, the backside silicon dioxide layer 50 and the backside aluminum oxide layer 60 are deposited in the same chamber of the same equipment, for example, both in the chamber of an ALD equipment. The annealed silicon wafer is placed in the chamber of the ALD equipment, and ozone gas is introduced into the chamber of the ALD equipment for oxidation treatment, forming the backside silicon dioxide layer 50 on the backside of the polished silicon wafer. Then, a passivation process is continued in the ALD equipment, with ozone being introduced into the ALD equipment as an oxygen source and an aluminum source added, to deposit the backside aluminum oxide layer 60 on the surface of the backside silicon dioxide layer 50 away from the silicon wafer. Depositing the backside silicon dioxide layer 50 between the backside aluminum oxide layer 60 and the silicon wafer can effectively enhance passivation and incident light utilization, and reduce the loss of non-equilibrium carriers caused by surface defects. This improves the battery's short-circuit current and open-circuit voltage, while also enhancing the battery's resistance to light decay, PID control, and reliability.

[0021] The deposition of the back silica layer 50 and the deposition of the back alumina layer 60 are performed in the same equipment, which improves process compatibility and eliminates the need for additional ozone oxidation equipment for the formation of the back silica layer 50. This maintains the cleanliness of the contact interface between the back silica layer 50 and the back alumina layer 60, thereby improving the battery's conversion efficiency. By introducing ozone gas into the chamber of the ALD equipment, the ozone gas reacts with silicon to produce a more compact back silica layer 50, further improving the back defects of the battery and enhancing its anti-PID performance.

[0022] The back silicon dioxide layer 50 has a thickness of 2-5 nm. The back aluminum oxide layer 60 has a thickness of 2-6 nm. Optionally, the thickness of the back silicon dioxide layer 50 can be 2 nm, 3 nm, 4 nm or 5 nm; the thickness of the back aluminum oxide layer 60 can be 2 nm, 3 nm, 4 nm, 5 nm or 6 nm.

[0023] To deposit a back silicon dioxide layer 50 on the back side of a silicon wafer, the conditions for oxidation treatment by introducing ozone gas into the chamber of the ALD device include: an ozone flow rate of 5-150 sccm, an oxidation time of 1-10 min, and an oxidation temperature of 150-300℃. For example, the ozone gas flow rate can be 5 sccm, 10 sccm, 20 sccm, 40 sccm, 80 sccm, 120 sccm, or 150 sccm; the oxidation time can be 1 min, 3 min, 5 min, 7 min, 9 min, or 10 min; and the oxidation temperature can be 150℃, 200℃, 250℃, or 300℃.

[0024] Furthermore, the deposition of the back alumina layer 60 can continue within the chamber of the ALD device. During the deposition of the back alumina layer 60, ozone gas is directly used as the oxygen source, and deposition is carried out at a temperature of 150-300°C.

[0025] The aluminum source for depositing the back-side alumina layer 60 is an aluminum-containing precursor, which can be one or more of aluminum trichloride, trimethylaluminum, triethylaluminum, dimethylaluminum chloride, aluminum ethoxide, and aluminum isopropoxide, and is formed using atomic layer deposition (ALD). ALD is performed within the chamber of an ALD equipment, and ozone gas is also introduced into the chamber of the ALD equipment, allowing for compatibility of two processes within the same equipment and reducing production costs.

[0026] Further, a back silicon nitride layer 70 is deposited on the back alumina layer 60. Optionally, the back silicon nitride layer 70 can be deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition (PECVD).

[0027] Please continue reading. Figure 1 and Figure 2 If the fabricated PERC cell is a single-sided cell, the thickness of the back silicon nitride layer 70 is 110-180 nm. For example, the thickness of the back silicon nitride layer 70 can be 110 nm, 130 nm, 150 nm, 170 nm, or 180 nm. If the fabricated PERC cell is a bifacial cell, the thickness of the back silicon nitride layer 70 is 85-105 nm. For example, the thickness of the back silicon nitride layer 70 can be 85 nm, 90 nm, 95 nm, 100 nm, or 105 nm.

[0028] S70, Front-side coating: A front-side silicon nitride layer is formed on the front side of the silicon wafer. Using plasma-enhanced chemical vapor deposition (PECVD), a front-side silicon nitride (SiNx) layer (front-side antireflection layer 80) is formed on the front-side silicon dioxide layer of the silicon wafer, which reduces light reflectivity and also provides a certain passivation effect. Optionally, the thickness of the front-side silicon nitride layer is 73-83 nm. For example, the thickness of the front-side silicon nitride layer can be 73 nm, 75 nm, 77 nm, 79 nm, 81 nm, or 83 nm.

[0029] S80, laser grooving: Laser etching is used to selectively etch away part of the passivation layer (back silicon dioxide layer + back aluminum oxide layer + back silicon nitride layer) on the back of the silicon wafer, thereby creating a groove or opening on the back of the silicon wafer to expose the P-type silicon substrate layer structure.

[0030] S90, screen printing and sintering: Using screen printing, silver paste is printed on the front side of the silicon wafer and aluminum paste is printed on the back side according to the screen design. After high-temperature sintering, ohmic contacts are formed to produce PERC cells.

[0031] Optionally, the silver paste printed on the front side is sintered to form a front electrode 90, which makes a 30-ohm contact with the phosphorus-doped N++ silicon layer. The front electrode 90 is a front gate line with a height of 18-25 μm and a width of 35-45 μm. For example, the height of the front gate line can be 18 μm, 20 μm, 22 μm, 24 μm, or 25 μm, and the width can be 35 μm, 37 μm, 39 μm, 41 μm, 43 μm, or 45 μm.

[0032] Please continue reading. Figure 1 If the fabricated PERC cell is a single-sided cell, the back side of the cell is an aluminum back field 91, which makes ohmic contact with the P-type silicon substrate. Optionally, the amount of aluminum paste consumed when forming the aluminum back field 91 in a single-sided cell is between 0.8 and 0.9 g. For example, the amount of aluminum paste consumed can be 0.8 g, 0.82 g, 0.84 g, 0.86 g, 0.88 g, or 0.9 g. During the printing of the aluminum paste, the aluminum paste enters the groove structure in S80, so that the sintered aluminum back field 91 makes 10-ohmic contact with the P-type silicon substrate.

[0033] Please continue reading. Figure 2 If the prepared PERC cell is a bifacial cell, the back side of the cell has aluminum grid lines 92, which make ohmic contact with the P-type silicon substrate. Optionally, the amount of aluminum paste consumed when forming the aluminum grid lines 92 in the bifacial cell is between 0.2 and 0.4 g. For example, the amount of aluminum paste consumed can be 0.2 g, 0.25 g, 0.3 g, 0.35 g, or 0.4 g. During the printing of the aluminum paste, the aluminum paste enters the groove structure in S80, so that the sintered aluminum grid lines 92 make 10-ohmic contact with the P-type silicon substrate.

[0034] The single-sided PERC cell prepared by the above method (e.g.) Figure 1 (as shown) or bifacial PERC cells (such as...) Figure 2 The beneficial effects (as shown) include:

[0035] (1) The two processes of depositing the back silica layer 50 and depositing the back alumina layer 60 are carried out in the same chamber of the ALD equipment, which can make the process more compatible and does not require the addition of an ozone oxidation equipment for the formation of back silica. It can maintain the cleanliness of the contact interface between the back silica layer 50 and the back alumina layer 60, improve the anti-PID performance and conversion efficiency of the battery, and enhance the reliability of the battery.

[0036] (2) A phosphorus-doped N++ silicon layer 30 is formed between the N+ emitter junction layer 20 and the P-type silicon substrate 10, which reduces the contact resistance between the silicon wafer and the electrode, reduces surface recombination, and improves minority carrier lifetime.

[0037] (3) The process is highly compatible, and can meet the requirements for the preparation of both single-sided and double-sided PERC cells.

[0038] Example 1

[0039] The fabrication method of a single-sided PERC cell includes the following steps:

[0040] (1) Texturing: The silicon wafer is cleaned and texturized to remove the damaged layer on the surface of the silicon wafer. At the same time, texturing is performed on the front side of the silicon wafer to form a pyramid textured surface with a height of 3μm.

[0041] (2) Diffusion: The silicon wafer is placed in a diffusion furnace and diffused at a diffusion temperature of 800℃ for 40 minutes to deposit phosphorus oxychloride on the front side of the silicon wafer and perform thermal diffusion to prepare a phosphorus-doped N+ emitter junction with a thickness of 0.3μm.

[0042] (3) Heavy doping: Laser doping is used to perform localized doping diffusion on the phosphorus-doped N+ emitter junction layer, so that a phosphorus-doped N++ silicon layer is formed between the N+ emitter junction layer and the P-type silicon substrate.

[0043] (4) Etching and back polishing: The N-type layer on the edge and back of the silicon wafer is removed by wet etching, the phosphorus glass on the front is removed, and the back of the silicon wafer is polished.

[0044] (5) Annealing: The silicon wafer is placed in an annealing furnace and a certain amount of oxygen is introduced to grow a front silicon dioxide layer with a thickness of 4nm at a temperature of 800℃.

[0045] (6) Backside Deposition: The annealed silicon wafer is placed in the chamber of the ALD equipment. Ozone gas with a flow rate of 40 sccm is introduced into the chamber of the ALD equipment, and oxidation is carried out at a temperature of 200℃ for 5 min to form a backside silicon dioxide layer with a thickness of 3 nm. Then, at a temperature of 250℃, using ozone gas as an oxygen source, a backside aluminum oxide layer with a thickness of 4 nm is deposited. Finally, a backside silicon nitride layer with a thickness of 150 nm is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0046] (7) Front coating: A silicon nitride layer with a thickness of 80 nm is formed on the front side of the silicon wafer using plasma enhanced chemical vapor deposition (PECVD).

[0047] (8) Laser grooving: Laser etching is used to selectively etch away part of the passivation layer (back silicon dioxide layer + back aluminum oxide layer + back silicon nitride layer) on the back of the silicon wafer, thereby creating a groove or opening on the back of the silicon wafer to expose the P-type silicon substrate layer structure.

[0048] (9) Screen printing and sintering: Using screen printing, silver paste is printed on the front side of the silicon wafer and 0.85g of aluminum paste is printed on the back side according to the screen pattern design. After high-temperature sintering, a front electrode and an aluminum back field are formed. The front electrode is in ohmic contact with the phosphorus-doped N++ silicon layer, and the aluminum back field is in ohmic contact with the P-type silicon substrate.

[0049] Example 2

[0050] The difference between Example 2 and Example 1 is that Example 2 does not perform the heavy doping step (3) in Example 1. The other steps and methods are the same as those in the examples.

[0051] Example 3

[0052] The difference between Example 3 and Example 1 is that Example 3 involves the fabrication of a bifacial PERC cell. The difference lies in:

[0053] (6) Backside Deposition: The annealed silicon wafer is placed in the chamber of the ALD equipment. Ozone gas with a flow rate of 40 sccm is introduced into the chamber of the ALD equipment, and oxidation is carried out at a temperature of 200℃ for 5 min to form a backside silicon dioxide layer with a thickness of 3 nm. Then, at a temperature of 250℃, using ozone gas as an oxygen source, a backside aluminum oxide layer with a thickness of 4 nm is deposited. Finally, a backside silicon nitride layer with a thickness of 95 nm is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0054] (9) Screen printing and sintering: Using screen printing, silver paste is printed on the front side of the silicon wafer and 0.32g of aluminum paste is printed on the back side according to the screen pattern design. After high-temperature sintering, the front electrode and aluminum grid lines are formed. The front electrode is in ohmic contact with the phosphorus-doped N++ silicon layer, and the aluminum grid lines are in ohmic contact with the P-type silicon substrate.

[0055] The other steps and methods are consistent with those in the embodiments.

[0056] Comparative Example 1

[0057] Comparative Example 1 prepared a single-sided PERC cell. The difference between Comparative Example 1 and Example 1 is:

[0058] (6) Backside Coating: The annealed silicon wafer is placed in an ozone generator for oxidation treatment to form a 3nm thick backside silicon dioxide layer. The silicon wafer is then transferred to the chamber of the ALD equipment, where a 4nm thick backside aluminum oxide layer is deposited at 400°C. A 150nm thick backside silicon nitride layer is then deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0059] The other steps and methods are consistent with those in the embodiments.

[0060] Experimental Example

[0061] The performance of the PERC cells obtained in Examples 1-4 and the PERC cells provided in Comparative Examples 1-4 is shown in Table 1. The testing method was to use the BERGER online IV test system to test the open-circuit voltage, short-circuit current, fill factor, conversion efficiency and other electrical performance parameters of the solar cells under the conditions of 25°C, AM 1.5 and 1 standard sun.

[0062] Table 1 Performance of PERC Batteries

[0063] project count Eta(%) Uoc(V) Isc(A) Rs Example 1 800 22.493 0.6774 10.382 0.0020 Example 2 400 22.496 0.6778 10.378 0.0020 Example 3 800 22.464 0.6767 10.375 0.0019 Comparative Example 1 1200 22.396 0.6757 10.360 0.0019

[0064] As can be seen from Table 1, when ozone gas is introduced into the chamber of the ALD device to obtain a back silicon dioxide layer, and ozone is continued to be introduced into the same device to form a back aluminum oxide layer, the conversion efficiency, open-circuit voltage and short-circuit current of the resulting single-sided PERC cells and double-sided PERC cells all increase to varying degrees, indicating that the PERC cells have better performance.

[0065] The embodiments described above are some, but not all, of the embodiments of this application. The detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

Claims

1. A preparation method of a PERC cell, comprising texturing, diffusion, etching, backside polishing, annealing, backside film plating and front side film plating, characterized in that, the backside film plating step comprises: ozone gas is introduced into a device containing the annealed silicon wafer to perform oxidation treatment, so that a backside silicon dioxide layer is formed on the backside of the silicon wafer; the conditions of introducing ozone gas into the device containing the annealed silicon wafer to perform oxidation treatment comprise: ozone flow rate is 5-150 sccm, oxidation time is 1-10 min, and oxidation temperature is 150-300 ℃; then ozone is continuously introduced into the device as an oxygen source, and an aluminum source is added to deposit a backside aluminum oxide layer on the backside silicon dioxide layer; a backside silicon nitride layer is deposited on the backside aluminum oxide layer.

2. The production method according to claim 1, characterized by, In the step of depositing a backside aluminum oxide layer on the backside silicon dioxide layer, the deposition temperature is 150-300 ℃.

3. The production method according to any one of claims 1 or 2, characterized in that, The device is an ALD device.

4. The production method according to claim 3, characterized by, The diffusion comprises: doping phosphorus on the textured silicon wafer to form a phosphorus-doped N+emitter junction layer; The preparation method further comprises: performing local area doping diffusion on the phosphorus-doped N+emitter junction layer to form a phosphorus-doped N++silicon layer between the N+emitter junction layer and the silicon wafer.

5. The production method according to claim 4, characterized by, The method of forming the phosphorus-doped N++silicon layer is laser doping.

6. A mono-faced PERC cell prepared according to the preparation method of any one of claims 1-5. Comprise: a P-type silicon substrate; the front side of the P-type silicon substrate is sequentially provided with a phosphorus-doped N+emitter junction layer, a front side silicon dioxide layer, a front side anti-reflection layer and a front side electrode, a phosphorus-doped N++silicon layer is provided between the phosphorus-doped N+emitter junction layer and the P-type silicon substrate, and the front side electrode is in ohmic contact with the phosphorus-doped N++silicon layer; the backside of the silicon substrate is sequentially provided with a backside silicon dioxide layer, a backside aluminum oxide layer, a backside silicon nitride layer and an aluminum back field, and the aluminum back field is in ohmic contact with the P-type silicon substrate.

7. The single-side PERC cell according to claim 6, characterized in that, The thickness of the phosphorus-doped N+emitter junction layer is 0.2-0.4 μm, and the thickness of the backside silicon dioxide layer and the thickness of the front side silicon dioxide layer are both 2-5 nm.

8. A bifacial PERC cell prepared according to the method of any one of claims 1-5, characterized in that, Comprise: a P-type silicon substrate; the front side of the P-type silicon substrate is sequentially provided with a phosphorus-doped N+emitter junction layer, a front side silicon dioxide layer, a front side anti-reflection layer and a front side electrode, a phosphorus-doped N++silicon layer is provided between the phosphorus-doped N+emitter junction layer and the P-type silicon substrate, and the front side electrode is in ohmic contact with the phosphorus-doped N++silicon layer; the backside of the silicon substrate is sequentially provided with a backside silicon dioxide layer, a backside aluminum oxide layer, a backside silicon nitride layer and an aluminum gate line, and the aluminum gate line is in ohmic contact with the P-type silicon substrate.

9. The dual-side PERC cell according to claim 8, characterized in that, The thickness of the phosphorus-doped N+emitter junction layer is 0.2-0.4 μm, and the thickness of the backside silicon dioxide layer and the thickness of the front side silicon dioxide layer are both 2-5 nm.

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