A device for controlling wireless charging output power based on PWM integration circuit

Abstract

The present invention provides a device for controlling the output power of wireless charging based on a PWM integration circuit, including a magnetic resonance transmitting module and a magnetic resonance receiving module connected to the magnetic resonance transmitting module. In the present invention, the transmitting and receiving ends of wireless charging use Bluetooth communication. The receiving end collects the voltage and current of the charging circuit via Bluetooth, and feeds back the voltage and current information to the transmitting end via Bluetooth. The transmitting end dynamically adjusts the output power of the transmitting end according to the information fed back by the receiving end via Bluetooth to maintain the efficiency of wireless charging transmission. Through the above design, the present invention provides a stable and efficient magnetic resonance wireless power supply solution to solve the shortcomings of the current magnetic induction technology in transmission efficiency and make up for the function of dynamic power adjustment realized by magnetic resonance technology in wireless charging.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless power transmission, and in particular relates to a device for controlling wireless charging output power based on a PWM integration circuit. Background Art

[0002] With the continuous development of electronic information technology and automation control technology, various household appliances, consumer electronic products, mobile communication devices, etc. have been widely popularized. However, traditional household appliances rely on wired connections between power cords and power sockets to achieve power supply. Electronic devices with built-in batteries also require wired connections between charging cables and power sockets for charging. Therefore, we can see wires everywhere that provide power supply for these electronic devices. These wires not only occupy our activity space and limit the convenience of using the equipment, but also create hidden dangers for safe use of electricity. Therefore, with the growing demand for portable devices and green energy systems that can be used completely wirelessly, the research and application of wireless energy transmission technology has quickly become the focus of domestic and foreign academic and industrial circles.

[0003] At present, this technology has been gradually applied to low-power electronic products in people's daily life, replacing the original power cord to achieve wireless charging of devices, bringing extra convenience to people's lives, such as wireless charging toothbrushes and wireless charging blankets based on magnetic induction coupling technology. However, the application value and market potential of wireless energy transmission technology are far more than this. For example, the application of wireless energy transmission technology in the field of smart home will subvert the use mode of traditional home appliances, mobile communication equipment, and electronic consumer products. With the residence as the platform, all power cords in the home living area are completely removed by using medium-distance wireless energy transmission technology, hidden wiring technology, and automatic control technology. Wireless charging or continuous power supply for devices can be performed to improve home safety, convenience, comfort and artistry, and build an efficient, environmentally friendly, and energy-saving living environment. In addition, for implantable medical devices that can be used for diagnosis and treatment in the biomedical field, considering the inconvenience, impracticability, and even high risk of continuous wired power supply or charging, the application of wireless energy transmission technology is also extremely important and critical. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a device for controlling the wireless charging output power based on a PWM integration circuit, which solves the problem of insufficient transmission efficiency of the current magnetic induction technology and makes up for the function of dynamic power adjustment achieved by magnetic resonance technology in wireless charging.

[0005] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0006] This solution provides a device for controlling wireless charging output power based on a PWM integration circuit, comprising a magnetic resonance transmitting module and a magnetic resonance receiving module connected to the magnetic resonance transmitting module;

[0007] The magnetic resonance transmitting module includes a wireless charging base, a Bluetooth host circuit, and a DC / DC voltage stabilizing circuit, a PWM integrating circuit, a radio frequency power amplifier source, a radio frequency current sampling circuit, and a magnetic resonance transmitting antenna respectively connected to the Bluetooth host circuit. The radio frequency power amplifier source and the magnetic resonance transmitting antenna are both installed on the wireless charging base, and the magnetic resonance transmitting antenna is connected to the magnetic resonance receiving module;

[0008] The magnetic resonance receiving module includes a heat sink, a magnetic resonance receiving antenna, a Bluetooth slave circuit, and a receiving rectification and voltage stabilizing circuit and a charging control circuit respectively connected to the Bluetooth slave circuit. The magnetic resonance receiving antenna, the receiving rectification and voltage stabilizing circuit and the charging control circuit are connected in sequence. The receiving rectification and voltage stabilizing circuit and the Bluetooth slave circuit are both fixed on the upper surface of the heat sink. The magnetic resonance receiving antenna is arranged directly above the magnetic resonance transmitting antenna.

[0009] The beneficial effects of the present invention are as follows: the present invention adopts magnetic resonance wireless charging technology to directly charge the lithium battery. The device transmits electromagnetic energy through the magnetic resonance transmitting antenna, and transfers energy to the receiving rectifier voltage stabilizing circuit through the magnetic resonance receiving antenna, and then powers the charging control circuit. The charging control circuit powers the lithium battery. In this process, the Bluetooth slave circuit monitors the voltage and current consumed by the charging control circuit, and transmits this information to the magnetic resonance transmitting module through Bluetooth. After receiving the voltage and current required for charging, the Bluetooth host circuit of the magnetic resonance transmitting module adjusts the PWM input duty cycle of the PWM integration circuit, and then adjusts the output voltage of the DC / DC voltage stabilizing circuit, thereby adjusting the transmission power of the output end. The present invention solves the problem that the wireless charging transmitting end cannot dynamically adjust the output power when the load power of the receiving end changes, so that the efficiency of the wireless transmitting end cannot be effectively utilized. The power of the wireless charging transmitting end is adjusted according to the real-time power required by the wireless charging receiving end, thereby ensuring the efficient operation of the wireless charging system.

[0010] Furthermore, the Bluetooth host circuit and the Bluetooth slave circuit have the same structure, both including a Bluetooth chip U6; the Bluetooth host circuit also includes a first LDO sub-circuit, the first LDO sub-circuit includes a voltage regulator chip U8; the Bluetooth slave circuit also includes a second LDO sub-circuit, the second LDO sub-circuit includes a voltage regulator chip U11, wherein:

[0011] The AVDD1 pin of the chip U6 is respectively connected to the AVDD2 pin of the chip U6, the AVDD3 pin of the chip U6, the AVDD4 pin of the chip U6, the AVDD5 pin of the chip U6, the AVDD6 pin of the chip U6, the grounding capacitor C95, the grounding capacitor C94, the grounding capacitor C93, the grounding capacitor C92, the grounding capacitor C91, the grounding capacitor C90, the DVDD1 pin of the chip U6, one end of the resistor R71, the NC pin of the chip U6, the chip U11 and the chip U8. The DVDD1 pin of the chip U6 is also respectively connected to the DVDD2 pin of the chip U6, one end of the capacitor C101 and the capacitor C100 is connected, the other end of capacitor C101 is connected to the other end of capacitor C100 and is grounded, the DCOUPL pin of the chip U6 is connected to one end of capacitor C104, the other end of capacitor C104 is respectively connected to one end of capacitor C107, the GND pin of the chip U6 and the ePAD pin of the chip U6 and is grounded, the other end of capacitor C107 is connected to the NC pin of the chip U6, the REST pin of the chip U6 is respectively connected to the grounded capacitor C110 and the other end of resistor R71, the R_BIAS pin of the chip U6 is connected to one end of resistor R75, the other end of resistor R75 is connected to the 4th pin of the crystal oscillator Y3 and is grounded, The XSOC_Q1 pin of the chip U6 is respectively connected to the first pin of the crystal oscillator Y3 and one end of the capacitor C114, the XSOC_Q2 pin of the chip U6 is respectively connected to one end of the capacitor C115 and the third pin of the crystal oscillator Y3, the other end of the capacitor C115 is respectively connected to the second pin of the crystal oscillator Y3 and the other end of the capacitor C114, and is grounded, the RF_P pin of the chip U6 is connected to one end of the capacitor C88, the other end of the capacitor C88 is respectively connected to one end of the capacitor C89 and one end of the inductor L14, the other end of the inductor L14 is grounded, the other end of the capacitor C89 is respectively connected to one end of the inductor L17 and one end of the inductor L15, and the inductor L17 is grounded. The other end of 7 is respectively connected to one end of capacitor C96 and grounded capacitor C98, the other end of capacitor C96 is connected to the RF_N pin of the chip U6, the other end of inductor L15 is respectively connected to grounded capacitor C97 and one end of inductor L16, the other end of inductor L16 is connected to one end of the magnetic resonance transmitting antenna, the other end of the magnetic resonance transmitting antenna is grounded, the P11 pin of the chip U6 is connected to the PWM integration circuit, the 2nd pin of the chip U6 is connected to the DC / DC voltage stabilizing circuit, the P06 pin of the chip U6 is respectively connected to the charging control circuit and the RF current sampling circuit, the P07 pin of the chip U6 is connected to the DC / DC voltage stabilizing circuit,The P13 pin, the P04 pin and the P05 pin of the chip U6 are respectively connected to the charging control circuit;

[0012] The Vin terminal of the chip U8 is respectively connected to one end of the capacitor CC1, the RF power amplifier source and the DC / DC voltage stabilizing circuit, the Vout terminal of the chip U8 is connected to one end of the inductor L18, the other end of the inductor L18 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC2, the GND grounding terminal of the chip U8 is respectively connected to the other end of the capacitor CC1 and the other end of the capacitor CC2, and is grounded;

[0013] The Vin pin of the chip U11 is respectively connected to one end of the capacitor CC31, the grounding capacitor C133 and one end of the inductor L21, the other end of the inductor L21 is respectively connected to the cathode of the diode D10 and the cathode of the diode D12, the anode of the diode D10 is respectively connected to the receiving rectifier voltage stabilizing circuit and the charging control circuit, the anode of the diode D12 is connected to the anode of the lithium battery, the Vout pin of the chip U11 is connected to one end of the inductor L22, the other end of the inductor L22 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC4, the other end of the capacitor CC4 is respectively connected to the GND pin of the chip U11 and the other end of the capacitor CC31, and grounded.

[0014] The beneficial effect of the above further scheme is: the Bluetooth host circuit and the Bluetooth slave circuit in the present invention control the charging process of the magnetic resonance receiving module when using the magnetic resonance wireless charging technology to directly power the magnetic resonance receiving module to charge the device; the Bluetooth host dynamically adjusts the input duty cycle of the PWM circuit and thus adjusts the output voltage of the magnetic resonance transmitting module through real-time monitoring of the charging current and voltage of the magnetic resonance receiving module, thereby achieving dynamic matching of the output power and the receiving power.

[0015] Furthermore, the DC / DC voltage stabilizing circuit includes a DC / DC rectifier subcircuit, a current and voltage detection subcircuit, and a voltage output control subcircuit, wherein:

[0016] The DC / DC rectifier circuit includes a rectifier chip U1, the IN pin of the chip U1 is respectively connected to the grounded capacitor C62, one end of the resistor R44, the positive electrode of the polarity capacitor C61, the grounded capacitor C60 and one end of the inductor L8, the other end of the inductor L8 is respectively connected to the Vin end of the chip U8 and the grounded capacitor C57, the negative electrode of the polarity capacitor C61 is grounded, the EN pin of the chip U1 is respectively connected to the other end of the resistor R44 and the grounded resistor R45, the VCC pin of the chip U1 is connected to the grounded capacitor C82, the GND pin of the chip U1 is grounded, and the FB pin of the chip U1 is respectively connected to one end of the capacitor C79, one end of the resistor R54, the negative electrode of the diode D4 and the negative electrode of the diode D5. The anode of the diode D5 is connected to the PWM integration circuit, the anode of the diode D4 is connected to the voltage output control subcircuit, the other end of the capacitor C79 is connected to one end of the resistor R47, the other end of the resistor R47 is respectively connected to one end of the resistor R50, the voltage output control subcircuit, the grounding capacitor C77, the grounding capacitor C76, the grounding capacitor C75 and one end of the inductor L11, the other end of the resistor R50 is respectively connected to the other end of the resistor R54 and the grounding resistor R55, the SW pin of the chip U1 is respectively connected to one end of the capacitor C58 and the other end of the inductor L11, the other end of the capacitor C58 is connected to one end of the resistor R43, and the other end of the resistor R43 is connected to the RST pin of the chip U1;

[0017] The current and voltage detection subcircuit includes a detection chip U5, the IN+ pin of the chip U5 is respectively connected to the V+ pin of the chip U5, the other end of the resistor R47, one end of the capacitor C81 and one end of the sampling resistor RSA1, the REF pin of the chip U5 is respectively connected to the other end of the capacitor C81 and the GND pin of the chip U5, and is grounded, the OUT pin of the chip U5 is connected to the positive electrode of the diode D4, the IN- pin of the chip U5 is respectively connected to the other end of the sampling resistor RSA1, one end of the resistor R51 and the voltage output control subcircuit, the other end of the resistor R51 is respectively connected to one end of the resistor R53 and one end of the resistor R60, the other end of the resistor R53 is respectively connected to the P07 pin of the chip U6 and one end of the capacitor C86, the other end of the resistor R60 is connected to the other end of the capacitor C86 and is grounded;

[0018] The voltage output control subcircuit includes a PMOS tube U2, the source of which is respectively connected to the IN-pin of the chip U5 and one end of the resistor R48, the gate of which is respectively connected to the other end of the resistor R48 and one end of the resistor R49, the other end of the resistor R49 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R56 and grounded, the base of the transistor Q3 is respectively connected to one end of the resistor R52 and the other end of the resistor R56, the other end of the resistor R52 is connected to the P12 pin of the chip U6, the drain of the PMOS tube U2 is respectively connected to the grounding capacitor C69 and one end of the inductor L12, and the other end of the inductor L12 is connected to the RF power amplifier source.

[0019] The beneficial effect of the above further scheme is: the voltage divider circuit composed of R51 and R60 in the present invention divides the output voltage and sends it to the AD sampling port of the Bluetooth chip, and the Bluetooth chip can monitor the output voltage of the voltage stabilizing circuit in real time. By monitoring the output voltage of the voltage stabilizing circuit, the power supply of the RF power amplifier source can be effectively guaranteed, and the safe operation of the system can be guaranteed.

[0020] Furthermore, the PWM integration circuit includes an operational amplifier chip U7A, an operational amplifier chip U7B, an operational amplifier chip N1A, an operational amplifier chip N1B and an NMOS tube Q4, wherein:

[0021] The gate of the NMOS tube Q4 is connected to one end of the resistor R70, the other end of the resistor R70 is connected to the P11 pin of the chip U6, the source of the NMOS tube Q4 is grounded, the drain of the NMOS tube Q4 is respectively connected to one end of the resistor R65, the grounding resistor R74 and one end of the resistor R66, the other end of the resistor R65 is connected to the AVDD1 pin of the chip U6, the other end of the resistor R66 is respectively connected to one end of the resistor R67 and one end of the capacitor C103, the other end of the resistor R67 is respectively connected to the grounding capacitor C109 and the The positive phase input terminal of the chip U7B is connected, the other end of the capacitor C103 is respectively connected to one end of the resistor R63 and the inverting input terminal of the chip U7B, the other end of the resistor R63 is respectively connected to one end of the resistor R69 and the output terminal OB of the chip U7B, the other end of the resistor R69 is respectively connected to the positive phase input terminal of the chip U7A, the inverting input terminal of the chip U7A is connected to one end of the resistor R64, the output terminal of the chip U7A is respectively connected to the other end of the resistor R64, the grounding capacitor C108 and one end of the resistor R2, the The V- pin is connected to one end of the capacitor C105 and grounded, the V+ pin of the chip U7A is respectively connected to the AVDD1 pin of the chip U6 and the other end of the capacitor C105, the other end of the resistor R2 is respectively connected to the grounded capacitor C3, the grounded capacitor C4 and one end of the resistor R3, the other end of the resistor R3 is respectively connected to one end of the capacitor C5 and one end of the resistor R4, the other end of the resistor R4 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the inverting input end of the chip N1B is respectively connected to the other end of the capacitor C5 ... the grounded capacitor C5 and the positive phase input end of the chip N1B, the other end of the resistor R3 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the other end of the resistor R3 is respectively connected to the grounded capacitor C5, the grounded capacitor C4 and one end of the resistor R4, the other end of the resistor R4 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the other end of the capacitor C5, the grounded capacitor C4 and the grounded capacitor C4 The output terminal OB of the chip U6 is connected to the positive input terminal of the chip N1A, the inverting input terminal of the chip N1A is respectively connected to the output terminal of the chip N1A and the positive electrode of the diode D5, the V- pin of the chip N1A is respectively connected to one end of the capacitor C1 and one end of the capacitor C2, and is grounded, the V+ pin of the chip N1A is respectively connected to one end of the resistor R1, the other end of the capacitor C2 and the other end of the capacitor C1, the other end of the resistor R1 is connected to one end of the inductor FB1, and the other end of the inductor FB1 is connected to the AVDD1 pin of the chip U6.

[0022] The beneficial effect of the above further scheme is: the Bluetooth host circuit in the present invention analyzes the charging current and voltage fed back by the Bluetooth slave circuit, and then adjusts the PWM input duty cycle of the PWM integration circuit according to demand, changes the voltage output by the integration circuit, and correspondingly adjusts the voltage of the FB pin of the DC / DC voltage regulator circuit, thereby changing the output voltage of the DC / DC voltage regulator circuit, and realizing dynamic adjustment of the wireless charging output power, thereby ensuring that the efficiency of unlimited charging is always maintained at a high level; the PWM signal with an adjustable duty cycle output by the Bluetooth circuit enters the follower circuit after passing through the integration circuit, and then the ripple signal generated by the integration circuit is filtered out by the third-order low-pass filter circuit composed of N1A and N1B, and finally connected to the FB input network of the DC / DC circuit through the follower circuit. The third-order low-pass filter circuit ensures the stability of the DC voltage signal output by the PWM integration circuit, reduces the influence of the DC level output by the PWM integration circuit on the ripple of the DC / DC feedback circuit, and ensures the stability of the DC / DC adjustable output voltage.

[0023] Furthermore, the RF power amplifier source includes a voltage stabilizing chip U3, a power amplifier tube U4, a gate bias subcircuit, an input matching subcircuit, a drain bias subcircuit and an output matching subcircuit, wherein:

[0024] The Vin end of the chip U3 is respectively connected to one end of the capacitor C72, the other end of the inductor L8 and the Vin end of the chip U8, the Vout end of the chip U3 is respectively connected to the capacitor C73, the capacitor C74, the 5V-RF power supply, one end of the inductor L9 and the gate bias sub-circuit, the GND end of the chip U3 is respectively connected to the other end of the capacitor C74, the other end of the capacitor C73 and the other end of the capacitor C72, and is grounded, the other end of the inductor L9 is respectively connected to the grounded capacitor C70, the grounded capacitor C71 and the 4th pin of the connector Y2, the 2nd pin of the connector Y2 is grounded, and the 3rd pin of the connector Y2 is connected to the input matching sub-circuit;

[0025] The gate bias subcircuit includes a capacitor C84, a resistor R57, a resistor R58, a capacitor C85, a resistor R59 and a resistor R46. One end of the capacitor C84 is connected to the Vout end of the chip U3 and one end of the resistor R57, respectively. The other end of the capacitor C84 is grounded. The other end of the resistor R57 is connected to one end of the resistor R58. The other end of the resistor R58 is connected to one end of the capacitor C85, one end of the resistor R59 and one end of the resistor R46, respectively. The other end of the resistor R59 is connected to the capacitor C85. The other end of the resistor R46 is connected to the input matching sub-circuit and the gate of the power amplifier tube U4, the source of the power amplifier tube U4 is grounded, the drain of the power amplifier tube U4 is connected to one end of the capacitor C64, one end of the capacitor C59, the drain bias sub-circuit, one end of the capacitor C55 and one end of the capacitor C66, the other end of the capacitor C64 is connected to the other end of the capacitor C59 and grounded, the other end of the capacitor C55 is connected to the other end of the capacitor C66 and the output matching sub-circuit;

[0026] The input matching subcircuit includes a capacitor C65 and a capacitor C78, ​​one end of the capacitor C65 is respectively connected to the third pin of the connector Y2 and one end of the capacitor C78, ​​and the other end of the capacitor C65 is respectively connected to the other end of the capacitor C78 and the other end of the resistor R46;

[0027] The drain bias subcircuit includes an inductor L13, a capacitor C80, a capacitor C83 and a capacitor C87, one end of the inductor L13 is connected to the drain of the power amplifier tube U4, the other end of the inductor L13 is respectively connected to one end of the capacitor C80, one end of the capacitor C83, one end of the capacitor C87 and the other end of the inductor L12, the other end of the capacitor C80 is respectively connected to the other end of the capacitor C83 and the other end of the capacitor C87, and is grounded;

[0028] The output matching subcircuit includes capacitor C54, capacitor C56, inductor L10, capacitor C67, capacitor C68 and capacitor C63. One end of the capacitor C54 is respectively connected to one end of the capacitor C56, one end of the inductor L10 and the other end of the capacitor C55. The other end of the capacitor C54 is respectively connected to the other end of the capacitor C56, the other end of the inductor L10, one end of the capacitor C67, one end of the capacitor C68 and one end of the capacitor C63. The other end of the capacitor C67 is respectively connected to the other end of the capacitor C68, the RF output terminal J8 and the RF output terminal J9 and is grounded. The other end of the capacitor C63 is connected to the RF output terminal J3.

[0029] The beneficial effect of the above further solution is that the RF power amplifier source in the present invention adopts a narrowband matching solution made of lumped components, which effectively improves the transmission efficiency and greatly improves the wireless energy transmission efficiency of the system.

[0030] Furthermore, the radio frequency current sampling circuit includes a radio frequency operational amplifier chip U9A and a radio frequency operational amplifier chip U9B;

[0031] The in-phase input terminal of the chip U9A is connected to one end of the resistor R72, and the other end of the resistor R72 is respectively connected to the output terminal OB of the chip U9B, the inverting input terminal of the chip U9B and one end of the capacitor C106. The inverting input terminal of the chip U9A is respectively connected to the grounding resistor R62 and one end of the resistor R61, and the other end of the resistor R61 is respectively connected to the P06 pin of the chip U6 and the output terminal of the chip U9A. The V+ pin of the chip U9A is respectively connected to the grounding capacitor C102 and the The AVDD1 pin is connected, the V- pin of the chip U9A is grounded, the other end of the capacitor C106 is respectively connected to one end of the resistor R68 and the resistor R73, the other end of the resistor R73 is respectively connected to the grounded capacitor C113, the grounded capacitor C112, the grounded capacitor C111 and the in-phase input terminal of the chip U9B, the other end of the resistor R68 is respectively connected to one end of the sampling resistor RS5, the grounded capacitor C99 and one end of the sampling resistor RS4, the other end of the sampling resistor RS4 is grounded, and the other end of the sampling resistor RS5 is grounded.

[0032] The beneficial effect of the above further scheme is: the RF current sampling circuit in the present invention is responsible for detecting the normal current consumption of the RF power amplifier source, and the Bluetooth chip can calculate the RF output power of the magnetic resonance transmitting module by detecting the output voltage value, and calculate the current magnetic resonance wireless charging efficiency by comparing the charging power of the receiving end. When the efficiency decreases, the Bluetooth host circuit at the transmitting end can change the output voltage of the voltage regulator circuit by adjusting the output voltage of the PWM integration circuit to adjust the output power of the RF power amplifier source, thereby changing the transmission efficiency of the magnetic resonance transceiver module.

[0033] Furthermore, the charging control circuit includes a battery voltage sampling subcircuit, an overcurrent protection and switch subcircuit, a charging voltage sampling subcircuit and a charging current sampling subcircuit, wherein:

[0034] The battery voltage sampling subcircuit includes a resistor R76, a grounding resistor R80, a resistor R78, a capacitor C121 and a capacitor C122, one end of the resistor R76 is respectively connected to the overcurrent protection and switch subcircuit, the receiving rectifier voltage stabilizing circuit and the positive electrode of the diode D10, the other end of the resistor R76 is respectively connected to the grounding resistor R80, one end of the capacitor C122 and one end of the resistor R78, the other end of the resistor R78 is respectively connected to the P04 pin of the chip U6, the other end of the capacitor C121 is connected to the other end of the capacitor C122 and grounded;

[0035] The overcurrent protection and switch subcircuit includes a MOS tube Q5, a fuse F1, and a triode Q6. The source of the MOS tube Q5 is respectively connected to one end of the resistor R83, one end of the capacitor C135, and one end of the inductor L19. The other end of the inductor L19 is respectively connected to one end of the capacitor C134, the positive electrode of the receiving rectifier voltage stabilizing circuit diode D10, and one end of the resistor R76. The other end of the capacitor C134 is connected to the other end of the capacitor C135 and is grounded. The gate of the MOS tube Q5 is respectively connected to the gate of the inductor L19. The other end of the resistor R83 is connected to one end of the resistor R87, the other end of the resistor R87 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is grounded, the base of the transistor Q6 is connected to one end of the resistor R91, the other end of the resistor R91 is connected to the P13 pin of the chip U6, the drain of the MOS tube Q5 is connected to one end of the fuse F1, the other end of the fuse F1 is connected to the positive electrode of the lithium battery BT, and the negative electrode of the lithium battery BT is respectively connected to the grounding resistor RS6 and the charging current sampling sub-circuit;

[0036] The charging voltage sampling subcircuit includes a resistor R77, a grounding resistor R81, a resistor R79, a capacitor C123 and a capacitor C124, one end of the resistor R77 is connected to the positive electrode of the lithium battery, the other end of the resistor R77 is respectively connected to the grounding resistor R81, one end of the capacitor C124 and one end of the resistor R79, the other end of the resistor R79 is respectively connected to one end of the capacitor C123 and the P05 pin of the chip U6, the other end of the capacitor C123 is connected to the other end of the capacitor C124 and grounded;

[0037] The charging current sampling subcircuit includes an operational amplifier chip U13, the negative power supply terminal of the chip U13 is connected to the CC3 network, the power supply pin of the chip U13 is respectively connected to the CC3 network and one end of the capacitor C158, the other end of the capacitor C153 is connected to the CC3 network, the in-phase input terminal of the chip U13 is respectively connected to one end of the capacitor C155, one end of the capacitor C156 and one end of the resistor R92, the other end of the resistor R92 is respectively connected to one end of the capacitor C153, one end of the capacitor C154 and the CC3 network, the other end of the capacitor C153 is respectively connected to the other end of the capacitor C154 and the CC3 network, the other end of the capacitor C155 is respectively connected to the other end of the capacitor C156 and the CC3 network, the inverting input terminal of the chip U13 is respectively connected to one end of the resistor R94 and one end of the resistor R95, the other end of the resistor R95 is connected to the CC3 network, and the other end of the resistor R94 is respectively connected to the output terminal of the chip U13 and the P06 pin of the chip U6.

[0038] The beneficial effect of the above further scheme is: the charging control circuit in the present invention is used to realize overcharge protection, over-discharge protection, overcurrent protection and temperature detection of the lithium battery through circuit integration. The overcharge protection is to detect the voltage across the lithium battery, and send the detected voltage to the Bluetooth chip for comparison with the set maximum charging threshold voltage. When this threshold voltage is exceeded, the Bluetooth chip controls to shut down the charging; the over-discharge protection is also to detect the voltage across the battery, and send the detected voltage to the Bluetooth chip for comparison with the set minimum discharge threshold voltage. When it is lower than this threshold voltage, the Bluetooth chip controls to shut down the discharge; the overcurrent protection is to detect the charging current, and send the detected maximum charging current to the Bluetooth chip for comparison. When it exceeds the set maximum charging current, the charging of the lithium battery is shut down; the temperature detection is to detect the surface temperature of the lithium battery. When the detected temperature exceeds the normal temperature, the charging and discharging of the lithium battery is stopped.

[0039] Further, the receiving rectifier and voltage stabilization circuit includes a second matching network, a receiving rectifier sub-circuit and a receiving voltage stabilization sub-circuit, wherein:

[0040] The second matching network includes a capacitor C116, a capacitor C117, a capacitor C125 and a capacitor C126, one end of the capacitor C116 is respectively connected to one end of the capacitor C117, one end of the capacitor C125, one end of the capacitor C126 and the J11 input terminal of the magnetic resonance transmitting antenna, the other end of the capacitor C116 is respectively connected to the other end of the capacitor C117 and the receiving rectifier circuit, and the other end of the capacitor C125 is respectively connected to the other end of the capacitor C126 and the receiving rectifier circuit;

[0041] The receiving rectifier circuit includes a diode D6, a diode D7, a diode D8, a diode D9, a capacitor C118, a capacitor C119 and a capacitor C120, the positive electrode of the diode D6 is respectively connected to the negative electrode of the diode D7 and the other end of the capacitor C116, the positive electrode of the diode D7 is respectively connected to the positive electrode of the diode D9, one end of the capacitor C118, one end of the capacitor C119 and one end of the capacitor C120, and is grounded, the negative electrode of the diode D6 is respectively connected to the negative electrode of the diode D8, the other end of the capacitor C118, the other end of the capacitor C119, the other end of the capacitor C120 and the receiving voltage stabilizing sub-circuit, and the positive electrode of the diode D8 is respectively connected to the negative electrode of the diode D9, the other end of the capacitor C125 and the input end of J12 of the magnetic resonance transmitting antenna;

[0042] The receiving voltage stabilization subcircuit includes a step-down integrated chip U10 and a diode D11, the VIN pin of the chip U10 is respectively connected to one end of the resistor R82, the grounding capacitor C132 and the negative electrode of the diode D6, the EN pin of the chip U10 is respectively connected to the grounding resistor R84 and the other end of the resistor R82, the RT / CLK pin of the chip U10 is connected to one end of the resistor R85, the GND pin of the chip U10 is respectively connected to the ePAD pin of the chip U10 and the other end of the resistor R85, and is grounded, the BOOT pin of the chip U10 is connected to one end of the capacitor C127, the other end of the capacitor C127 is respectively connected to the SW pin of the chip U10, the negative electrode of the diode and one end of the inductor L20, the other end of the inductor L20 is respectively connected to one end of the capacitor C128, one end of the capacitor C129, and the negative electrode of the capacitor C130. One end, one end of capacitor C131, one end of resistor R86, one end of resistor R90, the other end of inductor L19, the positive electrode of diode D10 and the other end of resistor R76 are connected, the positive electrode of diode D11 is respectively connected to the other end of capacitor C128, the other end of capacitor C129, the other end of capacitor C130 and the other end of capacitor C131, and are grounded, the other end of resistor R86 is connected to one end of capacitor C136, the other end of capacitor C136 is respectively connected to one end of resistor R89 ​​and the FB pin of the chip U10, the other end of resistor R89 ​​is connected to the other end of resistor R90, the COMP pin of chip U10 is respectively connected to one end of resistor R88 and one end of capacitor C137, the other end of resistor R88 is connected to one end of capacitor C138, the other end of capacitor C138 is connected to the other end of capacitor C137 and are grounded.

[0043] The beneficial effect of the above further scheme is: in the receiving rectification and voltage-stabilizing circuit of the present invention, the bridge rectifier circuit is composed of four rectifier diodes, namely diode D6, diode D7, diode D8, and diode D9 to form a bridge rectifier, which converts the high-frequency alternating current received by the magnetic resonance receiving antenna into direct current; the receiving voltage-stabilizing subcircuit is composed of a step-down integrated chip U10 and a feedback circuit, and the direct current after bridge rectification is sent to the step-down integrated chip U10. The required voltage value can be set by adjusting the value of the feedback pin, so that the output voltage is more stable and clean.

[0044] Furthermore, the magnetic resonance transmitting antenna and the magnetic resonance receiving antenna are both planar structures, wherein:

[0045] The front side of the magnetic resonance transmitting antenna is a first transmitting resonant coil, and the back side thereof is a second transmitting resonant coil. The first transmitting resonant coil and the second transmitting resonant coil are both quadrilateral spiral ring coils with notches. A first connection point is provided on the first transmitting resonant coil, and a second connection point is provided on the second transmitting resonant coil. A through hole is provided between the first connection point and the second connection point.

[0046] The front side of the magnetic resonance receiving antenna is a receiving resonant coil, and the back side thereof includes a microstrip line and a pad. The receiving resonant coil is a square spiral ring coil with a notch, on which a third connection point is arranged, and the microstrip line is divided into three sections, the first section of the microstrip line and the second section of the microstrip line are vertically connected to each other, two pads are arranged between the second section of the microstrip line and the third section of the microstrip line, and the microstrip line is connected to the receiving rectifier and voltage stabilizing circuit through the pad, the first section of the microstrip line and the third section of the microstrip line are arranged with a fourth connection point, and a through hole is arranged between the third connection point and the fourth connection point.

[0047] The beneficial effect of the above further solution is that the present invention uses a planar printed circuit board to process the structure of the magnetic resonance transmitting antenna and the magnetic resonance receiving antenna, thereby realizing the miniaturization and integration of the system and greatly reducing the production, installation and maintenance costs of the system.

[0048] Furthermore, the geometric parameters and electrical parameters of the magnetic resonance transmitting antenna are set as follows:

[0049] The outer length L of the first transmitting resonant coil is res_TX1 50mm-150mm;

[0050] The outer width H of the first transmitting resonant coil res_TX1 50mm-150mm;

[0051] The width W of the microstrip line in the first transmitting resonant coil res_TX1 3mm-5mm;

[0052] The distance S between the microstrip lines in the first transmitting resonant coil res_TX1 1mm-3mm;

[0053] The outer length L of the second transmitting resonant coil is res_TX2 50mm-150mm;

[0054] The outer width H of the second transmitting resonant coil res_TX2 50mm-150mm;

[0055] The width W of the microstrip line in the second transmitting resonant coil res_TX2 3mm-5mm;

[0056] The distance S between the microstrip lines in the second transmitting resonant coil res_TX2 1mm-3mm;

[0057] The resonant capacitance value of the magnetic resonance transmitting antenna is 100pF-500pF;

[0058] The matching capacitance value of the magnetic resonance transmitting antenna is 100pF-500pF;

[0059] The geometric parameters and electrical parameters of the magnetic resonance receiving antenna are set as follows:

[0060] The external length L of the receiving resonant coil res_RX 30mm-50mm;

[0061] The outer width H of the receiving resonant coil res_RX 30mm-50mm;

[0062] The width W of the microstrip line in the receiving resonant coil res_RX 0.5mm-1.5mm;

[0063] The distance S between the microstrip lines in the receiving resonant coil res_RX 0.3mm-0.7mm;

[0064] The length L of the first microstrip line res_RX1 3mm-5mm;

[0065] The width W of the first microstrip line res_RX1 0.5mm-1.5mm;

[0066] The length L of the second microstrip line res_RX2 5mm-7mm;

[0067] The width W of the second microstrip line res_RX2 0.5mm-1.5mm;

[0068] The length L of the third microstrip line res_RX3 5mm-7mm;

[0069] The width W of the third microstrip line res_RX3 0.5mm-1.5mm;

[0070] The length L of the pad pad_RX 3mm-5mm;

[0071] The width W of the pad pad_RX 1mm-3mm;

[0072] The resonant capacitance value of the magnetic resonance receiving antenna is 100pF-500pF;

[0073] The matching capacitance value of the magnetic resonance receiving antenna is 100pF-500pF.

[0074] The beneficial effect of the above further scheme is that the geometric parameters of the antenna structure adopted by the present invention can effectively improve the quality factor of the magnetic resonance transceiver antenna, and the electrical parameters can improve the coupling coefficient of the magnetic resonance transceiver antenna, so that the transmission efficiency between the magnetic resonance transceiver antennas is greatly increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 It is a structural schematic diagram of the present invention.

[0076] Figure 2 It is a structural schematic diagram of the magnetic resonance transmission module in the present invention.

[0077] Figure 3 It is a structural schematic diagram of the magnetic resonance receiving module in the present invention.

[0078] Figure 4 It is a circuit diagram of a Bluetooth host circuit or a Bluetooth slave circuit in the present invention.

[0079] Figure 5 This is a DC / DC voltage stabilizing circuit diagram of the present invention.

[0080] Figure 6 This is a PWM integration circuit diagram of the present invention.

[0081] Figure 7 This is a circuit diagram of a radio frequency power amplifier source in the present invention.

[0082] Figure 8 This is a circuit diagram of radio frequency current sampling in the present invention.

[0083] Fig. 9 This is a charging control circuit diagram of the present invention.

[0084] Fig.10 This is a receiving, rectifying and voltage-stabilizing circuit diagram in the present invention.

[0085] Fig.11 Shown is a schematic diagram of the front structure of a magnetic resonance transmitting antenna provided by an embodiment of the present invention.

[0086] Fig.12 Shown is a schematic diagram of the back structure of the magnetic resonance transmitting antenna provided by the embodiment of the present invention.

[0087] Fig.13 Shown is a schematic diagram of the front structure of a magnetic resonance receiving antenna provided by an embodiment of the present invention.

[0088] Fig.14Shown is a schematic diagram of the back structure of the magnetic resonance receiving antenna provided by the embodiment of the present invention.

[0089] Among them, 1-magnetic resonance transmitting module, 2-magnetic resonance receiving module, 3-Bluetooth host circuit, 4-DC / DC voltage stabilizing circuit, 5-PWM integration circuit, 6-RF power amplifier source, 7-RF current sampling circuit, 8-magnetic resonance transmitting antenna, 9-Bluetooth slave circuit, 10-charging control circuit, 11-receiving rectification and voltage stabilizing circuit, 12-magnetic resonance receiving antenna, 801-first transmitting resonant coil, 802-second transmitting resonant coil, 803-first connection point, 804-second connection point, 1201-receiving resonant coil, 1202-microstrip line, 1203-soldering pad, 1204-third connection point, 1205-fourth connection point. DETAILED DESCRIPTION

[0090] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0091] Example

[0092] The embodiment of the present invention provides a device for controlling the output power of wireless charging based on a PWM integration circuit, in which a magnetic resonance transmitting module directly supplies power to a magnetic resonance receiving module using magnetic resonance wireless charging technology to charge the device. Figure 1 As shown, it includes a magnetic resonance transmitting module 1 and a magnetic resonance receiving module 2 connected to the magnetic resonance transmitting module 1; Figure 2 As shown, the magnetic resonance transmitting module 1 includes a wireless charging base, a Bluetooth host circuit 3, and a DC / DC voltage stabilizing circuit 4, a PWM integration circuit 5, a radio frequency power amplifier source 6, a radio frequency current sampling circuit 7 and a magnetic resonance transmitting antenna 8 respectively connected to the Bluetooth host circuit 3. The radio frequency power amplifier source 6 and the magnetic resonance transmitting antenna 8 are both installed on the wireless charging base, and the magnetic resonance transmitting antenna 8 is connected to the magnetic resonance receiving module 2; Figure 3 As shown, the magnetic resonance receiving module 2 includes a heat sink, a magnetic resonance receiving antenna 12, a Bluetooth slave circuit 9, and a receiving rectification and voltage stabilizing circuit 11 and a charging control circuit 10 respectively connected to the Bluetooth slave circuit 9. The magnetic resonance receiving antenna 12, the receiving rectification and voltage stabilizing circuit 11 and the charging control circuit 10 are connected in sequence. The receiving rectification and voltage stabilizing circuit 11 and the Bluetooth slave circuit 9 are both fixed on the upper surface of the heat sink. The magnetic resonance receiving antenna 12 is arranged directly above the magnetic resonance transmitting antenna 8.

[0093] In this embodiment, the magnetic resonance transmitting module 1 is used for transmitting magnetic resonance wireless energy, the magnetic resonance receiving module is used to directly power the magnetic induction transmitting module, and the magnetic resonance receiving module 2 also includes a lithium battery and a battery management circuit arranged above the magnetic resonance receiving antenna 12, a ferrite magnetic isolation sheet is arranged between the lithium battery and the magnetic resonance receiving antenna 12, and the lithium battery is respectively connected to the charging control circuit 10 and the battery management circuit. The present invention uses magnetic resonance wireless charging technology to directly charge the lithium battery, transmits electromagnetic energy through the magnetic resonance transmitting antenna 8, and transmits energy through the magnetic resonance receiving antenna 12 to reach the receiving rectification and voltage stabilizing circuit 11, and then powers the charging control circuit 10, and the charging control circuit 10 powers the lithium battery. In this process, the Bluetooth slave circuit 9 monitors the voltage and current required to be consumed by the charging control circuit 10, and transmits this information to the magnetic resonance transmitting module 1 through Bluetooth. After receiving the voltage and current required for charging, the Bluetooth host circuit 3 of the magnetic resonance transmitting module 1 adjusts the PWM input duty cycle of the PWM integration circuit 5, and then adjusts the output voltage of the DC / DC voltage stabilizing circuit 4, thereby achieving the adjustment of the transmission power of the output end.

[0094] like Figure 4 As shown, the Bluetooth host circuit 3 and the Bluetooth slave circuit 9 have the same structure, both including a Bluetooth chip U6; the Bluetooth host circuit also includes a first LDO sub-circuit, the first LDO sub-circuit includes a voltage regulator chip U8; the Bluetooth slave circuit also includes a second LDO sub-circuit, the second LDO sub-circuit includes a voltage regulator chip U11, wherein:

[0095] like Figure 4(a) The AVDD1 pin of the chip U6 is respectively connected to the AVDD2 pin of the chip U6, the AVDD3 pin of the chip U6, the AVDD4 pin of the chip U6, the AVDD5 pin of the chip U6, the AVDD6 pin of the chip U6, a grounding capacitor C95, a grounding capacitor C94, a grounding capacitor C93, a grounding capacitor C92, a grounding capacitor C91, a grounding capacitor C90, a DVDD1 pin of the chip U6, one end of a resistor R71, the NC pin of the chip U6, the chip U11 and the chip U8. The DVDD1 pin of the chip U6 is also respectively connected to the DVDD2 pin of the chip U6, one end of a capacitor C101 and a capacitor C90. The first end of the chip U6 is connected to the first end of the capacitor C100, the other end of the capacitor C101 is connected to the other end of the capacitor C100 and grounded, the DCOUPL pin of the chip U6 is connected to one end of the capacitor C104, the other end of the capacitor C104 is respectively connected to one end of the capacitor C107, the GND pin of the chip U6 and the ePAD pin of the chip U6, and grounded, the other end of the capacitor C107 is connected to the NC pin of the chip U6, the REST pin of the chip U6 is respectively connected to the grounded capacitor C110 and the other end of the resistor R71, the R_BIAS pin of the chip U6 is connected to one end of the resistor R75, the other end of the resistor R75 is connected to the 4th pin of the crystal oscillator Y3 and grounded, the chip The XSOC_Q1 pin of the chip U6 is respectively connected to the 1st pin of the crystal oscillator Y3 and one end of the capacitor C114, the XSOC_Q2 pin of the chip U6 is respectively connected to one end of the capacitor C115 and the 3rd pin of the crystal oscillator Y3, the other end of the capacitor C115 is respectively connected to the 2nd pin of the crystal oscillator Y3 and the other end of the capacitor C114, and grounded, the RF_P pin of the chip U6 is connected to one end of the capacitor C88, the other end of the capacitor C88 is respectively connected to one end of the capacitor C89 and one end of the inductor L14, the other end of the inductor L14 is grounded, the other end of the capacitor C89 is respectively connected to one end of the inductor L17 and one end of the inductor L15, the other end of the inductor L17 is grounded. The first and second pins of the chip U6 are connected to the PWM integration circuit 5, the second pin of the chip U6 is connected to the DC / DC voltage regulator circuit 4, the P06 pin of the chip U6 is connected to the charging control circuit 10 and the RF current sampling circuit 7, and the P07 pin of the chip U6 is connected to the DC / DC voltage regulator circuit 4.The P13 pin, the P04 pin and the P05 pin of the chip U6 are respectively connected to the charging control circuit 10;

[0096] like Figure 4 (b) The Vin terminal of the chip U8 is respectively connected to one end of the capacitor CC1, the RF power amplifier source 6 and the DC / DC voltage stabilizing circuit 4, the Vout terminal of the chip U8 is connected to one end of the inductor L18, the other end of the inductor L18 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC2, the GND grounding terminal of the chip U8 is respectively connected to the other end of the capacitor CC1 and the other end of the capacitor CC2, and is grounded;

[0097] like Figure 4 (c) The Vin pin of the chip U11 is respectively connected to one end of the capacitor CC31, the grounding capacitor C133 and one end of the inductor L21, the other end of the inductor L21 is respectively connected to the cathode of the diode D10 and the cathode of the diode D12, the anode of the diode D10 is respectively connected to the receiving rectifier voltage stabilizing circuit 11 and the charging control circuit 10, the anode of the diode D12 is connected to the anode of the lithium battery, the Vout pin of the chip U11 is connected to one end of the inductor L22, the other end of the inductor L22 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC4, the other end of the capacitor CC4 is respectively connected to the GND pin of the chip U11 and the other end of the capacitor CC31, and grounded.

[0098] like Figure 5 As shown, the DC / DC voltage stabilizing circuit 4 includes a DC / DC rectifier circuit, a current and voltage detection circuit, and a voltage output control circuit.

[0099] The DC / DC rectifier circuit includes a rectifier chip U1, the IN pin of the chip U1 is respectively connected to the grounded capacitor C62, one end of the resistor R44, the positive electrode of the polarity capacitor C61, the grounded capacitor C60 and one end of the inductor L8, the other end of the inductor L8 is respectively connected to the Vin end of the chip U8 and the grounded capacitor C57, the negative electrode of the polarity capacitor C61 is grounded, the EN pin of the chip U1 is respectively connected to the other end of the resistor R44 and the grounded resistor R45, the VCC pin of the chip U1 is connected to the grounded capacitor C82, the GND pin of the chip U1 is grounded, and the FB pin of the chip U1 is respectively connected to one end of the capacitor C79, one end of the resistor R54, the negative electrode of the diode D4 and the negative electrode of the diode D5. The anode of the diode D5 is connected to the PWM integration circuit 5, the anode of the diode D4 is connected to the voltage output control subcircuit, the other end of the capacitor C79 is connected to one end of the resistor R47, the other end of the resistor R47 is respectively connected to one end of the resistor R50, the voltage output control subcircuit, the grounding capacitor C77, the grounding capacitor C76, the grounding capacitor C75 and one end of the inductor L11, the other end of the resistor R50 is respectively connected to the other end of the resistor R54 and the grounding resistor R55, the SW pin of the chip U1 is respectively connected to one end of the capacitor C58 and the other end of the inductor L11, the other end of the capacitor C58 is connected to one end of the resistor R43, and the other end of the resistor R43 is connected to the RST pin of the chip U1;

[0100] The current and voltage detection subcircuit includes a detection chip U5, the IN+ pin of the chip U5 is respectively connected to the V+ pin of the chip U5, the other end of the resistor R47, one end of the capacitor C81 and one end of the sampling resistor RSA1, the REF pin of the chip U5 is respectively connected to the other end of the capacitor C81 and the GND pin of the chip U5, and is grounded, the OUT pin of the chip U5 is connected to the positive electrode of the diode D4, the IN- pin of the chip U5 is respectively connected to the other end of the sampling resistor RSA1, one end of the resistor R51 and the voltage output control subcircuit, the other end of the resistor R51 is respectively connected to one end of the resistor R53 and one end of the resistor R60, the other end of the resistor R53 is respectively connected to the P07 pin of the chip U6 and one end of the capacitor C86, the other end of the resistor R60 is connected to the other end of the capacitor C86 and is grounded;

[0101] The voltage output control subcircuit includes a PMOS tube U2, the source of which is respectively connected to the IN-pin of the chip U5 and one end of the resistor R48, the gate of which is respectively connected to the other end of the resistor R48 and one end of the resistor R49, the other end of the resistor R49 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R56 and grounded, the base of the transistor Q3 is respectively connected to one end of the resistor R52 and the other end of the resistor R56, the other end of the resistor R52 is connected to the P12 pin of the chip U6, the drain of the PMOS tube U2 is respectively connected to the grounded capacitor C69 and one end of the inductor L12, and the other end of the inductor L12 is connected to the RF power amplifier source 6.

[0102] In this embodiment, in this part of the circuit, the model of chip U1 is MP2315, the model of chip U5 is INA213A, and the model of chip U2 is CEM4435A. The chip U5 detects the current consumed by the RF power amplifier source 6 by sampling the voltage across the resistor RSA1. When the current exceeds the set threshold value, the output pin of the chip U5 will output a high level, which will cause the voltage on the feedback pin FB of the chip U1 to suddenly increase, so that the voltage output by the voltage stabilizing circuit drops below the normal working voltage to protect the subsequent RF power amplifier source circuit. When the current of the RF power amplifier source 6 returns to below the normal value, the output level of the chip U5 is maintained at a low level. At this time, the voltage on the FB pin of the chip U1 returns to normal, and the voltage output by the voltage stabilizing circuit returns to the normal set value. In this embodiment, the voltage divider circuit composed of resistor R51 and resistor R60 divides the output voltage and sends it to the AD sampling port of the Bluetooth host circuit chip. The Bluetooth host circuit chip can monitor the output voltage of the voltage stabilizing circuit in real time. By monitoring the output voltage of the voltage stabilizing circuit and the power switch circuit composed of chip U2, the power supply of the RF power amplifier source can be effectively guaranteed, thereby ensuring the safe operation of the system.

[0103] like Figure 6As shown, the PWM integration circuit 5 includes an operational amplifier chip U7A, an operational amplifier chip U7B, an operational amplifier chip N1A, an operational amplifier chip N1B and an NMOS tube Q4. The gate of the NMOS tube Q4 is connected to one end of the resistor R70, the other end of the resistor R70 is connected to the P11 pin of the chip U6, the source of the NMOS tube Q4 is grounded, the drain of the NMOS tube Q4 is respectively connected to one end of the resistor R65, the grounding resistor R74 and one end of the resistor R66, the other end of the resistor R65 is connected to the AVDD1 pin of the chip U6, the other end of the resistor R66 is respectively connected to one end of the resistor R67 and one end of the capacitor C103, the other end of the resistor R67 is respectively connected to the grounding capacitor C109 and the The positive phase input terminal of the chip U7B is connected, the other end of the capacitor C103 is respectively connected to one end of the resistor R63 and the inverting input terminal of the chip U7B, the other end of the resistor R63 is respectively connected to one end of the resistor R69 and the output terminal OB of the chip U7B, the other end of the resistor R69 is respectively connected to the positive phase input terminal of the chip U7A, the inverting input terminal of the chip U7A is connected to one end of the resistor R64, the output terminal of the chip U7A is respectively connected to the other end of the resistor R64, the grounding capacitor C108 and one end of the resistor R2, the The V- pin is connected to one end of the capacitor C105 and grounded, the V+ pin of the chip U7A is respectively connected to the AVDD1 pin of the chip U6 and the other end of the capacitor C105, the other end of the resistor R2 is respectively connected to the grounded capacitor C3, the grounded capacitor C4 and one end of the resistor R3, the other end of the resistor R3 is respectively connected to one end of the capacitor C5 and one end of the resistor R4, the other end of the resistor R4 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the inverting input end of the chip N1B is respectively connected to the other end of the capacitor C5 ... the grounded capacitor C5 and the positive phase input end of the chip N1B, the other end of the resistor R3 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the other end of the resistor R3 is respectively connected to the grounded capacitor C5, the grounded capacitor C4 and one end of the resistor R4, the other end of the resistor R4 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the other end of the capacitor C5, the grounded capacitor C4 and the grounded capacitor C4 The output terminal OB of the chip U6 is connected to the positive input terminal of the chip N1A, the inverting input terminal of the chip N1A is respectively connected to the output terminal of the chip N1A and the positive electrode of the diode D5, the V- pin of the chip N1A is respectively connected to one end of the capacitor C1 and one end of the capacitor C2, and is grounded, the V+ pin of the chip N1A is respectively connected to one end of the resistor R1, the other end of the capacitor C2 and the other end of the capacitor C1, the other end of the resistor R1 is connected to one end of the inductor FB1, and the other end of the inductor FB1 is connected to the AVDD1 pin of the chip U6.

[0104] In this embodiment, the parameters of the input duty cycle of the PWM integration circuit 5, the integration circuit output voltage, and the voltage stabilization circuit output voltage are as follows:

[0105]

[0106]

[0107] like Figure 7 As shown, the RF power amplifier source 6 includes a voltage stabilizing chip U3, a power amplifier tube U4, a gate bias subcircuit, an input matching subcircuit, a drain bias subcircuit and an output matching subcircuit. The Vin end of the chip U3 is respectively connected to one end of the capacitor C72, the other end of the inductor L8 and the Vin end of the chip U8, the Vout end of the chip U3 is respectively connected to the capacitor C73, the capacitor C74, the 5V-RF power supply, one end of the inductor L9 and the gate bias subcircuit, the GND end of the chip U3 is respectively connected to the other end of the capacitor C74, the other end of the capacitor C73 and the other end of the capacitor C72, and is grounded, the other end of the inductor L9 is respectively connected to the grounded capacitor C70, the grounded capacitor C71 and the 4th pin of the connector Y2, the 2nd pin of the connector Y2 is grounded, and the 3rd pin of the connector Y2 is connected to the input matching subcircuit;

[0108] The gate bias subcircuit includes a capacitor C84, a resistor R57, a resistor R58, a capacitor C85, a resistor R59 and a resistor R46. One end of the capacitor C84 is connected to the Vout end of the chip U3 and one end of the resistor R57, respectively. The other end of the capacitor C84 is grounded. The other end of the resistor R57 is connected to one end of the resistor R58. The other end of the resistor R58 is connected to one end of the capacitor C85, one end of the resistor R59 and one end of the resistor R46, respectively. The other end of the resistor R59 is connected to the capacitor C85. The other end of the resistor R46 is connected to the input matching sub-circuit and the gate of the power amplifier tube U4, the source of the power amplifier tube U4 is grounded, the drain of the power amplifier tube U4 is connected to one end of the capacitor C64, one end of the capacitor C59, the drain bias sub-circuit, one end of the capacitor C55 and one end of the capacitor C66, the other end of the capacitor C64 is connected to the other end of the capacitor C59 and grounded, the other end of the capacitor C55 is connected to the other end of the capacitor C66 and the output matching sub-circuit;

[0109] The input matching subcircuit includes a capacitor C65 and a capacitor C78, ​​one end of the capacitor C65 is respectively connected to the third pin of the connector Y2 and one end of the capacitor C78, ​​and the other end of the capacitor C65 is respectively connected to the other end of the capacitor C78 and the other end of the resistor R46;

[0110] The drain bias subcircuit includes an inductor L13, a capacitor C80, a capacitor C83 and a capacitor C87, one end of the inductor L13 is connected to the drain of the power amplifier tube U4, the other end of the inductor L13 is respectively connected to one end of the capacitor C80, one end of the capacitor C83, one end of the capacitor C87 and the other end of the inductor L12, the other end of the capacitor C80 is respectively connected to the other end of the capacitor C83 and the other end of the capacitor C87, and is grounded;

[0111] The output matching subcircuit includes capacitor C54, capacitor C56, inductor L10, capacitor C67, capacitor C68 and capacitor C63. One end of the capacitor C54 is respectively connected to one end of the capacitor C56, one end of the inductor L10 and the other end of the capacitor C55. The other end of the capacitor C54 is respectively connected to the other end of the capacitor C56, the other end of the inductor L10, one end of the capacitor C67, one end of the capacitor C68 and one end of the capacitor C63. The other end of the capacitor C67 is respectively connected to the other end of the capacitor C68, the RF output terminal J8 and the RF output terminal J9 and is grounded. The other end of the capacitor C63 is connected to the RF output terminal J3.

[0112] like Figure 8 As shown, the RF current sampling circuit 7 includes a RF operational amplifier chip U9A and a RF operational amplifier chip U9B; the in-phase input terminal of the chip U9A is connected to one end of a resistor R72, and the other end of the resistor R72 is respectively connected to the output terminal OB of the chip U9B, the inverting input terminal of the chip U9B and one end of a capacitor C106, the inverting input terminal of the chip U9A is respectively connected to a grounding resistor R62 and one end of a resistor R61, and the other end of the resistor R61 is respectively connected to the P06 pin of the chip U6 and the output terminal of the chip U9A, and the V+ pin of the chip U9A is respectively connected to the ... It is connected to the grounded capacitor C102 and the AVDD1 pin of the chip U6, the V- pin of the chip U9A is grounded, the other end of the capacitor C106 is respectively connected to one end of the resistor R68 and the resistor R73, the other end of the resistor R73 is respectively connected to the grounded capacitor C113, the grounded capacitor C112, the grounded capacitor C111 and the in-phase input end of the chip U9B, the other end of the resistor R68 is respectively connected to one end of the sampling resistor RS5, the grounded capacitor C99 and one end of the sampling resistor RS4, the other end of the sampling resistor RS4 is grounded, and the other end of the sampling resistor RS5 is grounded.

[0113] In this embodiment, the current sampling circuit composed of operational amplifier chips U9A and U9B is responsible for detecting the normal current consumption of the RF power amplifier source 6; the Bluetooth host circuit chip can calculate the RF output power of the magnetic resonance transmitting module 1 by detecting the output voltage value, and calculate the current magnetic resonance wireless charging efficiency by comparing the charging power of the receiving end. When the efficiency decreases, the Bluetooth host circuit at the transmitting end can change the output voltage of the voltage regulator circuit by increasing the output voltage of the PWM integration circuit 5, thereby adjusting the output power of the RF power amplifier source, thereby changing the transmission efficiency of the magnetic resonance transceiver module.

[0114] like Fig. 9As shown, the charging control circuit 10 includes a battery voltage sampling subcircuit, an overcurrent protection and switch subcircuit, a charging voltage sampling subcircuit and a charging current sampling subcircuit. The battery voltage sampling subcircuit includes a resistor R76, a grounding resistor R80, a resistor R78, a capacitor C121 and a capacitor C122, one end of the resistor R76 is respectively connected to the overcurrent protection and switch subcircuit, the receiving rectifier voltage stabilizing circuit 11 and the positive electrode of the diode D10, the other end of the resistor R76 is respectively connected to the grounding resistor R80, one end of the capacitor C122 and one end of the resistor R78, the other end of the resistor R78 is respectively connected to the P04 pin of the chip U6, the other end of the capacitor C121 is connected to the other end of the capacitor C122 and grounded;

[0115] The overcurrent protection and switch subcircuit includes a MOS tube Q5, a fuse F1, and a triode Q6. The source of the MOS tube Q5 is respectively connected to one end of the resistor R83, one end of the capacitor C135, and one end of the inductor L19. The other end of the inductor L19 is respectively connected to one end of the capacitor C134, the receiving rectifier voltage stabilizing circuit 11, the positive electrode of the diode D10, and one end of the resistor R76. The other end of the capacitor C134 is connected to the other end of the capacitor C135 and is grounded. The gate of the MOS tube Q5 is respectively connected to the The other end of the resistor R83 is connected to one end of the resistor R87, the other end of the resistor R87 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is grounded, the base of the transistor Q6 is connected to one end of the resistor R91, the other end of the resistor R91 is connected to the P13 pin of the chip U6, the drain of the MOS tube Q5 is connected to one end of the fuse F1, the other end of the fuse F1 is connected to the positive electrode of the lithium battery BT, and the negative electrode of the lithium battery BT is respectively connected to the grounding resistor RS6 and the charging current sampling sub-circuit;

[0116] The charging voltage sampling subcircuit includes a resistor R77, a grounding resistor R81, a resistor R79, a capacitor C123 and a capacitor C124, one end of the resistor R77 is connected to the positive electrode of the lithium battery, the other end of the resistor R77 is respectively connected to the grounding resistor R81, one end of the capacitor C124 and one end of the resistor R79, the other end of the resistor R79 is respectively connected to one end of the capacitor C123 and the P05 pin of the chip U6, the other end of the capacitor C123 is connected to the other end of the capacitor C124 and grounded;

[0117] The charging current sampling subcircuit includes an operational amplifier chip U13, the negative power supply terminal of the chip U13 is connected to the CC3 network, the power supply pin of the chip U13 is respectively connected to the CC3 network and one end of the capacitor C158, the other end of the capacitor C153 is connected to the CC3 network, the in-phase input terminal of the chip U13 is respectively connected to one end of the capacitor C155, one end of the capacitor C156 and one end of the resistor R92, the other end of the resistor R92 is respectively connected to one end of the capacitor C153, one end of the capacitor C154 and the CC3 network, the other end of the capacitor C153 is respectively connected to the other end of the capacitor C154 and the CC3 network, the other end of the capacitor C155 is respectively connected to the other end of the capacitor C156 and the CC3 network, the inverting input terminal of the chip U13 is respectively connected to one end of the resistor R94 and one end of the resistor R95, the other end of the resistor R95 is connected to the CC3 network, and the other end of the resistor R94 is respectively connected to the output terminal of the chip U13 and the P06 pin of the chip U6.

[0118] In this embodiment, the fuse F1 ensures that the lithium battery and the charging circuit are disconnected in time when the current is too large. The fuse F1 is a fast-blow self-recovering chip fuse. The MOS tube Q5 is responsible for opening and closing the charging circuit; the current sampling circuit composed of the operational amplifier chip U13 is responsible for detecting the charging current, and feeds back the detected current information to the Bluetooth host circuit 3 at the transmitting end through the Bluetooth slave circuit 9 at the receiving end. There is also a charging voltage sampling sub-circuit and a battery voltage detection sub-circuit to ensure effective monitoring and safety control of the charging process.

[0119] like Fig.10 As shown, the receiving rectifier and voltage stabilizing circuit 11 includes a second matching network, a receiving rectifier circuit and a receiving voltage stabilizing circuit. The second matching network includes capacitor C116, capacitor C117, capacitor C125 and capacitor C126, one end of the capacitor C116 is respectively connected to one end of the capacitor C117, one end of the capacitor C125, one end of the capacitor C126 and the J11 input terminal of the magnetic resonance transmitting antenna 8, the other end of the capacitor C116 is respectively connected to the other end of the capacitor C117 and the receiving rectifier circuit, and the other end of the capacitor C125 is respectively connected to the other end of the capacitor C126 and the receiving rectifier circuit;

[0120] The receiving rectifier circuit includes a diode D6, a diode D7, a diode D8, a diode D9, a capacitor C118, a capacitor C119 and a capacitor C120, the positive electrode of the diode D6 is respectively connected to the negative electrode of the diode D7 and the other end of the capacitor C116, the positive electrode of the diode D7 is respectively connected to the positive electrode of the diode D9, one end of the capacitor C118, one end of the capacitor C119 and one end of the capacitor C120, and is grounded, the negative electrode of the diode D6 is respectively connected to the negative electrode of the diode D8, the other end of the capacitor C118, the other end of the capacitor C119, the other end of the capacitor C120 and the receiving voltage stabilizing sub-circuit, and the positive electrode of the diode D8 is respectively connected to the negative electrode of the diode D9, the other end of the capacitor C125 and the input end of J12 of the magnetic resonance transmitting antenna 8;

[0121] The receiving voltage stabilization subcircuit includes a step-down integrated chip U10 and a diode D11, the VIN pin of the chip U10 is respectively connected to one end of the resistor R82, the grounding capacitor C132 and the negative electrode of the diode D6, the EN pin of the chip U10 is respectively connected to the grounding resistor R84 and the other end of the resistor R82, the RT / CLK pin of the chip U10 is connected to one end of the resistor R85, the GND pin of the chip U10 is respectively connected to the ePAD pin of the chip U10 and the other end of the resistor R85, and is grounded, the BOOT pin of the chip U10 is connected to one end of the capacitor C127, the other end of the capacitor C127 is respectively connected to the SW pin of the chip U10, the negative electrode of the diode and one end of the inductor L20, the other end of the inductor L20 is respectively connected to one end of the capacitor C128, one end of the capacitor C129, and the negative electrode of the capacitor C130. One end, one end of capacitor C131, one end of resistor R86, one end of resistor R90, the other end of inductor L19, the positive electrode of diode D10 and the other end of resistor R76 are connected, the positive electrode of diode D11 is respectively connected to the other end of capacitor C128, the other end of capacitor C129, the other end of capacitor C130 and the other end of capacitor C131, and are grounded, the other end of resistor R86 is connected to one end of capacitor C136, the other end of capacitor C136 is respectively connected to one end of resistor R89 ​​and the FB pin of the chip U10, the other end of resistor R89 ​​is connected to the other end of resistor R90, the COMP pin of chip U10 is respectively connected to one end of resistor R88 and one end of capacitor C137, the other end of resistor R88 is connected to one end of capacitor C138, the other end of capacitor C138 is connected to the other end of capacitor C137 and are grounded.

[0122] The magnetic resonance transmitting antenna 8 and the magnetic resonance receiving antenna 12 are both flat plate structures. Figure 11-12As shown, the front side of the magnetic resonance transmitting antenna 8 is a first transmitting resonant coil 801, and the back side thereof is a second transmitting resonant coil 802. Both the first transmitting resonant coil 801 and the second transmitting resonant coil 802 are quadrilateral spiral ring coils with notches. A first connecting point 803 is provided on the first transmitting resonant coil 801, and a second connecting point 804 is provided on the second transmitting resonant coil 802. A through hole is provided between the first connecting point 803 and the second connecting point 804.

[0123] like Figure 13-14 As shown, the front side of the magnetic resonance receiving antenna 12 is a receiving resonant coil 1201, and the back side thereof includes a microstrip line 1202 and a pad 1203. The receiving resonant coil 1201 is a square spiral ring coil with a notch, on which a third connection point 1204 is arranged, and the microstrip line 1202 is divided into three sections, the first section of the microstrip line and the second section of the microstrip line are vertically connected to each other, two pads 1203 are arranged between the second section of the microstrip line and the third section of the microstrip line, and the microstrip line 1202 is connected to the receiving rectifying and voltage stabilizing circuit 11 through the pad 1203, the first section of the microstrip line and the third section of the microstrip line are arranged with a fourth connection point 1205, and a through hole is arranged between the third connection point 1204 and the fourth connection point 1205.

[0124] In this embodiment, the magnetic resonance transmitting antenna 8 and the magnetic resonance receiving antenna 12 are both flat-plate structures, and are processed using a double-layer printed circuit board with a thickness of 0.6-1.0 mm. After determining the structural design of the magnetic resonance transmitting antenna 8 and the magnetic resonance receiving antenna 12, corresponding resonant capacitors and matching circuits are added to them to achieve the same-frequency magnetic resonance of the two. The specific positions of each connection point are as follows: Figure 11-Figure 14 As shown in , the two connection points with through holes between them are connected by microstrip lines arranged in the through holes. Figure 11-Figure 14 The symbol identification in the structure diagram shown is combined with the actual application requirements to set the geometric parameters and electrical parameters of the magnetic resonance transmitting antenna and the magnetic resonance receiving antenna as follows:

[0125] (1) The geometric parameters and electrical parameters of the magnetic resonance transmitting antenna 8 are set as follows:

[0126] The outer length L of the first transmitting resonant coil 801 is res_TX1 50mm-150mm;

[0127] The outer width H of the first transmitting resonant coil 801 is res_TX1 50mm-150mm;

[0128] The width W of the microstrip line in the first transmitting resonant coil 801 res_TX1 3mm-5mm;

[0129] The distance S between the microstrip lines in the first transmitting resonant coil 801 res_TX1 1mm-3mm;

[0130] The outer length L of the second transmitting resonant coil 802 is res_TX2 50mm-150mm;

[0131] The outer width H of the second transmitting resonant coil 802 res_TX2 50mm-150mm;

[0132] The width W of the microstrip line in the second transmitting resonant coil 802 res_TX2 3mm-5mm;

[0133] The distance S between the microstrip lines in the second transmitting resonant coil 802 res_TX2 1mm-3mm;

[0134] The resonant capacitance value of the magnetic resonance transmitting antenna 8 is 100pF-500pF;

[0135] The matching capacitance value of the magnetic resonance transmitting antenna 8 is 100pF-500pF;

[0136] (2) The geometric parameters and electrical parameters of the magnetic resonance receiving antenna 12 are set as follows:

[0137] The external length L of the receiving resonant coil 1201 is res_RX 30mm-50mm;

[0138] The outer width H of the receiving resonant coil 1201 is res_RX 30mm-50mm;

[0139] The width W of the microstrip line in the receiving resonant coil 1201 res_RX 0.5mm-1.5mm;

[0140] The distance S between the microstrip lines in the receiving resonant coil 1201 res_RX 0.3mm-0.7mm;

[0141] The length L of the first microstrip line res_RX1 3mm-5mm;

[0142] The width W of the first microstrip line res_RX1 0.5mm-1.5mm;

[0143] The length L of the second microstrip line res_RX2 5mm-7mm;

[0144] The width W of the second microstrip line res_RX2 0.5mm-1.5mm;

[0145] The length L of the third microstrip line res_RX3 5mm-7mm;

[0146] The width W of the third microstrip line res_RX3 0.5mm-1.5mm;

[0147] The length L of the pad 1203 pad_RX 3mm-5mm;

[0148] The width W of the pad 1203 pad_RX 1mm-3mm;

[0149] The resonant capacitance value of the magnetic resonance receiving antenna 12 is 100pF-500pF;

[0150] The matching capacitance value of the magnetic resonance receiving antenna 12 is 100 pF-500 pF.

[0151] In this embodiment, the magnetic resonance transmitting module 1 uses magnetic resonance wireless charging technology to directly power the magnetic resonance receiving module 2 and then charge the device. The wireless charging base generates electromagnetic energy with a frequency of 6.78MHz, which is transmitted through the magnetic resonance transmitting antenna 8, and then transmitted to the magnetic resonance receiving antenna 12 through the same-frequency magnetic resonance coupling between the magnetic resonance transmitting and receiving antennas. The magnetic resonance receiving antenna 12 is connected to the receiving rectification and voltage stabilizing circuit 11, and the receiving rectification and voltage stabilizing circuit 11 is connected to the Bluetooth slave circuit 9. The Bluetooth slave circuit 9 controls the charging control circuit 10 to power the charging control circuit 10, and the charging control circuit 10 is then connected to a load device such as a battery. The operating frequency designed in this embodiment is not limited to 6.78MHz, and the operating frequency can be adjusted within the available frequency band range of 5MHz-20MHz. Figure 4 As shown, when the operating frequency is 6.78 MHz, the wireless energy transmission efficiency between the magnetic resonance transmitting antenna 8 and the magnetic resonance receiving antenna 12 can be maintained above 80%. Therefore, in the embodiment of the present invention, the operating frequency is preferably 6.78 MHz.

[0152] In this embodiment, the magnetic resonance receiving module 2 provides multiple voltage output interfaces of 3.3V-15V to meet the input voltage requirements of different electrical equipment. The total wireless power supply provided by the system can reach 100W, which can provide stable and efficient wireless power supply for magnetic induction devices with different voltage interfaces and different powers.

Claims

1. A device for controlling wireless charging output power based on a PWM integration circuit, characterized in that: It comprises a magnetic resonance transmitting module (1), and a magnetic resonance receiving module (2) connected to the magnetic resonance transmitting module (1); The magnetic resonance transmitting module (1) comprises a wireless charging base, a Bluetooth host circuit (3), and a DC / DC voltage stabilizing circuit (4), a PWM integration circuit (5), a radio frequency power amplifier source (6), a radio frequency current sampling circuit (7), and a magnetic resonance transmitting antenna (8) respectively connected to the Bluetooth host circuit (3); the radio frequency power amplifier source (6) and the magnetic resonance transmitting antenna (8) are both installed on the wireless charging base, and the magnetic resonance transmitting antenna (8) is connected to the magnetic resonance receiving module (2); The magnetic resonance receiving module (2) comprises a heat sink, a magnetic resonance receiving antenna (12), a Bluetooth slave circuit (9), and a receiving rectification and voltage stabilizing circuit (11) and a charging control circuit (10) respectively connected to the Bluetooth slave circuit (9); the magnetic resonance receiving antenna (12), the receiving rectification and voltage stabilizing circuit (11) and the charging control circuit (10) are connected in sequence; the receiving rectification and voltage stabilizing circuit (11) and the Bluetooth slave circuit (9) are both fixed to the upper surface of the heat sink; and the magnetic resonance receiving antenna (12) is arranged directly above the magnetic resonance transmitting antenna (8); The Bluetooth host circuit (3) and the Bluetooth slave circuit (9) have the same structure and both include a Bluetooth chip U6; the Bluetooth host circuit also includes a first LDO sub-circuit, the first LDO sub-circuit includes a voltage regulator chip U8; the Bluetooth slave circuit also includes a second LDO sub-circuit, the second LDO sub-circuit includes a voltage regulator chip U11, wherein: The AVDD1 pin of the chip U6 is respectively connected to the AVDD2 pin of the chip U6, the AVDD3 pin of the chip U6, the AVDD4 pin of the chip U6, the AVDD5 pin of the chip U6, the AVDD6 pin of the chip U6, the grounding capacitor C95, the grounding capacitor C94, the grounding capacitor C93, the grounding capacitor C92, the grounding capacitor C91, the grounding capacitor C90, the DVDD1 pin of the chip U6, one end of the resistor R71, the NC pin of the chip U6, the chip U11 and the chip U8. The DVDD1 pin of the chip U6 is also respectively connected to the DVDD2 pin of the chip U6, one end of the capacitor C101 and the end of the capacitor C100. The other end of the capacitor C101 is connected to the other end of the capacitor C100 and is grounded. The DCOUPL pin of the chip U6 is connected to one end of the capacitor C104. The other end of the capacitor C104 is respectively connected to one end of the capacitor C107, the GND pin of the chip U6 and the ePAD pin of the chip U6 and is grounded. The other end of the capacitor C107 is connected to the NC pin of the chip U6. The REST pin of the chip U6 is respectively connected to the grounded capacitor C110 and the other end of the resistor R71. The R_BIAS pin of the chip U6 is connected to one end of the resistor R75. The other end of the resistor R75 is connected to the 4th pin of the crystal oscillator Y3 and is grounded. The XSOC pin of the chip U6 is connected to the NC pin of the chip U6. The _Q1 pin is respectively connected to the 1st pin of the crystal oscillator Y3 and one end of the capacitor C114, the XSOC_Q2 pin of the chip U6 is respectively connected to one end of the capacitor C115 and the 3rd pin of the crystal oscillator Y3, the other end of the capacitor C115 is respectively connected to the 2nd pin of the crystal oscillator Y3 and the other end of the capacitor C114, and grounded, the RF_P pin of the chip U6 is connected to one end of the capacitor C88, the other end of the capacitor C88 is respectively connected to one end of the capacitor C89 and one end of the inductor L14, the other end of the inductor L14 is grounded, the other end of the capacitor C89 is respectively connected to one end of the inductor L17 and one end of the inductor L15, the other end of the inductor L17 is respectively connected to one end of the capacitor C96 and one end of the inductor L96. and grounded capacitor C98, the other end of capacitor C96 is connected to the RF_N pin of the chip U6, the other end of inductor L15 is respectively connected to grounded capacitor C97 and one end of inductor L16, the other end of inductor L16 is connected to one end of the magnetic resonance transmitting antenna (8), the other end of the magnetic resonance transmitting antenna (8) is grounded, the P11 pin of the chip U6 is connected to the PWM integration circuit (5), the second pin of the chip U6 is connected to the DC / DC voltage regulator circuit (4), the P06 pin of the chip U6 is respectively connected to the charging control circuit (10) and the RF current sampling circuit (7), the P07 pin of the chip U6 is connected to the DC / DC voltage regulator circuit (4),The P13 pin, the P04 pin and the P05 pin of the chip U6 are respectively connected to the charging control circuit (10); The Vin terminal of the chip U8 is respectively connected to one end of the capacitor CC1, the radio frequency power amplifier source (6) and the DC / DC voltage stabilizing circuit (4); the Vout terminal of the chip U8 is connected to one end of the inductor L18; the other end of the inductor L18 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC2; the GND grounding terminal of the chip U8 is respectively connected to the other end of the capacitor CC1 and the other end of the capacitor CC2, and is grounded; The Vin pin of the chip U11 is respectively connected to one end of the capacitor CC31, the grounding capacitor C133 and one end of the inductor L21; the other end of the inductor L21 is respectively connected to the cathode of the diode D10 and the cathode of the diode D12; the anode of the diode D10 is respectively connected to the receiving rectifier voltage stabilizing circuit (11) and the charging control circuit (10); the anode of the diode D12 is connected to the anode of the lithium battery; the Vout pin of the chip U11 is connected to one end of the inductor L22; the other end of the inductor L22 is respectively connected to the AVDD1 pin of the chip U6 and one end of the capacitor CC4; the other end of the capacitor CC4 is respectively connected to the GND pin of the chip U11 and the other end of the capacitor CC31 and is grounded.

2. The device for controlling wireless charging output power based on PWM integration circuit according to claim 1, characterized in that: The DC / DC voltage stabilizing circuit (4) comprises a DC / DC rectifier circuit, a current and voltage detection circuit, and a voltage output control circuit, wherein: The DC / DC rectifier circuit includes a rectifier chip U1, the IN pin of the chip U1 is respectively connected to a grounded capacitor C62, one end of a resistor R44, a positive electrode of a polar capacitor C61, a grounded capacitor C60 and one end of an inductor L8, the other end of the inductor L8 is respectively connected to a Vin end of the chip U8 and a grounded capacitor C57, the negative electrode of the polar capacitor C61 is grounded, the EN pin of the chip U1 is respectively connected to the other end of the resistor R44 and a grounded resistor R45, the VCC pin of the chip U1 is connected to a grounded capacitor C82, the GND pin of the chip U1 is grounded, the FB pin of the chip U1 is respectively connected to one end of a capacitor C79, one end of a resistor R54, the negative electrode of a diode D4 and the negative electrode of a diode D5 The anode of the diode D5 is connected to the PWM integration circuit (5), the anode of the diode D4 is connected to the voltage output control subcircuit, the other end of the capacitor C79 is connected to one end of the resistor R47, the other end of the resistor R47 is respectively connected to one end of the resistor R50, the voltage output control subcircuit, the grounding capacitor C77, the grounding capacitor C76, the grounding capacitor C75 and one end of the inductor L11, the other end of the resistor R50 is respectively connected to the other end of the resistor R54 and the grounding resistor R55, the SW pin of the chip U1 is respectively connected to one end of the capacitor C58 and the other end of the inductor L11, the other end of the capacitor C58 is connected to one end of the resistor R43, and the other end of the resistor R43 is connected to the RST pin of the chip U1; The current and voltage detection subcircuit includes a detection chip U5, the IN+ pin of the chip U5 is respectively connected to the V+ pin of the chip U5, the other end of the resistor R47, one end of the capacitor C81 and one end of the sampling resistor RSA1, the REF pin of the chip U5 is respectively connected to the other end of the capacitor C81 and the GND pin of the chip U5, and is grounded, the OUT pin of the chip U5 is connected to the positive electrode of the diode D4, the IN- pin of the chip U5 is respectively connected to the other end of the sampling resistor RSA1, one end of the resistor R51 and the voltage output control subcircuit, the other end of the resistor R51 is respectively connected to one end of the resistor R53 and one end of the resistor R60, the other end of the resistor R53 is respectively connected to the P07 pin of the chip U6 and one end of the capacitor C86, the other end of the resistor R60 is connected to the other end of the capacitor C86 and is grounded; The voltage output control subcircuit comprises a PMOS tube U2, wherein the source of the PMOS tube U2 is respectively connected to the IN-pin of the chip U5 and one end of a resistor R48, the gate of the PMOS tube U2 is respectively connected to the other end of the resistor R48 and one end of a resistor R49, the other end of the resistor R49 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to one end of a resistor R56 and is grounded, the base of the transistor Q3 is respectively connected to one end of a resistor R52 and the other end of the resistor R56, the other end of the resistor R52 is connected to the P12 pin of the chip U6, the drain of the PMOS tube U2 is respectively connected to a grounded capacitor C69 and one end of an inductor L12, the other end of the inductor L12 is connected to the RF power amplifier source (6).

3. The device for controlling wireless charging output power based on PWM integration circuit according to claim 2, characterized in that: The PWM integration circuit (5) comprises an operational amplifier chip U7A, an operational amplifier chip U7B, an operational amplifier chip N1A, an operational amplifier chip N1B and an NMOS tube Q4, wherein: The gate of the NMOS tube Q4 is connected to one end of the resistor R70, the other end of the resistor R70 is connected to the P11 pin of the chip U6, the source of the NMOS tube Q4 is grounded, the drain of the NMOS tube Q4 is respectively connected to one end of the resistor R65, the grounding resistor R74 and one end of the resistor R66, the other end of the resistor R65 is connected to the AVDD1 pin of the chip U6, the other end of the resistor R66 is respectively connected to one end of the resistor R67 and one end of the capacitor C103, the other end of the resistor R67 is respectively connected to the grounding capacitor C109 and the The positive phase input terminal of the chip U7B is connected, the other end of the capacitor C103 is respectively connected to one end of the resistor R63 and the inverting input terminal of the chip U7B, the other end of the resistor R63 is respectively connected to one end of the resistor R69 and the output terminal OB of the chip U7B, the other end of the resistor R69 is respectively connected to the positive phase input terminal of the chip U7A, the inverting input terminal of the chip U7A is connected to one end of the resistor R64, the output terminal of the chip U7A is respectively connected to the other end of the resistor R64, the grounding capacitor C108 and one end of the resistor R2, the The V- pin is connected to one end of the capacitor C105 and grounded, the V+ pin of the chip U7A is respectively connected to the AVDD1 pin of the chip U6 and the other end of the capacitor C105, the other end of the resistor R2 is respectively connected to the grounded capacitor C3, the grounded capacitor C4 and one end of the resistor R3, the other end of the resistor R3 is respectively connected to one end of the capacitor C5 and one end of the resistor R4, the other end of the resistor R4 is respectively connected to the grounded capacitor C6 and the positive phase input end of the chip N1B, the inverting input end of the chip N1B is respectively connected to the other end of the capacitor C5 ... the grounded capacitor C5 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the grounded capacitor C5 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the grounded capacitor C5 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the grounded capacitor C5 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the grounded capacitor C5 and the positive phase input end of the chip N1B, the grounded capacitor C4 and the positive phase input end of the chip N1B, the The output terminal OB of the chip U6 is connected to the positive input terminal of the chip N1A, the inverting input terminal of the chip N1A is respectively connected to the output terminal of the chip N1A and the positive electrode of the diode D5, the V- pin of the chip N1A is respectively connected to one end of the capacitor C1 and one end of the capacitor C2, and is grounded, the V+ pin of the chip N1A is respectively connected to one end of the resistor R1, the other end of the capacitor C2 and the other end of the capacitor C1, the other end of the resistor R1 is connected to one end of the inductor FB1, and the other end of the inductor FB1 is connected to the AVDD1 pin of the chip U6.

4. The device for controlling wireless charging output power based on PWM integration circuit according to claim 2, characterized in that: The radio frequency power amplifier source (6) comprises a voltage stabilizing chip U3, a power amplifier tube U4, a gate bias subcircuit, an input matching subcircuit, a drain bias subcircuit and an output matching subcircuit, wherein: The Vin end of the chip U3 is respectively connected to one end of the capacitor C72, the other end of the inductor L8 and the Vin end of the chip U8, the Vout end of the chip U3 is respectively connected to the capacitor C73, the capacitor C74, the 5V-RF power supply, one end of the inductor L9 and the gate bias sub-circuit, the GND end of the chip U3 is respectively connected to the other end of the capacitor C74, the other end of the capacitor C73 and the other end of the capacitor C72, and is grounded, the other end of the inductor L9 is respectively connected to the grounded capacitor C70, the grounded capacitor C71 and the 4th pin of the connector Y2, the 2nd pin of the connector Y2 is grounded, and the 3rd pin of the connector Y2 is connected to the input matching sub-circuit; The gate bias subcircuit includes a capacitor C84, a resistor R57, a resistor R58, a capacitor C85, a resistor R59 and a resistor R46. One end of the capacitor C84 is connected to the Vout end of the chip U3 and one end of the resistor R57, respectively. The other end of the capacitor C84 is grounded. The other end of the resistor R57 is connected to one end of the resistor R58. The other end of the resistor R58 is connected to one end of the capacitor C85, one end of the resistor R59 and one end of the resistor R46, respectively. The other end of the resistor R59 is connected to the capacitor C85. The other end of the resistor R46 is connected to the input matching sub-circuit and the gate of the power amplifier tube U4, the source of the power amplifier tube U4 is grounded, the drain of the power amplifier tube U4 is connected to one end of the capacitor C64, one end of the capacitor C59, the drain bias sub-circuit, one end of the capacitor C55 and one end of the capacitor C66, the other end of the capacitor C64 is connected to the other end of the capacitor C59 and grounded, the other end of the capacitor C55 is connected to the other end of the capacitor C66 and the output matching sub-circuit; The input matching subcircuit includes a capacitor C65 and a capacitor C78, ​​one end of the capacitor C65 is connected to the third pin of the connector Y2 and one end of the capacitor C78, ​​and the other end of the capacitor C65 is connected to the other end of the capacitor C78 and the other end of the resistor R46; The drain bias subcircuit includes an inductor L13, a capacitor C80, a capacitor C83 and a capacitor C87, one end of the inductor L13 is connected to the drain of the power amplifier tube U4, the other end of the inductor L13 is respectively connected to one end of the capacitor C80, one end of the capacitor C83, one end of the capacitor C87 and the other end of the inductor L12, the other end of the capacitor C80 is respectively connected to the other end of the capacitor C83 and the other end of the capacitor C87, and is grounded; The output matching subcircuit includes capacitor C54, capacitor C56, inductor L10, capacitor C67, capacitor C68 and capacitor C63. One end of the capacitor C54 is respectively connected to one end of the capacitor C56, one end of the inductor L10 and the other end of the capacitor C55. The other end of the capacitor C54 is respectively connected to the other end of the capacitor C56, the other end of the inductor L10, one end of the capacitor C67, one end of the capacitor C68 and one end of the capacitor C63. The other end of the capacitor C67 is respectively connected to the other end of the capacitor C68, the RF output terminal J8 and the RF output terminal J9 and is grounded. The other end of the capacitor C63 is connected to the RF output terminal J3.

5. The device for controlling wireless charging output power based on PWM integration circuit according to claim 1, characterized in that: The radio frequency current sampling circuit (7) comprises a radio frequency operational amplifier chip U9A and a radio frequency operational amplifier chip U9B; The in-phase input terminal of the chip U9A is connected to one end of the resistor R72, and the other end of the resistor R72 is respectively connected to the output terminal OB of the chip U9B, the inverting input terminal of the chip U9B and one end of the capacitor C106. The inverting input terminal of the chip U9A is respectively connected to the grounding resistor R62 and one end of the resistor R61, and the other end of the resistor R61 is respectively connected to the P06 pin of the chip U6 and the output terminal of the chip U9A. The V+ pin of the chip U9A is respectively connected to the grounding capacitor C102 and the The AVDD1 pin is connected, the V- pin of the chip U9A is grounded, the other end of the capacitor C106 is respectively connected to one end of the resistor R68 and the resistor R73, the other end of the resistor R73 is respectively connected to the grounded capacitor C113, the grounded capacitor C112, the grounded capacitor C111 and the in-phase input terminal of the chip U9B, the other end of the resistor R68 is respectively connected to one end of the sampling resistor RS5, the grounded capacitor C99 and one end of the sampling resistor RS4, the other end of the sampling resistor RS4 is grounded, and the other end of the sampling resistor RS5 is grounded.

6. The device for controlling wireless charging output power based on PWM integration circuit according to claim 1, characterized in that: The charging control circuit (10) comprises a battery voltage sampling subcircuit, an overcurrent protection and switch subcircuit, a charging voltage sampling subcircuit and a charging current sampling subcircuit, wherein: The battery voltage sampling subcircuit comprises a resistor R76, a grounding resistor R80, a resistor R78, a capacitor C121 and a capacitor C122, one end of the resistor R76 is respectively connected to the overcurrent protection and switch subcircuit, the receiving rectifier voltage stabilizing circuit (11) and the positive electrode of the diode D10, the other end of the resistor R76 is respectively connected to the grounding resistor R80, one end of the capacitor C122 and one end of the resistor R78, the other end of the resistor R78 is respectively connected to the P04 pin of the chip U6, the other end of the capacitor C121 is connected to the other end of the capacitor C122 and is grounded; The overcurrent protection and switch subcircuit comprises a MOS tube Q5, a fuse F1, and a triode Q6. The source of the MOS tube Q5 is respectively connected to one end of a resistor R83, one end of a capacitor C135, and one end of an inductor L19. The other end of the inductor L19 is respectively connected to one end of a capacitor C134, the receiving rectifier voltage stabilizing circuit (11), the positive electrode of a diode D10, and one end of a resistor R76. The other end of the capacitor C134 is connected to the other end of the capacitor C135 and is grounded. The gate of the MOS tube Q5 is respectively connected to one end of a resistor R83, one end of a capacitor C135, and one end of an inductor L19. The MOS tube Q5 is connected to the other end of the resistor R83 and one end of the resistor R87, the other end of the resistor R87 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is grounded, the base of the transistor Q6 is connected to one end of the resistor R91, the other end of the resistor R91 is connected to the P13 pin of the chip U6, the drain of the MOS tube Q5 is connected to one end of the fuse F1, the other end of the fuse F1 is connected to the positive electrode of the lithium battery BT, and the negative electrode of the lithium battery BT is respectively connected to the grounding resistor RS6 and the charging current sampling sub-circuit; The charging voltage sampling subcircuit includes a resistor R77, a grounding resistor R81, a resistor R79, a capacitor C123 and a capacitor C124, one end of the resistor R77 is connected to the positive electrode of the lithium battery, the other end of the resistor R77 is respectively connected to the grounding resistor R81, one end of the capacitor C124 and one end of the resistor R79, the other end of the resistor R79 is respectively connected to one end of the capacitor C123 and the P05 pin of the chip U6, the other end of the capacitor C123 is connected to the other end of the capacitor C124 and grounded; The charging current sampling subcircuit includes an operational amplifier chip U13, the negative power supply terminal of the chip U13 is connected to the CC3 network, the power supply pin of the chip U13 is respectively connected to the CC3 network and one end of the capacitor C158, the other end of the capacitor C153 is connected to the CC3 network, the in-phase input terminal of the chip U13 is respectively connected to one end of the capacitor C155, one end of the capacitor C156 and one end of the resistor R92, the other end of the resistor R92 is respectively connected to one end of the capacitor C153, one end of the capacitor C154 and the CC3 network, the other end of the capacitor C153 is respectively connected to the other end of the capacitor C154 and the CC3 network, the other end of the capacitor C155 is respectively connected to the other end of the capacitor C156 and the CC3 network, the inverting input terminal of the chip U13 is respectively connected to one end of the resistor R94 and one end of the resistor R95, the other end of the resistor R95 is connected to the CC3 network, and the other end of the resistor R94 is respectively connected to the output terminal of the chip U13 and the P06 pin of the chip U6.

7. The device for controlling wireless charging output power based on PWM integration circuit according to claim 6, characterized in that: The receiving rectifier and voltage stabilizing circuit (11) comprises a second matching network, a receiving rectifier subcircuit and a receiving voltage stabilizing subcircuit, wherein: The second matching network comprises a capacitor C116, a capacitor C117, a capacitor C125 and a capacitor C126, one end of the capacitor C116 is respectively connected to one end of the capacitor C117, one end of the capacitor C125, one end of the capacitor C126 and the J11 input terminal of the magnetic resonance transmitting antenna (8), the other end of the capacitor C116 is respectively connected to the other end of the capacitor C117 and the receiving rectifier circuit, and the other end of the capacitor C125 is respectively connected to the other end of the capacitor C126 and the receiving rectifier circuit; The receiving rectifier circuit comprises a diode D6, a diode D7, a diode D8, a diode D9, a capacitor C118, a capacitor C119 and a capacitor C120, wherein the positive electrode of the diode D6 is respectively connected to the negative electrode of the diode D7 and the other end of the capacitor C116, the positive electrode of the diode D7 is respectively connected to the positive electrode of the diode D9, one end of the capacitor C118, one end of the capacitor C119 and one end of the capacitor C120, and is grounded, the negative electrode of the diode D6 is respectively connected to the negative electrode of the diode D8, the other end of the capacitor C118, the other end of the capacitor C119, the other end of the capacitor C120 and the receiving voltage stabilizing subcircuit, and the positive electrode of the diode D8 is respectively connected to the negative electrode of the diode D9, the other end of the capacitor C125 and the input end J12 of the magnetic resonance transmitting antenna (8); The receiving voltage stabilization subcircuit includes a step-down integrated chip U10 and a diode D11, the VIN pin of the chip U10 is respectively connected to one end of the resistor R82, the grounding capacitor C132 and the negative electrode of the diode D6, the EN pin of the chip U10 is respectively connected to the grounding resistor R84 and the other end of the resistor R82, the RT / CLK pin of the chip U10 is connected to one end of the resistor R85, the GND pin of the chip U10 is respectively connected to the ePAD pin of the chip U10 and the other end of the resistor R85, and is grounded, the BOOT pin of the chip U10 is connected to one end of the capacitor C127, the other end of the capacitor C127 is respectively connected to the SW pin of the chip U10, the negative electrode of the diode and one end of the inductor L20, the other end of the inductor L20 is respectively connected to one end of the capacitor C128, one end of the capacitor C129, and the negative electrode of the capacitor C130. One end, one end of capacitor C131, one end of resistor R86, one end of resistor R90, the other end of inductor L19, the positive electrode of diode D10 and the other end of resistor R76 are connected, the positive electrode of diode D11 is respectively connected to the other end of capacitor C128, the other end of capacitor C129, the other end of capacitor C130 and the other end of capacitor C131, and are grounded, the other end of resistor R86 is connected to one end of capacitor C136, the other end of capacitor C136 is respectively connected to one end of resistor R89 ​​and the FB pin of the chip U10, the other end of resistor R89 ​​is connected to the other end of resistor R90, the COMP pin of chip U10 is respectively connected to one end of resistor R88 and one end of capacitor C137, the other end of resistor R88 is connected to one end of capacitor C138, the other end of capacitor C138 is connected to the other end of capacitor C137 and are grounded.

8. The device for controlling wireless charging output power based on PWM integration circuit according to claim 1, characterized in that: The magnetic resonance transmitting antenna (8) and the magnetic resonance receiving antenna (12) are both planar structures, wherein: The front side of the magnetic resonance transmitting antenna (8) is a first transmitting resonant coil (801), and the back side thereof is a second transmitting resonant coil (802); the first transmitting resonant coil (801) and the second transmitting resonant coil (802) are both square spiral ring coils with a notch; a first connection point (803) is provided on the first transmitting resonant coil (801), and a second connection point (804) is provided on the second transmitting resonant coil (802); and a through hole is provided between the first connection point (803) and the second connection point (804); The front side of the magnetic resonance receiving antenna (12) is a receiving resonant coil (1201), and the back side thereof comprises a microstrip line (1202) and a solder pad (1203); the receiving resonant coil (1201) is a square spiral ring coil with a notch, on which a third connection point (1204) is arranged; the microstrip line (1202) is divided into three sections; the first section of the microstrip line and the second section of the microstrip line are vertically connected to each other; two solder pads (1203) are arranged between the second section of the microstrip line and the third section of the microstrip line; the microstrip line (1202) is connected to the receiving rectifying and voltage-stabilizing circuit (11) via the solder pad (1203); the first section of the microstrip line and the third section of the microstrip line are provided with a fourth connection point (1205); and a through hole is arranged between the third connection point (1204) and the fourth connection point (1205).

9. The device for controlling wireless charging output power based on PWM integration circuit according to claim 8, characterized in that: The geometric parameters and electrical parameters of the magnetic resonance transmitting antenna (8) are set as follows: The outer length L of the first transmitting resonant coil (801) is res_TX1 50mm-150mm; The outer width H of the first transmitting resonant coil (801) is res_TX1 50mm-150mm; The width W of the microstrip line in the first transmitting resonant coil (801) is res_TX1 3mm-5mm; The distance S between the microstrip lines in the first transmitting resonant coil (801) is res_TX1 1mm-3mm; The outer length L of the second transmitting resonant coil (802) res_TX2 50mm-150mm; The outer width H of the second transmitting resonant coil (802) is res_TX2 50mm-150mm; The width W of the microstrip line in the second transmitting resonant coil (802) is res_TX2 3mm-5mm; The distance S between the microstrip lines in the second transmitting resonant coil (802) is res_TX2 1mm-3mm; The resonant capacitance value of the magnetic resonance transmitting antenna (8) is 100pF-500pF; The matching capacitance value of the magnetic resonance transmitting antenna (8) is 100pF-500pF; The geometric parameters and electrical parameters of the magnetic resonance receiving antenna (12) are set as follows: The external length L of the receiving resonant coil (1201) res_RX 30mm-50mm; The outer width H of the receiving resonant coil (1201) res_RX 30mm-50mm; The width W of the microstrip line in the receiving resonant coil (1201) is res_RX 0.5mm-1.5mm; The distance S between the microstrip lines in the receiving resonant coil (1201) is res_RX 0.3mm-0.7mm; The length L of the first microstrip line res_RX1 3mm-5mm; The width W of the first microstrip line res_RX1 0.5mm-1.5mm; The length L of the second microstrip line res_RX2 5mm-7mm; The width W of the second microstrip line res_RX2 0.5mm-1.5mm; The length L of the third microstrip line res_RX3 5mm-7mm; The width W of the third microstrip line res_RX3 0.5mm-1.5mm; The length L of the pad (1203) pad_RX 3mm-5mm; The width W of the pad (1203) pad_RX 1mm-3mm; The resonant capacitance value of the magnetic resonance receiving antenna (12) is 100pF-500pF; The matching capacitance value of the magnetic resonance receiving antenna (12) is 100 pF-500 pF.

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