Semiconductor device and semiconductor package including the same

Abstract

A semiconductor device and a semiconductor package are provided. The semiconductor device includes: a substrate including a semiconductor chip region and a scribe region surrounding the semiconductor chip region; an insulating film disposed on the substrate above the semiconductor chip region and the scribe region, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening formed on the second surface and the fourth surface of the insulating film to expose the substrate, wherein the opening is formed in the scribe region, and wherein the first surface and the third surface of the insulating film do not include the opening exposing the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0098968, filed with the Korean Intellectual Property Office on August 24, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus and methods consistent with exemplary embodiments of the present invention relate to semiconductor devices and semiconductor packages including the semiconductor devices. Background Technology

[0004] Recently, semiconductor devices have been miniaturized and their performance improved. Therefore, low-dielectric-constant insulating films can be used in semiconductor devices.

[0005] When semiconductor devices are cut for packaging, physical stress can be applied to them. To prevent this physical stress, a low-dielectric-constant insulating film can be used in the semiconductor device. However, when using a low-dielectric-constant insulating film, the wiring underneath may peel off. Summary of the Invention

[0006] An exemplary embodiment of the present invention provides semiconductor device fabrication by means of an improved method in which openings are formed only on a limited number of side surfaces of the semiconductor device on a substrate.

[0007] However, the inventive concept is not limited to the embodiments described herein. Various other embodiments of the inventive concept will become apparent to those skilled in the art upon referring to the following detailed description.

[0008] According to some exemplary embodiments, a semiconductor device is provided, which may include: a substrate including a semiconductor chip region and a scribe region surrounding the semiconductor chip region; an insulating film disposed on the substrate above the semiconductor chip region and the scribe region, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening formed on the second surface and the fourth surface of the insulating film to expose the substrate, wherein the opening is formed in the scribe region, and the first surface and the third surface of the insulating film do not include the opening exposing the substrate.

[0009] According to some exemplary embodiments, a semiconductor device is provided, which may include: a substrate including a semiconductor chip region and a scribe region surrounding the semiconductor chip region; an insulating film disposed on the substrate above the semiconductor chip region and the scribe region, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and a passivation film disposed on the insulating film and disposed above the semiconductor chip region and the scribe region, wherein the first surface of the insulating film is defined by a first portion and a second portion of the insulating film, the first portion of the insulating film being located in the scribe region, protruding from the passivation film and having a first width, and the second portion of the insulating film being located in the scribe region, protruding from the passivation film and having a second width less than the first width, and the second surface of the insulating film being defined by a third portion of the insulating film, the third portion of the insulating film being located in the scribe region, protruding from the passivation film and having a third width less than the first width.

[0010] According to some embodiments of the present invention, a semiconductor package is provided, which may include: a substrate having four side surfaces; a semiconductor chip formed on the upper surface of the substrate; and an insulating film surrounding the semiconductor chip and having four side surfaces, wherein, in a plan view of the semiconductor device, only two of the four side surfaces of the insulating film expose the upper surface of the substrate, while the other two side surfaces of the insulating film are respectively connected to two of the four side surfaces of the substrate in the same plane. Attached Figure Description

[0011] The above and other aspects and features of the inventive concept will become apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, wherein:

[0012] Figure 1 This is a diagram showing a substrate on which a semiconductor device according to some embodiments is integrated prior to substrate dicing;

[0013] Figure 2 yes Figure 1 A magnified view of region K;

[0014] Figure 3 This is a diagram illustrating a semiconductor device according to some embodiments;

[0015] Figure 4 It is along Figure 3 A sectional view of line A-A';

[0016] Figure 5 It is along Figure 3 A sectional view of line B-B' in the middle;

[0017] Figure 6 It is along Figure 3 A sectional view of the C-C' line in the middle;

[0018] Figure 7 It is along Figure 3 A cross-sectional view of the D-D' line;

[0019] Figure 8 This is a diagram illustrating a semiconductor package according to some embodiments;

[0020] Figure 9 This is a diagram showing a substrate on which a semiconductor device according to some embodiments is integrated;

[0021] Figures 10 to 14 These are intermediate process diagrams illustrating methods for manufacturing semiconductor devices according to some embodiments; and

[0022] Figure 15 It was executed until Figure 14 The manufacturing process of semiconductor devices after Figure 9 A magnified view of region J. Detailed Implementation

[0023] The embodiments given herein are exemplary and do not limit the inventive concept. It should be understood that when an element or layer is referred to as “above,” “on,” “on,” “connected to,” or “coupled to” another element or layer, it may be directly above, directly on, directly connected to, or directly coupled to another element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as “directly above,” “directly on,” “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers present. The same reference numerals always denote the same element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0024] In the following text, reference will be made to Figures 1 to 7 A semiconductor device is described according to some embodiments.

[0025] Figure 1 This illustrates that, prior to dicing substrate 100, a semiconductor device according to some embodiments is integrated thereon. Figure 3 Figure 100 of substrate 1100. Figure 2 yes Figure 1 A magnified view of region K. Figure 2For clarity, the dicing line SL, substrate 100, third insulating film 115, first alignment bond 201, second alignment bond 202, third alignment bond 203, fourth alignment bond 204, and passivation film 117 are shown.

[0026] Reference Figure 1 and Figure 2 According to some embodiments, the substrate 100 of the semiconductor device may include a semiconductor chip region I and a scribing region II.

[0027] Multiple semiconductor chip regions I can be arranged on substrate 100. Each semiconductor chip region I can be spaced apart from each other by scribed regions II. Semiconductor chip regions I may include, for example, semiconductor chip wiring ( Figure 4 105 in the middle), bottom wiring structure ( Figure 4 121), upper wiring structure ( Figure 4 122) and rewire layer ( Figure 4 (123).

[0028] The scribing region II can be a region positioned around the semiconductor chip region I. For example, the scribing region II can be a region positioned along the periphery of the semiconductor chip region I. The scribing region II can include a dicing line SL. The dicing line SL can be a line used to dice the substrate 100 to fabricate a reference in subsequent processes. Figure 3 The semiconductor device 1100 is described.

[0029] The third insulating film 115 and the passivation film 117 can be disposed above the semiconductor chip region I and the scribing region II of the substrate 100. (See below for further details.) Figures 4 to 7 Describe its details.

[0030] The first alignment key 201, the second alignment key 202, the third alignment key 203, and the fourth alignment key 204 can be arranged in the scribing area II. The first alignment key 201, the second alignment key 202, the third alignment key 203, and the fourth alignment key 204 can be arranged between adjacent semiconductor chip areas I.

[0031] The dicing line SL can pass through the first alignment bond 201, the second alignment bond 202, the third alignment bond 203, and the fourth alignment bond 204. Therefore, when the substrate 100 is diced along the dicing line SL to form a semiconductor device in subsequent processes... Figure 3 When aligning the substrate 100 (as described in section 1100), each of the first alignment bond 201, the second alignment bond 202, the third alignment bond 203, and the fourth alignment bond 204 can be halved. The semiconductor device formed by cleaving the substrate 100 along the cleaving line SL... Figure 3 1100 in the text may include a portion of the scribing region II and the semiconductor chip region I.

[0032] Figure 3 This is a diagram illustrating a semiconductor device according to some embodiments. Figure 3 This shows a cut along the cutting line SL. Figure 1 and Figure 2 The semiconductor device 1100 is formed after the substrate 100. Figure 3 For clarity, only the substrate 100, the third insulating film 115, the passivation film 117, the first alignment bond 201, the second alignment bond 202, the third alignment bond 203, and the fourth alignment bond 204 are shown. Figure 4 It is along Figure 3 A sectional view of line A-A'. Figure 5 It is along Figure 3 A cross-sectional view of line B-B' in the middle. Figure 6 It is along Figure 3 A cross-sectional view of line C-C' in the middle. Figure 7 It is along Figure 3 A cross-sectional view of the D-D' line.

[0033] Reference Figures 3 to 7 According to some embodiments, the semiconductor device 1100 may include a portion of the scribing region II of the substrate 100 and the semiconductor chip region I.

[0034] Semiconductor chip region I may include a semiconductor chip. The semiconductor chip may include, for example, semiconductor chip wiring 105, lower wiring structure 121, upper wiring structure 122, and redistribution layer 123.

[0035] Semiconductor chips can be, for example, memory chips, logic chips, etc. When the semiconductor chip is a logic chip, various designs can be implemented considering the operations to be performed. When the semiconductor chip is a memory chip, the memory chip can be, for example, a non-volatile memory chip. Specifically, the memory chip can be a flash memory chip. More specifically, the memory chip can be one of a NAND flash memory chip or a NOR flash memory chip. On the other hand, the form of the storage device conceived according to the present invention is not limited thereto. In some embodiments, the memory chip may include one of PRAM (phase-change random access memory), MRAM (magnetoresistive random access memory), and RRAM (resistive random access memory).

[0036] Substrate 100 may have a structure in which a substrate and an epitaxial layer are stacked, but the inventive concept is not limited thereto. Substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, etc., and may be an SOI (semiconductor on insulator) substrate. In the following description, a silicon substrate will be used as an example. Furthermore, substrate 100 may have an insulating film formed on the silicon substrate.

[0037] Substrate 100 may include semiconductor chip wiring 105. Semiconductor chip wiring 105 may be disposed, for example, in semiconductor chip region I. In semiconductor devices according to some embodiments, it is assumed that semiconductor chip wiring 105 is metal wiring, but this is merely for illustrative purposes, and the embodiments are not limited thereto. Of course, semiconductor chip wiring 105 may be a transistor, diode, etc., formed in substrate 100, and may be, for example, the gate of a transistor or the source / drain of a transistor.

[0038] The first insulating film 111 can be disposed on the substrate 100. The first insulating film 111 can be disposed above the semiconductor chip region I and the scribing region II.

[0039] The first insulating film 111 may be a low-dielectric material whose dielectric constant is lower than that of the silicon oxide film. The first insulating film 111 may have a dielectric constant of about 1.0 to 3.0, and may comprise at least one of organic, inorganic, and organic-inorganic hybrid materials. Furthermore, the first insulating film 111 may be porous or non-porous. The first insulating film 111 may be formed from, for example, an impurity-doped oxide film-based material or an organic polymer having a low dielectric constant (low k).

[0040] For example, impurity-doped oxide film-based materials can be, for example, fluorine-doped oxide films (or FSG), carbon-doped oxide films, silicon oxide films, HSQ (hydrogen silsesquioxane; SiO:H), MSQ (methyl silsesquioxane; SiO:CH3), or a-SiOC (SiOC:H), etc. Organic polymers with low dielectric constants can be, for example, polyallyl ether resins, cyclic fluoropolymers, siloxane copolymers, fluorinated polyallyl ether resins, polypentafluorostyrene, polytetrafluorostyrene resins, fluorinated polynaphthalene fluorides, polyamide resins, etc.

[0041] In the accompanying drawings, the first insulating film 111 is shown as a single film, but the inventive concept is not limited thereto. For example, the first insulating film 111 may comprise vertically stacked insulating films and barrier films disposed between each of the vertically stacked insulating films. The barrier films may comprise, for example, insulating materials such as SiN, SiON, SiC, SiCN, SiOCH, SiOC, and SiOF.

[0042] The lower wiring structure 121 can be arranged in the first insulating film 111. The lower wiring structure 121 can be arranged in the semiconductor chip region I.

[0043] The lower wiring structure 121 can be electrically connected to the semiconductor chip wiring 105. The lower wiring structure 121 may include a lower wiring and a lower via. The lower via of the lower wiring structure 121 can be inserted between the lower wiring and the semiconductor chip wiring 105. In the figures, the sidewalls of the lower via are shown to have a vertical inclination, but the inventive concept is not limited thereto. For example, the sidewalls of the lower via can, of course, extend from the semiconductor chip wiring 105 to the lower wiring at any inclination.

[0044] The lower wiring structure 121 may include a conductive material.

[0045] The second insulating film 113 can be disposed on the first insulating film 111. The second insulating film 113 can be disposed above the semiconductor chip region I and the scribing region II.

[0046] The second insulating film 113 can be, for example, a high-density plasma (HDP) oxide film.

[0047] The upper wiring structure 122 can be arranged in the second insulating film 113. The upper wiring structure 122 can be arranged in the semiconductor chip region I.

[0048] The upper wiring structure 122 can electrically connect the redistribution layer 123 and the lower wiring structure 121. The upper wiring structure 122 may include upper wiring and upper vias. The upper via of the upper wiring structure 122 can be inserted between the upper wiring and the lower wiring structure 121. In the drawings, the sidewall of the upper via is shown to have a vertical inclination, but the inventive concept is not limited thereto. For example, the sidewall of the upper via can of course extend from the lower wiring structure 121 to the upper wiring at any inclination.

[0049] The upper wiring structure 122 may include a conductive material.

[0050] The insertion film 131 can be disposed on the second insulating film 113. The insertion film 131 can be disposed above the semiconductor chip region I and the scribing region II. The insertion film 131 can expose at least a portion of the upper wiring structure 122.

[0051] The insertion film 131 may include an insulating material that has etch selectivity relative to the second insulating film 113 and the third insulating film 115. The insertion film 131 may be, for example, a silicon nitride film or a silicon oxynitride film.

[0052] The third insulating film 115 can be disposed on the insertion film 131. The third insulating film 115 can be disposed above the semiconductor chip region I and the scribing region II. The third insulating film 115 can expose at least a portion of the upper wiring structure 122.

[0053] The third insulating film 115 may include a first surface 115_1, a second surface 115_2, a third surface 115_3, and a fourth surface 115_4. The first surface 115_1 and the second surface 115_2 of the third insulating film 115 may be opposite to each other. The third surface 115_3 of the third insulating film 115 may be connected to the first surface 115_1 and the second surface 115_2 of the third insulating film 115. The fourth surface 115_4 of the third insulating film 115 may be opposite to the third surface 115_3 of the third insulating film 115, and may be connected to the first surface 115_1 and the second surface 115_2 of the third insulating film 115.

[0054] For example, when the first surface 115_1 and the second surface 115_2 of the third insulating film 115 extend in the first direction, the third surface 115_3 and the fourth surface 115_4 of the third insulating film 115 can extend in the second direction. Here, the second direction can be a direction that intersects with the first direction.

[0055] Each of a portion of the first surface 115_1 and a portion of the third surface 115_3 of the third insulating film 115 may coincide with the cutting line SL. Each of the second surface 115_2 and the fourth surface 115_4 of the third insulating film 115 may be spaced apart from the cutting line SL.

[0056] Each of the first surface 115_1, the second surface 115_2, the third surface 115_3, and the fourth surface 115_4 of the third insulating film 115 can be located in the scribed region II.

[0057] The third insulating film 115 may include a first part 115a, a second part 115b, a third part 115c, a fourth part 115d, a fifth part 115e, a sixth part 115f, and a seventh part 115g.

[0058] The first surface 115_1 of the third insulating film 115 may be defined by the first portion 115a and the second portion 115b of the third insulating film 115.

[0059] The first portion 115a of the third insulating film 115 may be located in the scribing region II. The first portion 115a of the third insulating film 115 may protrude from the passivation film 117. For example, the first portion 115a of the third insulating film 115 may protrude from the first distal end 117_1 of the passivation film 117. The first portion 115a of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. Here, the vertical direction may be a direction perpendicular to the upper surface of the substrate 100. The first portion 115a of the third insulating film 115 may be exposed through the passivation film 117.

[0060] The first portion 115a of the third insulating film 115 may have a first width W1. The first width W1 may be, for example, the distance between the first distal end 117_1 of the passivation film 117 and the first surface 115_1 of the third insulating film 115.

[0061] The second portion 115b of the third insulating film 115 may be located in the scribed region II. The second portion 115b of the third insulating film 115 may protrude from the passivation film 117. For example, the second portion 115b of the third insulating film 115 may protrude from the first distal end 117_1 of the passivation film 117. The second portion 115b of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. The second portion 115b of the third insulating film 115 may be exposed through the passivation film 117.

[0062] The second portion 115b of the third insulating film 115 may have a second width W2. The second width W2 may be, for example, the distance between the first distal end 117_1 of the passivation film 117 and the first surface 115_1 of the third insulating film 115.

[0063] The second surface 115_2 of the third insulating film 115 may be defined by the third portion 115c of the third insulating film 115.

[0064] The third portion 115c of the third insulating film 115 may be located in the scribed region II. The third portion 115c of the third insulating film 115 may protrude from the passivation film 117. For example, the third portion 115c of the third insulating film 115 may protrude from the second distal end 117_2 of the passivation film 117. The third portion 115c of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. The third portion 115c of the third insulating film 115 may be exposed through the passivation film 117.

[0065] The third portion 115c of the third insulating film 115 may have a third width W3. The third width W3 may be, for example, the distance between the second distal end 117_2 of the passivation film 117 and the second surface 115_2 of the third insulating film 115.

[0066] The third surface 115_3 of the third insulating film 115 may be defined by the fourth portion 115d and the fifth portion 115e of the third insulating film 115.

[0067] The fourth portion 115d of the third insulating film 115 may be located within the scribed region II. The fourth portion 115d of the third insulating film 115 may protrude from the passivation film 117. For example, the fourth portion 115d of the third insulating film 115 may protrude from the third distal end 117_3 of the passivation film 117. The fourth portion 115d of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. The fourth portion 115d of the third insulating film 115 may be exposed through the passivation film 117.

[0068] The fourth portion 115d of the third insulating film 115 may have a fourth width W4. The fourth width W4 may be, for example, the distance between the third distal end 117_3 of the passivation film 117 and the third surface 115_3 of the third insulating film 115.

[0069] The fifth portion 115e of the third insulating film 115 may be located within the scribed region II. The fifth portion 115e of the third insulating film 115 may protrude from the passivation film 117. For example, the fifth portion 115e of the third insulating film 115 may protrude from the third distal end 117_3 of the passivation film 117. The fifth portion 115e of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. The fifth portion 115e of the third insulating film 115 may be exposed through the passivation film 117.

[0070] The fifth portion 115e of the third insulating film 115 may have a fifth width W5. The fifth width W5 may be, for example, the distance between the third distal end 117_3 of the passivation film 117 and the third surface 115_3 of the third insulating film 115.

[0071] The fourth surface 115_4 of the third insulating film 115 may be defined by the sixth portion 115f of the third insulating film 115.

[0072] The sixth portion 115f of the third insulating film 115 may be located within the scribed region II. The sixth portion 115f of the third insulating film 115 may protrude from the passivation film 117. For example, the sixth portion 115f of the third insulating film 115 may protrude from the fourth distal end 117_4 of the passivation film 117. The sixth portion 115f of the third insulating film 115 may be a portion that does not overlap with the passivation film 117 in the vertical direction. The sixth portion 115f of the third insulating film 115 may be exposed through the passivation film 117.

[0073] The sixth portion 115f of the third insulating film 115 may have a sixth width W6. The sixth width W6 may be, for example, the distance between the fourth distal end 117_4 of the passivation film 117 and the fourth surface 115_4 of the third insulating film 115.

[0074] The seventh portion 115g of the third insulating film 115 can be disposed above the semiconductor chip region I and the scribing region II. The seventh portion 115g of the third insulating film 115 can be a portion that vertically overlaps with the passivation film 117.

[0075] The first width W1 can be greater than the second width W2. The first width W1 can be greater than the third width W3. The second width W2 and the third width W3 can be the same as or different from each other.

[0076] The fourth width W4 can be greater than the fifth width W5. The fourth width W4 can be greater than the sixth width W6. The fifth width W5 and the sixth width W6 can be the same or different from each other.

[0077] The first width W1 can be greater than the fifth width W5 and the sixth width W6. The fourth width W4 can be greater than the second width W2 and the third width W3. The first width W1 and the fourth width W4 can be the same as or different from each other.

[0078] The third insulating film 115 may include an insulating material different from the insulating material of the second insulating film 113. For example, the third insulating film 115 may include TEOS (tetraethyl orthosilicate).

[0079] The opening OP can be formed in the scribing region II. The opening OP can be formed on the second surface 115_2 and the fourth surface 115_4 of the third insulating film 115. The opening OP can expose the substrate 100. For example, the opening OP can expose the insulating material disposed on the uppermost surface of the substrate 100.

[0080] At least a portion of the sidewall of the opening portion OP may be defined by the second surface 115_2 of the third insulating film 115, the fourth surface 115_4 of the third insulating film 115, the insertion film 131, the second insulating film 113, and the first insulating film 111. The bottom surface of the opening portion OP may be defined by the substrate 100.

[0081] In the accompanying drawings, the sidewalls of the opening portion OP are shown to have an inclination perpendicular to the substrate 100, but the inventive concept is not limited thereto. For example, the sidewalls of the opening portion OP may of course have any inclination relative to the substrate 100.

[0082] The opening portion OP may not be formed on the first surface 115_1 and the third surface 115_3 of the third insulating film 115. In other words, the substrate 100 may not be exposed on the first surface 115_1 and the third surface 115_3 side of the third insulating film 115.

[0083] The first alignment key 201 may be disposed on the first surface 115_1 of the third insulating film 115. For example, the first alignment key 201 may be disposed side by side with the second portion 115b of the third insulating film 115. The first alignment key 201 may be disposed on the insertion film 131. The first alignment key 201 may be exposed by the passivation film 117. At least one surface of the first alignment key 201 may be surrounded by the first portion 115a and the second portion 115b of the third insulating film 115.

[0084] The sum of the second width W2 and the width WA1 of the first alignment key 201 can be basically the same as the first width W1.

[0085] The first alignment key 201 may include a first surface and a second surface opposite to each other. The first surface of the first alignment key 201 may be closer to the second portion 115b of the third insulating film 115 than the second surface of the first alignment key 201. For example, the first surface of the first alignment key 201 may be in direct contact with the second portion 115b of the third insulating film 115.

[0086] A portion of the first surface 115_1 of the third insulating film 115 and the second surface of the first alignment key 201 may coincide with the cutting line SL. Here, a portion of the first surface 115_1 of the third insulating film 115 may be the portion defining the first portion 115a of the third insulating film 115.

[0087] The second alignment key 202 can be disposed on the third surface 115_3 of the third insulating film 115. For example, the second alignment key 202 can be disposed side by side with the fifth portion 115e of the third insulating film 115. The second alignment key 202 can be disposed on the insertion film 131. The second alignment key 202 can be exposed by the passivation film 117. At least one surface of the second alignment key 202 can be surrounded by the fourth portion 115d and the fifth portion 115e of the third insulating film 115.

[0088] The sum of the fifth width W5 and the width WA2 of the second alignment key 202 can be basically the same as the fourth width W4.

[0089] The second alignment key 202 may include a first surface and a second surface opposite to each other. The first surface of the second alignment key 202 may be closer to the fifth portion 115e of the third insulating film 115 than the second surface of the second alignment key 202. For example, the first surface of the second alignment key 202 may be in direct contact with the fifth portion 115e of the third insulating film 115.

[0090] A portion of the third surface 115_3 of the third insulating film 115 and the second surface of the second alignment key 202 may coincide with the cutting line SL. Here, a portion of the third surface 115_3 of the third insulating film 115 may be the portion defining the fourth portion 115d of the third insulating film 115.

[0091] The third alignment key 203 can be disposed on the second surface 115_2 of the third insulating film 115. For example, the third alignment key 203 can be disposed side by side with the third portion 115c of the third insulating film 115. The third alignment key 203 can be disposed on the insertion film 131. The third alignment key 203 can be exposed by the passivation film 117.

[0092] The third alignment key 203 may include a first surface and a second surface facing each other. The first surface of the third alignment key 203 may be closer to the third portion 115c of the third insulating film 115 than the second surface of the third alignment key 203. For example, the first surface of the third alignment key 203 may be in direct contact with the third portion 115c of the third insulating film 115.

[0093] The second surface of the third alignment key 203 can coincide with the cutting line SL.

[0094] The fourth alignment key 204 can be disposed on the fourth surface 115_4 of the third insulating film 115. For example, the fourth alignment key 204 can be disposed side by side with the sixth portion 115f of the third insulating film 115. The fourth alignment key 204 can be disposed on the insertion film 131. The fourth alignment key 204 can be exposed by the passivation film 117.

[0095] The fourth alignment key 204 may include a first surface and a second surface facing each other. The first surface of the fourth alignment key 204 may be closer to the sixth portion 115f of the third insulating film 115 than the second surface of the fourth alignment key 204. For example, the first surface of the fourth alignment key 204 may be in direct contact with the sixth portion 115f of the third insulating film 115.

[0096] The second surface of the fourth alignment key 204 can coincide with the cutting line SL.

[0097] The redistribution layer 123 can be disposed in semiconductor chip region I. A portion of the redistribution layer 123 can extend into the seventh portion 115g of the third insulating film 115 and the insertion film 131. The remaining portion of the redistribution layer 123 can be disposed on the seventh portion 115g of the third insulating film 115. The redistribution layer 123 can be electrically connected to the upper wiring structure 122. The redistribution layer 123 can be disposed between the upper wiring structure 122 and the connection terminal 101.

[0098] In this figure, it is assumed that the sidewalls of the seventh portion 115g of the redistribution layer 123 extending into the third insulating film 115 and the portion inserted into the insertion film 131 have a vertical inclination, but the concept of the invention is not limited to this. For example, the sidewalls of the seventh portion 115g of the redistribution layer 123 extending into the third insulating film 115 and the portion inserted into the insertion film 131 can, of course, extend from the upper wiring structure 122 to the passivation film 117 with any inclination.

[0099] The redistribution layer 123 may include at least one metal or metal alloy selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (in), zinc (Zn), and carbon (C).

[0100] The protective film 133 may be disposed above the semiconductor chip region I and the scribing region II. The protective film 133 may be disposed on the seventh portion 115g of the third insulating film 115 and the redistribution layer 123. The protective film 133 may not extend to, for example, the first portion 115a, second portion 115b, third portion 115c, fourth portion 115d, fifth portion 115e, and sixth portion 115f of the third insulating film 115. For example, the protective film 133 may expose the first portion 115a, second portion 115b, third portion 115c, fourth portion 115d, fifth portion 115e, and sixth portion 115f of the third insulating film 115. The protective film 133 may expose a portion of the redistribution layer 123.

[0101] The protective film 133 can be, for example, a silicon nitride film or a silicon oxynitride film.

[0102] Passivation film 117 can be disposed above semiconductor chip region I and scribing region II. Passivation film 117 can be disposed on protective film 133. Passivation film 117 can be disposed on the seventh portion 115g of third insulating film 115. Passivation film 117 may not be disposed on the first portion 115a, second portion 115b, third portion 115c, fourth portion 115d, fifth portion 115e, and sixth portion 115f of third insulating film 115.

[0103] For example, the passivation film 117 may not vertically overlap with the first portion 115a, the second portion 115b, the third portion 115c, the fourth portion 115d, the fifth portion 115e, and the sixth portion 115f of the third insulating film 115. The passivation film 117 may expose the first portion 115a, the second portion 115b, the third portion 115c, the fourth portion 115d, the fifth portion 115e, and the sixth portion 115f of the third insulating film 115.

[0104] The passivation film 117 may include a first distal end 117_1, a second distal end 117_2, a third distal end 117_3, and a fourth distal end 117_4. The first distal end 117_1 and the second distal end 117_2 of the passivation film 117 may be opposite to each other. The third distal end 117_3 of the passivation film 117 may connect the first distal end 117_1 and the second distal end 117_2 to each other. The fourth distal end 117_4 of the passivation film 117 may be opposite to the third distal end 117_3 and connect the first distal end 117_1 and the second distal end 117_2.

[0105] The first distal end 117_1 of the passivation film 117 may be located at, for example, the boundary between the seventh portion 115g and the first portion 115a of the third insulating film 115. Furthermore, the first distal end 117_1 of the passivation film 117 may be located at, for example, the boundary between the seventh portion 115g and the second portion 115b of the third insulating film 115.

[0106] The second distal end 117_2 of the passivation film 117 may be located at the boundary between, for example, the seventh portion 115g and the third portion 115c of the third insulating film 115.

[0107] The third distal end 117_3 of the passivation film 117 may be located at, for example, the boundary between the seventh portion 115g and the fourth portion 115d of the third insulating film 115. Furthermore, the third distal end 117_3 of the passivation film 117 may be located at, for example, the boundary between the seventh portion 115g and the fifth portion 115e of the third insulating film 115.

[0108] The fourth distal end 117_4 of the passivation film 117 may be located at the boundary between, for example, the seventh portion 115g and the sixth portion 115f of the third insulating film 115.

[0109] In the accompanying drawings, the first distal end 117_1, the second distal end 117_2, the third distal end 117_3, and the fourth distal end 117_4 of the passivation film 117 are shown having an inclination perpendicular to the upper surface of the third insulating film 115, but the inventive concept is not limited thereto. For example, the first distal end 117_1, the second distal end 117_2, the third distal end 117_3, and the fourth distal end 117_4 of the passivation film 117 can of course have any inclination relative to the upper surface of the third insulating film 115.

[0110] The passivation film 117 may include a polyimide-based material, such as photosensitive polyimide (PSPI).

[0111] The connection terminal 101 can be disposed, for example, in semiconductor chip region I. A portion of the connection terminal 101 can penetrate the passivation film 117 and the protective film 133 and extend into the redistribution layer 123. For example, the connection terminal 101 can protrude from the upper surface of the passivation film 117.

[0112] Semiconductor chip wiring 105 can be electrically connected to the semiconductor packaging substrate via connection terminal 101. Figure 8 (of 1200).

[0113] In a semiconductor device according to some embodiments, the opening portion OP is formed only on the second surface 115_2 and the fourth surface 115_4 of the third insulating film 115, and the opening portion OP is not formed on the first surface 115_1 and the third surface 115_3 of the third insulating film 115. Therefore, the portion where stress applied to the substrate 100 is concentrated during the dicing process of the substrate 100 can be aligned with the dicing line SL. For example, in order to form a semiconductor device 1100 by dicing the substrate 100, stress can be applied to the dicing line SL. At this time, for example, since the dicing line SL aligns with a portion of the first surface 115_1 of the third insulating film 115 and the second surface of the first alignment bond 201, and at least one surface of the alignment bond 201 is surrounded by the first portion 115a and the second portion 115b of the third insulating film 115, the peeling phenomenon of the first alignment bond 201 can be reduced. Therefore, the yield of the semiconductor device can be increased.

[0114] In the following text, reference will be made to Figure 8 A semiconductor package 1000 is described according to some embodiments. For clarity, repeated descriptions will be simplified or omitted.

[0115] Figure 8 It shows that Figure 1 and Figure 2 The semiconductor device formed after the substrate 100 is cut along the dicing line SL. Figure 3 A diagram of a semiconductor package 1000 according to some embodiments, after the package 1100 is mounted on a semiconductor package substrate 1200. For clarity, Figure 8 Molding materials are not shown.

[0116] Reference Figure 8 According to some embodiments, the semiconductor package 1000 may include a semiconductor package substrate 1200 and a semiconductor device 1100.

[0117] The semiconductor packaging substrate 1200 may be a packaging substrate, and may be, for example, a printed circuit board (PCB) or a ceramic substrate. The semiconductor packaging substrate 1200 may include a first surface 1200a and a second surface 1200b. The first surface 1200a and the second surface 1200b of the semiconductor packaging substrate 1200 may be opposite to each other. The semiconductor device 1100 may be mounted on the first surface 1200a of the semiconductor packaging substrate 1200. An external connection terminal 1210 may be attached to the second surface 1200b of the semiconductor packaging substrate 1200.

[0118] Here, semiconductor device 1100 can be a reference. Figures 1 to 7 The semiconductor device 1100 is described. The semiconductor device 1100 may be mounted on the semiconductor packaging substrate 1200 in, for example, flip-chip form, but is not limited thereto. For example, the semiconductor device 1100 may of course be mounted on the semiconductor packaging substrate 1200 in a suitable form as needed.

[0119] The semiconductor packaging substrate 1200 and the semiconductor device 1100 can be electrically connected to each other via a connection terminal 101. The connection terminal 101 can be inserted between the first surface 1200a of the semiconductor packaging substrate 1200 and the semiconductor device 1100.

[0120] External connection terminal 1210 can electrically connect semiconductor package 1000 to external devices.

[0121] The connecting terminal 101 and the external connecting terminal 1210 can be conductive balls or solder balls, but the inventive concept is not limited thereto. The connecting terminal 101 and the external connecting terminal 1210 can be, for example, a conductive bump, a conductive spacer, and a pin grid array (PGA).

[0122] External connection terminal 1210 and connection terminal 101 can be electrically connected to each other via first pad 1213, connection wiring 1215 and second pad 1217.

[0123] A first pad 1213 may be disposed on a second surface 1200b of the semiconductor package substrate 1200. A second pad 1217 may be disposed on a first surface 1200a of the semiconductor package substrate 1200. Although the upper surface of the first pad 1213 is shown to be in the same plane as the second surface 1200b of the semiconductor package substrate 1200, the inventive concept is not limited thereto. Similarly, although the upper surface of the second pad 1217 is shown to be in the same plane as the first surface 1200a of the semiconductor package substrate 1200, the inventive concept is not limited thereto. For example, at least a portion of at least one of the first pad 1213 and the second pad 1217 may protrude from each surface of the semiconductor package substrate 1200.

[0124] The first pad 1213 and the second pad 1217 can be electrically connected to each other via the connecting wire 1215.

[0125] The first pad 1213, the second pad 1217, and the connection wiring 1215 may include conductive material.

[0126] In the following text, reference will be made to Figures 9 to 15 Methods for manufacturing a semiconductor device according to some embodiments are described. For clarity, repeated descriptions will be simplified or omitted.

[0127] Figure 9 This is a diagram showing a substrate 100 on which semiconductor devices according to some embodiments are integrated. Figures 10 to 14 This is an intermediate process diagram used to illustrate a method of manufacturing a semiconductor device according to some embodiments. Figures 10 to 14 It is along Figure 9 The sectional views taken from lines E-E', F-F', G-G', and H-H'.

[0128] Reference Figure 9 and Figure 10 A substrate 100 on which semiconductor chip wiring 105 is formed can be provided. Furthermore, a first insulating film 111, a second insulating film 113, an insertion film 131, and a third insulating film 115 can be sequentially stacked on the substrate 100. The first insulating film 111, the second insulating film 113, the insertion film 131, and the third insulating film 115 can be formed above the semiconductor chip region I and the scribing region II.

[0129] The lower wiring structure 121 can be formed in the first insulating film 111. The upper wiring structure 122 can be formed in the second insulating film 113. The lower wiring structure 121 and the upper wiring structure 122 can be formed in the semiconductor chip region I.

[0130] The first alignment key 201 can be formed on the third insulating film 115. The first alignment key 201 can be formed in the scribing region II.

[0131] Reference Figure 11 A first trench T1 can be formed in the semiconductor chip region I. For example, a portion of the third insulating film 115 and a portion of the insertion film 131 formed in the semiconductor chip region I can be removed. The upper wiring structure 122 can be exposed through the first trench T1.

[0132] Reference Figure 12 It can form a redistribution layer 123 and a protective film 133.

[0133] The redistribution layer 123 can be formed to fill the first trench T1. Furthermore, the redistribution layer 123 can also be formed on the upper surface of the third insulating film 115. The redistribution layer 123 can be formed in the semiconductor chip region I.

[0134] A protective film 133 may be formed on the third insulating film 115 to cover the redistribution layer 123. The protective film 133 may be formed over semiconductor chip region I and scribing region II.

[0135] Reference Figure 13 The opening portion OP can be formed in the scribing area II.

[0136] The opening portion OP can be formed by removing a portion of the protective film 133, a portion of the third insulating film 115, a portion of the insertion film 131, a portion of the second insulating film 113, and a portion of the first insulating film 111 formed in the scribing area II.

[0137] When the opening portion OP is formed, the first surface 115_1 of the third insulating film 115 can coincide with the cutting line SL. Furthermore, the second surface 115_2 of the third insulating film 115 can be spaced apart from the cutting line SL.

[0138] The opening portion OP can be formed on one side of the cutting line SL.

[0139] Reference Figure 14 The passivation film 117 can be formed on the protective film 133.

[0140] Since the first distal end 117_1 of the passivation film 117 is separated by a first width W1 from the cutting line SL that coincides with the first surface 115_1 of the third insulating film 115, a first portion 115a of the third insulating film 115 can be defined. Since the first distal end 117_1 of the passivation film 117 is separated by a second width W2 from the first alignment key 201, a second portion 115b of the third insulating film 115 can be defined.

[0141] Since the second distal end 117_2 of the passivation film 117 is separated from the second surface 115_2 of the third insulating film 115 by a third width W3, the third portion 115c of the third insulating film 115 can be defined.

[0142] The passivation film 117 can be formed to expose the first alignment bond 201.

[0143] The protective film 133 on the first part 115a of the third insulating film 115, the second part 115b of the third insulating film 115, the third part 115c of the third insulating film 115, and the alignment key 201 can be removed.

[0144] A portion of the passivation film 117, a portion of the protective film 133, and a portion of the redistribution layer 123 formed in the semiconductor chip region I can be removed to form a second trench T2. The second trench T2 is formed in the passivation film 117 and the protective film 133 formed in the semiconductor chip region I, and can extend into a portion of the redistribution layer 123.

[0145] The second groove T2 can accommodate the connection terminal in subsequent processes. Figures 4 to 7 (101 in the middle).

[0146] Figure 15 It was executed until Figure 14 The manufacturing process of semiconductor devices after Figure 9 A magnified view of region J.

[0147] Reference Figure 15 The opening portion OP can be formed on the second surface 115_2 and the fourth surface 115_4 of the third insulating film 115. The opening portion OP may not be formed on the first surface 115_1 and the third surface 115_3 of the third insulating film 115. The opening portion OP can expose the third alignment bond 203 and the fourth alignment bond 204. The opening portion OP can expose the substrate 100.

[0148] The substrate 100 is cut along the cutting line SL, and a reference can be formed. Figures 3 to 7 The semiconductor device 1100 is described.

[0149] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, it is intended that the embodiments be considered illustrative rather than restrictive in all respects, and that the scope of the invention be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A semiconductor device, comprising: A substrate comprising a semiconductor chip region and a scribing region surrounding the semiconductor chip region; An insulating film is disposed on the substrate above the semiconductor chip region and the scribing region, and includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface. as well as An opening is formed on the second surface and the fourth surface of the insulating film to expose the substrate. The opening portion is formed in the scribed area, and Wherein, the first surface and the third surface of the insulating film do not include openings that expose the substrate.

2. The semiconductor device according to claim 1, further comprising a passivation film disposed on the insulating film and arranged above the semiconductor chip region and the scribing region. in, The first surface of the insulating film is defined by a first portion and a second portion of the insulating film, the first portion of the insulating film being located in the scribing region, protruding from the passivation film and having a first width, and the second portion of the insulating film being located in the scribing region, protruding from the passivation film and having a second width less than the first width. The second surface of the insulating film is defined by a third portion of the insulating film, which is located in the scribed region, protrudes from the passivation film, and has a third width smaller than the first width.

3. The semiconductor device according to claim 2, wherein, The third surface of the insulating film is defined by a fourth portion and a fifth portion of the insulating film. The fourth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fourth width. The fifth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fifth width smaller than the fourth width. The fourth surface of the insulating film is defined by a sixth portion of the insulating film, which is located in the scribed region, protrudes from the passivation film, and has a sixth width smaller than the fourth width.

4. The semiconductor device according to claim 3, wherein, The third width is smaller than the fourth width, and the sixth width is smaller than the first width.

5. The semiconductor device according to claim 3, further comprising: A first alignment key is disposed on the first surface of the insulating film; and A second alignment key is disposed on the third surface of the insulating film. Wherein, the sum of the second width and the width of the first alignment key is the same as the first width, and The sum of the fifth width and the width of the second alignment key is the same as the fourth width.

6. The semiconductor device of claim 2, further comprising alignment keys disposed on the first surface of the insulating film. in, The sum of the second width and the width of the alignment key is the same as the first width.

7. A semiconductor device, comprising: A substrate comprising a semiconductor chip region and a scribing region surrounding the semiconductor chip region; An insulating film is disposed on the substrate above the semiconductor chip region and the scribing region, and includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface. as well as A passivation film is disposed on the insulating film and arranged above the semiconductor chip region and the scribing region. Wherein, the first surface of the insulating film is defined by a first portion and a second portion of the insulating film, the first portion of the insulating film being located in the scribing region, protruding from the passivation film and having a first width, and the second portion of the insulating film being located in the scribing region, protruding from the passivation film and having a second width less than the first width, and The second surface of the insulating film is defined by a third portion of the insulating film, which is located in the scribed region, protrudes from the passivation film, and has a third width smaller than the first width.

8. The semiconductor device of claim 7, further comprising an opening formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate.

9. The semiconductor device of claim 8, wherein the opening portion is formed in the scribed region, and in, The first surface and the third surface of the insulating film do not include openings that expose the substrate.

10. The semiconductor device according to claim 7, wherein, The third surface of the insulating film is defined by a fourth portion and a fifth portion of the insulating film. The fourth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fourth width. The fifth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fifth width smaller than the fourth width. The fourth surface of the insulating film is defined by a sixth portion of the insulating film, which is located in the scribed region, protrudes from the passivation film, and has a sixth width smaller than the fourth width.

11. The semiconductor device of claim 10, wherein the third width is smaller than the fourth width, and the sixth width is smaller than the first width.

12. The semiconductor device of claim 10, further comprising: A first alignment key is disposed on the first surface of the insulating film; and A second alignment key is disposed on the third surface of the insulating film. Wherein, the sum of the second width and the width of the first alignment key is the same as the first width, and The sum of the fifth width and the width of the second alignment key is the same as the fourth width.

13. The semiconductor device according to claim 7, wherein, The first surface, the second surface, the third surface, and the fourth surface of the insulating film are located in the scribed area.

14. The semiconductor device of claim 7, further comprising alignment keys disposed on the first surface of the insulating film. in, The sum of the second width and the width of the alignment key is the same as the first width.

15. The semiconductor device of claim 7, further comprising a redistribution layer, the redistribution layer being disposed at least partially in the insulating film.

16. A semiconductor device, comprising: A substrate having four side surfaces; A semiconductor chip formed on the upper surface of the substrate; as well as An insulating film surrounds the semiconductor chip and has four side surfaces. In the plan view of the semiconductor device, only two of the four side surfaces of the insulating film expose the upper surface of the substrate, and the other two side surfaces of the insulating film are respectively connected to two of the four side surfaces of the substrate on the same plane. The other two side surfaces of the insulating film are connected to each other.

17. The semiconductor device of claim 16, further comprising a passivation film formed on the insulating film and the semiconductor chip. in, In the plan view of the semiconductor device, the area of ​​the passivation film is smaller than the area of ​​the insulating film.

18. A semiconductor package, comprising: Semiconductor packaging substrate; and The semiconductor device of claim 7 is mounted on the semiconductor packaging substrate.

19. The semiconductor package of claim 18, wherein the third surface of the insulating film is defined by a fourth portion and a fifth portion of the insulating film: The fourth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fourth width; and The fifth portion of the insulating film is located in the scribed region, protrudes from the passivation film, and has a fifth width smaller than the fourth width. in, The fourth surface of the insulating film is defined by a sixth portion of the insulating film, which is located in the scribed region, protrudes from the passivation film, and has a sixth width smaller than the fourth width.

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