Improved amplifier and method for amplifying an input signal

Abstract

An amplifier and a method for amplifying an input signal are disclosed. A multi-stage device includes a plurality of stages, such as a first stage and a second stage. During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and generate an output signal. According to one configuration, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. The transistor component is controlled to obtain an output signal from the intermediate signal input to the circuit path.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular to an amplifier. Background Art

[0002] A conventional low noise amplifier (LNA) is an electronic amplifier that amplifies a very low voltage input signal to an output signal without significantly reducing its signal-to-noise ratio. As a specific example, depending on the corresponding gain setting, the amplifier circuit preferably produces a higher amplitude replica of the input signal with limited noise amplification.

[0003] Conventional LNA circuits used in mobile communication devices typically support a so-called "linearity on demand" feature, which requires the implementation of different gain step modes. One of these modes is the so-called "high gain mode", which uses the maximum allowable current to achieve the best gain and noise figure performance from input to output. Proper operation and performance of a communication device often depends on the ability of the amplifier circuit to provide appropriate gain.

[0004] Figure 1 is based on a 1.8 volt DC power supply (e.g. V DD ) is an example diagram of a conventional amplifier circuit that operates with an input voltage Vout. Typically, during operation, the input stage 110 of the amplifier 100 generates a signal 120. The output stage 130 receives the signal 120 as an input from the input stage 110 and generates an output signal Vout. The output voltage Vout is an amplified rendition of the input voltage Vin. Summary of the invention

[0005] Figure 1 One disadvantage of conventional amplifiers in the embodiment of the present invention is the voltage divider, i.e., the combination of capacitor C1 and capacitor C2 in output stage 130. For example, typically, the output voltage Vout = Vtank*[C1 / (C1+C2)]; where Vtank = the voltage at node 118. The high gain performance (~18 dB) of amplifier 100 (e.g., a single cascode amplifier) ​​is primarily achieved by the capacitive voltage divider C1 and C2 in output stage 130 (tank circuit) to achieve a good output match (transformation from 200 ohms to 50 ohms). This transformation has a significant disadvantage because 25% to 50% of the voltage gain may be lost.

[0006] Furthermore, the output stage 130 of the amplifier 100 is adjusted by selecting appropriate values ​​of C1 and C2. Unfortunately, the conventional output stage 130 of the amplifier 100 can only provide appropriate impedance matching within a very narrow frequency range, such as 20 MHz. This is very limiting because the amplifier 100 cannot be used in broadband applications.

[0007] It is also noted that in industry it is common to operate circuits at lower supply voltages. For example, in the near future it is expected that amplifiers will operate based on 1.2 VDC instead of 1.8 VDC. The lower voltage makes it even more difficult to achieve high gain from the amplifier.

[0008] Therefore, there are challenges associated with implementing conventional amplifier circuits at lower voltages, such as 1.2 VDC. For example, as previously discussed, operating conventional amplifiers at such low voltages can result in degraded RF performance, negatively impacting parameters such as gain, noise figure, linearity, etc. of the corresponding amplifier. Furthermore, as previously discussed, the present disclosure includes the observation that conventional CMOS LNA implementations achieve only narrowband output matching, thereby preventing such devices from being used in wideband applications.

[0009] In contrast to conventional approaches, embodiments herein include novel methods that provide improved performance of multi-stage devices.

[0010] For example, according to one embodiment, a multi-stage device includes multiple stages, such as a first stage and a second stage. Typically, the stages of the multi-stage device take the form of circuits. However, such resources may be instantiated in any suitable manner.

[0011] During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and generate an output signal. In an exemplary embodiment, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. In one embodiment, the operation of the transistor derives the output signal from the intermediate signal input to the circuit path.

[0012] If necessary, a combination of the bias voltage and / or the intermediate signal through the capacitor is applied to the gate of the transistor to control the operation of the transistor and the generation of the output signal.

[0013] According to a further embodiment, the gate of the transistor is controlled primarily via application of a DC bias voltage and a DC current (which flows through the transistor).

[0014] In one embodiment, the intermediate signal is a radio frequency signal (AC signal) that changes the voltage input to the gate node of the transistor.

[0015] According to another embodiment, at least a portion of the current associated with the intermediate signal and input to the circuit path flows through the transistor to obtain the output signal.

[0016] In one embodiment, the multi-stage device as described herein is an amplifier. In such a case, the output signal is an amplified reproduction of the input signal. The overall gain of the multi-stage device is represented by dividing the amplitude of the output signal by the amplitude of the input signal. In one embodiment, the intermediate signal is an amplified reproduction of the input signal. The output signal is an amplified reproduction of the intermediate signal. In one embodiment, the amplification or gain of the output signal relative to the intermediate signal is zero or quite small. In such a case, the input stage provides amplification of the input signal. The output stage acts as a buffer.

[0017] According to other embodiments, a circuit path (or dual circuit paths) in a multi-stage device couples a node of a first stage generating an intermediate signal to one or both of an input terminal (e.g., a gate node) and an output terminal (e.g., a source node) of a transistor.

[0018] According to other embodiments, an intermediate signal generated by the first stage and input to the circuit path controls the operation of the transistor and the corresponding current flow through the circuit path. Such current control generates an output signal from the second stage.

[0019] In one embodiment, the second stage of the multi-stage device is operable to use (or reuse) the current associated with the intermediate signal output from the first stage to generate an output signal. As further discussed herein, using or reusing the current from the first stage to generate the output signal from the second stage reduces the power consumption of the multi-stage circuit.

[0020] Additional embodiments herein include a circuit path, such as a capacitor, coupling a node of a first stage that outputs an intermediate signal to a gate node of a transistor.

[0021] Note that the gate node of the transistor may also be biased via the input of a bias voltage through a resistor to the gate of the transistor, if desired.

[0022] According to other embodiments, the first stage includes a transistor operable to control the amount of current associated with the intermediate signal output to the second stage. In one embodiment, as discussed further below, the current amplitude provided by the intermediate signal controls the gain associated with the multi-stage circuit.

[0023] The multi-stage circuit may include any number of passive components, such as resistors, capacitors, and / or inductors. For example, in one embodiment, the second stage includes a first passive circuit component and a second passive circuit component, which are arranged in series between a node of the first stage that generates the intermediate signal and a node (e.g., a source node) of a transistor in the second stage. The output signal of the multi-stage device is obtained from a circuit node that couples the first passive circuit component to the second passive circuit component.

[0024] As discussed above, the multi-stage circuit includes any number of circuit paths to provide connectivity between the node of the stage generating the intermediate signal and one or more nodes of the transistor. In one embodiment, the circuit path as described herein is a first circuit path from the node of the first stage to the gate node of the transistor. The multi-stage circuit can be configured to also include a second circuit path between the node of the first stage generating the intermediate signal and the source node of the transistor.

[0025] In one embodiment, the first circuit path includes a capacitor coupling a node of the first stage outputting the intermediate signal to a gate node of the transistor.

[0026] According to further embodiments, the second stage is implemented as a common drain circuit.With the new common drain output buffer stage as described herein, the second stage can be used to achieve higher gain and wideband output matching.

[0027] Furthermore, as discussed previously, in one embodiment, the multi-stage device is an amplifier circuit for any suitable application. For example, in one non-limiting example embodiment, a device (e.g., a communication device) includes one or more versions of a multi-stage device as described herein. In one embodiment, the device includes an antenna for receiving a wireless signal. The antenna converts the wireless signal into an input signal that is input to a first stage of the multi-stage device. The multi-stage device amplifies the input signal into an output signal in the manner described herein.

[0028] According to other embodiments, the impedance of the second stage is matched (or substantially matched) to the impedance of the first stage. In one embodiment, the impedance of the second stage is substantially matched to the impedance of the first stage over a broadband frequency range, such as between 1 GHz and 3 GHz or any other frequency range.

[0029] Other embodiments herein include implementing the second stage of the multi-stage device as a common drain amplifier circuit to amplify an input signal into an output signal.

[0030] Embodiments herein also include methods of receiving an input signal and generating an output signal. For example, in one embodiment, the method includes: receiving an input signal; generating an intermediate signal from the input signal; outputting the intermediate signal to a transistor through a first circuit path; and controlling the operation of the transistor to obtain the output signal from the intermediate signal. In one embodiment, as discussed above, the method includes generating the output signal as an amplified reproduction of the input signal.

[0031] According to one embodiment, the control operation of the transistor includes controlling an input node (eg, a gate node) of the transistor using an intermediate signal as input (eg, via a capacitor) and a corresponding current flow through the transistor to generate an output signal.

[0032] According to other embodiments, outputting the intermediate signal includes: outputting the intermediate signal to a first circuit component of the second stage, a second circuit component and the first component being arranged in series between nodes of the first stage generating an intermediate signal input to a node (e.g., a source node) of the transistor. Other embodiments herein include outputting the output signal through a circuit path, for example, from a third circuit component, the third circuit component being coupled to a circuit node that couples the first circuit component to the second circuit component.

[0033] Other embodiments herein include inputting an intermediate signal generated by the first stage on a circuit path coupled to an input node (e.g., a gate node) of the transistor. If desired, the method may further include inputting an intermediate signal generated by the first stage through a first circuit path coupled to an output node (e.g., a source node) of the transistor.

[0034] According to other embodiments, to reduce power consumption, a method as described herein may include generating the output signal using a current associated with the intermediate signal output from the first stage.

[0035] According to yet another embodiment, the method is implemented in a wireless device. In this case, the method further comprises: receiving a wireless signal at an antenna; and generating an input signal input to the first stage based on the received wireless signal.

[0036] Note that other embodiments herein include improved multi-stage amplifier devices and methods to improve the "high gain mode" performance of LNA circuits with matched impedances. In one embodiment, the matching inductor components in the multi-stage device require very high quality factors to have less impact on the LNA key parameter noise figure.

[0037] These and other more specific embodiments are disclosed in greater detail below.

[0038] Note that while the embodiments discussed herein apply to amplifier circuits, the concepts disclosed herein may be advantageously applied to any other suitable topology.

[0039] Note that, although each of the various features, techniques, configurations, etc. herein may be discussed at different locations in the present disclosure, it is contemplated that each of the concepts may be optionally performed independently of each other or in combination with each other where appropriate. Thus, one or more of the present inventions as described herein may be embodied and considered in many different ways.

[0040] In addition, it is noted that this preliminary discussion of the embodiments herein does not intentionally specify every embodiment and / or value-added novel aspect of the present disclosure or the claimed invention. Instead, this brief description only presents general embodiments and corresponding novel points compared to conventional techniques. For other details and / or possible viewpoints (configurations) of the present invention, as will be further discussed below, the reader is directed to the detailed description section of the present disclosure and the corresponding drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a diagram showing an example of a multi-stage amplifier device according to conventional technology;

[0042] Figure 2 is an example diagram showing an implementation of a multi-stage device according to an embodiment of the present invention;

[0043] Figure 3 is an example diagram showing a more specific implementation of a multi-stage amplifier circuit according to an embodiment of the present invention;

[0044] Figure 4 is shown by a conventional circuit (such as Figure 1 The gain provided by the multi-stage device according to the embodiments of the present invention (such as Figure 3 (middle) provides an example graph of the theoretical difference in gain;

[0045] Figure 5 is an example diagram illustrating an implementation of a multi-stage amplifier circuit using multiple inductor components according to embodiments herein;

[0046] Fig. 6A It is a diagram showing an embodiment according to the present invention Figure 5 An example diagram of a simplified view of a multi-stage amplifier circuit;

[0047] Figure 6B is a diagram showing a method for executing Fig. 6A An example diagram of a replacement circuit for small signal analysis of a multi-stage amplifier circuit in FIG.

[0048] Figure 6C is a diagram showing a method for calculating Figure 6B Example diagram of the equation for Rout of a simplified circuit;

[0049] Figure 7 is an example diagram showing an implementation of a multi-stage amplifier circuit according to an embodiment of the present invention;

[0050] Figure 8 is an example diagram showing the general form of a multi-stage amplifier circuit according to an embodiment of the present invention;

[0051] Fig. 9is an example diagram showing an implementation of a multi-stage amplifier circuit including a plurality of input stages according to an embodiment of the present invention;

[0052] Fig.10 is an example diagram showing an implementation of a multi-stage amplifier circuit according to an embodiment of the present invention;

[0053] Fig.11 is an example diagram showing an implementation of a multi-stage amplifier circuit according to an embodiment of the present invention;

[0054] Fig.12 is an example diagram showing the implementation of a multi-stage circuit in a wireless device application according to an embodiment of the present invention;

[0055] Fig.13 is an exemplary diagram illustrating a method of providing signal amplification according to an embodiment of the present invention.

[0056] The foregoing and other objects, features and advantages of the embodiments of the present invention will become apparent from the following more detailed description of the present invention, as shown in the accompanying drawings, in which like reference numerals refer to the same parts throughout the different views. The accompanying drawings are not necessarily drawn to scale, but emphasis is placed on illustrating embodiments, principles, concepts, etc. DETAILED DESCRIPTION

[0057] Embodiments herein include an amplifier device including: a first stage for receiving an input signal, the first stage generating an intermediate signal based on the input signal; and a second stage coupled to the first stage to receive the intermediate signal and generate an output signal. The second stage includes: 1) a transistor; 2) a circuit path between the first stage and the transistor. The intermediate signal is input to the circuit path to obtain an output signal from the intermediate signal.

[0058] Now, more specifically, Figure 2 is an example diagram illustrating a novel multi-stage device according to an embodiment of the present invention. By way of non-limiting example embodiment, the multi-stage device described herein is a multi-stage amplifier device. For example, the multi-stage device is a low noise amplifier or so-called LNA device, apparatus, circuit, etc.

[0059] As shown, in this example embodiment, multi-stage device 200 includes any number of stages.

[0060] For example, in one embodiment, multi-stage device 200 includes stage 221 (eg, input stage) and stage 222 (eg, output buffer or output stage). As further shown, stage 222 includes circuit path 225 and transistor 228.

[0061] As discussed previously, typically, each of the stages in multi-stage apparatus 200 and the corresponding components take the form of hardware such as circuits. However, such resources may be instantiated in any suitable manner.

[0062] In one embodiment, transistor 228 is an N-channel CMOS (complementary metal oxide semiconductor) component where the substrate is connected to V SUBSTRATE Note, however, that transistor 228 may be any suitable transistor (field effect transistor, bipolar junction transistor, etc.) or switching device functionally supported herein.

[0063] During operation, the first stage 221 (eg, an oscillating circuit or a resonant circuit) receives the input signal 210 and outputs the intermediate signal 230 based on the input signal 210. As shown, the second stage 222 (eg, another oscillating circuit or a resonant circuit) is coupled to the first stage 221 to receive the intermediate signal 230.

[0064] In one embodiment, the second stage includes: i) a transistor 228, and ii) a circuit path 225 disposed between the first stage 221 and the transistor 228. As further discussed herein, an intermediate signal 230 is input to the circuit path 225 to control the transistor 228 and / or an output signal 240 is derived from the intermediate signal 230. As further discussed below, embodiments herein also include applying a bias voltage to the transistor 228 to control its operation or state.

[0065] In embodiments where the multi-stage device 200 is an amplifier (eg, a low noise amplifier circuit), the output signal 240 is an amplified reproduction of the input signal 210 .

[0066] As another example, in one embodiment, note that intermediate signal 230 is an amplified reproduction of input signal 210. Output signal 240 is an amplified reproduction of intermediate signal 230. As previously discussed, the amplification or gain of the output signal relative to the intermediate signal can be selected to be zero or quite small. In other words, the amount of gain provided by stage 222 can be small or zero. In such a case, input stage 221 provides most or all of the gain associated with multi-stage device 200.

[0067] According to other embodiments, circuit path 225 couples a node of the first stage generating intermediate signal 230 to one or more nodes (eg, input node and / or output node) of transistor 228 .

[0068] More specifically, as discussed further herein, circuit path 225 may be configured to provide connectivity from stage 221 to a gate node (input node) of transistor 228 ; circuit path 225 may be configured to provide connectivity from stage 221 to a source node of transistor 228 .

[0069] According to yet another embodiment, intermediate signal 230 generated by first stage 221 and input to circuit path 225 controls operation of transistor 228 and flow of corresponding current via circuit path 225. Such control of current via circuit path 225 generates output signal 240 output from second stage 222.

[0070] As further discussed herein, in one embodiment, the second stage 222 is operable to use or reuse current associated with the intermediate signal 230 output from the first stage 221 to generate the output signal 240. As further discussed herein, using or reusing current from the first stage 221 to generate the output signal 240 from the second stage reduces power consumption of the multi-stage device 200 when converting the input signal 210 to the output signal 240.

[0071] Figure 3 is an exemplary diagram showing a more specific implementation of a multi-stage device according to an embodiment of this document.

[0072] In this exemplary embodiment, the multi-stage device 200-1 (eg, amplifier circuit) includes a stage 221-1 and a stage 222-2. As previously discussed, the multi-stage device 200-1 may include any number of stages.

[0073] Typically, each of the stages of the multi-stage apparatus 200-2 and the corresponding components take the form of hardware such as circuits. However, such resources may be instantiated in any suitable manner.

[0074] As shown in this example embodiment, the input stage 221 - 1 of the multi-stage device 200 - 1 includes a transistor 322 , a transistor 323 , an inductor Lmatch, a capacitor Ccoupling, a resistor RbiasCS, and an inductor Lds.

[0075] In this example implementation, as shown in stage 221 - 1 , the input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccoupling connected to the gate node of transistor 323 . BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DSThe series combination of connects node 392 of stage 221-1 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323; and the inductor LDS couples the source node (S) of transistor 323 to the ground reference (GND). As further shown, the output stage 222-1 (or output buffer) of the multi-stage device 200-1 includes capacitor 351, power supply V DD , component 341 , component 342 , component 343 , component 344 , transistor 228 , resistor RbiasGY and capacitor 345 .

[0076] Furthermore, in this exemplary embodiment, capacitor 351 provides connectivity between node 392 and the gate node of transistor 228, as shown in stage 222-1. BIASGY Receive input voltage V BIASGY and coupled to the gate node of transistor 228. Component 341 couples power supply 310 (e.g., voltage VDD) to the drain node (D) of transistor 228; component 342 couples the source node (S) of transistor 342 to node 393; component 343 couples node 392 to node 393; and the series combination of component 344 and capacitor 345 couples node 393 to the output of multi-stage device 200-1 that generates output signal 240.

[0077] As previously discussed, input signal 210 (Vin) is input to input stage 221 - 1 (eg, a single cascode amplifier in this example).

[0078] The input stage 221-1 is tuned to convert the input signal 210 to an intermediate signal 230 output at a node 392. Differently, the input signal 210 (Vin) controls at least the operation of the transistor 323 in the stage 221-1 (which is controlled to be in the correct or desired DC bias state) to produce the intermediate signal 230 output from the node 392 of the first stage 221-1 to the second stage 222-1.

[0079] In one embodiment, transistor 323 is an N-channel CMOS (complementary metal oxide semiconductor) component in which the substrate is connected to a reference voltage V SUBSTRATE Note, however, that transistor 323 may be any suitable transistor (field effect transistor, bipolar junction transistor, etc.) or switching device functionally supported herein.

[0080] As further shown, note that the first stage 221-1 can be configured to include a transistor 322 to control the amount of current associated with the intermediate signal 230 (e.g., RF signal) output to the second stage 222-1. Transistor 323 controls the flow of DC current through the multi-stage device to a ground reference (GND).

[0081] In one embodiment, transistor 322 is an N-channel CMOS (complementary metal oxide semiconductor) component in which the substrate is connected to a reference voltage V SUBSTRATE Note, however, that transistor 322 may be any suitable transistor (field effect transistor, bipolar junction transistor, etc.) or switching device that is functionally supported herein.

[0082] More specifically, in one embodiment, an input voltage 333 (i.e., VbiasCG, e.g., a DC voltage value) is applied to the gate (G) of transistor 322 in stage 221-1. Voltage VbiasCG is set to an appropriate DC bias voltage to control the RF performance of transistor 322. As described herein, the current amplitude provided by intermediate signal 230 to stage 222-1 is one parameter that controls the gain associated with multi-stage device 200-1. More specifically, in one embodiment, an appropriate setting of the DC voltage of VbiasCG is selected to obtain the most desired gain and linearity performance, depending on the overall circuit.

[0083] Therefore, setting of voltage VBiasCG is one way to control the gain associated with multi-stage device 100 .

[0084] Note that the impedance settings of components 341, 342, 343, 344 (eg, including one or more different types of passive components) in stage 222-1 can be simple values ​​of any suitable complex impedance value. As discussed further below, the settings of these components control various parameters associated with stage 322.

[0085] In some cases, embodiments herein include setting one or more corresponding components (341, 342, 343, 344) to zero ohms (i.e., short circuit). Alternatively, any of these components may be set to a complex impedance value. In one embodiment, one or more components being set to zero ohms would be for a 1.2VDC V DD Optimal solution for supply voltage to achieve high performance.

[0086] As previously discussed, the multi-stage device 200 - 1 may include any number of passive components, such as resistors, capacitors, and / or inductors.

[0087] Multi-stage device 200 - 1 includes any number of one or more circuit paths coupling node 392 of stage 221 - 1 to transistor 228 .

[0088] For example, in one embodiment, second stage 222-1 includes circuit path 225-1 (e.g., including capacitor 351) coupling node 392 to the gate node (G) of transistor 228. Intermediate signal 230 input to circuit path 225-1 and the gate of transistor 228 controls the current through transistor 228, which is in an appropriate DC bias state.

[0089] The second stage 222-1 also includes a circuit path 225-2. The circuit path 225-2 includes components 343 and 342 arranged in series between the node 392 of the first stage 221-1 and the node (output node, e.g., source node S) of the transistor 228 in the second stage 222-1. As further discussed herein, the circuit path 225-2 provides at least a partial path through which the power from the power supply V DD In one embodiment, at least a portion of the DC current associated with the intermediate signal 230 (e.g., a network RF signal) input to the circuit path 225-2 is internally passed through the transistor 228 (e.g., from its drain to its source or from its source to its drain) and the component 341 to the reference voltage V DD To obtain the output signal 240. According to other embodiments, the DC current mainly flows through the circuit path 225-2.

[0090] Furthermore, in the exemplary embodiment, an output signal 240 (eg, voltage Vout) is derived from node 393 , whose voltage is based at least in part on the intermediate signal 230 input to circuit path 225 - 2 .

[0091] Typically, in one embodiment, the value of component 342 is selected to match the overall impedance of stage 222-1 to the impedance of stage 221-1 (eg, approximately 50 ohms or other suitable value).The impedance value selected for component 343 typically controls or adjusts the gain of stage 222-1.

[0092] As further shown, and as previously discussed, capacitor 351 provides coupling of node 392 of first stage 221-1 outputting intermediate signal 230 to gate node (G) of transistor 228. Note that the size / value / setting selected for capacitor 351 affects the gain and impedance associated with stage 222-1.

[0093] More specifically, the intermediate signal 230 input to the circuit path 225-2 is passed through the component 351 (capacitor) to the gate node (G) of the transistor 228. The capacitance of the component 351 can be any suitable value. A higher capacitance value of the component 351 results in a higher gain provided by the multi-stage device 200-1; a lower capacitance value of the component 351 results in a lower gain provided by the multi-stage device 200-1.

[0094] Typically, the impedance value or setting of component 343 is selected to control the gain of multi-stage device 200-1. For example, the higher the impedance (eg, inductance) value of component 343, the higher the gain; the lower the impedance (eg, inductance) value of component 343, the lower the gain.

[0095] Note also that the channel width (and generally the corresponding drain-source conductance) associated with transistor 228 can also be used to control the overall gain of multi-stage device 200-1. For example, the larger the width of transistor 228, the lower the gain provided by stage 222-1; the smaller the width, the higher the gain provided by stage 222-1.

[0096] V BIASGY Through the resistor R BIASGY The voltage V applied to the gate node of transistor 228 biases the gate node (G) of transistor 228 to set transistor 228 to a desired operating point / state. In one embodiment, the voltage V BIASGY The setting of is controlled to provide appropriate linearity for stage 222-1.

[0097] During operation, as previously discussed, the input to the gate of transistor 228 (e.g., the voltage at the gate node of transistor 228 or the intermediate signal 230 through component 351) controls the state of transistor 228 and the flow of DC current, which flows primarily through the following circuit path: from voltage source 310 (VDD) through component 341, the drain to source of transistor 228, component 342, component 343, the drain to source of transistor 322, the drain to source of transistor 323, and inductor L DS to the ground reference (GND).

[0098] As previously discussed, as shown, output signal 240 is derived from the voltage at node 393. In one embodiment, as shown, the output of multi-stage device 200-1 that produces output signal 240 includes a series connection of component 344 and capacitor 345.

[0099] Note that other embodiments herein include implementing the combination of the first stage 221-1 and the second stage 222-1 of the multi-stage device 200-1 as a common drain amplifier circuit to amplify the input signal 210 to the output signal 240. Thus, in one embodiment, the second stage 222-1 is a common drain circuit (e.g., the drain of the transistor 228 is coupled to the power supply voltage V DD ). Through the example common drain output buffer stage (stage 222-1), the embodiments herein include the same as previously described Figure 1 The invention provides higher gain and impedance output matching of stage 221-1 and stage 222-1 over a wide frequency range compared to conventional circuits and techniques.

[0100] More specifically, again referring to Figure 3 , the output impedance of the second stage 222-1 matches (or substantially matches) the output impedance of the first stage 221-1. In one embodiment, the impedance of the second stage 222-1 may substantially match the impedance of the first stage 221-1 over a frequency range greater than 1.5 GHz or over any other suitable value. As discussed previously, the wider the range of stage matching, the better the ability of the multi-stage device 200-1 to operate in broadband applications.

[0101] In one embodiment, if Figure 4 As discussed in , the multi-stage device 200 - 1 provides impedance matching between 1 GHz and 3 GHz, or any other frequency range.

[0102] Refer again Figure 3 As discussed previously, input stage 221-1 can be a single cascode amplifier. However, note that the output buffer stage (stage 222-1) is compatible with any suitable type of input stage (e.g., for low gain or <1.2VDC V DD Common source of supply voltage for high gain or >1.8VDC V DD The dual cascode stage with the power supply voltage is used in combination.

[0103] Embodiments herein provide advantages over conventional amplifiers. For example, the novel multi-stage device 200-1 supports:

[0104] Higher gain with fewer cascode stages (this may be important for low voltages <1.2VDC LNAs)

[0105] · Output impedance matching in a wide range

[0106] Lower processing variation impact (no S22 frequency shift)

[0107] Broadband application area (only external matching changes)

[0108] Reduced semiconductor chip area (circuit size) on the corresponding substrate implementing the multi-stage device 200

[0109] Significantly reduce LNA development time and cost

[0110] Developing a universal LNA that can be used in many frequency bands, stage 222-1 (e.g., output buffer stage) can be used with several input stages:

[0111] Public source level

[0112] Single cascode stage

[0113] Multiple cascode stages.

[0114] Figure 4 is an example graph illustrating the theoretical difference between the gain provided by a conventional amplifier circuit and the gain provided by a multi-stage device according to embodiments herein.

[0115] according to Figure 4 In the graph 400, Figure 1 The conventional amplifier circuit 100 in provides a hypothetical gain 410 over a frequency range from 0 to 5 GHz. In contrast, Figure 2 and Figure 3 The improved multi-stage device 200 (200-1) provides a hypothetical gain 420 in the frequency range from 0 to 5 GHz.

[0116] Therefore, the multi-stage device 200 according to embodiments herein provides a higher gain than the conventional amplifier circuit 100 .

[0117] It is also noted that at lower operating frequencies, the multi-stage device 200 provides higher gain than the conventional amplifier 100. This indicates that the semiconductor chip area of ​​the corresponding circuit implementing the multi-stage device 200 can be reduced because the inductance value required in the LB frequency (e.g., 3nH to >10nH) is much lower than the inductance required to implement the conventional amplifier 100 (e.g., the combination of the cascode input stage and the capacitive dividers C1 and C2).

[0118] Figure 5 is an example diagram illustrating an implementation of a multi-stage amplifier circuit according to embodiments of the present invention.

[0119] As shown in this example embodiment, the input stage 221 - 2 of the multi-stage device 200 - 2 includes a transistor 322 , a transistor 323 , an inductor Lmatch, a capacitor Ccoupling, a resistor RbiasCS, and an inductor Lds.

[0120] In this example implementation, as shown in stage 221-2, the input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccoupling connected to the gate node of transistor 323. BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DS The series combination of connects node 392 of stage 221-1 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323; and the inductor LDS couples the source node (S) of transistor 323 to the ground reference (GND).

[0121] As further shown, the output stage 222-2 (or output buffer) of the multi-stage device 200-2 includes a capacitor 351, a power supply V DD , component 342 - 1 (eg, inductor L2 ), component 343 - 1 (eg, inductor L1 ), transistor 228 , resistor RbiasGY and capacitor 345 .

[0122] Furthermore, in this example implementation, capacitor 351 provides connectivity between node 392 and the gate node of transistor 228, as shown in stage 222-2. BIASGY Receive input voltage V BIASGY and is coupled to the gate node of transistor 228. Power supply 310 (VDD) is directly connected to the drain node (D) of transistor 228; component 342-1 (e.g., inductor L2) couples the source node (S) of transistor 228 to node 393; component 343-1 (e.g., inductor L1) couples node 392 to node 393; component 345 (e.g., capacitor) couples node 393 to the output of multi-stage device 200-2 that generates output signal 240.

[0123] In this exemplary embodiment, power supply VDD (power supply 310) is directly connected to the drain (D) of transistor 228. For example, (as previously described with respect to Figure 3 The component 341 in question is short-circuited or has a near zero-ohm connection.

[0124] As further shown, component 342 - 1 is instantiated as inductor L2 ; component 343 - 1 is instantiated as inductor L1 .

[0125] Generally, in one embodiment, the value of inductor L1 (component 343-1) is selected to control the gain of multi-stage device 200-2. For example, the higher the inductance value or setting of L1, the higher the gain of multi-stage device 200-2; the lower the inductance value of L1, the lower the gain of multi-stage device 200-2.

[0126] Generally, in one embodiment, the value or setting of inductor L2 (component 342 - 1 ) is selected to control the output impedance of the second stage 222 - 2 of the multi-stage device 200 - 2 .

[0127] To calculate the output match (Rout) and voltage / power gain (Av) of the multi-stage device 200-2, the total impedance value 625 as shown in FIG. 6 may be advantageously used in place of the stage 221-2 (eg, a cascode amplifier). In other words, Fig. 6A The multi-stage device 200-2 is Figure 5 A simplification of the multi-stage device 200-2 in FIG.

[0128] Fig. 6A is a simplified example diagram showing a multi-stage amplifier circuit according to embodiments herein.

[0129] In this exemplary embodiment, the input stage 221-2 is simplified to an impedance 625. This simplified circuit of the multi-stage device 200-2 can be used, for example, using Figure 6B The small signal replacement circuit further shown in FIG. 2 is used to calculate Rout of stage 222 - 2 .

[0130] Figure 6B is a simplified example diagram showing a multi-stage amplifier circuit according to embodiments herein.

[0131] If necessary, a small signal replacement circuit can be inserted (such as Figure 6B 222 - 2 ) to perform simulations and verify broadband output matching of the impedance 625 associated with the input stage 221 - 2 and the impedance of the output stage 222 - 2 .

[0132] As shown in this example embodiment, impedance 625 is coupled between node 392 and ground reference (GND). Capacitor 351 and capacitor C GS is coupled in series between node 392 and node 693. Inductor L2 is coupled between node 693 and node 692. Inductor L1 is connected between node 692 and node 392. Resistor rds is connected in parallel with source 620 between node 693 and a ground reference (GND).

[0133] Figure 6C is a diagram showing the calculation according to the embodiment of this article Figure 6B An example diagram of the equation for Rout of a simplified circuit.

[0134] In one embodiment, the small signal replacement circuit Rout is calculated as follows:

[0135] I DS =gm vgs

[0136] I CGS =vgs s C GS

[0137]

[0138] Grid:

[0139] 0=-U L2 -U rds -U out

[0140] 0=-U Z -U C +vgs-U rds

[0141] 0=-U out -U Z +U C +vgs-U L2

[0142] 0=-U L2 -U Z -U out

[0143] node:

[0144] 0=-I out -I L1 -I L2

[0145] 0=-I L2 +I CGS +I DS +I rds

[0146] 0=-I Z -I L1 -I CGS

[0147] As discussed earlier, see Figure 6C The equation for calculating Rout.

[0148] Figure 7 is an example diagram illustrating an implementation of a multi-stage amplifier circuit according to embodiments of the present invention.

[0149] As shown in this example embodiment, the input stage 221-3 of the multi-stage device 200-3 includes a transistor 322, a transistor 323, an inductor Lmatch, a capacitor Ccouple, a resistor R BIASCS and inductor L DS .

[0150] In this example implementation, as shown in stage 221-3, the input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccouple connected to the gate node of transistor 323. BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DS The series combination of connects node 392 of stage 221-1 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323; and the inductor L DS The source node (S) of transistor 323 is coupled to a ground reference (GND).

[0151] As further shown, the gyrator stage 722 (or output buffer) of the multi-stage device 200-3 includes a capacitor C GY , power supply 310 (such as V DD ), resistor R D , transistor 228, resistor R GY , capacitor C701 and resistor R BIASGY .

[0152] Furthermore, in this exemplary embodiment, as shown in gyrator stage 722, resistor R D Provides connectivity between source 310 and the drain node (D) of transistor 228. Resistor R GY The source node (S) of transistor 228 is coupled to node 392. Capacitor C GY Node 392 is coupled to the gate node (G) of transistor 228. Resistor R BIASGY Receive input voltage V BIASGY and is coupled to the gate node (G) of transistor 228. Capacitor C701 coupled to node 392 provides a circuit path for output signal 240 from multi-stage device 200-3.

[0153] In the present exemplary embodiment, the multi-stage device 200 - 3 is implemented based on the so-called gyrator principle (ie active inductor). Therefore, the multi-stage device 200 - 3 includes implementing the second stage 222 as a gyrator stage 722 .

[0154] As shown, the gyrator stage 722 in this example embodiment includes a capacitor C GY , resistor R GY , transistor 228 and resistor R BIASGY During operation in this embodiment, the multi-stage device 200-3 outputs an output signal 240 from the node 392 through the capacitor C701. Similar to the other embodiments discussed previously, the output signal 240 is an amplified reproduction of the input signal 210.

[0155] In one non-limiting example embodiment, the second stage of the multi-stage device 200 is implemented as a gyrator stage 722 (eg, Figure 7 2 (shown) reduces the footprint of the corresponding semiconductor chips used to manufacture the multi-stage device 200-3. However, the overall performance of the multi-stage device 200-3 may be lower than if the stage 222 is implemented using an inductor coil as in the previous embodiment.

[0156] Figure 8 is an example diagram showing the general form of a multi-stage amplifier circuit according to embodiments of the present invention.

[0157] As shown in this exemplary embodiment, the input stage 221-4 of the multi-stage device 200-4 includes a transistor 322, a transistor 323, an inductor Lmatch, a capacitor Ccouple, a resistor R BIASCS and inductor L DS .

[0158] In this exemplary embodiment, as shown in stage 221-4, the input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccouple connected to the gate node of transistor 323. BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DS The series combination of connects node 392 of stage 221 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323, and the inductor L DS The source node (S) of transistor 323 is coupled to a ground reference (GND).

[0159] As further shown, the gyrator stage 822 (or output buffer) of the multi-stage device 200-4 includes a power supply 310 (eg, V DD ), capacitor C GY, resistor R OUT , transistor 228, resistor R GY , capacitor C801 and resistor R BIASGY .

[0160] Also in this example implementation, source 310 is connected to the drain node (D) of transistor 228 as shown in gyrator stage 822. Resistor R GY Node 392 is coupled to the source node (S) of transistor 228. Capacitor C GY Node 392 is coupled to the gate node (G) of transistor 228. Resistor R BIASGY Receive input voltage V BIASGY , and is coupled to the gate node (G) of transistor 228. A resistor R coupled to node 852 OUT The series combination with capacitor C801 provides a circuit path for output signal 240 from multi-stage device 200-4.

[0161] In this example embodiment, stage 822 (output buffer) of the multi-stage device 200 - 4 is implemented using the so-called gyrator principle (ie, active inductor).

[0162] More specifically, as previously discussed, the gyrator stage 822 of the multi-stage device 200-4 includes a capacitor C GY , resistor R GY , transistor 228 and resistor R BIASGY In this case, the multi-stage device 200 - 4 outputs the output signal 240 from the node 852 through the resistor ROUT and the capacitor C801 .

[0163] As previously discussed, the output signal 240 from the multi-stage device 200 - 4 is an amplified reproduction of the input signal 210 .

[0164] In one embodiment, the second stage of the multi-stage device 200-4 is implemented as a gyrator stage 822 (eg, Figure 8 ) reduces the packaging of the corresponding semiconductor chips used to manufacture the multi-stage device 200. However, the overall performance of the multi-stage device 200-4 may be lower than that of the implementation of the stage 222 using the inductor coil as discussed above.

[0165] Fig. 9 is an example diagram illustrating an implementation of a multi-stage amplifier circuit using multiple input stages according to embodiments herein.

[0166] As shown in this exemplary embodiment, input stage 921 includes input stage 921 - 1 , . . . , input stage 921 -N, where N>1.

[0167] The input stage 921-1 of the multi-stage device 200-5 includes a transistor 322, a transistor 323-1, an inductor Lmatch1, a capacitor Ccouple1, a resistor R BIAS1 and inductor L DS1 The input stage 921-N of the multi-stage device 200-5 includes a transistor 322, a transistor 323-N, an inductor LmatchN, a capacitor CcoupleN, a resistor R BIASN and inductor L DSN .

[0168] In this example implementation, as shown in input stage 921-1, input signal 210-1 is input to a circuit path that includes a series combination of inductor Lmatch1 and capacitor Ccouple1 connected to the gate node of transistor 323-1. BIASC1 is input to a resistor R coupled to the gate node (G) of transistor 323-1. BIASC1 The transistor 322, the transistor 323-1 and the inductor L DS1 The series combination of connects node 392 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323-1; and the inductor L DS1 The source node (S) of transistor 323 - 1 is coupled to a ground reference (GND).

[0169] As shown in input stage 921-N, input signal 210-N is input to a circuit path that includes a series combination of inductor LmatchN and capacitor CcoupleN connected to the gate node (G) of transistor 323-N. BIASCSN is input to a resistor R coupled to the gate node (G) of transistor 323-N. BIASCSN The circuit path of transistor 322, transistor 323-N and inductor L DSN The series combination of connects node 392 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323-N; and the inductor L DSN The source node (S) of transistor 323 -N is coupled to a ground reference (GND).

[0170] As further shown, stage 922 (or output buffer) of multi-stage device 200-5 includes power supply 310 (eg, V DD ), capacitor C GY(1:N), transistor 228, resistor R BIASGY 、Inductor L GY2 、Inductor L GY1 and capacitor 902 (C couple ).

[0171] More specifically, in stage 922, capacitor 951 (C GY(1：N) ) provides connectivity between node 392 and the gate node (G) of transistor 228. Resistor R BIASGY Receive input voltage V BIASGY , and is coupled to the gate node of transistor 228. Power supply 310 (VDD) is directly connected to the drain node (D) of transistor 228; inductor L GY2 The source node (S) of transistor 228 is coupled to node 393 ; inductor LGY couples node 392 to node 393 ; capacitor 902 couples node 393 to the output of multi-stage device 200 - 2 that generates output signal 240 .

[0172] In this embodiment, input stage 921 includes a plurality of parallel cascode amplifiers for generating intermediate signal 930. In one embodiment, each of the corresponding inductors is disposed on a semiconductor chip. As shown, stage 922 includes a switchable capacitor C GY .

[0173] The impedances of input stage 921 and output stage 922 are selected so that multi-stage device 900 operates over a broadband frequency range.

[0174] Fig.10 is an example diagram illustrating an implementation of a multi-stage amplifier circuit according to embodiments of the present invention.

[0175] As shown in this exemplary embodiment, the input stage 221-6 of the multi-stage device 2006 includes a transistor 322, a transistor 323, an inductor Lmatch, a capacitor Ccouple, a resistor R BIASCS and inductor L DS .

[0176] In this example implementation, as shown in stage 221-6, input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccouple connected to the gate node (G) of transistor 323. Input voltage V BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DSThe series combination of connects node 392 of stage 221-1 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323; and the inductor L DS The source node (S) of transistor 323 is coupled to a ground reference (GND).

[0177] As further shown, the output stage 222-6 (or output buffer) of the multi-stage device 200-6 includes a capacitor 351, a power supply V DD , component 342-2 (such as a tapped inductor L GY ), transistor 228, resistor R BIASGY and capacitor 345.

[0178] Also in this example implementation, capacitor 351 provides connectivity between node 392 and the gate node (G) of transistor 228, as shown in stage 222-6. BIASGY Receive input voltage V BIASGY , and is coupled to the gate node (G) of transistor 228. Power supply 310 (V DD ) is directly connected to the drain node (D) of transistor 228; component 342-2 (e.g., tapped inductor L GY ) couples the source node (S) of transistor 228 to node 393; component 345 (eg, a capacitor) couples the inductor L GY The tap node 1093 is coupled to the output of the multi-stage device 200 - 6 that generates the output signal 240 .

[0179] Fig.10 The multi-stage device 200-6 in FIG. 2 operates in a similar manner as previously discussed. For example, stage 221-6 operates in a similar manner as previously discussed. However, Figure 5 The inductors L1 and L2 in the Fig.10 The tapped inductor L shown in stage 222-6 of the multi-stage device 200-6 GY .

[0180] Fig.11 is an example diagram illustrating an implementation of a multi-stage amplifier circuit according to embodiments of the present invention.

[0181] As shown in this exemplary embodiment, the input stage 221-7 of the multi-stage device 200-7 includes a transistor 322, a transistor 323, an inductor Lmatch, a capacitor Ccouple, a resistor R BIASCS and inductor L DS .

[0182] In this example implementation, as shown in stage 221-7, input signal 210 is input to a circuit path that includes a series combination of an inductor Lmatch and a capacitor Ccouple connected to the gate node (G) of transistor 323. Input voltage V BIASCS is input to a resistor R coupled to the gate node (G) of transistor 323. BIASCS The transistor 322, the transistor 323 and the inductor L DS The series combination of connects node 392 of stage 221-1 to the ground reference (GND). More specifically, the drain node (D) of transistor 322 is coupled to node 392; the source node (S) of transistor 322 is coupled to the drain node (D) of transistor 323; and the inductor L DS The source node (S) of transistor 323 is coupled to a ground reference (GND).

[0183] As further shown, the output stage 222-7 (or output buffer) of the multi-stage device 200-7 includes a capacitor 351, a power supply 310 (eg, a voltage V DD ), component 342 (e.g., inductor L GY ), transistor 228, resistor RbiasGY and capacitor 1105.

[0184] Furthermore, in this example implementation, capacitor 351 provides connectivity between node 392 and the gate node (G) of transistor 228, as shown in stage 222-7. BIASGY Receive input voltage V BIASGY , and is coupled to the gate node (G) of transistor 228. Power supply 310 (V DD ) is directly connected to the drain node (D) of transistor 228; component 342 (e.g., inductor L GY ) couples the source node (S) of transistor 228 to node 392; component C1105 (e.g., a capacitor) couples node 392 to the output of the multi-stage device 200-7 that generates the output signal 240.

[0185] In this example implementation, (as described above with respect to Figure 3 (as discussed above) component 341 is short-circuited; (as discussed above) Figure 3 Component 342 discussed in the GY ; (as mentioned above Figure 3 ) component 343 is short-circuited or connected at low impedance to node 392; (as discussed previously in Figure 3 Component 344 is shorted such that node 392 is coupled to the output of stage 222 via capacitor C1105. Additional capacitor C1102 shunts node 392 to ground.

[0186] In a similar manner to that discussed previously, through resistor R BIASGY V BIASGY The voltage applied to the gate (G) node of transistor 228 in stage 222 - 7 biases the gate node (G) to produce an output signal 240 based on the intermediate signal 230 output from stage 221 - 7 .

[0187] Fig.12 is an example diagram showing implementation of a multi-stage circuit in a wireless device according to an embodiment of this document.

[0188] As previously discussed, in one embodiment, the multi-stage device 200 is an amplifier circuit for use in any suitable application.

[0189] In this example embodiment, multi-stage device 200 is implemented in communication device 1200. As shown, communication device 1200 includes antenna 1230 to receive wireless signals 1225 transmitted from wireless station 1210. Wireless signals 1225 convey any suitable data, such as voice, video, text, etc.

[0190] Antenna 1230 converts wireless signal 1225 into RF signal 1212 which is input to filter 1240. As the name implies, filter 1240 filters received RF signal 1212 so that input signal 210 includes one or more frequencies from signal 1212 or one or more frequency ranges of interest.

[0191] In a similar manner as previously discussed, the multi-stage device 200 converts (eg, amplifies via a low noise amplifier) ​​a received input signal 210 into an output signal 240 .

[0192] The receiver 1260 of the communication device 1200 receives the output signal 240 and performs further operations such as demodulation, decoding, etc., and performs functions such as displaying video, displaying text, storing data, generating audio signals, etc.

[0193] Therefore, multi-stage devices are beneficial in supporting the amplification of low amplitude signals to high amplitude signals.

[0194] Now it will pass Fig.13 The flowcharts in discuss the functionality supported by different resources. Note that the steps in the flowcharts below can be performed in any suitable order.

[0195] Fig.13 is a flowchart 1300 illustrating an example method according to implementations herein. Note that, as discussed above, there is some overlap in concepts.

[0196] In processing operation 1310 , multi-stage device 200 receives input signal 210 .

[0197] In processing operation 1320 , the multi-stage device generates an intermediate signal 230 from the input signal 210 .

[0198] In processing operation 1330 , first stage 221 inputs intermediate signal 230 to circuit path 225 coupled to transistor 228 in second stage 222 of multi-stage device 200 .

[0199] In processing operation 1340 , the input intermediate signal 230 controls the operation of the transistor 228 in the second stage 222 to obtain the output signal 240 .

[0200] Note again that the techniques herein are well suited for use in amplifier circuits of multi-stage arrangements. However, it should be noted that the embodiments herein are not limited to use in such applications, and the techniques discussed herein are well suited for use in other applications as well.

[0201] Based on the description set forth herein, many specific details are set forth to provide a comprehensive understanding of the subject matter claimed. However, it should be understood by those skilled in the art that the subject matter claimed can be practiced without these specific details. In other cases, methods, devices, systems, etc. known to those of ordinary skill in the art are not described in detail to avoid blurring the subject matter claimed. Some parts of the detailed description have been presented in terms of the algorithm or symbolic representation of the operation of data bits or binary digital signals stored in a computing system memory such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the field of data processing to convey the essence of their work to those skilled in the art. Algorithms such as those described herein, and are generally considered to be self-consistent sequences of operations or similar processes that result in desired results. In this context, operations or processes involve physical manipulation of physical quantities. Typically, although not required, such quantities can take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or otherwise manipulated. Mainly for common use reasons, it is sometimes convenient to refer to such signals as bits, data, values, elements, symbols, characters, items, numbers, digits, etc. However, it should be understood that all of these and similar terms are associated with appropriate physical quantities and are merely convenient labels. Unless otherwise expressly stated, it will be apparent from the following discussion that it should be understood that throughout the specification, discussions utilizing terms such as "processing," "computing," "calculating," "determining," and the like refer to the actions or processes of a computing platform, such as a computer or similar electronic computing device, that manipulates or transforms data represented as physical electronic or magnetic quantities within the computing platform's memory, registers, or other information storage, transmission, or display device.

[0202] Although the present invention has been specifically shown and described with reference to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present application as defined by the appended claims. Such changes are intended to be covered by the scope of the present application. Therefore, the foregoing description of the embodiments of the present application is not intended to be limited. On the contrary, any limitation of the present invention is presented in the appended claims.

Claims

1. An amplifier, comprising: a first amplifier stage comprising a first transistor and a second transistor connected in series and configured to receive an input signal, the first amplifier stage generating an intermediate signal based on the input signal; as well as a second amplifier stage coupled to the first amplifier stage to receive the intermediate signal and generate an output signal, the second amplifier stage comprising: The third transistor, a power supply coupled to the drain node of the third transistor to provide a power supply voltage, and a circuit path between the first amplifier stage and the third transistor, the intermediate signal being input to the circuit path to control the third transistor and generating the output signal from a source node of the third transistor based on the intermediate signal, The circuit path is coupled between the first amplifier stage and a source node and a gate node of the third transistor.

2. The amplifier according to claim 1, wherein The output signal is an amplified reproduction of the input signal.

3. The amplifier according to claim 1, wherein The impedance of the second amplifier stage is matched to the impedance of the first amplifier stage.

4. The amplifier according to claim 1, further comprising: A capacitor couples an output node of the first amplifier stage outputting the intermediate signal to a gate node of the third transistor.

5. The amplifier according to claim 1, wherein The second transistor is operable to control an amount of current associated with the intermediate signal output to the second amplifier stage.

6. The amplifier according to claim 1, wherein The second amplifier stage is operable to reuse a current provided via the intermediate signal output from the first amplifier stage to generate the output signal.

7. The amplifier according to claim 1, wherein The combination of the first amplifier stage and the second amplifier stage is an amplifier circuit, the amplifier further comprising: An antenna for receiving a wireless signal, the antenna converting the wireless signal into the input signal that is input to the first amplifier stage, the amplifier circuit being operable to amplify the input signal into the output signal.

8. The amplifier of claim 1, the intermediate signal produced by the first amplifier stage controlling operation of the third transistor and corresponding current flow through the circuit path to produce the output signal.

9. The amplifier according to claim 1, wherein: The impedance of the second amplifier stage matches the impedance of the first amplifier stage over a frequency range of 1.5 GHz.

10. The amplifier according to claim 1, wherein The combination of the first amplifier stage and the second amplifier stage is a common drain amplifier circuit to amplify the input signal into the output signal.

11. The amplifier according to claim 1, wherein The intermediate signal is an amplified reproduction of the input signal.

12. The amplifier of claim 1, further comprising a first component disposed in the circuit path between an output node of the first amplifier stage outputting the intermediate signal and a gate node of the third transistor.

13. The amplifier of claim 12, further comprising a second component disposed between an output node of the first amplifier stage outputting the intermediate signal and a source node of the third transistor.

14. The amplifier of claim 1, further comprising a bias voltage source operable to generate a bias voltage that is output to the circuit path.

15. The amplifier of claim 1, further comprising a first component disposed between an output node of the first amplifier stage outputting the intermediate signal and a gate node of the third transistor.

16. The amplifier of claim 1 , further comprising a first component and a second component, the first component and the second component being arranged in series between a node of the first amplifier stage outputting the intermediate signal and a source node of the third transistor, the first component being arranged so as to control a gain provided by the second amplifier stage.

17. The amplifier according to claim 16, wherein The arrangement of the second components is selected such that the impedance of the second amplifier stage matches the impedance of the first amplifier stage.

18. The amplifier of claim 16, wherein: The second component is arranged to control an output impedance associated with the output signal.

19. The amplifier of claim 1, further comprising: a first component provided between a node of the first amplifier stage outputting the intermediate signal and a gate node of the third transistor, the gate node being an input node, the intermediate signal being transmitted through the first component to the gate node of the third transistor and controlling activation of the third transistor; and A second component is provided between a node of the first amplifier stage outputting the intermediate signal and a source node of the third transistor, the second component controlling a gain of the output signal with respect to the intermediate signal.

20. The amplifier of claim 19, wherein The output signal is an amplified reproduction of the intermediate signal.

21. An amplifier, comprising: a first stage including a first transistor and a second transistor connected in series and configured to receive an input signal, the first stage generating an intermediate signal based on the input signal; as well as a second stage coupled to the first stage to receive the intermediate signal and generate an output signal, the second stage comprising: a third transistor, and a circuit path between the first stage and the third transistor, the intermediate signal being input to the circuit path to obtain the output signal from the intermediate signal, The amplifier further comprises: a first component and a second component which are arranged in series between a node of the first stage outputting the intermediate signal and a source node of the third transistor, the output signal being obtained from a circuit node coupling the first component to the second component, The circuit path is coupled between the source node and the gate node of the first stage and the third transistor.

22. The amplifier of claim 21, wherein The circuit path includes a capacitor coupling a node of the first stage outputting the intermediate signal to a gate node of the third transistor.

23. A method for amplifying an input signal, comprising: receiving the input signal at a first stage of the circuit, the first stage comprising a first transistor and a second transistor connected in series; generating an intermediate signal from the input signal; inputting the intermediate signal into a circuit path between a third transistor in the first stage and a second stage of the circuit, a power supply being coupled to a drain node of the third transistor to provide a power supply voltage, the intermediate signal controlling the operation of the third transistor; and generating an output signal from a source node of the third transistor by controlling the third transistor based on the intermediate signal input to the circuit path, The circuit path is coupled between the source node and the gate node of the first stage and the third transistor.

24. The method according to claim 23, wherein: Generating the output signal comprises: The intermediate signal is used as an input to the circuit path to control a gate node of the third transistor and a corresponding current flow through the third transistor to produce the output signal, the gate node being an input node of the third transistor.

25. The method according to claim 23, wherein: Inputting the intermediate signal includes inputting the intermediate signal to a first component of the second stage, the first component and the second component of the second stage being arranged in series between a node of the first stage generating the intermediate signal and a source node of the third transistor.

26. The method according to claim 25, further comprising: The output signal is output from a third component that is coupled to a circuit node that couples the first component to the second component.

27. The method of claim 23, further comprising: The intermediate signal generated by the first stage is input to a gate node of the third transistor through the circuit path.

28. The method of claim 23, further comprising: The output signal is generated using a current associated with the intermediate signal output from the first stage into the circuit path.

29. The method of claim 23, further comprising: receiving a wireless signal at an antenna; as well as generating the input signal based on the received wireless signal; as well as The input signal is amplified to generate the output signal.

30. The method of claim 23, further comprising: The output signal is generated as an amplified reproduction of the input signal.

31. The method of claim 23, further comprising: The intermediate signal is input to control the operation of the third transistor and the corresponding current flow through the circuit path to generate the output signal.

Images