Heat treatment method and heat treatment device

Abstract

The present invention provides a heat treatment method and a heat treatment device capable of properly managing the processing history of dummy chips. When a carrier accommodating a plurality of dummy chips is moved into the heat treatment device, the carrier is registered as a dummy carrier dedicated to the dummy chips. A dummy database is stored in a storage unit, which associates the processing history of each of the plurality of dummy chips with the carrier. The processing history of the dummy chips registered in the dummy database is displayed on a display unit of the heat treatment device. The operator of the heat treatment device can properly grasp and manage the processing history of the dummy chips by confirming the displayed information.

Description

Technical Field

[0001] The invention relates to a heat treatment method and a heat treatment device for managing dummy chips contained in a carrier. Background Art

[0002] In the manufacturing process of semiconductor devices, flash lamp annealing (FLA) for heating semiconductor wafers in a very short time is attracting attention. Flash lamp annealing is a heat treatment technology that heats only the surface of a semiconductor wafer in a very short time (several milliseconds or less) by irradiating a flash of light on the surface of a semiconductor wafer using a xenon flash lamp (hereinafter simply referred to as a "flash lamp").

[0003] The radiation spectrum of a xenon flash lamp is distributed from the ultraviolet region to the near infrared region, and has a shorter wavelength than conventional halogen lamps, which is roughly consistent with the fundamental absorption band of a silicon semiconductor wafer. Therefore, when a xenon flash lamp is used to irradiate a semiconductor wafer with a flash, less light is transmitted, and the temperature of the semiconductor wafer can be rapidly increased. In addition, it has been found that the temperature of only the surface of a semiconductor wafer can be selectively increased by flash irradiation for an extremely short time of less than a few milliseconds.

[0004] This flash lamp annealing is used for a process that requires heating for a very short time, and is typically used, for example, for activation of impurities implanted in a semiconductor wafer. If a flash lamp is irradiated to the surface of a semiconductor wafer into which impurities have been implanted by ion implantation, the surface of the semiconductor wafer can be heated to the activation temperature in a very short time, and only the impurity activation can be performed without deeply diffusing the impurities.

[0005] Typically, not only heat treatment but also semiconductor wafer processing is performed in batches (a group of semiconductor wafers that are subjected to the same processing under the same conditions). In a single-wafer substrate processing apparatus, multiple semiconductor wafers constituting a batch are processed continuously and sequentially. In a flash lamp annealing apparatus, multiple semiconductor wafers constituting a batch are also transferred into a chamber one by one and heat treated sequentially.

[0006] However, the temperature of the chamber structure such as the susceptor that holds the semiconductor wafer may change while the plurality of semiconductor wafers constituting a batch are being processed sequentially. This phenomenon may occur when the flash lamp annealing apparatus that is temporarily stopped is used to restart the process or when the processing conditions such as the processing temperature of the semiconductor wafer are changed. If the temperature of the chamber structure such as the susceptor changes while the plurality of semiconductor wafers constituting a batch are being processed, there may be a problem that the temperature history of the semiconductor wafers at the beginning of the batch and the semiconductor wafers in the latter half of the batch are different when being processed.

[0007] In order to solve this problem, before starting the batch processing, a dummy wafer that is not the processing target is moved into the chamber and supported on a susceptor, and flash heating treatment is performed under the same conditions as the batch to be processed, thereby preheating the temperature of the chamber structure such as the susceptor (dummy operation). Patent document 1 discloses that the flash heating treatment is performed on about 10 dummy wafers so that the temperature of the chamber structure such as the susceptor reaches a stable temperature during processing.

[0008] [Prior art literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2017-092102 Summary of the invention

[0011] [Problems to be solved by the invention]

[0012] The dummy wafers that are not to be processed are used in multiple dummy operations and repeatedly supplied to the heat treatment. As a result, the dummy wafers are prone to cracking or warping due to degradation. If cracking or warping of the dummy wafers occurs during the dummy operation, it will cause contamination in the chamber or transport failure. Therefore, it is important to accurately grasp the degradation state of the dummy wafers to prevent the cracking or warping of the dummy wafers in advance. However, in the past, the operators managed the processing history of the dummy wafers by visual inspection or writing on paper, so they could not fully grasp the degradation state.

[0013] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a heat treatment method and a heat treatment apparatus capable of appropriately managing the treatment history of a dummy wafer.

[0014] [Technical means to solve the problem]

[0015] In order to solve the above-mentioned problem, the invention of Technical Solution 1 is a heat treatment method for managing dummy chips contained in a carrier, which is characterized by comprising: a moving-in step, moving the carrier containing multiple dummy chips into a heat treatment device; a registration step, registering the carrier as a dummy carrier dedicated to dummy chips; a heating step, performing heat treatment on the multiple dummy chips; a storage step, associating the processing history of each of the multiple dummy chips with the carrier and storing them; and a display step, displaying the processing history of each of the multiple dummy chips stored in the storage step.

[0016] In addition, the invention of Technical Solution 2 is a heat treatment method according to the invention of Technical Solution 1, characterized in that: in the storage step, the number of pre-heating times using continuously lit lamps and the number of flash heating times using flash lamps related to each of the multiple virtual chips are associated with the carrier and stored.

[0017] In addition, the invention of technical solution 3 is a heat treatment device for managing dummy chips contained in a carrier, and is characterized in that it comprises: a receiving unit for receiving a carrier containing multiple dummy chips; a registration unit for registering the carrier moved into the receiving unit as a dummy carrier dedicated to dummy chips; a heating unit for performing heat treatment on the multiple dummy chips; a storage unit for associating the processing history of each of the multiple dummy chips with the carrier and storing them; and a display unit for displaying the processing history of each of the multiple dummy chips stored in the storage unit.

[0018] In addition, the invention of technical solution 4 is a heat treatment device according to the invention of technical solution 3, characterized in that: the heating unit includes a continuously lighting lamp and a flash lamp, and the storage unit associates the number of pre-heating times of the multiple virtual chips using the continuously lighting lamp and the number of flash heating times of the flash lamp with the carrier and stores them.

[0019] [Effects of the Invention]

[0020] According to the invention of technical solutions 1 and 2, the processing history of each of the multiple virtual chips is associated with the carrier registered as a virtual carrier dedicated to the virtual chip and stored, and the processing history of each of the multiple virtual chips is displayed, so that the processing history of the virtual chip can be properly managed.

[0021] According to the invention of technical solutions 3 and 4, the processing history of each of the multiple virtual chips is associated with the carrier registered as a virtual carrier dedicated to the virtual chip and stored, and the processing history of each of the multiple virtual chips is displayed, so that the processing history of the virtual chip can be properly managed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a top view showing the heat treatment apparatus of the present invention.

[0023] Figure 2 yes Figure 1 Front view of the heat treatment device.

[0024] Figure 3 It is a longitudinal sectional view showing the structure of the heat treatment section.

[0025] Figure 4 It is a perspective view showing the overall appearance of the holding portion.

[0026] Figure 5 This is a top view of the base.

[0027] Figure 6 is a cross-sectional view of the base.

[0028] Figure 7 It is a top view of the transfer mechanism.

[0029] Figure 8 It is a side view of the transfer mechanism.

[0030] Fig. 9 It is a top view showing the arrangement of a plurality of halogen lamps.

[0031] Fig.10 It is a block diagram showing the configuration of a control unit.

[0032] Fig.11 Yes means Figure 1 Flowchart of the management procedure of dummy wafers in a heat treatment apparatus.

[0033] Fig.12 This is a diagram showing an example of a vehicle ID authentication screen displayed on the display unit.

[0034] Fig.13 This is a diagram showing an example of a dummy chip management table. DETAILED DESCRIPTION

[0035] Below, while referring to the attached Figure 1 Embodiments of the present invention will be described in detail.

[0036] First, the heat treatment apparatus of the present invention will be described. Figure 1 is a top view showing a heat treatment apparatus 100 of the present invention, Figure 2 1 is a front view of the heat treatment apparatus 100. The heat treatment apparatus 100 is a flash lamp annealing apparatus that irradiates a circular plate-shaped semiconductor wafer W as a substrate with a flash to heat the semiconductor wafer W. The size of the semiconductor wafer W to be processed is not particularly limited, and is, for example, φ300 mm or φ450 mm. Impurities are injected into the semiconductor wafer W before being transported into the heat treatment apparatus 100, and the injected impurities are activated by the heat treatment performed by the heat treatment apparatus 100. In addition, Figure 1 In the following figures, the size or quantity of each part is exaggerated or simplified as necessary for easy understanding. Figure 1 to Figure 3 In each figure, in order to clarify their directional relationship, an XYZ orthogonal coordinate system is attached with the Z-axis direction as the vertical direction and the XY plane as the horizontal plane.

[0037] like Figure 1 and Figure 2As shown, the heat treatment apparatus 100 includes: an indexer section 101 for carrying unprocessed semiconductor wafers W into the apparatus from the outside and carrying out processed semiconductor wafers W from the outside; an alignment section 230 for positioning the unprocessed semiconductor wafers W; two cooling sections 130 and 140 for cooling the semiconductor wafers W after the heat treatment; a heat treatment section 160 for performing flash heat treatment on the semiconductor wafers W; and a transfer robot 150 for transferring the semiconductor wafers W to and from the cooling sections 130 and 140 and the heat treatment section 160. In addition, the heat treatment apparatus 100 includes a control section 3, which controls the motion mechanisms provided in the respective treatment sections and the transfer robot 150 so that the flash heat treatment of the semiconductor wafers W is performed.

[0038] The indexer unit 101 includes a loading port 110 on which a plurality of carriers C (two in the present embodiment) are placed side by side, and a transfer robot 120 for taking out unprocessed semiconductor wafers W from each carrier C and storing processed semiconductor wafers W in each carrier C. The carrier C containing the unprocessed semiconductor wafers W is transported and placed on the loading port 110 by an unmanned transport vehicle (AGV, OHT) or the like, and the carrier C containing the processed semiconductor wafers W is taken away from the loading port 110 by the unmanned transport vehicle.

[0039] In addition, in the loading port 110, the carrier C is configured to be Figure 2 The transfer robot 120 is moved up and down as shown by the arrow CU, so that the transfer robot 120 can take and place any semiconductor wafer W relative to the carrier C. In addition, a barcode reader 115 (not shown) is provided at the loading port 110 (see Fig.10 ). The barcode reader 115 reads the carrier ID according to the barcode on the label attached to the carrier C. In addition, as a form of the carrier C, in addition to a FOUP (front opening unified pod) that stores semiconductor chips W in a closed space, it can also be a SMIF (Standard Mechanical Interface Face) box or an OC (open cassette) that exposes the stored semiconductor chips W to the external atmosphere.

[0040] In addition, the transfer robot 120 can perform the following operations: Figure 1The hand 121 slides as shown by the arrow 120S, and the handover and lifting movements are shown by the arrow 120R. Thus, the delivery robot 120 takes and places the semiconductor wafer W relative to the two carriers C and delivers the semiconductor wafer W to the alignment unit 230 and the two cooling units 130, 140. The handover robot 120 takes and places the semiconductor wafer W relative to the carrier C by sliding the hand 121 and lifting the carrier C. In addition, the handover robot 120 delivers the semiconductor wafer W to the alignment unit 230 or the cooling units 130, 140 by sliding the hand 121 and lifting the handover robot 120.

[0041] The alignment unit 230 is connected to the side of the indexer unit 101 along the Y-axis direction. The alignment unit 230 is a processing unit that rotates the semiconductor wafer W in a horizontal plane and faces the flash heating in an appropriate direction. The alignment unit 230 is configured by arranging a mechanism that supports the semiconductor wafer W in a horizontal posture and rotates it, and a mechanism that optically detects the grooves or orientation flat surfaces formed on the peripheral portion of the semiconductor wafer W, etc., inside an alignment chamber 231 that is an aluminum alloy frame.

[0042] The delivery of the semiconductor wafer W to the alignment section 230 is performed by the delivery robot 120. The semiconductor wafer W is delivered from the delivery robot 120 to the alignment chamber 231 in such a manner that the center of the wafer is located at a specific position. In the alignment section 230, the semiconductor wafer W is rotated around the vertical axis with the center of the semiconductor wafer W received from the indexer section 101 as the rotation center, and the grooves and the like are optically detected, thereby adjusting the orientation of the semiconductor wafer W. The semiconductor wafer W whose orientation has been adjusted is taken out from the alignment chamber 231 by the delivery robot 120.

[0043] As a transfer space for the transfer robot 150 to transfer the semiconductor wafer W, a transfer chamber 170 for accommodating the transfer robot 150 is provided. The transfer chamber 170 is connected in three directions to the processing chamber 6 of the heat treatment unit 160, the first cooling chamber 131 of the cooling unit 130, and the second cooling chamber 141 of the cooling unit 140.

[0044] The heat treatment unit 160, which is a main part of the heat treatment apparatus 100, is a substrate processing unit that irradiates the preheated semiconductor wafer W with flash from a xenon flash lamp FL to perform flash heating. The configuration of the heat treatment unit 160 will be described in detail below.

[0045] The two cooling units 130 and 140 have substantially the same structure. The cooling units 130 and 140 are respectively provided with a metal cooling plate and a quartz plate placed on the upper surface of the cooling plate in the first cooling chamber 131 and the second cooling chamber 141 which are aluminum alloy frames (both are omitted in the figure). The temperature of the cooling plate is adjusted to room temperature (about 23° C.) by a Peltier element or a constant temperature water circulation. The semiconductor wafer W subjected to flash heat treatment by the heat treatment unit 160 is carried into the first cooling chamber 131 or the second cooling chamber 141 and placed on the quartz plate for cooling.

[0046] The first cooling chamber 131 and the second cooling chamber 141 are connected to the indexer section 101 and the transfer chamber 170 between the two. Two openings are formed in the first cooling chamber 131 and the second cooling chamber 141 for carrying in and out the semiconductor wafer W. Of the two openings of the first cooling chamber 131, the opening connected to the indexer section 101 can be opened and closed by the gate valve 181. On the other hand, the opening of the first cooling chamber 131 connected to the transfer chamber 170 can be opened and closed by the gate valve 183. That is, the first cooling chamber 131 is connected to the indexer section 101 via the gate valve 181, and the first cooling chamber 131 is connected to the transfer chamber 170 via the gate valve 183.

[0047] When the semiconductor wafer W is transferred between the indexer part 101 and the first cooling chamber 131, the gate valve 181 is opened. When the semiconductor wafer W is transferred between the first cooling chamber 131 and the transfer chamber 170, the gate valve 183 is opened. When the gate valves 181 and 183 are closed, the interior of the first cooling chamber 131 becomes a closed space.

[0048] In addition, of the two openings of the second cooling chamber 141, the opening connected to the indexer section 101 can be opened and closed by the gate valve 182. On the other hand, the opening of the second cooling chamber 141 connected to the transfer chamber 170 can be opened and closed by the gate valve 184. That is, the second cooling chamber 141 is connected to the indexer section 101 via the gate valve 182, and the second cooling chamber 141 is connected to the transfer chamber 170 via the gate valve 184.

[0049] When the semiconductor wafer W is transferred between the indexer part 101 and the second cooling chamber 141, the gate valve 182 is opened. When the semiconductor wafer W is transferred between the second cooling chamber 141 and the transfer chamber 170, the gate valve 184 is opened. When the gate valves 182 and 184 are closed, the interior of the second cooling chamber 141 becomes a closed space.

[0050] The cooling units 130 and 140 further include a gas supply mechanism for supplying clean nitrogen gas to the first cooling chamber 131 and the second cooling chamber 141 and an exhaust mechanism for exhausting the atmosphere in the chamber. The gas supply mechanism and the exhaust mechanism may be configured to switch the flow rate to two levels.

[0051] The transport robot 150 provided in the transport chamber 170 can rotate as shown by arrow 150R along the axis in the vertical direction. The transport robot 150 has two link mechanisms including a plurality of arm sections, and transport hands 151a and 151b for holding the semiconductor wafer W are provided at the front ends of the two link mechanisms, respectively. These transport hands 151a and 151b are arranged up and down at a specific interval, and can slide linearly and independently in the same horizontal direction through the link mechanisms. In addition, the transport robot 150 moves the two transport hands 151a and 151b up and down in a state of being separated by a specific interval by moving the base on which the two link mechanisms are provided up and down.

[0052] When the transfer robot 150 transfers (takes and places) the semiconductor wafer W with the first cooling chamber 131, the second cooling chamber 141, or the processing chamber 6 of the heat treatment unit 160 as the transfer partner, the two transfer hands 151a and 151b are first rotated in a manner facing the transfer partner, and then (or during the rotation) the transfer hands are moved up and down so that one of the transfer hands is at a height to transfer the semiconductor wafer W to the transfer partner. Then, the transfer hands 151a (151b) are moved to slide linearly in the horizontal direction to transfer the semiconductor wafer W to the transfer partner.

[0053] The transfer robot 150 and the delivery robot 120 can transfer the semiconductor wafer W through the cooling units 130 and 140. That is, the first cooling chamber 131 of the cooling unit 130 and the second cooling chamber 141 of the cooling unit 140 also function as a passage for transferring the semiconductor wafer W between the transfer robot 150 and the delivery robot 120. Specifically, the semiconductor wafer W transferred to the first cooling chamber 131 or the second cooling chamber 141 by one of the transfer robot 150 and the delivery robot 120 is received by the other component, and the semiconductor wafer W is transferred.

[0054] As described above, gate valves 181 and 182 are provided between the first cooling chamber 131 and the second cooling chamber 141 and the indexer section 101, respectively. In addition, gate valves 183 and 184 are provided between the transfer chamber 170 and the first cooling chamber 131 and the second cooling chamber 141, respectively. Moreover, a gate valve 185 is provided between the transfer chamber 170 and the processing chamber 6 of the heat treatment section 160. When the semiconductor wafer W is transferred into the heat treatment apparatus 100, these gate valves are opened and closed as appropriate. In addition, nitrogen gas is also supplied to the transfer chamber 170 and the alignment chamber 231 from the gas supply section, and the atmosphere inside the transfer chamber 170 and the alignment chamber 231 is exhausted by the exhaust section (both are omitted in the figure).

[0055] Next, the configuration of the heat treatment unit 160 will be described. Figure 3 1 is a longitudinal sectional view showing the structure of the heat treatment unit 160. The heat treatment unit 160 includes a processing chamber 6 for accommodating a semiconductor wafer W and performing a heat treatment, a flash lamp room 5 having a plurality of flash lamps FL built therein, and a halogen lamp room 4 having a plurality of halogen lamps HL built therein. The flash lamp room 5 is provided on the upper side of the processing chamber 6, and the halogen lamp room 4 is provided on the lower side. In addition, the heat treatment unit 160 includes a holding unit 7 for holding the semiconductor wafer W in a horizontal position inside the processing chamber 6, and a transfer mechanism 10 for transferring the semiconductor wafer W between the holding unit 7 and the transfer robot 150.

[0056] The processing chamber 6 is formed by installing chamber windows made of quartz on the upper and lower parts of a cylindrical chamber side portion 61. The chamber side portion 61 has a roughly cylindrical shape with openings at the upper and lower parts, and an upper chamber window 63 is installed at the upper opening to be closed, and a lower chamber window 64 is installed at the lower opening to be closed. The upper chamber window 63 constituting the top of the processing chamber 6 is a disk-shaped component formed of quartz, and functions as a quartz window that allows the flash emitted from the flash lamp FL to pass through into the processing chamber 6. In addition, the lower chamber window 64 constituting the floor portion of the processing chamber 6 is also a disk-shaped component formed of quartz, and functions as a quartz window that allows the light from the halogen lamp HL to pass through into the processing chamber 6.

[0057] In addition, a reflection ring 68 is installed on the upper part of the inner wall of the chamber side portion 61, and a reflection ring 69 is installed on the lower part. The reflection rings 68 and 69 are both formed in a circular ring shape. The upper reflection ring 68 is installed by embedding from the upper side of the chamber side portion 61. On the other hand, the lower reflection ring 69 is installed by embedding from the lower side of the chamber side portion 61 and fixing it with screws omitted from the figure. That is, the reflection rings 68 and 69 are both installed on the chamber side portion 61 so as to be freely loaded and unloaded. The inner space of the processing chamber 6, that is, the space surrounded by the upper chamber window 63, the lower chamber window 64, the chamber side portion 61 and the reflection rings 68 and 69 is defined as a heat treatment space 65.

[0058] By installing the reflection rings 68 and 69 on the chamber side portion 61, a recessed portion 62 is formed on the inner wall surface of the processing chamber 6. That is, the recessed portion 62 is formed to be surrounded by the central portion of the inner wall surface of the chamber side portion 61 where the reflection rings 68 and 69 are not installed, the lower end surface of the reflection ring 68, and the upper end surface of the reflection ring 69. The recessed portion 62 is formed in a circular ring shape in the horizontal direction on the inner wall surface of the processing chamber 6, surrounding the holding portion 7 holding the semiconductor wafer W. The chamber side portion 61 and the reflection rings 68 and 69 are formed of a metal material (e.g., stainless steel) having excellent strength and heat resistance.

[0059] In addition, a transport opening (furnace port) 66 for carrying in and out semiconductor wafers W relative to the processing chamber 6 is formed in the chamber side portion 61. The transport opening 66 can be opened and closed by the gate valve 185. The transport opening 66 is connected to the outer peripheral surface of the recess 62. Therefore, when the gate valve 185 opens the transport opening 66, the semiconductor wafer W can be carried into the heat treatment space 65 through the recess 62 from the transport opening 66 and can be carried out from the heat treatment space 65. In addition, when the gate valve 185 closes the transport opening 66, the heat treatment space 65 in the processing chamber 6 becomes a closed space.

[0060] In addition, a gas supply hole 81 for supplying a processing gas to the heat treatment space 65 is formed on the upper part of the inner wall of the processing chamber 6. The gas supply hole 81 is formed and arranged at a position higher than the recess 62, and can also be arranged on the reflection ring 68. The gas supply hole 81 is connected to the gas supply pipe 83 via a buffer space 82 formed in an annular shape inside the side wall of the processing chamber 6. The gas supply pipe 83 is connected to the processing gas supply source 85. In addition, a valve 84 is inserted in the middle of the path of the gas supply pipe 83. When the valve 84 is opened, the processing gas is transported from the processing gas supply source 85 to the buffer space 82. The processing gas flowing into the buffer space 82 flows in a manner of diffusion in the buffer space 82 where the fluid resistance is smaller than the gas supply hole 81, and is supplied from the gas supply hole 81 to the heat treatment space 65. As the processing gas, an inert gas such as nitrogen (N2) or a reactive gas such as hydrogen (H2) or ammonia (NH3) (nitrogen in this embodiment) can be used.

[0061] On the other hand, a gas discharge hole 86 for exhausting the gas in the heat treatment space 65 is formed at the lower part of the inner wall of the processing chamber 6. The gas discharge hole 86 is formed at a position lower than the recess 62, and can also be set on the reflection ring 69. The gas discharge hole 86 is connected to the gas discharge pipe 88 via a buffer space 87 formed in an annular shape inside the side wall of the processing chamber 6. The gas discharge pipe 88 is connected to the exhaust mechanism 190. In addition, a valve 89 is inserted in the middle of the path of the gas discharge pipe 88. When the valve 89 is opened, the gas in the heat treatment space 65 is discharged from the gas discharge hole 86 to the gas discharge pipe 88 via the buffer space 87. In addition, the gas supply hole 81 and the gas discharge hole 86 can also be set in a plurality along the circumferential direction of the processing chamber 6, or can be slit-shaped. In addition, the processing gas supply source 85 and the exhaust mechanism 190 can also be a mechanism set in the heat treatment device 100, or can be equipment for a factory where the heat treatment device 100 is set.

[0062] In addition, a gas exhaust pipe 191 for exhausting the gas in the heat treatment space 65 is also connected to the front end of the transfer opening 66. The gas exhaust pipe 191 is connected to the exhaust mechanism 190 via a valve 192. By opening the valve 192, the gas in the processing chamber 6 is exhausted through the transfer opening 66.

[0063] Figure 4 : is a perspective view showing the overall appearance of the holding part 7. The holding part 7 is composed of a base ring 71, a connecting part 72 and a base 74. The base ring 71, the connecting part 72 and the base 74 are all formed of quartz. That is, the holding part 7 is formed of quartz as a whole.

[0064] The base ring 71 is a quartz component in an arc shape with a portion missing from the circular ring. The missing portion is provided to prevent interference between the transfer arm 11 of the transfer mechanism 10 described below and the base ring 71. The base ring 71 is supported on the wall surface of the processing chamber 6 by being placed on the bottom surface of the recess 62 (see Figure 3 ). On the upper surface of the base ring 71, a plurality of connecting parts 72 (four in this embodiment) are vertically provided along the circumferential direction of the annular shape. The connecting part 72 is also a quartz component and is fixed to the base ring 71 by welding.

[0065] The base 74 is supported by four connection parts 72 provided on the base ring 71 . Figure 5 74 is a top view of the base. Figure 6 74. The susceptor 74 includes a holding plate 75, a guide ring 76, and a plurality of substrate support pins 77. The holding plate 75 is a substantially circular flat plate-shaped member formed of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. That is, the holding plate 75 has a larger plane size than the semiconductor wafer W.

[0066] A guide ring 76 is provided on the peripheral portion of the upper surface of the retaining plate 75. The guide ring 76 is a ring-shaped component having an inner diameter larger than the diameter of the semiconductor wafer W. For example, when the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm. The inner periphery of the guide ring 76 is formed as a tapered surface that widens upward from the retaining plate 75. The guide ring 76 is formed of the same quartz as the retaining plate 75. The guide ring 76 may be welded to the upper surface of the retaining plate 75, or may be fixed to the retaining plate 75 by a separately processed pin or the like. Alternatively, the retaining plate 75 and the guide ring 76 may be processed into an integral component.

[0067] The area on the upper surface of the holding plate 75 that is closer to the inner side than the guide ring 76 is set as a planar holding surface 75a for holding the semiconductor wafer W. A plurality of substrate support pins 77 are erected on the holding surface 75a of the holding plate 75. In the present embodiment, a total of 12 substrate support pins 77 are erected in units of 30° along a circumference that is concentric with the outer circumference of the holding surface 75a (the inner circumference of the guide ring 76). The diameter of the circle on which the 12 substrate support pins 77 are arranged (the distance between the opposing substrate support pins 77) is smaller than the diameter of the semiconductor wafer W. If the diameter of the semiconductor wafer W is φ300 mm, the diameter of the circle on which the 12 substrate support pins 77 are arranged is φ270 mm to φ280 mm (φ270 mm in the present embodiment). Each substrate support pin 77 is formed of quartz. A plurality of substrate support pins 77 may be set on the upper surface of the holding plate 75 by welding, or may be processed integrally with the holding plate 75.

[0068] Back to Figure 4 , the four connecting parts 72 erected on the base ring 71 are fixed to the peripheral part of the holding plate 75 of the base 74 by welding. That is, the base 74 and the base ring 71 are fixedly connected by the connecting parts 72. The base ring 71 of the holding part 7 is supported on the wall surface of the processing chamber 6, and the holding part 7 is installed in the processing chamber 6. When the holding part 7 is installed in the processing chamber 6, the holding plate 75 of the base 74 is in a horizontal posture (a posture in which the normal line is consistent with the vertical direction). That is, the holding surface 75a of the holding plate 75 is a horizontal plane.

[0069] The semiconductor wafer W carried into the processing chamber 6 is placed and held in a horizontal position on the susceptor 74 of the holding portion 7 installed in the processing chamber 6. At this time, the semiconductor wafer W is supported by 12 substrate support pins 77 vertically provided on the holding plate 75 and held on the susceptor 74. More strictly speaking, the upper ends of the 12 substrate support pins 77 contact the lower surface of the semiconductor wafer W to support the semiconductor wafer W. The heights of the 12 substrate support pins 77 (the distance from the upper ends of the substrate support pins 77 to the holding surface 75a of the holding plate 75) are uniform, so the semiconductor wafer W can be supported in a horizontal position by the 12 substrate support pins 77.

[0070] In addition, the semiconductor wafer W is supported by the plurality of substrate support pins 77 at a certain interval from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the substrate support pins 77. Therefore, the guide ring 76 prevents the horizontal positional deviation of the semiconductor wafer W supported by the plurality of substrate support pins 77.

[0071] In addition, if Figure 4 and Figure 5 As shown, an opening 78 is formed in the holding plate 75 of the base 74 so as to penetrate vertically. The opening 78 is for the radiation thermometer 20 (see Figure 3 ) is provided to receive radiation light (infrared light) emitted from the lower surface of the semiconductor wafer W held on the susceptor 74. That is, the radiation thermometer 20 receives the light emitted from the lower surface of the semiconductor wafer W held on the susceptor 74 through the opening 78 to measure the temperature of the semiconductor wafer W. The holding plate 75 of the susceptor 74 is also provided with four through holes 79 through which the lift pins 12 of the transfer mechanism 10 described below pass to transfer the semiconductor wafer W.

[0072] Figure 7 1 is a top view of the transfer mechanism 10. Figure 8 1 is a side view of the transfer mechanism 10. The transfer mechanism 10 includes two transfer arms 11. The transfer arms 11 are formed into an arc shape substantially along the annular recess 62. Two lift pins 12 are vertically provided on each transfer arm 11. Each transfer arm 11 can be rotated by a horizontal moving mechanism 13. The horizontal moving mechanism 13 enables a pair of transfer arms 11 to be in a transfer operation position ( Figure 7 The solid line position) is the retreat position ( Figure 7 The transfer action position is below the base 74, and the retreat position is further outside the base 74. The horizontal movement mechanism 13 may be a horizontal movement mechanism that rotates each transfer arm 11 separately by an independent motor, or a horizontal movement mechanism that rotates a pair of transfer arms 11 in conjunction with each other by a single motor using a link mechanism.

[0073] In addition, the pair of transfer arms 11 are moved up and down together with the horizontal moving mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, a total of four lift pins 12 pass through the through holes 79 (see FIG. 1 ) provided on the base 74. Figure 4 , 5), the upper end of the lift pin 12 protrudes from the upper surface of the base 74. On the other hand, when the lifting mechanism 14 lowers the pair of transfer arms 11 from the transfer action position and pulls the lift pin 12 out of the through hole 79, and the horizontal moving mechanism 13 moves the pair of transfer arms 11 in an open manner, each transfer arm 11 moves to the retreat position. The retreat position of the pair of transfer arms 11 is directly above the base ring 71 of the holding portion 7. Since the base ring 71 is placed on the bottom surface of the recess 62, the retreat position of the transfer arm 11 becomes the inner side of the recess 62. In addition, an exhaust mechanism (not shown) is also provided near the portion of the transfer mechanism 10 where the drive portion (the horizontal moving mechanism 13 and the lifting mechanism 14) is provided, and is constructed in a manner to exhaust the atmosphere around the drive portion of the transfer mechanism 10 to the outside of the processing chamber 6.

[0074] Back to Figure 3 The flash lamp room 5 disposed above the processing chamber 6 is composed of a light source including a plurality of (30 in the present embodiment) xenon flash lamps FL and a reflector 52 disposed so as to cover the upper part of the light source on the inner side of a frame 51. In addition, a light irradiation window 53 is installed at the bottom of the frame 51 of the flash lamp room 5. The light irradiation window 53 constituting the floor portion of the flash lamp room 5 is a plate-shaped quartz window formed of quartz. The flash lamp room 5 is disposed above the processing chamber 6, so that the light irradiation window 53 is opposed to the upper chamber window 63. The flash lamp FL irradiates the heat treatment space 65 with flash light from above the processing chamber 6 through the light irradiation window 53 and the upper chamber window 63.

[0075] The flash lamps FL are long cylindrical rod-shaped lamps arranged in a plane so that their length directions are parallel to each other along the main surface (i.e., in the horizontal direction) of the semiconductor wafer W held by the holding portion 7. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

[0076] The xenon flash lamp FL includes: a rod-shaped glass tube (discharge tube) in which xenon gas is sealed and an anode and a cathode connected to a capacitor are arranged at both ends; and a trigger electrode is attached to the outer peripheral surface of the glass tube. Xenon gas is an electrical insulator, so even if the capacitor accumulates electric charge, no electricity will flow in the glass tube under normal conditions. However, when a high voltage is applied to the trigger electrode to break the insulation, the electricity accumulated in the capacitor will flow in the glass tube instantaneously, and light will be emitted due to the excitation of xenon atoms or molecules. In this xenon flash lamp FL, the electrostatic energy previously accumulated in the capacitor is converted into an extremely short light pulse of 0.1 milliseconds to 100 milliseconds, so it has the characteristic of being able to irradiate extremely strong light compared to a light source that is continuously lit like a halogen lamp HL. That is, the flash lamp FL is a pulse light lamp that emits light instantaneously in an extremely short time of less than 1 second. In addition, the light emission time of the flash lamp FL can be adjusted by the coil constant of the lamp power supply that supplies power to the flash lamp FL.

[0077] In addition, the reflector 52 is provided above the plurality of flash lamps FL so as to cover the entire plurality of flash lamps FL. The basic function of the reflector 52 is to reflect the flash emitted from the plurality of flash lamps FL to the heat treatment space 65. The reflector 52 is formed of an aluminum alloy plate, and its surface (the surface facing the flash lamp FL side) is roughened by sandblasting.

[0078] The halogen lamp chamber 4 disposed below the processing chamber 6 has a plurality of (40 in this embodiment) halogen lamps HL built inside a frame 41. The plurality of halogen lamps HL irradiate the heat treatment space 65 with light from below the processing chamber 6 through the lower chamber window 64.

[0079] Fig. 9 2 is a top view showing the arrangement of a plurality of halogen lamps HL. In the present embodiment, 20 halogen lamps HL are arranged in each of the upper and lower sections. Each halogen lamp HL is a rod-shaped lamp having a long cylindrical shape. In the upper section and the lower section, the 20 halogen lamps HL are arranged in a manner that each length direction is parallel to each other along the main surface of the semiconductor wafer W held by the holding portion 7 (i.e., in the horizontal direction). As a result, in the upper section and the lower section, the planes formed by the arrangement of the halogen lamps HL are all horizontal planes.

[0080] In addition, if Fig. 9 As shown, in both the upper and lower sections, the halogen lamps HL are arranged at a higher density in the area opposite to the peripheral portion than in the area opposite to the central portion of the semiconductor wafer W held by the holding portion 7. That is, in both the upper and lower sections, the arrangement spacing of the halogen lamps HL in the peripheral portion is shorter than in the central portion of the lamp arrangement. Therefore, when heating is performed by light irradiation from the halogen lamps HL, a larger amount of light can be irradiated to the peripheral portion of the semiconductor wafer W, which is prone to temperature drop.

[0081] The upper halogen lamps HL and the lower halogen lamps HL are arranged in a grid-like manner. That is, a total of 40 halogen lamps HL are arranged so that the length direction of the upper halogen lamps HL is perpendicular to the length direction of the lower halogen lamps HL.

[0082] The halogen lamp HL is a filament-type light source that emits light by energizing a filament disposed inside a glass tube to turn the filament incandescent. Inside the glass tube, a gas in which a trace amount of halogen elements (iodine, bromine, etc.) are introduced into an inert gas such as nitrogen or argon is sealed. By introducing the halogen element, the breakage of the filament can be suppressed and the temperature of the filament can be set to a high temperature. Therefore, the halogen lamp HL has the characteristics of longer life and continuous irradiation of strong light compared to ordinary incandescent bulbs. That is, the halogen lamp HL is a continuously lit lamp that emits light continuously for at least 1 second. In addition, the halogen lamp HL has a long life because it is a rod-shaped lamp. By arranging the halogen lamp HL in the horizontal direction, the radiation efficiency to the semiconductor wafer W above becomes excellent.

[0083] In addition, a reflector 43 ( Figure 3 ). The reflector 43 reflects the light emitted from the plurality of halogen lamps HL toward the heat treatment space 65 side.

[0084] The control unit 3 controls the various operating mechanisms provided in the heat treatment apparatus 100 . Fig.10 This is a block diagram showing the structure of the control unit 3. The hardware structure of the control unit 3 is the same as that of a normal computer. That is, the control unit 3 has: a circuit for performing various calculations, namely a CPU (Central Processing Unit); a read-only memory for storing basic programs, namely a ROM (Read-Only Memory); a read-write memory for storing various information, namely a RAM (Random Access Memory); and a disk 35 pre-stored with control software or data. The processing in the heat treatment device 100 is performed by the CPU of the control unit 3 executing a specific processing program. In addition, in Figure 1 In FIG. 1 , the control unit 3 is shown in the indexer unit 101 , but the present invention is not limited thereto, and the control unit 3 may be arranged at any position in the heat treatment apparatus 100 .

[0085] like Fig.10 As shown, the control unit 3 includes a registration unit 31. The registration unit 31 is a functional processing unit implemented by the CPU of the control unit 3 executing a specific processing program. The processing content of the registration unit 31 will be further described below.

[0086] In addition, the control unit 3 is connected to a display unit 34, an input unit 33, and a barcode reader 115 of the loading port 110. The control unit 3 causes the display unit 34 to display various information. The operator of the heat treatment device 100 can input various commands or parameters from the input unit 33 while confirming the information displayed on the display unit 34. As the input unit 33, for example, a keyboard or a mouse can be used. As the display unit 34, for example, a liquid crystal display can be used. In the present embodiment, as the display unit 34 and the input unit 33, a liquid crystal touch panel provided on the outer wall of the heat treatment device 100 is used to have the functions of both the display unit and the input unit.

[0087] In addition to the above-mentioned structure, the heat treatment section 160 is also equipped with various cooling structures to prevent the heat energy generated by the halogen lamp HL and the flash lamp FL from causing the halogen lamp chamber 4, the flash lamp chamber 5 and the processing chamber 6 to overheat. For example, a water cooling pipe (not shown) is provided on the wall of the processing chamber 6. In addition, the halogen lamp chamber 4 and the flash lamp chamber 5 are made into an air cooling structure that forms a gas flow inside to discharge heat. In addition, air is also supplied to the gap between the upper chamber window 63 and the light radiation window 53 to cool the flash lamp chamber 5 and the upper chamber window 63.

[0088] Next, the processing operation of the heat treatment apparatus 100 of the present invention is described. Here, after describing the processing operation for a normal semiconductor wafer W, the management of a dummy wafer is described. The semiconductor wafer W to be processed is a semiconductor substrate to which impurities (ions) are added by an ion implantation method. The activation of the impurities is performed by flash irradiation heating treatment (annealing) performed by the heat treatment apparatus 100.

[0089] First, unprocessed semiconductor wafers W injected with impurities are placed on the loading port 110 of the indexer section 101 in a state where a plurality of wafers are accommodated in the carrier C. Then, the delivery robot 120 takes out the unprocessed semiconductor wafers W from the carrier C one by one and carries them into the alignment chamber 231 of the alignment section 230. In the alignment chamber 231, the semiconductor wafer W is rotated around the vertical axis in the horizontal plane with its center as the rotation center, and the grooves and the like are optically inspected, thereby adjusting the orientation of the semiconductor wafer W.

[0090] Next, the transfer robot 120 of the indexer unit 101 takes out the semiconductor wafer W whose orientation has been adjusted from the alignment chamber 231, and carries it into the first cooling chamber 131 of the cooling unit 130 or the second cooling chamber 141 of the cooling unit 140. The unprocessed semiconductor wafer W carried into the first cooling chamber 131 or the second cooling chamber 141 is carried out to the transfer chamber 170 by the transfer robot 150. When the unprocessed semiconductor wafer W is transferred from the indexer unit 101 to the transfer chamber 170 via the first cooling chamber 131 or the second cooling chamber 141, the first cooling chamber 131 and the second cooling chamber 141 function as a passage for transferring the semiconductor wafer W.

[0091] The transfer robot 150 that has taken out the semiconductor wafer W rotates toward the heat treatment unit 160. Next, the gate valve 185 opens the space between the processing chamber 6 and the transfer chamber 170, and the transfer robot 150 transfers the unprocessed semiconductor wafer W into the processing chamber 6. At this time, if the semiconductor wafer W that has been previously heat-treated is present in the processing chamber 6, one of the transfer hands 151a and 151b takes out the heat-treated semiconductor wafer W and then transfers the unprocessed semiconductor wafer W into the processing chamber 6 for wafer replacement. Then, the gate valve 185 closes the space between the processing chamber 6 and the transfer chamber 170.

[0092] After the semiconductor wafer W loaded into the processing chamber 6 is preheated by the halogen lamp HL, a flash heating process is performed by flash irradiation from the flash lamp FL. The impurities implanted in the semiconductor wafer W are activated by the flash heating process.

[0093] After the flash heat treatment is completed, the gate valve 185 opens the space between the processing chamber 6 and the transfer chamber 170 again, and the transfer robot 150 carries out the semiconductor wafer W after the flash heat treatment from the processing chamber 6 to the transfer chamber 170. The transfer robot 150 that has taken out the semiconductor wafer W rotates from the processing chamber 6 toward the first cooling chamber 131 or the second cooling chamber 141. In addition, the gate valve 185 closes the space between the processing chamber 6 and the transfer chamber 170.

[0094] Then, the transfer robot 150 transfers the semiconductor wafer W after the heat treatment into the first cooling chamber 131 of the cooling unit 130 or the second cooling chamber 141 of the cooling unit 140. At this time, if the semiconductor wafer W passes through the first cooling chamber 131 before the heat treatment, it is transferred to the first cooling chamber 131 after the heat treatment, and if the semiconductor wafer W passes through the second cooling chamber 141 before the heat treatment, it is transferred to the second cooling chamber 141 after the heat treatment. The semiconductor wafer W after the flash heat treatment is cooled in the first cooling chamber 131 or the second cooling chamber 141. The temperature of the semiconductor wafer W as a whole is relatively high when it is transferred out of the processing chamber 6 of the heat treatment unit 160, so the semiconductor wafer W is cooled to a temperature close to room temperature in the first cooling chamber 131 or the second cooling chamber 141.

[0095] After a specific cooling treatment time, the transfer robot 120 moves the cooled semiconductor wafer W out of the first cooling chamber 131 or the second cooling chamber 141 and returns it to the carrier C. After a specific number of processed semiconductor wafers W are placed on the carrier C, the carrier C is moved out of the loading port 110 of the indexer unit 101 .

[0096] The heat treatment in the heat treatment unit 160 is further described. Before the semiconductor wafer W is carried into the processing chamber 6, the valve 84 for gas supply is opened and the valves 89 and 192 for exhaust are opened to start supplying and exhausting gas in the processing chamber 6. When the valve 84 is opened, nitrogen gas is supplied from the gas supply hole 81 to the heat treatment space 65. In addition, when the valve 89 is opened, the gas in the processing chamber 6 is exhausted from the gas exhaust hole 86. As a result, the nitrogen gas supplied from the upper part of the heat treatment space 65 in the processing chamber 6 flows downward and is exhausted from the lower part of the heat treatment space 65.

[0097] In addition, by opening the valve 192, the gas in the processing chamber 6 is also exhausted from the transfer opening 66. The atmosphere around the driving part of the transfer mechanism 10 is also exhausted by the exhaust mechanism (not shown). In addition, when the semiconductor wafer W is heat-treated in the heat treatment part 160, nitrogen gas is continuously supplied to the heat treatment space 65, and its supply amount is appropriately changed according to the processing steps.

[0098] Next, the gate valve 185 is opened to open the transport opening 66, and the semiconductor wafer W to be processed is transported into the heat treatment space 65 in the processing chamber 6 through the transport opening 66 by the transport robot 150. The transport robot 150 moves the transport hand 151a (or the transport hand 151b) holding the unprocessed semiconductor wafer W in and out to a position just above the holding portion 7 and stops. Then, the pair of transfer arms 11 of the transfer mechanism 10 horizontally moves from the retreat position and rises to the transfer operation position, whereby the lift pins 12 protrude from the upper surface of the holding plate 75 of the base 74 through the through holes 79 to receive the semiconductor wafer W. At this time, the lift pins 12 rise to a position higher than the upper ends of the substrate support pins 77.

[0099] After the unprocessed semiconductor wafer W is placed on the lift pins 12, the transport robot 150 withdraws the transport hand 151a from the heat treatment space 65 and closes the transport opening 66 by the gate valve 185. Then, the pair of transfer arms 11 descends, whereby the semiconductor wafer W is transferred from the transfer mechanism 10 to the base 74 of the holding portion 7 and is held from below in a horizontal posture. The semiconductor wafer W is supported by a plurality of substrate support pins 77 vertically provided on the holding plate 75 and is held on the base 74. In addition, the semiconductor wafer W is held in the holding portion 7 with the surface where the impurities are injected for pattern formation as the upper surface. A specific gap is formed between the back surface (the main surface on the opposite side to the front side) of the semiconductor wafer W supported by the plurality of substrate support pins 77 and the holding surface 75a of the holding plate 75. The pair of transfer arms 11 that have descended to the bottom of the base 74 retreat to the retreat position, that is, the inside of the recess 62, by the horizontal moving mechanism 13.

[0100] After the semiconductor wafer W is held horizontally from below by the base 74 of the holding portion 7, 40 halogen lamps HL are lit together to start preheating (auxiliary heating). The halogen light emitted from the halogen lamps HL passes through the lower chamber window 64 and the base 74 formed of quartz to irradiate from the lower surface of the semiconductor wafer W. Due to the irradiation of light from the halogen lamps HL, the semiconductor wafer W is preheated and the temperature rises. In addition, since the transfer arm 11 of the transfer mechanism 10 retreats to the inner side of the recess 62, it will not hinder the heating performed by the halogen lamps HL.

[0101] When preheating is performed using the halogen lamp HL, the temperature of the semiconductor wafer W is measured by the radiation thermometer 20. That is, the radiation thermometer 20 receives infrared light radiated from the lower surface of the semiconductor wafer W held on the susceptor 74 through the opening 78 to measure the temperature of the wafer during heating. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 controls the output of the halogen lamp HL while monitoring whether the temperature of the semiconductor wafer W heated by the light irradiation from the halogen lamp HL reaches a specific preheating temperature T1. That is, the control unit 3 feedback controls the output of the halogen lamp HL based on the measured value obtained by the radiation thermometer 20 so that the temperature of the semiconductor wafer W reaches the preheating temperature T1. The preheating temperature T1 is set to about 600°C to 800°C (700°C in the present embodiment) at which there is no concern about the diffusion of impurities added to the semiconductor wafer W due to heat.

[0102] After the temperature of the semiconductor wafer W reaches the preheating temperature T1, the control unit 3 temporarily maintains the semiconductor wafer W at the preheating temperature T1. Specifically, when the temperature of the semiconductor wafer W measured by the radiation thermometer 20 reaches the preheating temperature T1, the control unit 3 adjusts the output of the halogen lamp HL so that the temperature of the semiconductor wafer W is maintained at approximately the preheating temperature T1.

[0103] By performing the preheating using the halogen lamp HL, the temperature of the semiconductor wafer W as a whole is uniformly raised to the preheating temperature T1. In the preheating stage using the halogen lamp HL, although there is a tendency that the temperature of the peripheral portion of the semiconductor wafer W, which is more likely to generate heat dissipation, is lower than that of the central portion, the arrangement density of the halogen lamps HL in the halogen lamp chamber 4 is higher in the area opposite to the peripheral portion than in the area opposite to the central portion of the semiconductor wafer W. Therefore, the amount of light irradiated to the peripheral portion of the semiconductor wafer W, which is more likely to generate heat dissipation, becomes larger, and the in-plane temperature distribution of the semiconductor wafer W in the preheating stage can be made uniform.

[0104] When a specific time has passed after the temperature of the semiconductor wafer W reaches the preheating temperature T1, the flash lamp FL flashes the surface of the semiconductor wafer W. At this time, a part of the flash emitted from the flash lamp FL is directly directed into the processing chamber 6, and another part is first reflected by the reflector 52 and then directed into the processing chamber 6, and the semiconductor wafer W is flash heated by the flash irradiation.

[0105] Flash heating is performed by flash (flash) irradiation from the flash lamp FL, so the surface temperature of the semiconductor wafer W can be raised in a short time. That is, the flash irradiated from the flash lamp FL is an extremely short and strong flash of about 0.1 milliseconds to 100 milliseconds, which is a flash in which the electrostatic energy previously stored in the capacitor is converted into an extremely short light pulse. Moreover, the surface temperature of the semiconductor wafer W flash-heated by the flash irradiation from the flash lamp FL instantly rises to a processing temperature T2 of more than 1000°C, and the impurities injected into the semiconductor wafer W are activated, and then the surface temperature drops rapidly. In this way, the surface temperature of the semiconductor wafer W can be raised and lowered in a very short time during flash heating, so the impurities injected into the semiconductor wafer W can be activated while suppressing the impurities from being diffused by heat. In addition, the time required for the activation of the impurities is extremely short compared to the time required for the thermal diffusion thereof, so the activation is completed even in a short time of about 0.1 milliseconds to 100 milliseconds, where diffusion does not occur.

[0106] After the flash heating treatment is completed, the halogen lamp HL goes out after a specific time has passed. As a result, the semiconductor wafer W is rapidly cooled from the preheating temperature T1. The temperature of the semiconductor wafer W during cooling is measured by the radiation thermometer 20, and the measurement result is transmitted to the control unit 3. The control unit 3 monitors whether the temperature of the semiconductor wafer W has dropped to a specific temperature based on the measurement result of the radiation thermometer 20. Then, after the temperature of the semiconductor wafer W drops below a specific temperature, the pair of transfer arms 11 of the transfer mechanism 10 moves horizontally from the retreat position again and rises to the transfer action position, whereby the lift pins 12 protrude from the upper surface of the base 74 and receive the heat-treated semiconductor wafer W from the base 74. Next, the transport opening 66 closed by the gate valve 185 is opened, and the processed semiconductor wafer W placed on the lift pins 12 is carried out by the transfer hand 151b (or transfer hand 151a) of the transfer robot 150. The transfer robot 150 moves the transfer hand 151b in and out to a position directly below the semiconductor wafer W lifted by the lift pins 12 and stops. Then, the pair of transfer arms 11 descends, thereby transferring and placing the semiconductor wafer W after flash heating on the transfer hand 151b. Then, the transfer robot 150 withdraws the transfer hand 151b from the processing chamber 6 and carries out the processed semiconductor wafer W.

[0107] In addition, typically, the semiconductor wafers W are processed in batch units. A batch refers to a group of semiconductor wafers W that are subjected to the same processing under the same conditions. In the heat treatment apparatus 100 of the present embodiment, a plurality of semiconductor wafers W (for example, 25) constituting a batch are accommodated in a carrier C and loaded on the loading port 110 of the indexer unit 101, and the semiconductor wafers W are sequentially carried from the carrier C one by one into the processing chamber 6 for heat treatment.

[0108] Here, when the batch processing is started by using the heat treatment device 100 that has not been processed for a period of time, the first semiconductor wafer W of the batch is moved into the processing chamber 6 at substantially room temperature for preheating and flash heating processing. This situation is, for example, when the heat treatment device 100 is started to process the first batch after maintenance or when a long time has passed after the previous batch has been processed. During the heating treatment, heat conduction occurs from the heated semiconductor wafer W to the chamber structure such as the susceptor 74, so the susceptor 74, which is initially at room temperature, gradually heats up due to heat storage as the number of processed semiconductor wafers W increases. In addition, part of the infrared light emitted from the halogen lamp HL is absorbed by the lower chamber window 64, so as the number of processed semiconductor wafers W increases, the temperature of the lower chamber window 64 also gradually increases.

[0109] Then, when the heat treatment of about 10 semiconductor wafers W is performed, the temperature of the susceptor 74 and the lower chamber window 64 reaches a certain stable temperature. In the susceptor 74 that has reached the stable temperature, the amount of heat transferred from the semiconductor wafer W to the susceptor 74 is balanced with the amount of heat dissipated from the susceptor 74. Before the temperature of the susceptor 74 reaches the stable temperature, the amount of heat transferred from the semiconductor wafer W is greater than the amount of heat dissipated from the susceptor 74, so as the number of processed semiconductor wafers W increases, the temperature of the susceptor 74 gradually rises due to heat storage. In contrast, after the temperature of the susceptor 74 reaches the stable temperature, the amount of heat transferred from the semiconductor wafer W is balanced with the amount of heat dissipated from the susceptor 74, so the temperature of the susceptor 74 is maintained at a certain stable temperature. In addition, after the temperature of the lower chamber window 64 reaches the stable temperature, the heat absorbed by the lower chamber window 64 from the irradiation light of the halogen lamp HL is balanced with the heat released from the lower chamber window 64, so the temperature of the lower chamber window 64 is also maintained at a certain stable temperature.

[0110] When the process is started in the processing chamber 6 at room temperature, there is a problem that the temperature history of the initial semiconductor wafer W of the batch and the semiconductor wafer W from the middle are not uniform due to the different temperatures of the structures of the processing chamber 6. In addition, there is also a case where the initial semiconductor wafer W is supported on the low-temperature susceptor 74 and flash heated, causing the wafer to warp. Therefore, before starting the batch process, a dummy operation is implemented in which a dummy wafer that is not the processing object is moved into the processing chamber 6 and preheated and flash heated in the same way as the semiconductor wafer W to be processed, so that the susceptor 74 and other chamber structures are heated to a stable temperature. By preheating and flash heating about 10 dummy wafers, the susceptor 74 and other chamber structures can be heated to a stable temperature. This dummy operation is performed not only when the process is started in the processing chamber 6 at room temperature, but also when the preheating temperature T1 or the processing temperature T2 is changed. As described above, since the dummy wafer is repeatedly preheated and flash heated, it is easy to cause the wafer to crack or warp, and it is necessary to properly manage the processing history of the dummy wafer. Next, management of dummy wafers in the heat treatment apparatus 100 will be described.

[0111] Fig.11 It is a flow chart showing the management order of the dummy wafer in the heat treatment device 100 of the present invention. The dummy wafer is a silicon wafer in the same disk shape as the semiconductor wafer W to be processed, and has the same size and shape as the semiconductor wafer W. However, the dummy wafer is not patterned or ion implanted. That is, the dummy wafer is a so-called bare wafer. The dummy wafer used for the dummy operation is contained in a carrier C (dummy carrier) dedicated to the dummy wafer that is different from the carrier C that accommodates the usual semiconductor wafer W. When performing the dummy operation, the carrier C dedicated to the dummy wafer is moved into the heat treatment device 100 and placed on the loading port 110 of the indexer part 101 (step S1). In addition, the form of the carrier C dedicated to the dummy wafer is the same as the carrier C that accommodates the usual semiconductor wafer W, and is a FOUP in the present embodiment.

[0112] When the carrier C is placed on the loading port 110, the barcode reader 115 reads the barcode of the label attached to the carrier C, thereby obtaining the carrier ID (step S2). The carrier ID is a symbol for identifying a plurality of carriers C, and is composed of, for example, a combination of letters and numbers. The carrier ID is uniquely marked on a plurality of carriers C (including a carrier C for accommodating ordinary semiconductor wafers W) used in a factory where the heat treatment apparatus 100 is installed. The carrier ID read by the barcode reader 115 is transmitted to the control unit 3.

[0113] Next, the vehicle ID authentication screen is displayed on the display unit 34 (step S3). Fig.122 is a diagram showing an example of a carrier ID authentication screen displayed on the display unit 34. The carrier ID read by the barcode reader 115, that is, the carrier ID of the carrier C loaded on the loading port 110, is displayed in the ID display field 212 of the authentication screen 210.

[0114] The operator of the heat treatment apparatus 100 selects whether to re-register the carrier C placed on the load port 110 as a dummy carrier dedicated to the dummy wafer (step S4). When the operator re-registers the carrier C placed on the load port 110 as a dummy carrier, the operator selects the "register" button 213 displayed on the authentication screen 210. On the other hand, when the operator does not re-register the carrier C, the operator selects the "do not register" button 214 displayed on the authentication screen 210. Typically, when the carrier C placed on the load port 110 has not been registered as a dummy carrier, the operator selects the "register" button 213 to register the carrier C. In addition, when the carrier C has already been registered as a dummy carrier, the operator selects the "do not register" button 214 because re-registration is not necessary.

[0115] When the "Register" button 213 is selected in the authentication screen 210, the process proceeds to step S5 to confirm whether the registration unit 31 of the control unit 3 has registered the carrier C placed in the loading port 110 as a dummy carrier. The dummy database 39 (see Fig.10 The dummy database 39 is a database that associates and registers the carrier ID of the dummy carrier with the processing history of each of the plurality of dummy wafers contained in the dummy carrier. The registration unit 31 determines whether the carrier ID of the carrier C loaded on the loading port 110 has been registered in the dummy database 39 according to the operation of selecting the "register" button 213 on the authentication screen 210.

[0116] As described above, the operator usually selects the "register" button 213 when the carrier C placed on the load port 110 has not yet been registered as a dummy carrier. However, there are cases where a dummy carrier that has already been registered is re-registered when all dummy wafers in the carrier C are replaced with new dummy wafers. In this case, the "register" button 213 is selected on the authentication screen 210 and the carrier ID of the carrier C placed on the load port 110 has already been registered in the dummy database 39.

[0117] In step S5, if it is determined that the carrier C placed on the load port 110 has been registered as a dummy carrier in the dummy database 39, the process proceeds to step S6, and the registration unit 31 overwrites the carrier ID of the carrier C into the dummy database 39. Then, the registration unit 31 initializes the parameters representing the processing history of the plurality of dummy wafers associated with the carrier ID of the carrier C in the dummy database 39 (step S8).

[0118] In this embodiment, the number of preheating times by the halogen lamp HL and the number of flash heating times by the flash lamp FL are used as parameters indicating the processing history of the dummy wafer. When the parameters are initialized in step S8, the registration unit 31 resets the number of preheating times and the number of flash heating times of the plurality of dummy wafers associated with the carrier ID of the carrier C in the dummy database 39 to 0.

[0119] On the other hand, in step S5, if it is determined that the carrier C placed on the load port 110 is not registered in the dummy database 39, the process proceeds to step S7, and the registration unit 31 re-registers the carrier ID of the carrier C in the dummy database 39. Then, the process proceeds to step S8, and the registration unit 31 initializes the parameters of the plurality of dummy wafers associated with the re-registered carrier ID. Specifically, the registration unit 31 sets the number of pre-heating times and the number of flash heating times of the plurality of dummy wafers associated with the re-registered carrier ID to 0.

[0120] Next, a dummy heat treatment is performed on the dummy wafer contained in the carrier C placed on the loading port 110 (step S9). The dummy heat treatment for the dummy wafer is the same as the normal heat treatment for the semiconductor wafer W to be processed. That is, the dummy wafer contained in the carrier C placed on the loading port 110 is transported to the processing chamber 6 of the heat treatment unit 160. In the heat treatment unit 160, after the dummy wafer is preheated by light irradiation from the halogen lamp HL, the surface of the dummy wafer is flash-heated by flash irradiation from the flash lamp FL. Then, the dummy wafer removed from the processing chamber 6 is returned to the original carrier C. Typically, about 10 dummy wafers are sequentially transported from the carrier C to the processing chamber 6 for dummy heat treatment and then returned to the carrier C again. By performing this dummy operation, the temperature of the chamber structure such as the susceptor 74 can be adjusted to the target stable temperature.

[0121] Each time the dummy heat treatment for the dummy wafer is completed, the registering unit 31 updates the parameters of the dummy wafer recorded in the dummy database 39 (step S10). Specifically, for example, when the dummy wafer accommodated in the slot No. 23 of the carrier C with the carrier ID "A145" is preheated by the halogen lamp HL and flash-heated by the flash lamp FL, the registering unit 31 increases the number of preheating times and the number of flash-heating times of the dummy wafer in the slot No. 23 of the carrier ID "A145" by 1, respectively.

[0122] On the other hand, when the "Do Not Register" button 214 is selected in step S4, the carrier C placed on the loading port 110 has already been registered in the dummy database 39 as a dummy carrier, and the registration of the carrier C or the initialization of the parameters are not performed again. The registration unit 31 retrieves the carrier ID read by the barcode reader 115 from the dummy database 39 to identify the carrier C placed on the loading port 110. Then, the process directly proceeds from step S4 to step S9, and a dummy heat treatment is performed on the dummy wafer accommodated in the carrier C placed on the loading port 110. Next, the process proceeds to step S10, and each time the dummy heat treatment for the dummy wafer is completed, the registration unit 31 updates the parameters of the dummy wafer recorded in the dummy database 39.

[0123] In addition, the dummy wafer management table is displayed on the display unit 34 when the operator of the heat treatment apparatus 100 selects the management table button 215 displayed on the authentication screen 210 or the like. Fig.13 2 is a diagram showing an example of a dummy chip management table. A selection box 251 is displayed in the dummy chip management table 250. Fig.13 In the example of FIG. 25 , any one of the 10 registered virtual vehicles can be selected from the selection box 251. The operator can select the desired virtual vehicle from the selection box 251. Fig.13 In the example, the No.4 dummy vehicle was selected.

[0124] The ID display column 252 of the dummy wafer management table 250 displays the carrier ID of the dummy carrier selected in the selection box 251. Alternatively, the operator can register the unregistered carrier C as a dummy carrier by inputting the carrier ID of the unregistered carrier C from the ID display column 252 of the dummy wafer management table 250.

[0125] The processing history display column 255 of the dummy wafer management table 250 displays the parameters associated with the carrier ID of the carrier C selected in the selection box 251 among the parameters registered in the dummy database 39. For example, when the carrier C with the carrier ID "A145" is selected from the selection box 251, the parameters of the plurality of (here, 25) dummy wafers associated with the carrier ID "A145" in the dummy database 39 are displayed in the processing history display column 255. In the present embodiment, the number of preheating times and the number of flash heating times are recorded in the dummy database 39 as parameters indicating the processing history of the dummy wafer, and therefore the number of preheating times and the number of flash heating times of the plurality of dummy wafers accommodated in the carrier C with the carrier ID "A145" are displayed in the processing history display column 255.

[0126] The operator of the heat treatment apparatus 100 selects a desired carrier C from the selection box 251, and the preheating times and flash heating times of the plurality of dummy wafers accommodated in the carrier C are displayed in the process history display column 255. The operator can appropriately manage the process history of the dummy wafers by checking the preheating times and flash heating times of the dummy wafers displayed in the process history display column 255.

[0127] For example, an operator who recognizes that the number of flash heating times of the dummy chip accommodated in slot number 24 of carrier C with carrier ID "A145" has exceeded 50 times by confirming the processing history display bar 255 can judge that the life of the dummy chip is approaching and the dummy chip needs to be replaced. When replacing the dummy chip in slot number 24 of carrier C with a new dummy chip, the operator resets the parameters (preheating times and flash heating times) of the dummy chip in slot number 24 to 0 by selecting the "Clear" button 256 of slot number 24. In addition, when replacing all the dummy chips accommodated in the carrier C with new dummy chips, the operator initializes the parameters of all the dummy chips to 0 by selecting the "Clear All" button 257. In addition, when closing the dummy chip management table 250, the operator can select the "Close" button 258.

[0128] In the present embodiment, a carrier C accommodating a plurality of dummy wafers is registered as a dummy carrier, and a dummy database 39 is stored in which the processing histories of the plurality of dummy wafers are associated with the carrier C. Then, the processing histories of the dummy wafers registered in the dummy database 39 are displayed in the dummy wafer management table 250. The operator of the heat treatment apparatus 100 can appropriately manage the processing histories of the dummy wafers by confirming the information displayed in the dummy wafer management table 250.

[0129] The above is a description of the embodiment of the present invention, but the invention can be modified in various ways beyond the above contents as long as it does not deviate from the main purpose. For example, in the above embodiment, the number of preheating times and the number of flash heating times are used as parameters to represent the processing history of the dummy wafer, but it is not limited to this. For example, the contamination degree of the dummy wafer can also be used as a parameter to represent the processing history. When the dummy heat treatment is performed in the atmosphere of the reactive processing gas, a film is formed on the surface of the dummy wafer and the contamination degree increases.

[0130] In the above embodiment, both preheating by the halogen lamp HL and flash heating by the flash lamp FL are performed as dummy heat treatment, but only one of the heating may be performed. In this case, the preheating number and the flash heating number displayed in the process history display column 255 are different.

[0131] In the above embodiment, the flash lamp room 5 is provided with 30 flash lamps FL, but the present invention is not limited thereto, and the number of flash lamps FL can be set to any number. In addition, the flash lamp FL is not limited to a xenon flash lamp, and can also be a krypton flash lamp. In addition, the number of halogen lamps HL provided in the halogen lamp room 4 is not limited to 40, and can be set to any number.

[0132] In addition, in the above-described embodiment, a filament-type halogen lamp HL is used as a continuous lighting lamp that continuously emits light for more than 1 second to preheat the semiconductor wafer W, but the present invention is not limited thereto, and a discharge-type arc lamp (e.g., a xenon arc lamp) may be used instead of the halogen lamp HL as a continuous lighting lamp for preheating. In this case, preheating of the dummy wafer is also performed by light irradiation from the arc lamp.

[0133] In addition, the substrate to be processed by the heat treatment apparatus 100 is not limited to a semiconductor wafer, and may be a glass substrate used for a flat panel display such as a liquid crystal display device or a substrate for a solar cell.

[0134] [Explanation of Symbols]

[0135] 3. Control Unit

[0136] 4 Halogen lamp housing

[0137] 5 Flash Room

[0138] 6 Processing Chamber

[0139] 7. Maintaining part

[0140] 10 Transfer mechanism

[0141] 31 Registration Department

[0142] 33 Input section

[0143] 34 Display

[0144] 35 Disk

[0145] 39 Dummy Database

[0146] 65 Heat treatment space

[0147] 74 Base

[0148] 100 Heat treatment device

[0149] 101 Indexer

[0150] 130, 140 Cooling unit

[0151] 150 Transport Robot

[0152] 151a, 151b Carrying hand

[0153] 160 Heat Treatment Department

[0154] 210 Authentication screen

[0155] 230 Alignment

[0156] 250 Virtual chip management table

[0157] 255 Processing history display bar

[0158] FL Flash

[0159] HL halogen lamp

[0160] W Semiconductor Wafer

Claims

1. A heat treatment method, characterized in that: Manage the dummy chips contained in the carrier and have: A loading step of loading a carrier containing a plurality of dummy wafers into a heat treatment device; A registration step of registering the carrier as a dummy carrier dedicated to the dummy wafer; A heating step of heating the plurality of dummy wafers; A storage step of associating the processing history of each of the plurality of dummy chips with the carrier for storage; and a display step of displaying the processing history of each of the plurality of dummy chips stored in the storage step; and In the storing step, the number of times of preheating by the continuous lighting lamp and the number of times of flash heating by the flash lamp related to each of the plurality of dummy wafers are associated with the carrier and stored.

2. A heat treatment device, characterized in that: Manage the dummy chips contained in the carrier and have: A receiving unit receives a carrier containing a plurality of dummy chips; a registering unit, registering the carrier moved into the receiving unit as a dummy carrier dedicated to a dummy wafer; A heating unit, for performing a heating process on the plurality of dummy wafers; A storage unit, storing the processing history of each of the plurality of dummy chips in association with the carrier; and A display unit displays the processing history of each of the plurality of dummy chips stored in the storage unit; and The heating unit includes a continuous lighting lamp and a flash lamp, and The storage unit stores the number of times of preheating by the continuous lighting lamp and the number of times of flash heating by the flash lamp related to each of the plurality of dummy wafers in association with the carrier.

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