Arithmetic logic unit, data processing system, method and module

Abstract

The present application discloses an arithmetic logic unit, a data processing system, a method and a module. An arithmetic logic unit (300) includes: an adding unit (320), the adding unit (320) is used to determine a sum (320i) of a first input (310a) and a second input (310b); and a logarithmic adding unit (330), the logarithmic adding unit (330) is used to use the sum (320i) and a third input (310c) to determine an output (340). When the first input (310a), the second input (310b) and the third input (310c) are represented in a logarithmic domain, the output (340) is a multiplication-accumulation output represented in the logarithmic domain.

Description

Technical Field

[0001] The present invention relates to an arithmetic logic unit, a data processing module, a system and a method. More specifically, the arithmetic logic unit, the data processing module, the system and the method operate in a logarithmic domain, wherein the input and output are in the logarithmic domain. Background Art

[0002] Many functions and processes undertaken by modern computing devices often require that the functions be implemented within the hardware of the device. The demand for increased speed and processing power in smaller devices means that it is desirable to reduce the area required for each of these functions. In particular, with the advent of neural networks, neural network accelerators are becoming more common. Neural network accelerators typically contain a number of arithmetic logic units ('ALUs'), each of which typically contains at least one multiplier accumulator ('MAC') unit. A typical MAC unit 100 is shown in FIG. Figure 1 The MAC unit 100 is arranged to receive a plurality of inputs 110a, 110b, 110c in order to perform a multiply-accumulate operation:

[0003] d = a*b+c (Equation 1)

[0004] The MAC unit 100 includes a multiplication section 120 and an addition section 130. If the MAC unit 100 is configured to receive 16-bit inputs 110a, 110b, 110c, the multiplication section 120 will include 15 16-bit adders, and the addition section 130 will include one 32-bit adder and receive the intermediate output 120i from the multiplication section 120. As a result, one MAC unit 100 requires a relatively large area within the ALU. Therefore, it is desirable to reduce the area required for each MAC unit 100 so that a greater number of MAC units 100 can be incorporated into a single ALU and thus increase the processing power and speed of a particular device. Summary of the invention

[0005] According to a first aspect of the present invention, an arithmetic logic unit is provided, comprising: an addition unit, the addition unit being used to determine the sum of a first input and a second input; and a logarithmic addition unit, the logarithmic addition unit being used to determine an output using the sum and a third input, wherein when the first input, the second input and the third input are represented in a logarithmic domain, the output is a multiplication-accumulation output represented in the logarithmic domain.

[0006] According to a second aspect of the present invention, a data processing system is provided, the data processing system comprising: a processor; a neural network accelerator, the neural network accelerator comprising one or more arithmetic logic units; and a storage device, wherein the arithmetic logic unit is configured to perform data processing operations in a logarithmic domain.

[0007] According to a third aspect of the present invention, there is provided a data processing module for generating an output, the module comprising: a maximum detection unit for determining a maximum value between a first input and a second input; a difference unit for determining a difference between the first input and the second input; and a decimal separation unit for determining an integer part and a decimal part of the difference, wherein when the first input and the second input are represented in a logarithmic domain, the output is represented in the logarithmic domain.

[0008] According to a fourth aspect of the present invention, there is provided a data processing method, the method comprising the following steps: receiving a first input and a second input; determining a maximum value between the first input and the second input; determining a difference between the first input and the second input; determining an integer part and a decimal part of the difference; calculating the inverse of the decimal part; shifting the inverse by the integer part to produce a shift value; adding the shift value and the maximum value to produce an output for use by a data processor, wherein, when the first input and the second input are represented in a logarithmic domain, the output is represented in the logarithmic domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Further features will become apparent from the following description, given by way of example only, with reference to the accompanying drawings in which like reference numerals are used to indicate similar features.

[0010] Figure 1 Schematically illustrates a known multiplier-accumulator unit;

[0011] Figure 2 is a flow chart showing a data processing method according to an embodiment;

[0012] Figure 3 schematically illustrates a multiplier-accumulator unit according to an embodiment;

[0013] Figure 4 Schematically illustrating the Figure 3 An internal component of a logarithmic addition module of a multiplier-accumulator unit;

[0014] Figure 5 schematically illustrates an arithmetic logic unit according to an embodiment;

[0015] Figure 6 Schematically shows Figure 2 Internal components of the neural network accelerator; and

[0016] Figure 7A computer device used with the data processing method according to the embodiment is schematically shown. DETAILED DESCRIPTION

[0017] With reference to the accompanying drawings, the details of the methods, systems, modules and arithmetic logic units according to the embodiments will become apparent from the following description. In this specification, for the purpose of illustration, many specific details of certain embodiments are set forth. Reference to "embodiment" or similar language in this specification means that a particular feature, structure or characteristic described together with the embodiment is included in at least one embodiment, but not necessarily in other embodiments. It should be further noted that certain embodiments are schematically described, and certain features are omitted and / or necessarily simplified for ease of illustration and understanding of the concepts underlying the embodiments.

[0018] Figure 2 2 is a flow chart showing a data processing method 200 according to an embodiment. The data processing method 200 may be implemented as part of a multiplier-accumulator (MAC) unit, such as Figure 3 MAC unit (described below).

[0019] At item 210 of the data processing method 200, a first input and a second input are received. The first input and the second input are bit values ​​represented in the logarithmic domain. That is, the first input (such as Figure 1 The input 110a) shown in can be represented as:

[0020] A = log2(a) (Equation 2)

[0021] Similarly, a second input (such as Figure 1 The input 110b) shown in FIG. 1 can be represented as:

[0022] B = log2(b) (Equation 3)

[0023] In some embodiments, it will be appreciated that one or more of these inputs may be the result of earlier processing, for example, one of the inputs may be the sum of two other inputs to a processing device or system.

[0024] Upon receiving two inputs, the maximum of the two inputs is determined at step 220 such that:

[0025] M = max(A, B) (Equation 4)

[0026] In addition, the difference between the first input and the second input is also determined at step 230. In some embodiments, the absolute value of the difference is calculated at step 230. It should be appreciated that, depending on the input to the method, the calculated difference may be less than zero, in which case the absolute value of the difference may be obtained. Such that:

[0027] S = |AB| (Equation 5)

[0028] At step 240, the integer and fractional parts of the difference calculated at step 230 are determined. In some embodiments, this is determined by rounding the result of the difference from step 230 down to the nearest integer value and subtracting the rounded result from the difference calculated at step 230 to determine the fractional part. That is:

[0029]

[0030] F = SI (Equation 7)

[0031] At step 250, the fractional portion of the difference is negated. That is, when operating in a binary base, the negation step at 250 acts as a logical NOT. For example, when the fractional portion is equal to 00110011, the negated fractional portion will be equal to 11001100. That is:

[0032]

[0033] The negated fractional portion is then right shifted at step 260 by the number of bits equal to the integer portion of the difference. In binary this is represented by a right shift, however when operating in base 10 (i.e. decimal), this represents a division of the integer portion to the power of 2. That is, in binary:

[0034]

[0035] Or in decimal:

[0036]

[0037] At step 270, the shift value calculated at step 260 and the maximum value calculated at step 220 are added together and output to the data processor at step 280. That is:

[0038] D = M + E (Equation 11)

[0039] In summary, although each of steps 210 to 280 of method 200 is expressed using a mathematical equation, each of equations 2 to 11 can be implemented in hardware, for example by using logic gates (such as AND, OR, NOR, XOR, and NOT) to perform addition in the logarithmic domain, such that:

[0040]

[0041] Figure 3A MAC unit 300 is schematically shown for use in the logarithmic domain. The MAC unit 300 receives three inputs 310a, 310b, 310c, each represented in the logarithmic domain, such as A and B of equations 2 and 3 above. The MAC unit 300 includes a first module 320 and a second module 330. The first module 320 is an addition module for determining the multiplication between the first input 310a and the second input 310b. When the MAC unit operates in the logarithmic domain:

[0042] log(a×b)=log(a)+log(b) (Equation 13)

[0043] Therefore, operating in the logarithmic domain removes the need for multiplication parts such as Figure 1 In the case of using 16-bit input values, the above requirement on Figure 1 Fifteen 16-bit adders are mentioned.

[0044] However, when the MAC unit 300 operates in the logarithmic domain, Figure 1 The addition portion 130 of the MAC unit 100 may no longer provide an accurate output value 140 because it is designed to perform the addition function in the linear domain. Therefore, a logarithmic addition module 330 is required. The logarithmic addition module 330 can be implemented as described above with respect to Figure 2 The logarithmic addition module 330 receives the intermediate output 320i from the first module 320 and the third input 310c also represented in the logarithmic domain. This can produce an output 340 represented in the logarithmic domain, which when compared with the output 340 represented in the logarithmic domain using Figure 1 The MAC unit 100 has a maximum relative error of 6% when compared to the corresponding output 140 in the linear domain, thereby ensuring accurate results while reducing cost and power consumption and allowing a processing device to include a larger number of MAC units 300 in the same area.

[0045] In one embodiment, the logarithmic addition module 330 may be implemented in hardware (such as Figure 4 It can be implemented by hardware in . Figure 4 Schematically shows Figure 3 330 of the MAC unit 300. It should be appreciated that other methods and modules may be used to achieve similar outputs based on multiply-accumulate functions in the logarithmic domain, where the error degree varies when compared to a substantially equivalent multiply-accumulate function in the linear domain.

[0046] As mentioned above, the logarithmic addition module 330 may receive the third input 310c and Figure 3The third input 310c and the intermediate output 320i can be represented in the logarithmic domain. The logarithmic addition module 330 includes a Figure 2 The method 200 is used to perform a plurality of units 410-460 of logarithmic addition.

[0047] The third input 310c and the intermediate output 320i may be provided to a maximum detection unit 410. The maximum detection unit 410 includes hardware, for example, logic gates such as AND, OR, NOR, XOR, and NOT, for determining the maximum of the third input 310c and the intermediate output 320i.

[0048] The third input 310c and the intermediate output 320i may also be provided to a difference unit 420 capable of determining the difference between the third input 310c and the intermediate output 320i. The difference unit 420 may include logic gates and / or other components for first subtracting the intermediate output 320i from the third input 310c to calculate the difference. The difference unit 420 may also include logic gates and / or other components for determining the modulus of a particular input and / or determining which of the third input 310c and the intermediate output 320i is larger. For example, in the case where the intermediate output 320i is greater than the third input 310c, this is then output to the decimal separation unit 430. In other embodiments where the third input 310c is greater than the intermediate output 320i, these values ​​may be negated so that the difference unit 420 subtracts the intermediate output 320i from the third input 320c, or alternatively performs the same subtraction as above (i.e., subtracting the third input 320c from the intermediate output 320i), and then uses the logic for determining the modulus to calculate the absolute value of the result. In either embodiment, the result is the same and is provided to the decimal separation unit 430 .

[0049] The fraction separation unit 430 generates an integer part and a fractional part from the output of the difference unit 420. The fraction separation unit 430 may include an integer determination unit 432 and a fraction determination unit 434 for generating the integer part and the fractional part, respectively. The integer determination unit 432 and the fraction determination unit 434 both include logic gates and / or other components for generating the integer part and the fractional part.

[0050] The integer determination unit 432 includes logic gates and / or components for rounding down an input value, which is the output of the difference unit 420, to the nearest integer. That is, the integer determination unit 432 applies the equivalent of a floor function to the output of the difference unit 420.

[0051] Fractional determination unit 434 includes logic capable of determining the difference between the output of difference unit 420 and the output of integer determination unit 432. This is accomplished by subtracting the outputs of integer determination unit 432 and difference unit 420.

[0052] The output of the decimal determination unit 434 is then provided to the negation unit 440. The negation unit 440 includes a logic NOT gate for negating the output of the decimal determination unit 434. For example, the output of the negation unit 440 will be 10001001 in the case where the output of the decimal determination unit 434 is 01110110.

[0053] The output of negation unit 440 is then provided to shift unit 450 along with the output of integer determination unit 432 of fraction determination unit 430. Shift unit 450 includes logic gates and / or other components, such as registers, for performing a right shift, wherein the output of negation unit 440 is right shifted by the number of bits representing the output of the integer determination unit. Continuing with the above embodiment where the output of negation unit 440 is 10001001, if the output of integer determination unit 432 is four (4), the output of shift unit 450 will be 00001000, wherein 10001001 has been right shifted by 4 bits.

[0054] The output of the shift unit 450 is then provided to an addition unit 460 along with the maximum of the third input 310c and the intermediate output 320i output by the maximum detection unit 410. The addition unit 460 includes logic gates and / or other components to determine the outputs of the maximum detection unit 410 and the shift unit 450. The output 340 of the addition unit 460 may then be provided for use in a data processor or a neural network accelerator such as a Figure 6 Used in other components such as those described below.

[0055] When used as a multiplier-accumulator (such as Figure 3 300) operating in the logarithmic domain, the output 340 is at least a known multiplier-accumulator (such as Figure 1 An approximation of the logarithmic representation of the multiply-accumulate output 140 of the MAC unit 100).

[0056] Figure 5 An arithmetic logic unit ('ALU') 500 is schematically shown according to an embodiment. The ALU 500 may be configured to perform data processing operations. Figure 5 In the ALU (which may be a system (such as for example Figure 7 One of the many ALUs in the system 700 described below includes a Figure 3 and Figure 4MAC unit 300 operates in the logarithmic domain as described. In other embodiments, an ALU for such a data processing system may include other components or may include components such as those described with respect to Figure 3 As described in the logarithmic domain and as above for Figure 1 A plurality of MAC units 100, 300 operating in the linear domain are described. Figure 5 The data processing operation that the MAC unit 300 is configured to perform is a multiplication-addition operation in the logarithmic domain. As described below, this can be used to implement the classification stage of a machine learning system (in this embodiment, a neural network).

[0057] In the embodiments described herein, ALU 500 may include a register arranged to receive an output of a data processing operation, the register including a plurality of one-bit storage devices arranged to store binary data of a predetermined data size. For example, in the case where ALU 500 includes a register configured to perform an addition operation using first module 310 and to perform a logarithmic addition operation using second module 320 (e.g., in accordance with Figure 2 MAC unit (such as the method described in Figure 3 In the case of the MAC unit 300 described above, the data processing operation can be considered as an addition operation or a logarithmic addition operation. If the data processing operation is considered to be an addition operation, the register is arranged to receive the output of the addition operation. Conversely, if the data processing operation is considered to be an addition operation, the register is arranged to receive the output of the logarithmic addition operation.

[0058] exist Figure 5 In an embodiment, the inputs 510a, 510b, 510c of the ALU 500 may be retrieved from a storage device (not shown). The storage device is, for example, external to the ALU 500 and may be a random access memory (RAM) such as DDR-SDRAM (double data rate synchronous dynamic random access memory). In other embodiments, the storage device may be or include a non-volatile memory such as a read-only memory (ROM) or a solid-state drive (SSD) such as a flash memory. The storage device in an embodiment may include another storage device, such as a magnetic, optical or tape medium, a compact disk (CD), a digital versatile disk (DVD), or other data storage medium. The storage device may be removable or non-removable from the computer device.

[0059] The inputs 510a, 510b, 510c may be stored in the linear domain and therefore would be incompatible with the MAC unit 300. Therefore, the inputs 510a, 510b, 510c would need to be transformed into the logarithmic domain. Therefore, the ALU 500 may also include a logarithmic conversion unit 520 for converting the inputs 510a, 510b, 510c in the linear domain into the logarithmic domain so that they can be used as inputs 310a, 310b, 310a of the MAC unit 300 of the ALU 500. It should be appreciated that although Figure 5 The ALU 500 shows a single MAC unit 300 and a single logarithmic conversion unit 520, but the ALU 500 may include a plurality of MAC units each connected to a single logarithmic conversion unit 520, or alternatively a plurality of logarithmic conversion units 520 associated with a plurality of MAC units 300. The number of logarithmic conversion units 520 does not necessarily have to be equal to the number of MAC units 300.

[0060] In some embodiments, ALU 500 may include a plurality of registers, each of which is arranged to store data at various stages. For example, each of inputs 510a, 510b, 510c may be transferred from a storage device to one or more input registers. The input registers provide inputs (sometimes referred to as operands) to data processing operations (such as logarithmic conversion). ALU 500 may also include a plurality of intermediate registers for receiving logarithmic conversion outputs from logarithmic conversion unit 520 and configured to provide inputs to further data processing operations (in this embodiment, addition operations implemented by first module 310 of MAC unit 300). The addition operation may be considered as a first data processing operation because the ALU is capable of performing multiple data processing operations in this embodiment.

[0061] The output 340 of the MAC unit 300 may also be stored in one or more registers for use in further data processing operations. In some embodiments, the output 340 may also / alternatively be stored in a storage device, which may or may not be the same storage device as the input 510a, 510b, 510c as described above.

[0062] Although it should be understood that Figure 5 The ALU 500 shown in FIG. 5 includes a logarithmic conversion unit 320, but a system and / or data processor including the ALU 500 may operate only in the logarithmic domain and thus does not require such a logarithmic conversion unit 320. Alternatively, the logarithmic conversion unit 320 may be external to the ALU 500, for example, the logarithmic conversion unit 320 may be a processor or a neural network accelerator (such as with respect to FIG. Figure 6 part of the description below).

[0063] Due to the high power consumption of neural networks, for example during classification of images or other data, the processing of the neural network may be performed using a neural network accelerator 600 dedicated to this process. Figure 6 The internal components of the neural network accelerator 600 are schematically shown in FIG.

[0064] The neural network accelerator 600 includes a plurality of ALUs 500a, 500b, and 500c. Figure 5 The components of one of the ALUs 500a are shown in more detail in . The ALUs 500a, 500b, 500c are each arranged to perform a multiply-accumulate operation as described above, which may be used, for example, to perform convolutions required by a neural network.

[0065] The neural network accelerator 600 includes an interface 630, via which a computer device (such as Figure 7 Other components of a computer device (described below) receive inputs to the neural network. For example, the CPU may include software configured to determine at least one parameter related to a data processing operation arranged to be implemented by an ALU (such as one of ALUs 500a, 500b, 500c of neural network accelerator 600). The ALU typically includes at least one MAC unit 300 (typically an array of MAC units), but other ALUs are possible. In general, ALU 500 can be considered to be any electronic circuit that can perform arithmetic and bitwise operations on binary numbers. The at least one parameter can therefore be transferred to the neural network accelerator 600 via interface 630. In other embodiments, the at least one parameter can be determined by the neural network accelerator 600 itself, for example using hardware.

[0066] Other inputs that may be received by the neural network accelerator 600 via the interface 630 include image data representing an image to be classified using the neural network and kernel data representing kernels associated with the neural network after training. For example, the neural network may be trained by a computer device or by an external computer device or computer system, such as using a GPU. The output of the training may be a plurality of kernels associated with a predetermined neural network architecture (e.g., where different kernels are associated with different corresponding layers of a multi-layer neural network architecture). The kernel data may be considered to correspond to weight data representing weights to be applied to the image data, as each element of the kernel may be considered to correspond to a weight, respectively. Each of these weights may be multiplied by a corresponding pixel value of an image patch as part of a convolution of the kernel with the image patch.

[0067] Figure 6The neural network accelerator 600 also includes direct memory access (DMA) that allows the neural network accelerator 600 to directly access the storage device independently of the CPU. This can improve the speed at which the neural network accelerator 600 can perform classification of input data. For example, the neural network accelerator 600 can directly access input to the classification process from the storage device (which can be main memory or system memory) without having to wait for the CPU to obtain it using direct memory 620 access. For example, at least one parameter, image data, and kernel data can be stored in the storage device and retrieved from the storage device by the neural network accelerator 600.

[0068] The neural network accelerator 600 includes a static random access memory (SRAM) 610, which can be used to store inputs to the classification process implemented by the ALUs 500a, 500b, 500c. For example, the SRAM can be an on-chip or local memory of the neural network accelerator 600, which is generally faster to access than a storage device. The SRAM can include multiple separate storage areas. For example, image data can be stored in a different storage area than kernel data (although in some cases, they can be stored in the same storage area).

[0069] exist Figure 7 The data processing method according to the embodiment (such as Figure 2 An embodiment of a computer device 700 for use with a method). Figure 7 The computer device 700 is a personal computer. However, in other embodiments, other computer devices such as smart phones, laptops, tablets, or onboard computer devices that can be coupled to or installed in a vehicle such as a car can be used to perform the methods described herein.

[0070] The computer device 700 includes at least one processor. In this embodiment, the computer device 700 includes a central processor unit (CPU) 710. The computer device 700 also includes a neural network accelerator 600, which is a processor dedicated to using a neural network to implement at least classification of data. However, in other embodiments, the computer device 700 may include other or alternative processors, such as a microprocessor designed to perform the functions described herein, a general-purpose processor, an image signal processor (ISP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any suitable combination thereof. The computer device 700 may also or alternatively include a processor implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. The computer device may also or alternatively include at least one graphics processing unit (GPU).

[0071] Figure 7 The CPU 710 includes a driver 720 that, for example, provides an interface between software configured to control or configure a neural network and a neural network accelerator 600 that is configured to perform processing to implement a neural network. However, in other embodiments, a more general processor (such as a CPU or a GPU) may be used to implement the neural network.

[0072] Figure 7 The computer device 700 also includes a dynamic memory controller (DMC) 740, which can be used to control access to a storage device 750 of the computer device 700. The storage device 750 is, for example, external to the neural network accelerator 600 and can be a random access memory (RAM) such as DDR-SDRAM (double data rate synchronous dynamic random access memory). In other embodiments, the storage device 750 can be or include a non-volatile memory such as a read-only memory (ROM) or a solid-state drive (SSD) such as a flash memory. The storage device 750 in an embodiment may include another storage device, such as a magnetic, optical or tape medium, a compact disk (CD), a digital versatile disk (DVD), or other data storage medium. The storage device 750 may be removable or non-removable from the computer device 700.

[0073] Figure 7 The components of the computer device 700 in the embodiment of the present invention are interconnected using a system bus 760. This allows data to be transferred between the various components. The bus 760 can be or include any suitable interface or bus. For example, a system bus 760 can be used. Advanced Microcontroller Bus Architecture Interface, such as Advanced Extensible Interface (AXI).

[0074] As explained above, Figure 7 The computer device 700 of the embodiment may be arranged to implement a classification stage of a neural network.

[0075] The order of the processing steps in the above-mentioned embodiment is only an embodiment. In other embodiments, these processing steps can be performed in a different order.

[0076] It should be understood that any feature described with respect to any one embodiment may be used alone or in combination with other features described, and may also be used in combination with one or more features of any other embodiment or any combination of any other embodiment. In addition, equivalents and modifications not described above may also be adopted without departing from the scope of the appended claims.

Claims

1. An arithmetic logic unit for generating an output in a logarithmic domain, comprising: an adding unit, the adding unit being configured to determine a sum of the first logarithmic input and the second logarithmic input; as well as a logarithmic adding unit for determining an output using a third logarithmic input and the sum, the logarithmic adding unit comprising: a maximum detection unit, the maximum detection unit being used to determine a maximum value between the third logarithmic input and the sum; a difference unit for determining a difference between the third logarithmic input and the sum; A decimal separation unit, the decimal separation unit is used to determine the integer part and the decimal part of the difference; a negation unit, the negation unit being used to determine a negation amount of the decimal part; a shift unit, configured to shift the negated amount by the integer part to generate a shift value; and An adding unit is configured to determine the output, wherein the output is a sum of the shift value and the maximum value. 2 . The arithmetic logic unit according to claim 1 , comprising a logarithmic conversion unit for converting data from a linear domain to the logarithmic domain to generate at least one of the first logarithmic input and the second logarithmic input.

3. An arithmetic logic unit according to claim 1, comprising one or more registers arranged to receive the output, the one or more registers comprising a plurality of one-bit storage devices, and wherein, The third logarithmic input is derived from the one or more registers.

4. The arithmetic logic unit according to claim 1, wherein: The difference unit comprises a modulus unit for determining an absolute value of the difference.

5. The arithmetic logic unit according to claim 1, wherein: The fraction separation unit includes a rounding module for rounding the difference value and a second subtraction unit for determining a second difference value between the difference value and the rounded difference value.

6. A method for generating an output in a logarithmic domain, the method comprising the steps of: receiving a first logarithmic input and a second logarithmic input; Determining a sum of the first logarithmic input and the second logarithmic input; determining a maximum value between a third logarithmic input and the sum; determining a difference between the third logarithmic input and the sum; determining an integer portion and a fractional portion of the difference; Calculate the negation of the decimal part; Shifting the negated amount by the integer portion to produce a shifted value; as well as The shift value and the maximum value are added to produce an output for use by a data processor.

7. The method according to claim 6, wherein: The step of determining the difference further includes determining an absolute value of the difference, and wherein the step of determining the integer part and the fractional part includes rounding the difference to produce a rounded value and calculating a second difference between the difference and the rounded value.

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