Semiconductor device and control method thereof

Abstract

Provided are a semiconductor device capable of preventing a decrease in reliability and usable as a bidirectional switch, and a control method for the semiconductor device. The semiconductor device includes: a power circuit chip (3) having a first semiconductor element (2a) and a second semiconductor element (2b), the first semiconductor element (2a) and the second semiconductor element (2b) sharing an n-type semiconductor region therebetween, p-type well regions being provided separately from each other above the semiconductor region, an n-type source region of the first semiconductor element (2a) being provided above one of the well regions, and an n-type source region of the second semiconductor element (2b) being provided above the other well region; and a control circuit chip (5) having a drive circuit (6) that supplies a first drive signal and a second drive signal, which are independent of each other, to a gate electrode of the first semiconductor element and a gate electrode of the second semiconductor element, respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a control method thereof, and more particularly to a power semiconductor device that can be used in a main switch circuit for protection in an electrical circuit and a control method thereof. Background Art

[0002] In Patent Document 1, a bidirectional power switch is proposed for use in a power conversion device or the like. In addition, in a drive circuit for automotive electrical equipment, a semiconductor switch is arranged on the upstream side in order to prevent damage to an electronic control unit (ECU) or the like. When an abnormality occurs in the drive circuit or the like, the circuit is cut off by the semiconductor switch to protect the ECU. In addition, in an electrical circuit used in an automobile or the like, the battery may sometimes be reversely connected by mistake, so a technique for preventing damage to the ECU or the like is sought.

[0003] Conventionally, in order to prevent damage to an electrical circuit or the like, a semiconductor switch formed by two-dimensionally arranging discrete devices such as n-type MIS (Metal-Insulator-Semiconductor) transistors is used. In a conventional bidirectional semiconductor switch, for example, the source electrode of the first MIS transistor is connected to the source electrode of the second MIS transistor. In the semiconductor switch, during normal use, the first MIS transistor and the second MIS transistor are made conductive, and current is passed from the drain electrode of the first MIS transistor to the drain electrode of the second MIS transistor. When a large current flows due to an abnormality in the load or the like, the first and second MIS transistors are made non-conductive to prevent damage to the load or the like. However, when a discrete device product such as an MIS transistor is two-dimensionally arranged to realize a semiconductor switch, the mounting area is large, and it is difficult to miniaturize the electrical circuit.

[0004] In Patent Document 2, the following structure is proposed: a bidirectional semiconductor switch is provided on one chip by sharing the drain electrode of the MIS transistor. In such a semiconductor switch, during normal use, current is passed from the source electrode of the first MIS transistor through the shared drain electrode to the source electrode of the second MIS transistor. In this case, the first MIS transistor is reversely connected, but it can be made conductive by increasing the gate voltage. In addition, since the body diode of the first MIS transistor is forwardly connected, current can also flow through the body diode. When an abnormality occurs in the load or the like or when the battery is reversely connected, the first MIS transistor and the second MIS transistor are made non-conductive to prevent damage to the electrical circuit and wiring that are connected to the power supply through the semiconductor switch.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent Publication No. 4178331

[0008] Patent Document 2: Japanese Patent Publication No. 5990437 SUMMARY OF THE INVENTION

[0009] Problems to be Solved by the Invention

[0010] In a bidirectional semiconductor switch with a shared drain electrode, parasitic bipolar transistors are formed with the p-type well regions of the first MIS transistor and the second MIS transistor serving as the emitter region and the collector region respectively, and the shared drain region serving as the base region. There is a concern that when there is a deviation in the driving timing for turning the first MIS transistor and the second MIS transistor on or off, the parasitic bipolar transistors operate, thereby degrading the reliability of the semiconductor switch.

[0011] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device and a control method for the semiconductor device that can prevent a decrease in reliability and can be used as a bidirectional switch or the like.

[0012] Solutions for Solving the Problems

[0013] To solve the above problems, the gist of one aspect of the semiconductor device according to the present invention is a semiconductor device including: (a) a first semiconductor element and a second semiconductor element. To form a main switch circuit, the first semiconductor element and the second semiconductor element have a shared region formed by a semiconductor region of a first conductivity type, and a first well region of a second conductivity type and a second well region of a second conductivity type are provided separately from each other above the shared region. A first source region of the first conductivity type of the first semiconductor element is provided above the first well region, and a second source region of the first conductivity type of the second semiconductor element is provided above the second well region; and (b) a drive circuit that supplies independent first drive signals and second drive signals to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element respectively.

[0014] Another aspect of the present invention lies in a control method for a semiconductor device. (a) The semiconductor device has a main switch circuit, which includes an insulated-gate type first semiconductor element and an insulated-gate type second semiconductor element. The first semiconductor element and the second semiconductor element have a semiconductor layer of a first conductivity type as a common region. A first well region of a second conductivity type and a second well region of a second conductivity type are provided separately from each other above the common region. In the first semiconductor element, a first surface electrode electrically connected to a power supply terminal is provided on the upper surface of a second main electrode region of the first conductivity type provided above the first well region. In the second semiconductor element, a second surface electrode electrically connected to an output terminal is provided on the upper surface of a fourth main electrode region provided above the second well region. The control method for this semiconductor device includes: (b) applying a first drive signal to the control electrode of the first semiconductor element to control the conduction and cutoff of the first semiconductor element; and (c) independently of the first drive signal, applying a second drive signal to the control electrode of the second semiconductor element to control the conduction and cutoff of the second semiconductor element, wherein the conduction and cutoff of the second drive signal are switched during the period when the first semiconductor element is in the conduction state.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide a semiconductor device and a control method for a semiconductor device that can prevent a decrease in reliability and can be used as a bidirectional switch or the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a block diagram showing an example of a semiconductor device according to a first embodiment of the present invention.

[0018] Figure 2 It is a circuit diagram showing an example of the operation of the main switch circuit of the semiconductor device according to the first embodiment of the present invention.

[0019] Figure 3 It is a schematic cross-sectional view showing an example of a power circuit chip of the semiconductor device according to the first embodiment of the present invention.

[0020] Figure 4 It is a timing diagram for explaining a control method of the main switch circuit.

[0021] Figure 5 It is a timing diagram showing an example of the control method of the semiconductor device according to the first embodiment of the present invention.

[0022] Figure 6 It is a top view showing an example of the semiconductor device according to the first embodiment of the present invention.

[0023] Figure 7 is a cross-sectional view of the main part of a semiconductor device taken perpendicularly along the A-A line of Figure 6 .

[0024] Figure 8 is a circuit diagram showing an example of a semiconductor device according to a first embodiment of the present invention.

[0025] Figure 9A is a circuit diagram showing a structural example of a booster circuit of a semiconductor device according to a first embodiment of the present invention.

[0026] Figure 9B is a diagram showing Figure 9A the rise of the output voltage of the booster circuit shown.

[0027] Figure 10 is a circuit diagram showing an example of a semiconductor device according to a second embodiment of the present invention.

[0028] Figure 11A is a circuit diagram showing a structural example of a booster circuit of a semiconductor device according to a second embodiment of the present invention.

[0029] Figure 11B is a diagram showing Figure 11A the rise of the output voltage of the booster circuit shown.

[0030] Figure 12 is a timing diagram showing an example of a control method of a semiconductor device according to a second embodiment of the present invention.

[0031] Figure 13A is a circuit diagram showing another structural example of a booster circuit of a semiconductor device according to a second embodiment of the present invention.

[0032] Figure 13B is a diagram showing Figure 13A the rise of the output voltage of the booster circuit shown.

[0033] Figure 14A is a circuit diagram showing yet another structural example of a booster circuit of a semiconductor device according to a second embodiment of the present invention.

[0034] Figure 14B is a diagram showing Figure 14A the rise of the output voltage of the booster circuit shown.

[0035] Figure 15 is a timing diagram showing another example of a control method of a semiconductor device according to a second embodiment of the present invention.

[0036] Explanation of Reference Numerals

[0037] 1: Main switch circuit; 2a: First semiconductor element; 2b: Second semiconductor element; 3: Power circuit chip; 4: Temperature sensor; 5: Control circuit chip; 6: Drive circuit; 7: Output circuit; 8: Overheat detection circuit; 9: Logic circuit; 10: Low voltage detection circuit; 11: Internal power supply; 12: Power supply node; 13: Output node; 14: Ground node; 15: Input node; 16: Processing circuit; 17a, 17b, 17c, 17d: Boost circuit; 18a, 18b, 24, 28, 32: Logic NOT circuit (inverter); 19a, 19b: Charge extraction semiconductor element; 20: Load; 22: External power supply; 50: Drift region; 51: Common drain region (first main electrode region and third main electrode region); 52: Semiconductor region; 53a, 53b, 54a, 54b: Well region; 53a: First well region; 53b: Second well region; 54a: Third well region; 54b: Fourth well region; 55: Channel stop region; 56a, 56b: Contact region; 57a: First source region (second main electrode region); 57b: Second source region (fourth main electrode region); 58a, 58b: Element isolation film; 59a, 59b: Trench; 60a, 60b: Gate insulating film; 61a, 61b: Gate electrode (control electrode); 61A, 61B: Gate lead electrode; 61C: Field plate electrode; 62a, 62b: Interlayer insulating film; 63a, 63b, 63c, 63d: Source contact layer; 64a, 64b, 64c, 64d: Source electrode; 65a, 65b: Source electrode pad; 66a, 66b: Gate electrode pad; 67: Drain electrode; 69: Protective film; 112, 113, 114, 115, 116: Lead terminal; 121, 122, 123, 124, 125, 126: Bonding wire; 130: Resin package. Detailed implementation mode

[0038] The first and second implementation modes of the present invention will be described below. In the following descriptions of the drawings, the same or similar parts are labeled with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each device and each component, etc. are different from the actual situation. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are also parts in the drawings where the dimensional relationships and ratios between each other are different.

[0039] In addition, the directions of "left and right" and "up and down" in the following description are only definitions for convenience of explanation and are not used to limit the technical idea of the present invention. Therefore, for example, if the paper surface is rotated by 90 degrees, "left and right" and "up and down" are exchanged for reading, and if the paper surface is rotated by 180 degrees, "left" becomes "right" and "right" becomes "left", which goes without saying. In addition, in the following description, the case where the first conductivity type is p-type and the second conductivity type is n-type is illustratively described. However, the conductivity types can also be selected to be in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, the + and - attached to p and n refer to semiconductor regions with relatively higher or lower impurity densities respectively compared to the semiconductor regions without the attached + and -. However, even for semiconductor regions with the same p and p attached, it does not mean that the impurity densities of the respective semiconductor regions are strictly the same.

[0040] Regarding the "first main electrode region or the third main electrode region" of each semiconductor element used in the main switch circuit of the semiconductor device, in a field effect transistor (FET) and a static induction transistor (SIT), it refers to the semiconductor region that is either the source region or the drain region. Regarding the "second main electrode region or the fourth main electrode region", in an FET and an SIT, it refers to the semiconductor region that is either the source region or the drain region and is not the above-mentioned first main electrode region or the third main electrode region. Thus, if the "first main electrode region or the third main electrode region" of each semiconductor element used in the main switch circuit is the drain region, the "second main electrode region or the fourth main electrode region" refers to the source region. If the biasing relationship is exchanged, in a symmetrically configured FET or the like, the functions of the "first main electrode region or the third main electrode region" and the "second main electrode region or the fourth main electrode region" can be exchanged. In addition, the "control electrode" refers to the electrode that controls the main current flowing between the first main electrode region and the second main electrode region or the main current flowing between the third main electrode region and the fourth main electrode region. For example, in an FET and an SIT, it is the gate electrode that controls the main current flowing between the source region and the drain region.

[0041] (First Embodiment)

[0042] As Figure 1 shown, the semiconductor device according to the first embodiment of the present invention includes a power circuit chip 3 and a control circuit chip 5. The power circuit chip 3 includes a main switch circuit 1 and a temperature sensor 4. The main switch circuit 1 is a bidirectional switch formed by a first semiconductor element 2a and a second semiconductor element 2b. The main switch circuit 1 is a bidirectional switch formed by commonly using the drain electrodes (the first main electrode and the third main electrode) of the first semiconductor element 2a and the second semiconductor element 2b and connecting them in opposite directions. The source electrode (the second main electrode) of the first semiconductor element 2a is connected to the power supply (V CC)The power supply node 12 for connection is connected, and the source electrode (fourth main electrode) of the second semiconductor element 2b is connected to the output node 13 for output (OUT). The temperature sensor 4 detects the temperature change caused by the energization of the main switch circuit 1.

[0043] The control circuit chip 5 includes a drive circuit 6, an output circuit 7, an overheat detection circuit 8, a low-voltage detection circuit 10, a logic circuit 9, and an internal power supply 11. The drive circuit 6 is connected to the gate electrodes (control electrodes) of the first semiconductor element 2a and the second semiconductor element 2b to drive the first semiconductor element 2a and the second semiconductor element 2b. The output circuit 7 is connected to the output node 13 to control the output of the main switch circuit 1. The overheat detection circuit 8 obtains the temperature detected by the temperature sensor 4 to detect overheating caused by a short circuit or the like of the load connected to the output node 13. The low-voltage detection circuit 10 detects a voltage drop of an external power supply such as a battery connected to the power supply node 12. The logic circuit 9 is connected to the drive circuit 6, the output circuit 7, the overheat detection circuit 8, and the low-voltage detection circuit 10. The logic circuit 9 is connected to the input node 15 for input (IN) of signals and the like. The logic circuit 9 sends a drive signal of the main switch circuit 1 to the drive circuit 6. In addition, when overheating and voltage drop are detected by the overheat detection circuit 8 and the low-voltage detection circuit 10, the logic circuit 9 sends a cut-off signal of the main switch circuit 1 to the drive circuit 6. The internal power supply 11 supplies a power supply voltage to the logic circuit 9. The ground (GND) wirings of the power circuit chip 3 and the control circuit chip 5 are connected to the ground node 14.

[0044] As the first semiconductor element 2a and the second semiconductor element 2b, preferably semiconductor elements with an insulated gate structure such as MIS field effect transistors (FETs) and MIS static induction transistors (SITs) are used. The first semiconductor element 2a and the second semiconductor element 2b can be either a vertical structure or a horizontal structure. However, for the purpose of understanding the following description, preferably, the first semiconductor element 2a and the second semiconductor element 2b have a vertical structure in which the main current flows in the depth direction of the chip. Hereinafter, the case where an MISFET using a trench gate structure of silicon (Si) is used as the first semiconductor element 2a and the second semiconductor element 2b will be described. However, as long as the gist of the present invention is understood from the following description, those skilled in the art should naturally understand that even a planar gate structure MIS transistor has the same effect. In addition, as the semiconductor materials of the first semiconductor element 2a and the second semiconductor element 2b, in addition to Si, semiconductor materials having a bandgap wider than the bandgap of Si of 1.1 eV, such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN), can be used respectively. In addition, the MIS transistor is a concept including MISFET and MISSIT.

[0045] As Figure 1 shown, the source S and drain D of the MIS transistor Tr1 of the first semiconductor element 2a are connected in reverse parallel to the anode and cathode of the body diode Di1, respectively. Further, the drain D and source S of the MIS transistor Tr2 of the second semiconductor element 2b are connected in reverse parallel to the cathode and anode of the body diode Di2, respectively. The gate G of the MIS transistor Tr1 and the gate G of the MIS transistor Tr2 are independently connected to the drive circuit 6. An external load is connected to the source S of the MIS transistor Tr2 of the second semiconductor element 2b via the output node 13.

[0046] Use Figures 2 to 4 to describe the operation when driving the main switch circuit 1 according to the first embodiment by the control method. As Figure 2 shown, the source S of the MIS transistor Tr1 of the first semiconductor element 2a is connected to an external power source 22 such as a battery of an automobile or the like, and the source S of the MIS transistor Tr2 of the second semiconductor element 2b is connected to a load 20 such as an ECU. Voltage signals (H (high) level) above the threshold are respectively applied from the drive circuit 6 to the gates G of the MIS transistors Tr1 and Tr2 to bring the MIS transistors Tr1 and Tr2 into the on state together. In this case, as Figure 2 indicated by the dashed line, current flows from the external power source 22 through the main switch circuit 1 to the load 20. Although the source S and drain D of the MIS transistor Tr1 are reversely connected, the MIS transistor Tr1 can be brought into the on state by increasing the gate voltage. When an abnormality occurs in the load 20 and a large current flows, voltage signals (L (low) level) lower than the threshold are sent from the drive circuit 6 to each gate G to cut off the MIS transistors Tr1 and Tr2. Although the body diode Di1 is in the on state, the MIS transistor Tr2 is in the cut-off state, so that the current can be cut off.

[0047] As Figure 3As shown, the main switch circuit 1 according to the first embodiment includes a first semiconductor element 2a and a second semiconductor element 2b. The drift region 50 is formed by epitaxially growing an n-type semiconductor region 52 on the upper surface of a common drain region 51. In addition, second conductivity type (p-type) well regions 53a, 53b, 54a, 54b and a p-type channel stop region 55 are provided in the semiconductor region 52. The first well region 53a and the second well region 53b function as base regions. The third well region 54a and the fourth well region 54b function as RESURF (REduced SURface Field) regions. The first well region 53a, the second well region 53b and the channel stop region 55 have substantially the same depth from the upper surface. The depths of the third well region 54a and the fourth well region 54b from the upper surface are deeper than the depths of the first well region 53a and the second well region 53b from the upper surface.

[0048] An n+ type first source region (second main electrode region) 57a is provided on the upper surface of the first well region 53a, and an n+ type second source region (fourth main electrode region) 57b is provided on the upper surface of the second well region 53b. Grooves 59a and 59b are provided which are in contact with the first source region 57a ​​and the second source region 57b, the first well region 53a and the second well region 53b, and the semiconductor region 52 in sequence from the surface of the semiconductor region 52. Gate electrodes (control electrodes) 61a and 61b are buried through gate insulating films 60a and 60b provided on the inner side walls and bottom surfaces of the trenches 59a and 59b, thereby forming insulated gate type electrode structures (60a, 61a), (60b, 61b). The gate insulating films 60a and 60b are made of, for example, silicon oxide (SiO 2) Films and the like, and the gate electrodes 61a and 61b use, for example, polycrystalline Si films. Grooves reaching the first well region 53a and the second well region 53b from the surface of the semiconductor region 52 are provided above the first well region 53a and the second well region 53b. Above the first well region 53a and the second well region 53b, p+-type contact regions 56a and 56b with a higher impurity concentration than the first well region 53a and the second well region 53b and connected to the bottoms of the grooves are provided. Source electrodes 64a and 64b are buried inside the grooves with source contact layers 63a and 63b interposed therebetween. Grooves reaching the third well region 54a and the fourth well region 54b from the surface of the semiconductor region 52 are provided above the third well region 54a and the fourth well region 54b. Above the third well region 54a and the fourth well region 54b, p+-type contact regions 56a and 56b with a higher impurity concentration than the third well region 54a and the fourth well region 54b and connected to the bottoms of the grooves are provided. Source electrodes 64c and 64d are buried inside the grooves with source contact layers 63c and 63d provided inside the grooves interposed therebetween. The source contact layers 63a and 63b use, for example, nickel silicide (NiSix) films and the like. The source electrodes 64a and 64b use, for example, aluminum (Al)-based aluminum alloy and the like.

[0049] Element isolation films 58a and 58b formed by local oxidation (LOCOS) or the like are provided on the upper surface of the semiconductor region 52 between the third well region 54a and the fourth well region 54b and the channel stopper region 55. Gate lead electrodes 61A and 61B electrically connected to the gate electrodes 61a and 61b are provided on the upper surfaces of the element isolation films 58a and 58b on the sides of the third well region 54a and the fourth well region 54b. A field plate electrode 61C is provided on the upper surface of the element isolation film 58a and 58b on the side of the channel stopper region 55. The gate lead electrodes 61A and 61B and the field plate electrode 61C use, for example, polycrystalline Si films and the like.

[0050] Interlayer insulating films 62a and 62b are provided on the gate electrodes 61a and 61b, the gate lead electrodes 61A and 61B, and the field plate electrode 61C. The source electrodes 64a, 64b, 64c, and 64d exposed between the respective interlayer insulating films 62a and 62b are physically connected to source electrode pads (surface electrodes) 65a and 65b formed of Al or the like, respectively. The gate lead electrodes 61A and 61B exposed between the respective interlayer insulating films 62a and 62b are physically connected to gate electrode pads 66a and 66b formed of Al or the like. On the lower surface of the common drain region 51, a drain electrode (back surface electrode) 67 is provided using, for example, a metal film formed of an aluminum (Al)-based aluminum alloy, gold (Au), or the like, or a stacked film thereof.

[0051] As Figure 3As shown, the MIS transistors Tr1 and Tr2 are trench gate type MIS transistors having insulated gate electrode structures (60a, 61a) and (60b, 61b), respectively. The body diodes Di1 and Di2 are composed of p+-type contact regions 56a and 56b, p-type well regions 53a, 53b, 54a, and 54b, and an n-type semiconductor region 52 and an n+-type common drain region 51. The channel stopper region 55 is formed in an annular shape in a planar form on the outer peripheries of the first semiconductor element 2a and the second semiconductor element 2b, respectively. The channel stopper region 55 between the first semiconductor element 2a and the second semiconductor element 2b is shared by the first semiconductor element 2a and the second semiconductor element 2b to form one region.

[0052] Figure 4 The voltage in represents the voltage of the gates G of the MIS transistors Tr1 and Tr2. As shown in (a), in a normal energized state, an H-level signal is applied as a drive signal to the gates G of the MIS transistors Tr1 and Tr2 from the drive circuit 6 substantially simultaneously. At this time, as shown by the dashed line in Figure 3 , current flows from the first source region 57a through the inversion layer formed in the first well region 53a, the common drain region 51, and the inversion layer formed in the second well region 53b to the second source region 57b. When the drive signal becomes an L level, the MIS transistors Tr1 and Tr2 are cut off substantially simultaneously.

[0053] As Figure 3 shown, the MIS transistors Tr1 and Tr2 are provided such that the common drain region 51 and the semiconductor region 52 are shared. Therefore, a parasitic bipolar transistor is formed with the p-type third well region 54a as the emitter E, the n+-type common drain region 51 or the n-type semiconductor region 52 as the base B, and the p-type fourth well region 54b as the collector C.

[0054] As Figure 4 shown in (b) of, there is a case where the application of the drive signal from the drive circuit 6 has a deviation, and the MIS transistor Tr2 rises with a delay time Dr earlier than the MIS transistor Tr1 to become an energized state. Conventionally, one signal line is branched from the drive circuit to apply the drive signal to the gates G of the MIS transistors Tr1 and Tr2. In this case, for example, the following occurs: the control of the transmission timing of the drive signal of the drive circuit 6 is poor, resulting in a deviation in the drive timing. In addition, the power supply voltage V is applied from the source S of the upstream MIS transistor Tr1. CC . Therefore, the voltage applied to the downstream MIS transistor Tr2 is more likely to drop compared to the upstream MIS transistor Tr1. Therefore, for the drive signal of the same voltage level, the MIS transistor Tr2 operates earlier than the MIS transistor Tr1. In Figure 4During the delay time Dr shown in (b), the MIS transistor Tr1 is in the off state, but the body diode Di1 is in the on state. As a result, the base potential is applied between the emitter E and the base B of the parasitic bipolar transistor, and the parasitic bipolar transistor operates.

[0055] In addition, as Figure 4 shown in (b), if the drive signal of the MIS transistor Tr2 has a signal width similar to that of the MIS transistor Tr1, the parasitic bipolar transistor does not operate during the fall delay time Df. Conversely, as Figure 4 shown in (c), when the drive signal of the MIS transistor Tr2 is applied with a delay compared to the MIS transistor Tr1, the parasitic bipolar transistor operates during the fall delay time Df. In this case, the parasitic bipolar transistor does not operate during the rise delay time Dr. Thus, when the MIS transistor Tr1 is in the off state and the MIS transistor Tr2 is in the on state, the parasitic bipolar transistor operates. When the parasitic bipolar transistor operates, there is a possibility that an unwanted current flows in the main switch circuit 1, resulting in problems such as a decrease in reliability.

[0056] In the first embodiment, as Figure 1 shown, signal lines are independently connected from the drive circuit 6 to the gates G of the MIS transistors Tr1 and Tr2 respectively. For example, as Figure 5 shown, the drive timing is controlled such that the width of the drive signal applied to the MIS transistor Tr1 is wide, and the H-level signal is applied to the MIS transistor Tr2 only when the MIS transistor Tr1 is in the state of being applied with the H-level signal. The parasitic bipolar transistor does not operate regardless of whether it is during the rise delay time Dr or the fall delay time Df. In addition, in Figure 5 , the voltage represents the voltages of the gates G of the MIS transistors Tr1 and Tr2. Thus, according to the first embodiment, the drive circuit 6 can apply independent drive signals to the gates G of the MIS transistors Tr1 and Tr2 respectively. As a result, the operation of the parasitic bipolar transistor can be prevented, and a bidirectional switch capable of preventing a decrease in reliability can be realized.

[0057] <Structure of semiconductor device>

[0058] Figure 6 is a top view showing a structural example of the semiconductor device according to the first embodiment. In Figure 6 , in order to show the inside of the semiconductor device, it is shown in a perspective view of the resin package 130. As Figure 6As shown, the semiconductor device according to the first embodiment includes lead frames (111, 112, 113, 114, 115, 116), a power circuit chip 3, a control circuit chip 5, and a resin package 130. The power circuit chip 3 is mounted on the lead frames (111 to 116). The control circuit chip 5 is stacked on the power circuit chip 3. The lead frames (111 to 116) have chip pads 111 and lead terminals 112, 113, 114, 115, 116. The chip pad 111 is electrically connected to the drain electrode 67 of the power circuit chip 3. The lead terminals 112, 113, 114, 115, 116 are respectively electrically connected to the electrode pads of the power circuit chip 3 and the control circuit chip 5.

[0059] As Figure 7 shown, the power circuit chip 3 is supported and fixed on the chip pad 111 by a conductive bonding member such as solder. An insulating protective film 69 such as a polyimide film is provided on the upper surface of the power circuit chip 3. An opening is provided in the protective film 69. For example, in Figure 7 it, the source electrode pad 65b of the second semiconductor element 2b is exposed in the opening of the protective film 69. In addition, the source electrode pad 65a of the first semiconductor element 2a, the gate electrode pads 66a, 66b of the first semiconductor element 2a and the second semiconductor element 2b, the electrode pad of the temperature sensor 4, etc. are also exposed in the opening of the protective film 69. As Figure 6 shown, the source electrode pad 65a of the first semiconductor element 2a corresponding to the power supply node 12 of Figure 1 is electrically connected to the lead terminal (power supply terminal) 112 via a bonding wire 125. The source electrode pad 65b of the second semiconductor element 2b corresponding to the output node 13 of Figure 1 is electrically connected to the lead terminal (output terminal) 113 via a bonding wire 126.

[0060] In addition, as Figure 7 shown, the control circuit chip 5 is mounted on the protective film 69 provided on the upper surface of the power circuit chip 3 by means of an insulating adhesion member. As Figure 6 shown, on the upper surface of the control circuit chip 5 is exposed the one corresponding to Figure 1Various electrode pads corresponding to the power supply node 12, the ground node 14, and the input node 15, respectively. The electrode pad corresponding to the ground node 14 is electrically connected to the lead terminal (ground terminal) 114 via the bonding wire 123. The electrode pad corresponding to the power supply node 12 is electrically connected to the lead terminal (power supply terminal) 112 via the bonding wire 122. The electrode pad corresponding to the input node 15 is electrically connected to the lead terminal (input terminal) 115 via the bonding wire 124. The lead terminal 116 is electrically connected to the chip pad 111. Further, a plurality of pads such as wirings between the power circuit chip 3 and the control circuit chip 5 are electrically connected via the bonding wire 121.

[0061] As described above, in the semiconductor device according to the first embodiment, the drift regions 50 of the first semiconductor element 2a and the second semiconductor element 2b constituting the main switch circuit 1 are shared with each other. The first well region 53a and the second well region 53b provided above the drift region 50 are provided with their respective first source regions 57a and second source regions 57b and insulated gate electrode structures. Thus, according to the first embodiment, it is easy to integrate the main switch circuit 1 into a single chip and thus integrate it, and miniaturization of the semiconductor device can be achieved. In addition, by adopting a structure (COC) in which the control circuit chip 5 is stacked on the power circuit chip 3, it becomes one package. Therefore, the mounting area of the semiconductor device can be reduced. Further, the power circuit chip 3 and the control circuit chip 5 may be used side by side. In addition, the control circuit chip 5 may be used externally.

[0062] In the semiconductor device according to the first embodiment of the present invention, as Figure 8 shown, the drive circuit 6 includes a processing circuit 16 to which a drive signal is input, and boost circuits 17a, 17b that are electrically connected to the processing circuit 16 independently of each other. In addition, the output circuit 7 includes logic NOT circuits (inverters) 18a, 18b and charge extraction semiconductor elements 19a, 19b.

[0063] As Figure 8As shown, the boost circuit 17a is electrically connected to the gate G of the MIS transistor Tr1 of the first semiconductor element 2a. The boost circuit 17b is electrically connected to the gate G of the MIS transistor Tr2 of the second semiconductor element 2b. As the boost circuits 17a and 17b, it is preferable to use a charge pump type DC / DC converter using a capacitor. The input of the NOT circuit 18a is electrically connected to the input side of the boost circuit 17a, and the output is electrically connected to the gate G of the charge extraction semiconductor element 19a. The drain D and source S of the MIS transistor Tra of the charge extraction semiconductor element 19a are connected to the cathode and anode of the body diode Dia in a reverse parallel manner, respectively. Further, the drain D and source S of the MIS transistor Trb of the charge extraction semiconductor element 19b are connected to the cathode and anode of the body diode Dib in a reverse parallel manner, respectively. The drain D and source S of the charge extraction semiconductor element 19a are connected to the output side of the boost circuit 17a and Figure 1 the output node 13 shown. Similarly, the input of the NOT circuit 18b is electrically connected to the input side of the boost circuit 17b, and the output is electrically connected to the gate G of the charge extraction semiconductor element 19b. The drain D and source S of the charge extraction semiconductor element 19b are connected to the output side of the boost circuit 17b and Figure 1 the output node 13 shown. The processing circuit 16, the boost circuit 17a, the boost circuit 17b, the NOT circuit 18a, and the NOT circuit 18b are all connected to a power supply V GND (ground (GND) or internal reference potential) as the reference potential. CC connected.

[0064] Figure 9A is a circuit diagram showing a structural example of the boost circuit 17a of the semiconductor device according to the first embodiment of the present invention. Figure 9B is showing Figure 9A a diagram of the rise of the output voltage of the boost circuit 17a shown. The boost circuit 17a includes: an oscillation circuit (oscillator) 21 that oscillates based on a signal output from the processing circuit 16; an inverter 24 that logically inverts the signal oscillated by the oscillation circuit 21; and a multi-stage boost section 23a composed of, for example, two stages.

[0065] The oscillation circuit 21 is input with a drive signal for turning on or off the MIS transistor Tr1 from the processing circuit 16, and performs an oscillation operation to output an oscillation signal only when the drive signal for turning on the MIS transistor Tr1 is input.

[0066] The inverter 24 inverts and outputs the oscillation signal output from the oscillation circuit 21.

[0067] In the multi-stage boosting section 23a, the first stage includes an inverter 24, a capacitor 25, and two diodes 26 and 27, and the second stage includes an inverter 28, a capacitor 29, and two diodes 30 and 31.

[0068] The input of the inverter 24 in the first stage is connected to the output of the oscillation circuit 21. The output of the inverter 24 is connected to one terminal of the capacitor 25. The other terminal of the capacitor 25 is connected to the cathode of the diode 26 and the anode of the diode 27. The anode of the diode 26 is connected to the power supply line of the voltage V CC . The power supply line of the voltage V CC is connected to the terminal V CC of the semiconductor device.

[0069] The input of the inverter 28 in the second stage is connected to the output of the inverter 24. The output of the inverter 28 is connected to one terminal of the capacitor 29. The other terminal of the capacitor 29 is connected to the cathode of the diode 30, the anode of the diode 31, and the cathode of the diode 27 in the first stage. The anode of the diode 30 is connected to the power supply line of the voltage V CC . The cathode of the diode 31 constitutes the output of the boosting circuit 17a.

[0070] In the boosting circuit 17a with the above structure, the oscillation circuit 21 starts the oscillation operation by being input with a drive signal that turns on the MIS transistor Tr1 from the processing circuit 16. When the signal output from the oscillation circuit 21 is, for example, at the H (High) level, this signal is input to the inverter 24 in the first stage of the multi-stage boosting section 23a. The output of the inverter 24 is at the L (Low) level, and one terminal of the capacitor 25 is connected to V GND , so that the capacitor 25 is charged with the power supply voltage V CC via the diode 26. As a result, the terminal voltage of the capacitor 25 becomes V CC - Vf (Vf is the forward voltage of the diode 26).

[0071] When the signal output from the oscillation circuit 21 becomes the L level, this signal is input to the inverter 24 in the first stage of the multi-stage boosting section 23a. The output of the inverter 24 becomes the H level, and the power supply voltage V CC is applied to one terminal of the capacitor 25. As a result, the voltage of the other terminal of the capacitor 25 becomes 2(V CC - V GND ) - Vf + V GND . At this time, since a signal at the H level is input to the inverter 28 in the second stage of the multi-stage boosting section 23a, the output of the inverter 28 becomes the L level. Thus, one terminal of the capacitor 29 is connected to V GND , and 2(VCC -V GND ) The voltage of -Vf. As a result, the terminal voltage of the capacitor 29 becomes 2(V CC -V GND ) -2Vf + V GND (Vf is the forward voltage of the diodes 26 and 27, and it is assumed that they have the same value).

[0072] The voltage boosted in this way is output to the output GS of the boost circuit 17a via the diode 31. By alternately repeating the L level and the H level of the signal output from the oscillation circuit 21 and continuously obtaining this output signal, it becomes the gate voltage of the MIS transistor Tr1. The boost circuit 17b has the same structure, and the output signal of the boost circuit 17b becomes the gate voltage of the MIS transistor Tr2.

[0073] (Second Embodiment)

[0074] Figure 10 It is a circuit diagram showing an example of a semiconductor device according to the second embodiment of the present invention. As Figure 10 shown, the drive circuit 6 includes a processing circuit 16b to which a drive signal is input and boost circuits 17c and 17d electrically connected in common with the processing circuit 16b. In addition, the output circuit 7 includes charge extraction semiconductor elements 19c and 19d electrically connected in common with a logical NOT circuit (inverter) 18c. The difference between the semiconductor device according to the second embodiment and the first embodiment is that it includes boost circuits 17c and 17d electrically connected in common with the processing circuit 16b and charge extraction semiconductor elements 19c and 19d electrically connected in common with the inverter 18c. Other structures are the same as those of the semiconductor device according to the first embodiment, so repeated descriptions are omitted.

[0075] Moreover, the output voltage of the boost circuit 17c rises faster than that of the boost circuit 17d. In addition, the charge extraction ability of the charge extraction semiconductor element 19c is lower than that of the charge extraction semiconductor element 19d. Here, a lower charge extraction ability means a lower current value that can flow. For example, the channel width of the charge extraction semiconductor element 19c can be formed narrower than the channel width of the charge extraction semiconductor element 19d. As a structure for making the output voltage of the boost circuit 17c rise faster than that of the boost circuit 17d, the following three examples can be cited.

[0076] (Structural Example 1 of Boost Circuit)

[0077] Figure 11A It is a circuit diagram showing Structural Example 1 of the boost circuit of the semiconductor device according to the second embodiment of the present invention, Figure 11B It shows Figure 11AGraph showing the rise of the output voltage of the boost circuit 17c. The boost circuit 17d is the same as Figure 9A the boost circuit 17a shown. Figure 11A The boost circuit 17c shown has more stages in the multi-stage boost section than the boost circuit 17d, with 3 stages. In this way, by making the number of stages in the multi-stage boost section of the boost circuit 17c more than that of the boost circuit 17d, the rise of the output voltage can be made faster.

[0078] When the oscillation signal from the oscillation circuit 21 is at the H level, the second-stage inverter 28 outputs the H level. As a result, the power supply voltage V is applied to one end of the capacitor 29 CC . As a result, regarding the voltage at the other end of the capacitor 29, a voltage of 2(V CC -V GND )-2Vf + V GND is superimposed with V CC to become 3(V CC -V GND )-2Vf + V GND . At this time, the third-stage inverter 32 of the boost circuit 17c outputs the L level. As a result, one end of the capacitor 33 is connected to the internal potential V GND , and a voltage of 3(V CC -V GND )-2Vf + V GND is applied to the other end of the capacitor 33 via the second-stage diode 31. As a result, the terminal voltage of the capacitor 33 becomes 3(V CC -V GND )-3Vf + V GND . The voltage boosted to 3(V CC -V GND )-3Vf + V GND is output as the gate signal GS1 via the diode 35.

[0079] Figure 12 is a timing chart for explaining the control method of the semiconductor device according to the second embodiment of the present invention. As Figure 12 shown, the input signal input to the drive circuit 6 is transmitted to the boost circuits 17c and 17d via the processing circuit 16b respectively. A drive signal of the voltage Vg1 is input to the gate G of the MIS transistor Tr1 from the boost circuit 17c and rises within the rise time Dr1. A drive signal of the voltage Vg2 is input to the gate G of the MIS transistor Tr2 from the boost circuit 17d and rises within the rise time Dr2. The voltage Vg1 is higher than the voltage Vg2. In addition, due to the difference in the rise time of the output voltages of the boost circuit 17c and the boost circuit 17d, the rise time Dr2 is made larger than the rise time Dr1. As a result, compared with the MIS transistor Tr2, the MIS transistor Tr1 reliably becomes conductive earlier, and it is possible to preventFigure 3 Operation of the parasitic bipolar transistor shown.

[0080] In addition, when the input signal is at the H level, the output of the logical NOT circuit 18c is at the L level, so the charge extraction semiconductor elements 19c and 19d are in the cut-off state. When the input signal changes to the L level to turn off the MIS transistors Tr1 and Tr2, the output of the logical NOT circuit 18c changes to the H level, and the charge extraction semiconductor elements 19c and 19d are turned on. Therefore, the charge accumulated in the boost circuits 17c and 17d and the gates G of the MIS transistors Tr1 and Tr2 can be extracted. As Figure 12 shown, the fall time Df1 when the MIS transistor Tr1 is turned off is longer than the fall time Df2 when the MIS transistor Tr2 is turned off. As a result, when the MIS transistor Tr2 is in the on state, the MIS transistor Tr1 must be in the on state, and the operation of the parasitic bipolar transistor can be prevented.

[0081] (Structural example 2 of boost circuit)

[0082] Figure 13A The figure is a circuit diagram showing a structural example 2 of the boost circuit of the semiconductor device according to the second embodiment of the present invention, Figure 13B which shows Figure 13A a diagram showing the rise of the output voltage of the boost circuit shown. The boost circuit 17d is the same as the Figure 9A boost circuit 17a shown. Figure 13A The frequency of the oscillation circuit 21a of the boost circuit 17c shown is higher than that of the boost circuit 17d. In this way, by making the frequency of the oscillation circuit 21a of the boost circuit 17c higher than the frequency of the oscillation circuit 21 of the boost circuit 17d, as Figure 13B shown, compared with the Figure 9A boost circuit 17a shown, the rise of the output voltage can be made faster.

[0083] (Structural example 3 of boost circuit)

[0084] Figure 14A The figure is a circuit diagram showing a structural example 3 of the boost circuit of the semiconductor device according to the second embodiment of the present invention, Figure 14B which shows Figure 14A a diagram showing the rise of the output voltage of the boost circuit shown. The boost circuit 17d is the same as the Figure 9A boost circuit 17a shown. Figure 14A The capacitance of the capacitor 25a of the boost circuit 17c shown is larger than that of the boost circuit 17d. In this way, by making the capacitance of the capacitor 25a of the boost circuit 17c larger than the capacitance of the capacitor 25 of the boost circuit 17d, as Figure 14B shown, compared with the Figure 9ACompared with the boost circuit 17a shown, it is possible to make the rise of the output voltage faster.

[0085] Figure 15 It is a timing chart for explaining the control method in the case of the structure example 2 of the boost circuit or the structure example 3 of the boost circuit. Compared with Figure 12 Similarly, compared with the MIS transistor Tr2, the MIS transistor Tr1 surely becomes conductive earlier, and the MIS transistor Tr1 is turned off later than the MIS transistor Tr2. As a result, when the MIS transistor Tr2 is in the conductive state, the MIS transistor Tr1 is surely in the conductive state, and the operation of the parasitic bipolar transistor can be prevented.

[0086] (Other Embodiments)

[0087] As described above, the present invention has been described by the embodiments and the modified examples, but it should not be understood that the descriptions and the drawings as a part of the present disclosure are used to limit the present invention. As long as the gist of the disclosure of the above embodiments is understood, those skilled in the art should understand that various alternative embodiments, examples, and application techniques can be included in the present invention. In addition, it goes without saying that the present invention includes various embodiments not described herein, such as structures obtained by arbitrarily applying each structure described in the above embodiments and each modified example. Therefore, the technical scope of the present invention is determined only by the technical features related to the claims that are appropriate according to the above illustrative description.

Claims

1. A semiconductor device, characterized in that, it includes: A first semiconductor element and a second semiconductor element. In order to form a main switch circuit, the first semiconductor element and the second semiconductor element have a common region formed by a semiconductor region of a first conductivity type. In the upper part of this common region, a first well region of a second conductivity type and a second well region of a second conductivity type are provided separately from each other. A first source region of a first conductivity type of the first semiconductor element is provided in the upper part of the first well region, and a second source region of a first conductivity type of the second semiconductor element is provided in the upper part of the second well region; and A drive circuit that respectively provides independent first and second drive signals to the control electrode of the first semiconductor element and the control electrode of the second semiconductor element, wherein the width of the first drive signal is wider than the width of the second drive signal, and during the period when the first semiconductor element is in the on state, the switching of the second drive signal from on to off and the switching from off to on are performed, the drive circuit has a processing circuit and a first boost circuit and a second boost circuit that are respectively and independently electrically connected to the control electrode of the first semiconductor element and the control electrode of the second semiconductor element. The first boost circuit and the second boost circuit are respectively and independently electrically connected to the processing circuit, and the output voltage of the first boost circuit connected to the control electrode of the first semiconductor element is higher than the output voltage of the second boost circuit connected to the control electrode of the second semiconductor element.

2. A semiconductor device, characterized in that, it includes: A first semiconductor element and a second semiconductor element. In order to form a main switch circuit, the first semiconductor element and the second semiconductor element have a common region formed by a semiconductor region of a first conductivity type. In the upper part of this common region, a first well region of a second conductivity type and a second well region of a second conductivity type are provided separately from each other. A first source region of a first conductivity type of the first semiconductor element is provided in the upper part of the first well region, and a second source region of a first conductivity type of the second semiconductor element is provided in the upper part of the second well region; and A drive circuit that respectively provides independent first and second drive signals to the control electrode of the first semiconductor element and the control electrode of the second semiconductor element, wherein the width of the first drive signal is wider than the width of the second drive signal, and during the period when the first semiconductor element is in the on state, the switching of the second drive signal from on to off and the switching from off to on are performed, the drive circuit has a processing circuit and a first boost circuit and a second boost circuit that are respectively and independently electrically connected to the control electrode of the first semiconductor element and the control electrode of the second semiconductor element. The first boost circuit and the second boost circuit are respectively and independently electrically connected to the processing circuit, The rise of the output voltage of the first boost circuit connected to the control electrode of the first semiconductor element is earlier than the rise of the output voltage of the second boost circuit connected to the control electrode of the second semiconductor element.

3. The semiconductor device according to claim 1 or 2, wherein, the first semiconductor element further includes a contact region of a second conductivity type provided on the upper part of the first well region, and the second semiconductor element further includes a contact region of a second conductivity type provided on the upper part of the second well region, the contact region of the first semiconductor element is electrically connected to a power supply terminal, and the contact region of the second semiconductor element is electrically connected to an output terminal.

4. The semiconductor device according to claim 1 or 2, wherein, the semiconductor region has: a first semiconductor region; and a second semiconductor region, which is adjacent to the first semiconductor region and has a distance from the first well region and the second well region, and the impurity concentration of the second semiconductor region is higher than the impurity concentration of the first semiconductor region.

5. The semiconductor device according to claim 4, wherein, the first semiconductor region is a first semiconductor layer including the first well region and the second well region, the second semiconductor region is a second semiconductor layer formed under the first semiconductor layer.

6. The semiconductor device according to claim 1 or 2, wherein, it further includes an output circuit, which has: an inverter circuit, each of whose inputs is electrically connected to the input sides of the first boost circuit and the second boost circuit respectively; and charge extraction semiconductor elements, each of whose control electrodes is electrically connected to the output of the inverter circuit, each of the first main electrode regions of the charge extraction semiconductor elements is electrically connected to the first boost circuit and the second boost circuit respectively, and each of the other electrode regions of the charge extraction semiconductor elements is electrically connected to an output terminal.

7. The semiconductor device according to claim 1 or 2, wherein, it includes: a power circuit chip, which is formed by integrating the first semiconductor element and the second semiconductor element on the same chip; a control circuit chip, which is formed by integrating the drive circuit on the same chip; and a package, which internally houses the power circuit chip and the control circuit chip, and has a power supply terminal for electrically leading out the first source region to the outside to be able to connect to an external power supply and an output terminal for electrically leading out the second source region to the outside to be able to connect to an external load.

8. A control method for a semiconductor device, the semiconductor device having a main switch circuit, the main switch circuit having an insulated-gate type first semiconductor element and an insulated-gate type second semiconductor element, the first semiconductor element and the second semiconductor element having a semiconductor region of a first conductivity type as a common region, a first well region of a second conductivity type and a second well region of a second conductivity type being provided separately from each other on the upper part of the common region, in the first semiconductor element, a first surface electrode electrically connected to a power supply terminal being provided on the upper surface of a second main electrode region of a first conductivity type provided on the upper part of the first well region, in the second semiconductor element, a second surface electrode electrically connected to an output terminal being provided on the upper surface of a fourth main electrode region provided on the upper part of the second well region, The control method for the semiconductor device is characterized in that, comprising: applying a first drive signal to the control electrode of the first semiconductor element to control conduction and cutoff of the first semiconductor element; and independently of the first drive signal, applying a second drive signal to the control electrode of the second semiconductor element to control conduction and cutoff of the second semiconductor element, wherein, the width of the first drive signal is wider than the width of the second drive signal, and during a period when the first semiconductor element is in a conduction state, switching of the second drive signal from conduction to cutoff and from cutoff to conduction is performed, the first drive signal and the second drive signal are respectively applied to the control electrodes of the first semiconductor element and the second semiconductor element via mutually independent booster circuits, the voltage level of the first drive signal that makes the first semiconductor element in a conduction state is higher than the voltage level of the second drive signal that makes the second semiconductor element in a conduction state.

9. A control method for a semiconductor device, the semiconductor device having a main switch circuit, the main switch circuit having an insulated-gate type first semiconductor element and an insulated-gate type second semiconductor element, the first semiconductor element and the second semiconductor element having a semiconductor region of a first conductivity type as a common region, a first well region of a second conductivity type and a second well region of a second conductivity type being provided separately from each other on the upper part of the common region, in the first semiconductor element, a first surface electrode electrically connected to a power supply terminal being provided on the upper surface of a second main electrode region of a first conductivity type provided on the upper part of the first well region, in the second semiconductor element, a second surface electrode electrically connected to an output terminal being provided on the upper surface of a fourth main electrode region provided on the upper part of the second well region, The control method for the semiconductor device is characterized in that, comprising: applying a first drive signal to the control electrode of the first semiconductor element to control conduction and cutoff of the first semiconductor element; and independently of the first drive signal, applying a second drive signal to the control electrode of the second semiconductor element to control conduction and cutoff of the second semiconductor element, Among them, the width of the first driving signal is wider than the width of the second driving signal, and during the period when the first semiconductor element is in the conducting state, the switching of the second driving signal from conduction to cut-off and the switching from cut-off to conduction are performed. The first driving signal and the second driving signal are respectively applied to the control electrodes of the first semiconductor element and the second semiconductor element via mutually independent boost circuits. The voltage rise of the first driving signal that makes the first semiconductor element become conductive is earlier than the voltage rise of the second driving signal that makes the second semiconductor element become conductive.

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