Dynamic latch, data operation unit, chip, computing board and computing device

Abstract

The present invention provides a dynamic latch, a data operation unit, a chip, a computing board, and a computing device. The dynamic latch includes an input terminal, an in-phase output terminal, an inverting output terminal, a clock signal terminal, a data transmission unit, a first data retention unit, and a second data retention unit. The data transmission unit, the first data retention unit, and the second data retention unit are sequentially connected in series between the input terminal and the in-phase output terminal. A first node is provided between the data transmission unit and the first data retention unit, a second node is provided between the first data retention unit and the second data retention unit, and the inverting output terminal is electrically connected to the second node. The dynamic latch further includes a leakage compensation unit, which is electrically connected between the in-phase output terminal and the first node. This can effectively compensate for the dynamic leakage current of the node, thereby improving the security and accuracy of the data.

Description

Technical Field

[0001] The present invention relates to a clock-controlled memory device, and in particular to a dynamic latch, a data operation unit, a chip, a computing board, and a computing device used in large-scale data computing equipment. Background Art

[0002] Dynamic latches are widely used and can be used to store digital signals. Figure 1 The circuit structure diagram of the existing dynamic latch is shown in FIG. Figure 1 As shown, dynamic latch 100 includes a transmission gate 101, an inverter 102, and an inverter 103 connected in series between an input terminal D and a non-inverting output terminal Q. A node S0 is formed between transmission gate 101 and inverter 102, and a node S1 is formed between inverter 102 and inverter 103. Data is temporarily stored at node S0 and / or node S1 through parasitic capacitances of transistors in inverter 102 and inverter 103. The dynamic latch outputs data in phase with the data at input terminal D through the non-inverting output terminal Q, and outputs data in phase opposite to the data at input terminal D through the inverting output terminal QN. However, nodes S0 and S1 are prone to dynamic leakage, resulting in loss of temporarily stored data.

[0003] Therefore, how to effectively reduce the dynamic leakage of the dynamic latch is a problem that needs to be solved. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a dynamic latch that can effectively compensate for the dynamic leakage current of the node and improve the security and accuracy of data.

[0005] In order to achieve the above-mentioned objectives, the present invention provides a dynamic latch, comprising an input terminal for inputting data; an in-phase output terminal for outputting the data in-phase; an inverting output terminal for outputting the data inverted; a clock signal terminal for providing a clock signal; a data transmission unit for transmitting the data under the control of the clock signal; a first data holding unit for inverting and holding the data transmitted by the data transmission unit; a second data holding unit for in-phase and holding the data transmitted by the data transmission unit; the data transmission unit, the first data holding unit and the second data holding unit are connected in series in sequence between the input terminal and the in-phase output terminal, a first node is provided between the data transmission unit and the first data holding unit, a second node is provided between the first data holding unit and the second data holding unit, and the inverting output terminal is electrically connected to the second node; wherein, a leakage compensation unit is also included, and the leakage compensation unit is electrically connected between the in-phase output terminal and the first node.

[0006] In the above-mentioned dynamic latch, the leakage compensation unit has a first terminal, a second terminal and a control terminal, the first terminal is electrically connected to the in-phase output terminal, and the second terminal is electrically connected to the first node.

[0007] In the above-mentioned dynamic latch, the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the in-phase output terminal and the first node.

[0008] The above-mentioned dynamic latch, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the first node.

[0009] In the above-mentioned dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the first node.

[0010] In the above-mentioned dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the second node.

[0011] In the above-mentioned dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

[0012] In the above-mentioned dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

[0013] The above-mentioned dynamic latch, wherein the leakage compensation unit includes an NMOS transistor, the NMOS transistor having a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the in-phase output terminal, the source terminal is electrically connected to the first node, and the gate terminal is electrically connected to a ground.

[0014] The above-mentioned dynamic latch, wherein the leakage compensation unit includes a PMOS transistor, the PMOS transistor having a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor being electrically connected to the in-phase output terminal, the drain terminal being electrically connected to the first node, and the gate terminal being electrically connected to a power supply.

[0015] In the above-mentioned dynamic latch, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

[0016] In the above-mentioned dynamic latch, the data transmission unit is a transmission gate.

[0017] In the above-mentioned dynamic latch, the first data holding unit and / or the second data holding unit is an inverter.

[0018] By using the dynamic latch of the present invention, leakage current can be fed back from the output end to the node to compensate for the dynamic leakage current of the node, thereby improving the stability of data storage and further enhancing the security and accuracy of the data.

[0019] In order to better achieve the above-mentioned purpose, the present invention also provides a data operation unit, including a control circuit, an operation circuit, and multiple dynamic latches that are interconnected, and the multiple dynamic latches are connected in series and / or in parallel; wherein the multiple dynamic latches are any one of the above-mentioned dynamic latches.

[0020] In order to better achieve the above-mentioned purpose, the present invention also provides a chip, which includes at least one of the above-mentioned data operation units.

[0021] In order to better achieve the above-mentioned purpose, the present invention also provides a computing power board for a computing device, which includes at least one of the above-mentioned chips.

[0022] In order to better achieve the above-mentioned purpose, the present invention also provides a computing device, including a power board, a control board, a connection board, a radiator, and a plurality of computing boards, wherein the control board is connected to the computing board through the connection board, the radiator is arranged around the computing board, and the power board is used to provide power to the connection board, the control board, the radiator, and the computing board, wherein the computing board is the above-mentioned computing board.

[0023] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the circuit structure of an existing dynamic latch;

[0025] Figure 2 Schematic diagram of the circuit structure of a dynamic latch according to an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of the circuit structure of a dynamic latch according to another embodiment of the present invention;

[0027] Figure 4Schematic diagram of the circuit structure of a dynamic latch according to another embodiment of the present invention;

[0028] Figure 5 Schematic diagram of the circuit structure of a dynamic latch according to another embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the circuit structure of a dynamic latch according to an expanded embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the circuit structure of a dynamic latch according to another extended embodiment of the present invention;

[0031] Figure 8 Schematic diagram of the structure of the data operation unit of the present invention;

[0032] Figure 9 Schematic diagram of the structure of the chip of the present invention;

[0033] Figure 10 This is a schematic diagram of the structure of the hashboard of the present invention;

[0034] Figure 11 Schematic diagram of the structure of the computing device of the present invention.

[0035] Wherein, the reference numerals:

[0036] 100, 200: Dynamic latch

[0037] 101: Transmission Gate

[0038] 102, 103: Inverter

[0039] 201: Data transmission unit

[0040] 202: First data holding unit

[0041] 203: Second data holding unit

[0042] 204: Leakage compensation unit

[0043] 201P, 204P: PMOS transistors

[0044] 201N, 204N: NMOS transistors

[0045] 800: Data processing unit

[0046] 801: Control circuit

[0047] 802: Operational Circuit

[0048] 900: Chip

[0049] 901: Control unit

[0050] 1000: Hash board

[0051] 1100: Computing devices

[0052] 1101: Connecting plate

[0053] 1102: Control Panel

[0054] 1103: Radiator

[0055] 1104: Power board

[0056] D: Input terminal

[0057] Q: non-inverting output terminal

[0058] QN: Inverting output terminal

[0059] CKP, CKN: clock signal

[0060] S0, S1: nodes DETAILED DESCRIPTION

[0061] The structural principle and working principle of the present invention are described in detail below with reference to the accompanying drawings:

[0062] Certain terms are used throughout this specification and the following claims to refer to specific components. A person skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and the following claims do not distinguish components by name, but rather by their functional differences.

[0063] Throughout this specification and the following claims, the words "include" and "comprising" are open-ended terms and should be interpreted as meaning "including, but not limited to." Furthermore, the word "connect" is intended to encompass both direct and indirect electrical connections. Indirect electrical connections include connection through other devices.

[0064] Example 1:

[0065] Figure 2 FIG. 1 is a schematic diagram of the circuit structure of a dynamic latch according to an embodiment of the present invention. Figure 2As shown, the dynamic latch 200 includes an input terminal D, a non-inverting output terminal Q, an inverting output terminal QN, a clock signal terminal CKN, a clock signal terminal CKP, a data transmission unit 201, a first data holding unit 202, a second data holding unit 203, and a leakage compensation unit 204. The data transmission unit 201, the first data holding unit 202, and the second data holding unit 203 are sequentially connected in series between the input terminal D and the non-inverting output terminal Q. A first node S0 is formed between the data transmission unit 201 and the first data holding unit 202, a second node S1 is formed between the first data holding unit 202 and the second data holding unit 203, and the inverting output terminal QN is electrically connected to the second node S1. The leakage compensation unit 204 is electrically connected between the first node S0 and the non-inverting output terminal Q. Among them, the input terminal D is used to input data, the in-phase output terminal Q is used to output data in-phase, the inverting output terminal QN is used to output data in inverted phase, the clock signal terminal CKN and the clock signal terminal CKP are used to provide clock signals CKN and CKP, and the clock signals CKN and CKP are inverted clock signals.

[0066] Specifically, such as Figure 2 As shown, the data transmission unit 201 of the dynamic latch 200 is a transmission gate structure. The data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N and is electrically connected to the input terminal D of the dynamic latch 200. The drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N and is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, and both the PMOS transistor 201P and the NMOS transistor 201N are in a conductive state. Data at the input terminal D of the dynamic latch 200 is transmitted to the first node S0 through the data transmission unit 201. When CKP is high, CKN is low, and both the PMOS transistor 201P and the NMOS transistor 201N are in the off state. Data at the input terminal D of the dynamic latch 200 cannot be transmitted to the first node S0 via the data transmission unit 201. In this embodiment, the data transmission unit 201 is exemplified by a transmission gate structure. Of course, other forms of data transmission units may also be used as long as they can implement a switching function under the control of a clock signal, and the present invention is not limited thereto.

[0067] Continue to refer to Figure 2As shown, the first data holding unit 202 and the second data holding unit 203 of the dynamic latch 200 are both inverter structures. The first data holding unit 202 can use its parasitic capacitance to temporarily store the data transmitted from the data transmission unit 201, that is, the data at the first node S0, and can also invert the data at the first node S0 and transmit it to the second data holding unit 203. The second data holding unit 203 similarly uses its parasitic capacitance to temporarily store the data transmitted from the first data holding unit 202, that is, the data at the second node S1, and can also invert the data at the second node S1 and transmit it to the non-inverting output terminal Q. As can be seen from this, the data at the first node S0 and the second node S1 are inverted data, and the inverting output terminal QN is electrically connected to the second node S1. Therefore, the data output by the non-inverting output terminal Q and the inverting output terminal QN are also inverted data.

[0068] As can be seen, the data transmission unit 201 is controlled by the clock signal and transmits data to the first data holding unit 202 and the second data holding unit 203. The data at the input terminal D of the dynamic latch 200 is inverted by the first data holding unit 202 and the second data holding unit 203, so that the data at the non-inverting output terminal Q is in phase with the data at the input terminal D, and the data at the inverting output terminal QN is in phase with the data at the input terminal D. Furthermore, the first data holding unit 202 and the second data holding unit 203 can also improve data driving capability.

[0069] like Figure 2 As shown, the dynamic latch 200 further includes a leakage compensation unit 204. In this embodiment, the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N. The PMOS transistor 204P and the NMOS transistor 204N are connected in series between the non-inverting output terminal Q and a first node S0. The source terminal of the PMOS transistor 204P is electrically connected to the non-inverting output terminal Q, the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the first node S0, and the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the first node S0.

[0070] Because the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are both electrically connected to the first node S0, when driven by a signal of the same level, the PMOS transistor 204P and the NMOS transistor 204N will not be turned on simultaneously; only one of them can be in the on state and the other in the off state. For example, when the potential at the first node S0 is high, the PMOS transistor 204P is in the off state, while the NMOS transistor 204N is in the on state; when the potential at the first node S0 is low, the PMOS transistor 204P is in the on state, while the NMOS transistor 204N is in the off state. In this case, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensating for the dynamic leakage current at the first node S0, improving the stability of data storage at the first node S0, and enhancing the accuracy and security of the data.

[0071] Example 2:

[0072] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a dynamic latch according to another embodiment of the present invention. Figure 3 As shown, Figure 2 The difference from the embodiment shown is that, in this embodiment, in the leakage compensation unit 204 , the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the second node S1 .

[0073] Because the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are both electrically connected to the second node S1, when driven by a signal of the same level, the PMOS transistor 204P and the NMOS transistor 204N will not be turned on simultaneously; only one of them can be in the on state and the other in the off state. For example, when the potential at the second node S1 is high, the PMOS transistor 204P is in the off state, while the NMOS transistor 204N is in the on state. When the potential at the second node S1 is low, the PMOS transistor 204P is in the on state, while the NMOS transistor 204N is in the off state. In this case, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensating for the dynamic leakage current at the first node S0, improving the stability of data storage at the first node S0, and enhancing the accuracy and security of the data.

[0074] Variations:

[0075] Figure 4 FIG. 1 is a circuit diagram of a dynamic register for leakage compensation according to another embodiment of the present invention. Figure 2 and Figure 4 As shown, Figure 2The difference between the illustrated embodiment and the embodiment is that, in this embodiment, in the leakage compensation unit 204 , the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the ground VSS.

[0076] Because the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are both electrically connected to the ground VSS, when driven by a low-level signal at the ground VSS, the PMOS transistor 203P is in the on state, while the NMOS transistor 203N is in the off state. At this time, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0 to compensate for the dynamic leakage current at the first node S0, thereby improving the stability of data storage at the first node S0 and enhancing the accuracy and security of the data.

[0077] Figure 5 FIG. 1 is a circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. Figure 2 and Figure 5 As shown, Figure 2 The difference between the illustrated embodiment and the embodiment is that, in this embodiment, in the leakage compensation unit 204 , the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the power source VDD.

[0078] Because the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are both electrically connected to the power supply VDD, when driven by a high-level signal from the power supply VDD, the PMOS transistor 203P is in a cutoff state, while the NMOS transistor 203N is in a conductive state. At this time, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0 to compensate for the dynamic leakage current at the first node S0, thereby improving the stability of data storage at the first node S0 and enhancing the accuracy and security of the data.

[0079] Figure 6 This is a schematic diagram of the circuit structure of the leakage compensation dynamic register of the expanded embodiment of the present invention. Figure 6 As shown, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes an NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the first node S0, the drain terminal of the NMOS transistor 204N is electrically connected to the in-phase output terminal Q, and the gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS.

[0080] Because the gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS, the NMOS transistor 204N is in the off state when driven by a low-level signal of the ground VSS. At this time, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0 to compensate for the dynamic leakage current at the first node S0, thereby improving the stability of data storage at the first node S0 and enhancing the accuracy and security of the data.

[0081] Figure 7 FIG. 1 is a circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. Figure 7 As shown, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes a PMOS transistor 204P, a source terminal of the PMOS transistor 204P is electrically connected to the in-phase output terminal, a drain terminal of the PMOS transistor 204P is electrically connected to the first node S0, and a gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD.

[0082] Because the gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD, when driven by a high-level signal from the power supply VDD, the PMOS transistor 204P is in the off state. At this time, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0 to compensate for the dynamic leakage current at the first node S0, thereby improving the stability of data storage at the first node S0 and enhancing the accuracy and security of the data.

[0083] The present invention also provides a data operation unit, Figure 8 Figure 1 is a schematic diagram of the structure of the data operation unit of the present invention. Figure 8 As shown, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of dynamic latches 200. The control circuit 801 refreshes the data in the dynamic latches 200 and reads the data from the dynamic latches 200. The operation circuit 802 operates on the read data, and the control circuit 801 outputs the operation result.

[0084] The present invention also provides a chip, Figure 9 FIG. 1 is a schematic diagram of the structure of the chip of the present invention. Figure 9 As shown, the chip 900 includes a control unit 901 and one or more data operation units 900. The control unit 901 inputs data to the data operation unit 900 and processes the data output by the data operation unit 900.

[0085] The present invention also provides a computing board. Figure 10 This is a schematic diagram of the structure of the hashboard of the present invention. Figure 10 As shown, each computing board 1000 includes one or more chips 900 to perform large-scale operations on the working data sent by the computing device.

[0086] The present invention also provides a computing device, which can be used for any massive calculations. Figure 11 FIG. 1 is a schematic diagram of the structure of the computing device of the present invention. Figure 11 As shown, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power board 1104, and one or more hash boards 1000. The control board 1102 is connected to the hash board 1000 via the connection board 1101, and the heat sink 1103 is arranged around the hash board 1000. The power board 1104 is used to provide power to the connection board 1101, control board 1102, heat sink 1103, and hash board 1000.

[0087] It should be noted that, in the description of the present invention, the terms "horizontal", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0088] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A dynamic latch, characterized in that: include: An input terminal for inputting data; an in-phase output terminal, for outputting the data in-phase; an inverting output terminal, for outputting the data in an inverted manner; A clock signal terminal, used for providing a clock signal; a data transmission unit, which is a transmission gate and transmits the data under the control of the clock signal; a first data holding unit, configured to invert and hold the data transmitted by the data transmission unit; a second data holding unit, configured to hold the data transmitted by the data transmission unit in phase; The data transmission unit, the first data holding unit, and the second data holding unit are sequentially connected in series between the input terminal and the non-inverting output terminal, a first node is defined between the data transmission unit and the first data holding unit, a second node is defined between the first data holding unit and the second data holding unit, and the inverting output terminal is electrically connected to the second node; Wherein, it further includes a leakage compensation unit, the leakage compensation unit being electrically connected between the in-phase output terminal and the first node, and being used to feed back the current of the in-phase output terminal to the first node for leakage compensation; The leakage compensation unit includes a PMOS transistor and an NMOS transistor, the PMOS transistor and the NMOS transistor are connected in series between the in-phase output terminal and the first node; the PMOS transistor has a source terminal, a drain terminal and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, the source terminal of the NMOS transistor is electrically connected to the first node, and the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the first node or the second node.

2. The dynamic latch according to claim 1, wherein: The clock signal includes a first clock signal and a second clock signal, and the first clock signal is in opposite phase to the second clock signal.

3. The dynamic latch according to claim 1, wherein: The first data holding unit and / or the second data holding unit is an inverter.

4. A data operation unit comprising a control circuit, an operation circuit, and a plurality of dynamic latches connected in series and / or in parallel; characterized in that: The multiple dynamic latches are the dynamic latches described in any one of claims 1-3.

5. A chip, characterized in that: The device comprises at least one data operation unit as claimed in claim 4.

6. A hashboard for computing equipment, characterized in that: Comprising at least one chip as claimed in claim 5.

7. A computing device comprising a power board, a control board, a connection board, a radiator, and a plurality of hash boards, wherein the control board is connected to the hash boards via the connection board, the radiator is disposed around the hash boards, and the power board is used to provide power to the connection board, the control board, the radiator, and the hash boards, characterized in that: The computing board is the computing board according to claim 6.

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