Electronic Devices

Abstract

The present invention relates to an electronic device for improving the mounting reliability of semiconductor devices. A QFP (5) includes: a chip pad (1c) on which a semiconductor chip (2) is mounted; a plurality of inner lead portions (1a) arranged around the chip pad; a plurality of outer lead portions (1b) respectively connected to the plurality of inner lead portions (1a); a plurality of wires (4) respectively electrically connecting the bonding pad (2c) of the semiconductor chip to the plurality of inner lead portions; and a sealing body (3) for sealing the semiconductor chip. Moreover, the thickness of the semiconductor chip is greater than the thickness (T5) from the lower surface (1cb) of the chip pad (1c) to the lower surface (3b) of the sealing body (3), and the distance (D1) between the lower surface (3b) of the sealing body and the front end portion (1be) of each of the plurality of outer lead portions (1b) is greater than the thickness (T4) of the sealing body from the main surface (2a) of the semiconductor chip to the upper surface (3a).

Description

[0001] This application is a divisional application of the invention patent application with application number 201410658551.7, application date November 18, 2014, and invention name “Semiconductor Device”. Technical Field

[0002] The present invention relates to a semiconductor device, and, for example, to a technology effectively applicable to a semiconductor device including a plurality of leads protruding from a side surface of a sealing body that seals a semiconductor chip. Background Art

[0003] In a semiconductor device having a sealing body (package), a structure in which a plurality of leads protrude outward from the side surface of the package is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-319954 (Patent Document 1).

[0004] Furthermore, the structure of a semiconductor device having a plurality of gull-wing shaped outer leads is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-3277 (Patent Document 2).

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-319954

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 5-3277 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] When the thermal expansion coefficient of the semiconductor device (semiconductor package) mounted on the motherboard (wiring substrate) is different from that of the motherboard, a bonding failure is likely to occur at the bonding portion between the motherboard and the semiconductor device mounted on the motherboard. The bonding failure occurs because when the motherboard with the semiconductor device mounted thereon is deformed (expanded, contracted) by heat, the deformation amount (expansion amount, contraction amount) of the motherboard is different from the deformation amount (expansion amount, contraction amount) of the semiconductor device that is also deformed (expanded, contracted) by heat.

[0011] On the other hand, for example, in a QFP (Quad Flat Package), a portion of the lead (outer lead portion) serving as an external terminal of a semiconductor device is bent outside a sealing body that seals the semiconductor chip. That is, a portion of the lead (outer lead portion) bonded to a motherboard is not fixed to the sealing body.

[0012] So, for example Fig.31As shown in the comparative example, even if the motherboard 12 shrinks more in the S direction than the semiconductor device (QFP 21), a part of the lead 21a (outer lead portion) follows the movement of the motherboard 12, so that bonding failure is less likely to occur.

[0013] However, in recent years, there has been a trend toward using semiconductor devices in harsher usage environments than previous products (for example, in automotive-related products).

[0014] Therefore, the inventors of the present application have studied the structure of a semiconductor device capable of ensuring higher mounting reliability (mounting strength) than conventional QFPs.

[0015] Other issues and novel features will become apparent from the description of this specification and the accompanying drawings.

[0016] Means used to solve problems

[0017] A semiconductor device according to one embodiment includes: a chip pad, a plurality of leads, and a sealing body for sealing a semiconductor chip, wherein the thickness of the semiconductor chip is greater than the thickness from the second surface of the chip pad to the lower surface of the sealing body. Furthermore, the distance between the lower surface of the sealing body and the front end of a portion of each of the plurality of leads is greater than the thickness of the sealing body from the main surface of the semiconductor chip to the upper surface of the sealing body.

[0018] Effects of the Invention

[0019] According to the above-described embodiment, the mounting reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a plan view showing an example of the structure of the semiconductor device (QFP) according to the embodiment.

[0021] Figure 2 It means along Figure 1 A cross-sectional view of an example of the structure taken along line AA.

[0022] Figure 3 Yes means Figure 1 An enlarged cross-sectional view showing the detailed structure of the semiconductor device.

[0023] Figure 4 Yes means Figure 1 A top view of an example of a mounting structure in which a semiconductor device is mounted on a mounting substrate.

[0024] Figure 5 Yes means Figure 4 A side view of an example of a mounting structure of a semiconductor device (QFP) shown.

[0025] Figure 6 It is a cross-sectional view showing the structure of a semiconductor device (QFP) according to the embodiment.

[0026] Figure 7 It is a cross-sectional view showing the structure of a QFP of a comparative example.

[0027] Figure 8 It is a plan view showing an example of the structure of the semiconductor device according to the embodiment.

[0028] Fig. 9 Yes means Figure 8 A side view of the mounting configuration of the semiconductor device is shown.

[0029] Fig.10 It is a top view showing the structure of a QFP of a comparative example.

[0030] Fig.11 Yes means Fig.10 A side view of the mounting configuration of the semiconductor device is shown.

[0031] Fig.12 Yes means Figure 8 Schematic diagram of the solder wetting state of the semiconductor device shown.

[0032] Fig.13 It is a schematic diagram showing the solder wetting state of a semiconductor device of a comparative example.

[0033] Fig.14 It means in Figure 1 A top view of an example of the structure of a lead frame used in assembling a semiconductor device.

[0034] Fig.15 Yes Fig.14 A partial enlarged top view showing the structure of part A.

[0035] Fig.16 It means along Fig.15 A cross-sectional view of an example of the structure taken along line AA.

[0036] Fig.17 Yes means Figure 1 A partially enlarged top view of an example of a structure after wafer bonding in the assembly of a semiconductor device.

[0037] Fig.18 It means along Fig.17 A cross-sectional view of an example of the structure taken along line AA.

[0038] Fig.19 Yes means Figure 1 A partially enlarged top view of an example of a structure after wire bonding in the assembly of a semiconductor device.

[0039] Fig. 20 It means along Fig.19 A cross-sectional view of an example of the structure taken along line AA.

[0040] Fig.21 Yes means Figure 1 A partially enlarged top view of an example of a structure after resin molding in the assembly of a semiconductor device.

[0041] Fig. 22 It means along Fig.21 A cross-sectional view of an example of the structure taken along line AA.

[0042] Fig.23 Yes means Figure 1 A cross-sectional view of an example of a structure after the dam is cut during assembly of a semiconductor device.

[0043] Fig.24 Yes means Figure 1 A cross-sectional view of an example of a structure after laser marking in the assembly of a semiconductor device.

[0044] Fig.25 Yes means Figure 1 A cross-sectional view of an example of a structure after exterior plating is formed in the assembly of a semiconductor device.

[0045] Fig.26 Yes means Figure 1 A partially enlarged top view of an example of a structure in which the front end of a pouring gate is cut off during the assembly of a semiconductor device.

[0046] Fig. 27 Yes means Figure 1 A partially enlarged top view of an example of a structure after leads are cut and formed during assembly of a semiconductor device.

[0047] Fig.28 Yes means Figure 1 A top view of an example of a structure after a corner is cut during assembly of a semiconductor device.

[0048] Fig.29 yes Fig.28 A cross-sectional view of the structure.

[0049] Fig.30 yes Fig.28 A three-dimensional diagram of the appearance of the structure.

[0050] Fig.31 It is a schematic diagram showing a mounting structure of a semiconductor device according to a comparative example on a motherboard.

[0051] Description of Reference Numerals

[0052] 1 lead frame, 1a inner lead portion (lead), 1aa upper surface, 1ab lower surface, 1ac wire bonding portion, 1b outer lead portion (lead), 1ba upper surface, 1bb lower surface, 1bc, 1bd bent portion, 1c chip pad (chip mounting portion, tab), 1ca upper surface (chip mounting surface), 1cb lower surface, 1d dam tie bar, 1e cantilever lead, 1f frame portion, 1fa inner frame, 1g hole portion, 1h slotted hole, 1i component area, 2 semiconductor chip , 2a main surface, 2b back surface, 2c bonding pad (bonding electrode, electrode pad), 3 sealing body, 3a upper surface (surface), 3b lower surface (mounting surface), 3c side surface, 4 wire, 5QFP (semiconductor device), 6 die bonding material, 7 plating (metal film, exterior plating), 8 solder, 9 cutting knife, 10 laser, 11 marking, 12 motherboard (wiring substrate, mounting substrate, module substrate), 12a wiring, 12b terminal, 13a, 13b, 13c, 13d QFP (semiconductor device), 14a, 14b SOP (semiconductor device), 15 capacitor (chip type tantalum capacitor), 16 resistor, 17 capacitor (laminated ceramic capacitor), 18 capacitor (electrolytic aluminum capacitor), 19 pin (bolt), 20 module (electronic device), 21a lead. DETAILED DESCRIPTION

[0053] In the following embodiments, unless particularly necessary, the same or similar parts will not be described repeatedly in principle.

[0054] Moreover, in the following embodiments, for the sake of convenience of explanation, the description is divided into multiple sections or implementation methods when necessary, but unless otherwise specified, these sections or implementation methods are not unrelated to each other, and there may be a relationship such as a modification example, detailed description, supplementary description, etc. where one is part or all of the other.

[0055] In addition, in the following embodiments, when referring to the number of elements (including number, value, amount, range, etc.), it is not limited to a specific number, and can be above or below the specific number, except for cases where it is specifically stated and cases where it is clearly limited to a specific number in principle.

[0056] In addition, in the following embodiments, it is needless to say that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or are clearly considered to be essential in principle.

[0057] In addition, in the following embodiments, when referring to constituent elements, etc., as "composed of A", "formed of A", "having A", or "including A", it is needless to say that the inclusion of other elements is not excluded, except for the case where only the element is specifically indicated. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of constituent elements, etc., except for the case where it is specifically indicated or the case where it is clearly considered that it is not the case in principle, shapes substantially similar to or similar to the shape, etc. are included. The same applies to the above-mentioned numerical values ​​and ranges.

[0058] Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. In addition, in all the drawings used to illustrate the embodiments, the same reference numerals are used for components having the same function, and their repeated descriptions are omitted. In addition, in order to facilitate understanding of the drawings, hatching is sometimes also marked even in the top view.

[0059] (Implementation Method)

[0060] Figure 1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment, Figure 2 It means along Figure 1 A cross-sectional view of an example of a structure cut along line AA of Figure 3 Yes means Figure 1 An enlarged cross-sectional view of the detailed structure of the semiconductor device shown, Figure 4 Yes means Figure 1 A top view of an example of a mounting structure for mounting a semiconductor device on a mounting substrate, Figure 5 Yes means Figure 4 A side view of an example of a mounting structure of a semiconductor device (QFP) shown.

[0061] <Electronic Devices>

[0062] Figure 4 The mounting structure shown is a module (electronic device) 20 in which a plurality of semiconductor devices and / or electronic components are mounted on a motherboard 12 as a wiring substrate. In this embodiment, as an example, a vehicle-mounted motherboard (which is a mounting substrate, hereinafter also referred to as an ECU (Electronic Control Unit) board) 12 is selected for description. In addition, in this embodiment, in order to distinguish from electronic components such as capacitors and resistors, electronic components with semiconductor chips mounted therein are referred to as semiconductor devices.

[0063] The engine control ECU board among the vehicle-mounted ECU boards is connected and fixed to the engine room via metal pins (bolts). Therefore, the heat generated in the engine room is transferred to the ECU board via the metal pins.

[0064] Therefore, semiconductor devices and electronic components mounted on engine control ECU boards in particular must be used in extremely harsh environments.

[0065] like Figure 4 As shown, various semiconductor devices such as QFP13a, 13b, 13c, 13d and / or SOP (small outline package) 14a, 14b are mounted on the motherboard 12. Various electronic components such as capacitors (chip tantalum capacitors 15, multilayer ceramic capacitors 17, electrolytic aluminum capacitors 18) and / or resistors (including chip resistors) 16 are also mounted. In addition, these semiconductor devices are electrically connected to each other, a semiconductor device and an electronic component, or electronic components are electrically connected to each other via the wiring 12a of the motherboard 12.

[0066] Furthermore, a plurality of (eg, five) metal pins (bolts) 19 are inserted into the motherboard 12 .

[0067] Here, as described above, since each pin 19 is connected to the engine room, it is easy to transfer the heat of the engine room. For this reason, in the motherboard 12 constituting the module (electronic device) 20, especially in the vicinity of each pin 19, the motherboard 12 is easy to deform (expand, shrink, twist, bend, etc.). In other words, compared with semiconductor devices and / or electronic components not arranged (mounted) near the pins 19, semiconductor devices and / or electronic components arranged (mounted) near the pins 19 are in an environment that is easy to cause poor installation.

[0068] <Semiconductor devices>

[0069] Figure 1 and Figure 2 The semiconductor device of the present embodiment shown is a semiconductor package including a sealing body that seals a semiconductor chip and having a plurality of leads protruding from the sealing body. In the present embodiment, as an example of the semiconductor device, a QFP (Quad Flat Package) 5 is used for description, in which a plurality of external lead portions (external connection terminals) 1b protrude from a sealing body 3 formed of resin, and each of the external lead portions 1b is bent into a gull-wing shape.

[0070] That is, the QFP 5 is a semiconductor device in which a plurality of outer lead portions 1 b serving as external connection terminals protrude from two pairs of sides facing each other in a sealing body 3 having a substantially quadrilateral planar shape.

[0071] The structure of QFP5 is described, which includes: a chip pad (chip mounting portion, tab) 1c, which has an upper surface (chip mounting surface) 1ca and a lower surface 1cb on the opposite side of the upper surface 1ca; a semiconductor chip 2 mounted on the chip pad 1c; a plurality of leads arranged around the chip pad 1c; and a sealing body 3.

[0072] The semiconductor chip 2 has a main surface 2a, a plurality of bonding pads (bonding electrodes) 2c formed on the main surface 2a, and a back surface 2b on the opposite side to the main surface 2a. Figure 2 As shown, the semiconductor chip 2 is mounted on the upper surface 1ca of the die pad 1c with the back surface 2b facing the upper surface 1ca of the die pad 1c via the die bonding material 6. As the die bonding material, a paste-like adhesive such as Ag paste is used, but a film-like adhesive may also be used.

[0073] In addition, the chip pad 1c is provided with a plurality of suspension leads (see the following description). Fig.15 ) 1e supports, and the above-mentioned multiple leads that do not support the chip pad 1c are electrically connected to the multiple bonding electrodes 2c of the semiconductor chip 2 via multiple wires 4.

[0074] Each of the plurality of conductive wires 4 is, for example, a gold wire or a copper wire.

[0075] In addition, the sealing body 3 has an upper surface (surface) 3a located on the main surface 2a side of the semiconductor chip 2, a lower surface (mounting surface) 3b on the opposite side of the upper surface 3a, and a side surface 3c located between the upper surface 3a and the lower surface 3b, and is formed by a sealing resin, etc. Here, the lower surface 3b of the sealing body 3 is a surface located on the lower surface 1cb side of the chip pad 1c.

[0076] The sealing body 3 seals the chip pad 1c, another part (inner lead part) of each of the plurality of leads, the semiconductor chip 2 and the plurality of wires 4 in such a manner that a part (outer lead part) of each of the plurality of leads protrudes from the side.

[0077] That is, the portion of each of the plurality of leads buried inside the sealing body 3 is the inner lead portion 1a, and the portion protruding from the side surface 3c of the sealing body 3 to the outside is the outer lead portion (a portion) 1b. In addition, in each of the plurality of leads, the inner lead portion 1a and the outer lead portion 1b are formed as one piece.

[0078] Furthermore, a part (outer lead portion) of each of the plurality of leads is bent outside the sealing body 3. That is, the outer lead portion 1b of each of the plurality of leads is bent in a gull-wing shape.

[0079] Furthermore, the surface of the outer lead portion 1b of each of the plurality of leads is plated with a film (metal film) 7 (see the following description). Fig.29 , but except for the cut surface).

[0080] In addition, the sealing body 3 is made of, for example, a thermosetting epoxy resin.

[0081] The semiconductor chip 2 is composed of a substrate made of silicon and a multilayer wiring layer formed on a device forming surface of the substrate and having a thickness thinner than that of the substrate.

[0082] In the QFP 5 of this embodiment, a portion of the sealing body 3 is disposed above the main surface 2a of the semiconductor chip 2 and below the lower surface 1cb of the die pad 1c. That is, the die pad 1c is embedded in the sealing body 3, which is a so-called tab-embedded semiconductor device.

[0083] And, if Figure 3 As shown, in QFP 5, thickness T1 of semiconductor chip 2 is larger than thickness T5 from lower surface 1cb of die pad 1c to lower surface 3b of sealing body 3. Here, T1 is, for example, 0.4 mm, and T5 is, for example, 0.39 mm.

[0084] In addition, QFP5 is a semiconductor device in which the occupancy rate of the semiconductor chip 2 in the sealing body 3 is high. Here, the occupancy rate of the semiconductor chip 2 refers to the ratio (dominance) of the thickness of the semiconductor chip 2 to the total thickness of the sealing body 3 in the thickness direction of the sealing body 3. Here, as an example of a comparison object of the chip thickness, the thickness of the sealing body 3 below the chip can be cited. In QFP5, as described above, the thickness T5 of the sealing body 3 on the lower surface 1cb side of the wafer pad 1c is smaller than the thickness T1 of the semiconductor chip 2.

[0085] In addition, in QFP5, the distance D1 between the lower surface 3b of the sealing body 3 and the front end portion (main bonding surface) 1be of the outer lead portion 1b of each of the plurality of leads is greater than the thickness T4 of the sealing body 3 from the main surface 2a of the semiconductor chip 2 to the upper surface 3b of the sealing body 3. Here, T1 is, for example, 0.73 mm, and T4 is, for example, 0.47 mm.

[0086] In addition, the above-mentioned distance D1 is the stand-off height (stand off) of the QFP5 of this embodiment. The stand-off height of the QFP5 is the distance from the lower surface 3b of the sealing body 3 to the lowest point of the front end 1be of the outer lead portion 1b. At this time, regarding the most accurate lowest point, considering the size detection of the scanner, the three sides of the lowest point of the bottom surface 0.1mm inside the front end of the outer lead portion 1b are averaged as a hypothetical layer plane, and the hypothetical layer plane is used as the lowest point. Moreover, at the front end 1be of each outer lead portion 1b, the electrode pad (for example) of the motherboard 12 on which the QFP5 is mounted (solder-bonded) is connected. Fig.31 The surface (lower surface 1bb) opposite to the terminal 12b of the motherboard 12 shown in the figure is used as the main bonding surface. That is, the front end portion 1be of each outer lead portion 1b is the surface wetted by the solder material, so the entire surface (except the cut surface) formed with the above-mentioned plating film 7 becomes the bonding surface, but the surface (lower surface 1bb) opposite to the electrode pad of the mounting substrate becomes the main bonding surface, so this surface is used as the main bonding surface.

[0087] In addition, each of the plurality of inner lead portions 1a of the QFP 5 has a wire bonding portion 1ac, which is bonded to the wire 4 and sealed by the sealing body 3. On the other hand, each of the plurality of outer lead portions 1b has a bent portion 1bc bent in the thickness direction of the sealing body 3 and a bent portion 1bd bent in a direction parallel to the upper surface 3a of the sealing body 3, and is formed into a gull-wing shape by the bent portion 1bc and the bent portion 1bd.

[0088] In addition, the bending portion 1bc and the bending portion 1bd are respectively formed on the outer lead portion 1b, and are therefore exposed from the sealing body 3. The bending portion 1bc is arranged at a position farther away from the semiconductor chip 2 than the wire bonding portion 1ac of the inner lead portion 1a, and the bending portion 1bd is formed at a position farther away from the semiconductor chip 2 than the bending portion 1bc.

[0089] In addition, the distance (interval, D1 (lifting height)) from the lower surface 3b of the sealing body 3 to the bending portion 1bd of each of the multiple outer lead portions 1b is greater than the thickness T8 of each of the multiple inner lead portions 1a from the upper surface 1aa of the wire bonding portion 1ac to the upper surface 3a of the sealing body 3, or greater than the thickness T9 of each of the multiple inner lead portions 1a from the lower surface 1ab of the wire bonding portion 1ac to the lower surface 3b of the sealing body 3.

[0090] That is, in QFP5, D1>T8 or D1>T9. Here, in QFP5, T8 and T9 are both 0.64 mm, for example, but T8 and T9 may be different.

[0091] In QFP5, the distance (interval, D1 (standoff height)) from lower surface 3b of sealing body 3 to tip end 1be of each of outer lead portions 1b is greater than the thickness of semiconductor chip 2. That is, in QFP5, D1>T1.

[0092] Next, the differences between the QFP 5 of the present embodiment and the QFP, LQFP (Low profile Quad Flat Package), and TQFP (Thin Quad Flat Package) based on JEITA (Japan Electronics and Information Technology Industries Association) are described.

[0093] Figure 6 is a cross-sectional view showing the structure of a semiconductor device (QFP) according to an embodiment, Figure 7 is a cross-sectional view showing the structure of a QFP of a comparative example, Figure 8 is a plan view showing an example of the structure of a semiconductor device according to an embodiment, Fig. 9 Yes means Figure 8 A side view of the mounting structure of the semiconductor device shown, Fig.10 is a top view showing the structure of a QFP of a comparative example, Fig.11 Yes means Fig.10 A side view of the mounting configuration of the semiconductor device is shown.

[0094] As described above, the QFP 5 of the present invention is a semiconductor device having a large stand-off height (D1).

[0095] Figure 6 The thickness of the sealing body 3 of the QFP 5 of the present embodiment shown is, for example, as follows: Figure 3 As shown in FIG. 1 , T6 = 1.40 mm. However, the thicknesses of the sealing bodies of the JEITA-compliant QFP, LQFP, and TQFP are 2.00 mm, 1.40 mm, and 1.00 mm, respectively.

[0096] The stand-up height of the QFP5 in this embodiment is, for example, Figure 3 As shown in D1-0.73mm. Based on JEITA's QFP, LQFP, and TQFP, the respective sealing body lifting heights (e.g. Figure 7 The three types of d1) of the QFP21 shown have a minimum height of 0.10 mm and a maximum height of 0.40 mm.

[0097] That is, the QFP5 of this embodiment is based on the JEITA structure, and the thickness of the sealing body 3 is equivalent to the LQFP of JEITA, but the length of each outer lead portion 1b (especially the length in the thickness direction relative to the sealing body 3) is longer, and is greater than the lifting height (especially the height value) of the QFP, LQFP, and TQFP based on JEITA.

[0098] In other words, in the mounting structure on the motherboard (wiring substrate) 12, Figure 8 to Figure 11 As shown, the distance (gap) between the sealing body 3 and the motherboard 12 of the QFP 5 of the present embodiment is large.

[0099] in addition, Figure 7 The QFP21 shown has the same structure as the LQFP based on JEITA, that is, the distance between the lower surface 21aba of the front end 21ac of the outer lead portion 21ab among the multiple leads 21a composed of the inner lead portion 21aa and the outer lead portion 21ab and the lower surface 3b of the sealing body 3, that is, the lifting height d1, is smaller than the thickness of the semiconductor chip 2 and / or the distance between the lower surface 1cb of the chip pad 1c and the lower surface 3b of the sealing body 3.

[0100] That is, compared with the stand-off height D1 of the QFP 5 of the present embodiment, the stand-off height d1 of the QFP 21 is extremely small.

[0101] Here, as a comparison target of the QFP 5 of the present embodiment, an example of the dimensions of each part of the LQFP and the TQFP will be described.

[0102] Regarding the thickness of the semiconductor chip 2: LQFP=0.40mm, TQFP=0.28mm, regarding the thickness of the die-bonding material 6: LQFP and TQFP are both 0.02mm, regarding the thickness of the lead frame (inner lead part, outer lead part, etc.): LQFP=0.125mm or 0.15mm, TQFP=0.15mm.

[0103] In addition, regarding the thickness from the chip surface to the upper surface 3a of the sealing body 3: LQFP = 0.59mm, TQFP = 0.33mm, regarding the thickness from the lower surface 1cb of the chip pad 1c to the lower surface 3b of the sealing body 3: LQFP = 0.38mm, TQFP = 0.23mm (wherein the lowering amount of the chip pad 1c caused by the bending of the cantilever lead 1e is 0.24mm). In addition, the above numerical values ​​are only examples and can be changed in various ways.

[0104] In the QFP5 of the present embodiment, as described above, the thickness of the sealing body 3 is equivalent to the LQFP of JEITA, so it is a semiconductor device that realizes the thinning of the sealing body 3. However, it is difficult to make the semiconductor chip 2 smaller due to its high functionality. Therefore, the QFP5 of the present embodiment is a semiconductor device in which the occupancy rate of the semiconductor chip 2 in the sealing body 3 tends to increase, and the rigidity of the semiconductor device itself is also improved.

[0105] For example, in the QFP 5, the plane size of the sealing body 3 is a square with a side of about 5 to 6 mm, and the plane size of the semiconductor chip 2 is a rectangle or square with a side of about 2 to 2.5 mm.

[0106] When such a QFP5 having a large occupancy rate of the semiconductor chip 2 inside the sealing body 3 is mounted on a wiring substrate such as a motherboard 12, the rigidity of the QFP itself (sealing body 3) is high, so when the substrate bends due to heat, the movement of the QFP5 is difficult to follow the bending of the substrate.

[0107] Therefore, in the QFP 5 of the present embodiment, by increasing the stand-off height of each outer lead portion 1 b , the movement of the main body (sealing body 3 ) can be easily made to follow the deflection of the substrate.

[0108] Here, the main components and linear expansion coefficients of the semiconductor chip 2, the sealing body 3, and the wafer pad 1c (the same applies to each lead) are described. In addition, the thermal expansion coefficient includes a linear expansion coefficient as an expansion coefficient index in a straight line direction and a volume expansion coefficient as an expansion coefficient index in a three-dimensional space. As a cause of stress caused by temperature cycle load, the difference in linear expansion coefficient has a great influence.

[0109] Therefore, in this embodiment, the description will be given focusing mainly on the linear expansion coefficient.

[0110] In QFP5, the main component of semiconductor chip 2 is silicon, whose linear expansion coefficient is 4 to 5 ppm / °C, and the main component of sealing body 3 (resin) is epoxy resin, whose linear expansion coefficient is 8 to 12 ppm / °C. Therefore, the linear expansion coefficient of semiconductor chip 2 is smaller than that of sealing body 3.

[0111] In addition, the lead frame 1 including the chip pad 1c (see the following) Fig.14 ) is mainly composed of copper (Cu) material, and its linear expansion coefficient is 17ppm / ℃.

[0112] The main component of the motherboard 12 on which the QFP 5 is mounted is a resin material, and its linear expansion coefficient is, for example, 15 ppm / °C.

[0113] As described above, the linear expansion coefficient of semiconductor chip 2 is smaller than that of sealing body 3. Therefore, when the occupancy rate of semiconductor chip 2 inside sealing body 3 increases, the linear expansion coefficient of QFP5 itself decreases, and as described above, the rigidity of QFP itself (sealing body 3) increases.

[0114] Here, a description will be given of the problem of poor bonding when a semiconductor device having a high occupancy rate of the semiconductor chip 2 in the sealing body 3 is mounted on a substrate.

[0115] The sealing body 3 of the QFP 5 is made of a thermosetting epoxy resin, whereas the semiconductor chip 2 includes a substrate made of silicon and a multilayer wiring layer (with an insulating layer between each wiring layer) formed on the element forming surface of the substrate and having a thickness thinner than the substrate. Therefore, the linear expansion coefficient of the semiconductor chip 2 (4 to 5 ppm) is lower than the linear expansion coefficient of the sealing body 3 (8 to 12 ppm).

[0116] In addition, in this embodiment, the thickness of the semiconductor chip 2 (LQFP: 0.40 mm, TQFP: 0.28 mm) is greater than, for example, the thickness from the lower surface 1cb of the chip pad 1c to the lower surface 3b of the sealing body 3 (LQFP: 0.38 mm, TQFP: 0.23 mm).

[0117] This is because, in recent years, as semiconductor devices have become smaller (thinner), the overall thickness of the sealing body 3 has also tended to decrease. Therefore, as the overall thickness of the sealing body 3 becomes thinner, the thickness of the sealing body 3 located below the wafer pad 1c becomes thinner than the thickness of the semiconductor chip 2. As a result, the occupancy rate of the semiconductor chip 2 in the sealing body 3 increases, and the linear expansion coefficient of the semiconductor device itself decreases (the rigidity of the semiconductor device itself (sealing body 3) becomes higher).

[0118] Therefore, if Fig.31 As shown in the comparative example, in the structure where QFP21 is mounted on a motherboard 12 serving as a wiring substrate, when the motherboard 12 shrinks in the S direction due to the influence of heat or the like, the rigidity of QFP21 itself (sealing body 3) becomes higher, so that the movement of QFP21 becomes difficult to follow the bending of the motherboard 12.

[0119] That is, at the joint portion between the motherboard 12 and the QFP21 mounted on the motherboard 12 (the joint portion between the outer lead portion 21ab and the terminal (electrode pad) 12b via the solder 8), when the motherboard 12 with the QFP21 mounted thereon is deformed due to heat, the amount of deformation of the motherboard 12 is different from the amount of deformation of the QFP21 which is also deformed due to heat, and thus poor bonding occurs at the above-mentioned joint portion.

[0120] However, in the QFP 5 of the present embodiment, since the stand-off height of each of the plurality of outer lead portions 1 b is large, the movement of the QFP 5 itself (sealing body 3 ) can easily follow the deflection of the motherboard 12 .

[0121] Here, Fig.12 1 is a diagram showing the solder wetting state of the QFP 5 according to the embodiment. Fig.12 As shown in FIG. 1 , in the QFP 5 , the stand-off height of each outer lead portion 1 b is large, and therefore, in each outer lead portion 1 b , the wetting of the solder 8 increases in the height direction of each outer lead portion 1 b .

[0122] As a result, the solder joint strength between each outer lead portion 1b and the joint portion increases. Furthermore, as described above, the movement of the QFP5 itself (sealing body 3) easily follows the bending of the motherboard 12, so that high mounting reliability (mounting strength) can be ensured in the QFP5.

[0123] In other words, even in the QFP 5 whose main body (sealing body 3 ) has a low linear expansion coefficient, its mounting reliability (mounting strength) can be improved, and poor bonding with the mounting substrate (motherboard 12 ) can be reduced.

[0124] Furthermore, by increasing the amount of solder 8 wetted on each outer lead portion 1 b , the electrical characteristics of the QFP 5 can be improved.

[0125] In addition, as in the QFP 5 of the present embodiment, in a semiconductor device of a die pad embedded type in which heat is easily accumulated in the sealing body 3 and thermal stress is easily applied, the mounting reliability (mounting strength) can be improved.

[0126] Next, the semiconductor device Figure 4 The problem of poor bonding of semiconductor devices in the mounting structure (module 20) of the motherboard 12 (such as an in-vehicle ECU board) shown in FIG. 1 will be described.

[0127] The engine control ECU board among the vehicle-mounted ECU boards is connected and fixed to the engine room via metal pins (bolts). Therefore, the heat generated in the engine room is transferred to the ECU board via the metal pins, and thus, semiconductor devices and electronic components mounted on the engine control ECU board are used in a very harsh environment.

[0128] Specifically, a motherboard (for example, ECU board) 12 on which semiconductor devices are mounted is fixed to an engine room by a plurality of pins (bolts) 19. Each pin 19 is made of metal, and therefore the temperature of the pin 19 is likely to rise when the use environment is exposed to high temperatures.

[0129] As a result, the vicinity of each pin 19 on the motherboard 12 is more likely to bend (deform) than other regions (regions far from the pins 19). Furthermore, semiconductor devices arranged (mounted) near the pins 19 are more likely to have bonding defects than semiconductor devices arranged in other regions.

[0130] For example, Figure 4 In the module 20 shown, two pins 19 are respectively arranged near the QFP 13b and 13c, so by adopting the structure of the present embodiment with a large stand-off height for these QFP 13b and 13c, the mounting reliability (mounting strength) can be improved even in the QFP 13b and 13c that are easily affected by heat. As a result, it is possible to reduce the poor bonding with the motherboard 12 (ECU board).

[0131] However, it goes without saying that the structure with a large stand-off height of the present embodiment can also be employed for a semiconductor device disposed in a region away from the pins 19 .

[0132] For example, in the module 20, the structure with a large standoff height of the present embodiment can also be adopted for the QFP 13a, 13d or the SOP 14a, SOP 14b, so that the mounting reliability (mounting strength) of these semiconductor devices can be further improved.

[0133] In addition, in the semiconductor device, it is considered to adopt a method of replacing the raised height of each outer lead portion 1b with a higher Fig.13 The structure of QFP21 is shown. Fig.13 It is a schematic diagram showing the solder wetting state of a semiconductor device of a comparative example.

[0134] Fig.13 The QFP 21 shown is a structure in which each outer lead portion 21ab is extended long along the mounting surface direction of the substrate. Fig.13 In the case of the QFP 21 of the present embodiment, the wetting amount of the solder 8 is inferior to that of the QFP 5 of the present embodiment, and therefore the mounting reliability (mounting strength) cannot be sufficiently improved.

[0135] That is, since the wetting of the solder 8 is directional, Fig.13 In the case of the QFP21 of the embodiment, the solder 8 is wetted and retained at the bent portion of the outer lead portion 12ab. Therefore, it is not possible to ensure sufficient mounting reliability (mounting strength) as in the QFP5 of the present embodiment, and it is not possible to achieve the same Figure 4 The motherboard 12 (ECU board) of the module 20 shown is designed to withstand use in a very harsh environment.

[0136] <Method for manufacturing semiconductor device>

[0137] Fig.14 It means in Figure 1A top view of the structure of a lead frame used in the assembly of a semiconductor device, Fig.15 Yes Fig.14 A partial enlarged top view showing the structure of part A. Fig.16 It means along Fig.15 The cross-sectional view of the structure cut along the AA line. Fig.17 Yes means Figure 1 A partially enlarged top view of the structure after wafer bonding in the assembly of a semiconductor device. Fig.18 It means along Fig.17 A cross-sectional view of the structure taken along line AA.

[0138] also, Fig.19 Yes means Figure 1 A partially enlarged top view of the structure after wire bonding in the assembly of a semiconductor device, Fig. 20 It means along Fig.19 The cross-sectional view of the structure cut along the AA line. Fig.21 Yes means Figure 1 A partially enlarged top view of the structure of the semiconductor device after resin molding in the assembly, Fig. 22 It means along Fig.21 A cross-sectional view of the structure taken along line AA.

[0139] also, Fig.23 Yes means Figure 1 A cross-sectional view of the structure after the dam is cut during the assembly of the semiconductor device. Fig.24 Yes means Figure 1 A cross-sectional view of an example of a structure after laser marking in the assembly of a semiconductor device. Fig.25 Yes means Figure 1 A cross-sectional view of an example of a structure after the exterior plating is formed in the assembly of a semiconductor device. Fig.26 Yes means Figure 1 A partially enlarged top view of an example of a structure in which the front end of a pouring gate is cut off during the assembly of a semiconductor device.

[0140] also, Fig. 27 Yes means Figure 1 A partially enlarged top view of an example of a structure after the lead is cut and formed in the assembly of a semiconductor device, Fig.28 Yes means Figure 1 A top view of an example of a structure after a corner portion is cut off during assembly of a semiconductor device. Fig.29 yes Fig.28 A cross-sectional view of the structure, Fig.30 yes Fig.28 A three-dimensional diagram of the appearance of the structure.

[0141] 1. Prepare the lead frame

[0142] like Fig.14As shown, in the assembly of the semiconductor device of the present embodiment, a sheet-like lead frame 1 is prepared in which a plurality of component areas (component forming parts) 1i are formed on the inner side of the frame portion 1f. In addition, the component area 1i refers to an area in which one QFP5 is formed. In addition, in the present embodiment, the plurality of component areas 1i are arranged in a matrix shape when viewed from above, but can also be arranged in a row (single row), and the number of component areas 1i formed on one lead frame 1 is not particularly limited. In addition, in the present embodiment, the planar shape of the lead frame is composed of a rectangle. And, along a pair of sides (long sides) facing each other in the frame portion 1f of the lead frame 1, a plurality of hole portions 1g for positioning or guiding are respectively formed. Moreover, between the mutually adjacent component areas in the plurality of component areas 1i, a plurality of long holes 1h are formed along a pair of sides (short sides) facing each other.

[0143] Next, the component area 1i will be described in detail.

[0144] like Fig.15 As shown, a chip pad 1c is provided in a component area 1i. Here, the plane shape of the chip pad in this embodiment is composed of a roughly quadrilateral. In addition, each corner of the fine pad 1c is supported by a cantilever lead 1e. Furthermore, a plurality of leads are formed around the chip pad 1c. Each lead includes an inner lead portion 1a and an outer lead portion 1b connected thereto. In addition, the end of each outer lead portion 1b is connected to an inner frame 1fa provided on the inner side of the frame portion 1f (chip pad side).

[0145] Furthermore, in the plurality of outer lead portions 1b, adjacent outer lead portions are connected to each other by dam bars 1d at positions slightly outside the boundary between the inner lead portion 1a and the outer lead portion 1b.

[0146] Furthermore, each of the plurality of outer lead portions 1b is formed to be long so that the stand-off height of the lead formed in the subsequent lead forming step becomes large.

[0147] In addition, the chip pad 1c supported by the cantilever lead 1e, such as Fig.16 That is, each cantilever lead 1e is bent in the middle, whereby the wafer lead 1c is located at a position lower than each inner lead 1a.

[0148] In addition, the lead frame 1 is made of a metal material mainly composed of copper, for example.

[0149] In this embodiment, for convenience of explanation, one component region 1i is used as a representative to explain the subsequent mounting of the QFP 5.

[0150] 2. Wafer bonding

[0151] After the lead frame is prepared, wafer bonding is performed.

[0152] In the wafer bonding process, such as Fig.17 and Fig.18 As shown, the semiconductor chip 2 is mounted on the upper surface 1ca of the die pad 1c via the die bonding material 6. That is, the semiconductor chip 2 having a plurality of bonding pads 2c formed on the main surface 2a is mounted on the die pad 1c via the die bonding material 6.

[0153] 3. Wire bonding

[0154] After the wafer bonding is completed, wire bonding is performed.

[0155] In the wire bonding process, Fig.19 and Fig. 20 As shown, the plurality of bonding pads 2c of the semiconductor chip 2 and the plurality of inner leads 1a are electrically connected via the plurality of wires 4. At this time, one end of each of the plurality of wires 4 is bonded to the wire bonding portion 1ac of each of the plurality of inner leads 1a.

[0156] 4. Molding

[0157] After wire bonding is completed, molding is performed.

[0158] In the molding process, such as Fig.21 and Fig. 22 As shown, a sealing resin is used to seal the semiconductor chip 2, the die pad 1c, the plurality of inner lead portions 1a and the plurality of wires 4. First, the lead frame 1 to which the wires are bonded is arranged in the cavity of a resin molding mold (not shown), and after the lead frame 1 is clamped by the mold, the sealing resin is filled into the cavity to form a sealing body 3. The sealing resin is, for example, a thermosetting epoxy resin, and the sealing body 3 is formed by thermal curing after filling.

[0159] In addition, the sealing resin is injected from one of the four corners of the sealing body 3 to be formed, so that a sealing resin is formed at one corner of the sealing body 3 when viewed from above. Fig.21 The pouring port resin 22 is shown. After the sealing body 3 is formed, Fig. 22 As shown in FIG. 1 , a plurality of outer lead portions 1 b are protruded from respective side surfaces 3 c of the sealing body 3 .

[0160] 5. Lead wire cutting (dam connecting rod cutting)

[0161] After molding is completed, lead cutting (dam bar cutting) is performed.

[0162] In the dam connecting rod cutting process, Fig.23As shown, the dam bar 1d disposed between the adjacent outer lead portions is cut by the cutting blade 9. In the dam bar cutting step, only the dam bar 1d is cut.

[0163] 6. Marking

[0164] After the dam connecting rod is cut off, marking is carried out.

[0165] In the marking process, Fig.24 As shown, the upper surface 3a of the sealing body 3 is irradiated with laser light 10, as described later. Fig.26 As shown in FIG. 1 , a mark 11 such as a predetermined manufacturing number or management number is marked on the upper surface 3 a of the sealing body 3 .

[0166] 7. Plating

[0167] After the marking process is completed, the plating film is formed.

[0168] In the plating process, Fig.25 As shown, a plating film (external plating) such as solder plating is formed on the surface of each of the plurality of outer lead portions 1b (including the surfaces of the upper surface 1ba and the lower surface 1bb).

[0169] When solder plating is used as the plating film 7, lead-free solder is preferably used. By using lead-free solder, the environmental burden can be reduced. Here, lead-free solder refers to solder with a lead (Pb) content of 0.1 wt% or less, which is based on the RoHS (Restriction of Hazardous Substances) directive.

[0170] 8. Lead cutting (gating gate cutting)

[0171] After the plating step is completed, the lead cutting (gate cutting) is performed.

[0172] In the pouring gate cutting process, a Fig.21 The frame at the corner of the gate resin 22 is cut off. Thus, the sealing body 3 is supported by the lead frame 1 at the remaining three corners.

[0173] 9. Lead forming

[0174] After the gate is cut, the lead is formed.

[0175] In the lead forming step, first, the inner frame 1fa connecting the front ends of the outer lead portions 1b to each other is separated from the frame portion 1f (see Fig.26 Then, while keeping the front ends of the outer lead portions 1b connected, the outer lead portions 1b are formed (bent) into a shape such as Fig.29Thereafter, the inner frame 1fa connecting the front ends of the outer lead portions 1b is cut off to separate the outer lead portions 1b from each other (see Fig. 27 ).

[0176] The step of forming the outer lead portion 1b is performed in a state where the plurality of cantilever leads 1e are connected to the frame portion 1f.

[0177] 10. Lead cutting (corner cutting)

[0178] After the lead forming step is completed, lead cutting (corner cutting) is performed.

[0179] In the corner cutting process, Fig. 27 The remaining three corners of the support sealing body 3 are cut into individual pieces by cutting the lead frame. Figure 28 to Figure 30 As shown, the assembly of the QFP 5 in which the stand-off height of each outer lead portion 1b is large is completed.

[0180] <Method of Mounting Semiconductor Device>

[0181] In the installation of the QFP5 of this embodiment, as Fig.12 As shown in FIG. 1 , the QFP 5 is mounted on a motherboard 12 as a mounting substrate by means of solder 8. At this time, the lifting height of each outer lead 1b in the QFP 5 is large, so the amount of solder 8 wetted on each outer lead 1b increases, and the solder 8 wets to a higher position in the height direction of each outer lead 1b ( Figure 3 The bent portion 1bc shown).

[0182] Therefore, the bonding strength of each outer lead portion 1b of the QFP 5 during solder bonding is improved. As a result, high mounting reliability (mounting strength) can be ensured in the QFP 5.

[0183] Furthermore, since the QFP 5 is a semiconductor device in which the semiconductor chip 2 occupies a large proportion of the sealing body 3, even the QFP 5 in which the semiconductor chip 2 occupies a large proportion can improve its mounting reliability and reduce bonding defects with the motherboard 12.

[0184] Furthermore, even in Figure 4 QFP13b, 13c, etc. installed on an ECU board (motherboard 12) that is highly affected by heat and is in a very harsh environment as shown can also improve its installation reliability and reduce poor bonding with the ECU board (wherein, a structure with a large support height can also be used for other semiconductor devices on the motherboard 12).

[0185] <Modification>

[0186] As mentioned above, the invention completed by the present inventors has been specifically described based on the embodiments, but the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention.

[0187] (Variant 1)

[0188] In the above embodiment, the case where the QFP has a die pad embedded structure is described as an example, but the above QFP may have a so-called tab exposed structure in which a portion of the die pad 1c (eg, the lower surface 1cb) is exposed from the sealing body 3.

[0189] (Variant 2)

[0190] In the above embodiment, the case where the semiconductor device is a QFP is described, but the above semiconductor device may also be a so-called SOP (Small Outline Package) type semiconductor device, that is, a plurality of leads serving as external connection terminals protrude from two opposite sides of a sealing body 3 having a roughly rectangular planar shape.

[0191] (Variant 3)

[0192] In the QFP5 of the above-mentioned embodiment, it is explained that when the occupancy rate of the semiconductor chip 2 in the sealing body in the thickness direction of the sealing body 3 increases, the linear expansion coefficient of the sealing body 3 decreases, but as a comparison object of the thickness of the semiconductor chip 2, the thickness of the sealing body above the chip can be used. That is, the occupancy rate of the semiconductor chip 2 refers to the ratio (dominant amount) of the thickness of the semiconductor chip 2 in the thickness direction of the sealing body 3 to the total thickness of the sealing body 3. Therefore, even if the thickness of the sealing body 3 below the chip pad is larger than the thickness of the semiconductor chip 2, when the thickness of the sealing body 3 above the chip is smaller than the thickness of the semiconductor chip 2, there may be a risk of a decrease in the linear expansion coefficient of the sealing body 3 and a poor installation of the semiconductor device caused by the deformation (expansion, contraction) of the sealing body 3. Therefore, as a comparison object of the chip thickness, it is not limited to the thickness of the sealing body 3 below the chip pad, and the thickness of the sealing body 3 above the chip can also be used. However, as in the QFP5 of the above-mentioned embodiment, when the semiconductor chip 2 and the lead are electrically connected via the wire 4, in order to prevent the wire 4 from being exposed on the surface of the sealing body 3, the thickness of the sealing body 3 formed above the semiconductor chip 2 (main surface side) is often made greater than the thickness of the semiconductor chip 2. Therefore, when judging the occupancy rate (dominance) of the semiconductor chip 2 in the sealing body 3, it is preferred to use the thickness of the sealing body 3 below the die pad as a comparison object.

[0193] (Variant 4)

[0194] In the above embodiment, the case where the plurality of outer lead portions 1b of the semiconductor device (QFP5) are formed in a gull-wing shape is described, but the plurality of outer lead portions 1b may be formed in, for example, a J-shaped lead shape. That is, the semiconductor device may also be a QFJ (Quad Flat J-leaded Package) or SOJ (Small Outline J-leaded Package).

[0195] (Variant 5)

[0196] In the assembly of the semiconductor device in the above-mentioned embodiment, a case is described in which a sealing body 3 is formed in a molding process, and a plating film (external plating) 7 is formed on the surface of each outer lead portion 1b after the sealing body is formed. However, it is also possible to prepare a lead frame 1 in which a plating film having palladium (Pd) as a main component is formed on the entire surface of the lead frame 1 in advance, and use the lead frame 1 to assemble the semiconductor device.

[0197] According to such assembly, the exterior plating coating step after the molding step can be omitted.

[0198] (Variant 6)

[0199] In the above embodiment, the plating film 7 formed on each outer lead portion 1b in the exterior plating process is a plating film composed of a solder material, and the above solder material is a lead-free solder substantially free of lead (Pb), but the above solder material may be a solder material containing lead. However, considering the problem of environmental pollution, it is preferable to use a solder material composed of the above lead-free solder.

[0200] (Variant 7)

[0201] Furthermore, modifications may be applied in combination without departing from the gist of the technical concept described in the above-mentioned embodiments.

Claims

1. An electronic device, characterized in that: include: motherboard; a plurality of metal pins inserted into the motherboard; a first semiconductor device mounted on the motherboard; as well as a second semiconductor device mounted on the motherboard, The plurality of metal pins have: a first metal pin located closest to the first semiconductor device, and a second metal pin, located closest to the second semiconductor device, A first distance between the first metal pin and the first semiconductor device is smaller than a second distance between the second metal pin and the second semiconductor device, The first semiconductor device comprises: A chip pad, comprising a first surface and a second surface opposite to the first surface; a semiconductor chip having a main surface, a plurality of bonding electrodes formed on the main surface, and a back surface opposite to the main surface, wherein the semiconductor chip is mounted on the first surface of the chip pad via a die bonding material in a manner that the back surface faces the first surface of the chip pad, and the semiconductor chip is mainly composed of a first material having a first linear expansion coefficient; a plurality of leads electrically connected to the plurality of bonding electrodes respectively via a plurality of wires; a sealing body having an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface on the opposite side to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and on the opposite side to the first side surface, wherein the sealing body seals the semiconductor chip and the plurality of wires, and the sealing body is mainly composed of a second material having a second linear expansion coefficient higher than the first linear expansion coefficient, Each of the plurality of leads has an inner lead portion sealed by the sealing body and an outer lead portion exposed from the sealing body. The outer lead portion comprises: a first portion connected to the inner lead portion and extending in a horizontal direction along the upper surface of the sealing body; a second portion connected to the first portion via a first bending portion, the first bending portion being formed by bending the outer lead portion in a thickness direction of the sealing body from the upper surface toward the lower surface; and a third portion connected to the second portion via a second bending portion, the second bending portion being formed by bending the outer lead portion in a horizontal direction. wherein the plurality of leads include: a first lead, which is electrically connected to a first bonding electrode among the plurality of bonding electrodes via a first wire among the plurality of wires, and the first lead protrudes from the first side surface of the sealing body; a second lead, which is electrically connected to a second bonding electrode among the plurality of bonding electrodes via a second wire among the plurality of wires, and the second lead protrudes from the second side surface of the sealing body, wherein in cross-section, the semiconductor chip is located between the inner lead portion of the first lead and the inner lead portion of the second lead, wherein in cross-section, the first thickness of the semiconductor chip is greater than the second thickness of the sealing body from the second surface of the chip pad to the lower surface of the sealing body, and the second thickness is greater than the third thickness of the chip pad and the die bonding material, respectively; wherein in cross-section, the lifting height of each of the plurality of leads is greater than 0.40 mm and less than a fourth thickness from the upper surface of the sealing body to the lower surface of the sealing body, the lifting height being the distance from the lower surface of the sealing body to the third portion of the outer lead portion in the thickness direction of the sealing body, In which, in the cross-sectional view, the lifting height of each of the multiple leads is greater than the fifth thickness of each of the multiple leads from the upper surface of the inner lead portion located on the same side as the main surface of the semiconductor chip to the upper surface of the sealing body, or greater than the sixth thickness of each of the multiple leads from the lower surface of the inner lead portion located on the same side as the second surface of the chip pad to the lower surface of the sealing body.

2. The electronic device according to claim 1, wherein: The first material is silicon, and the second material is epoxy resin.

3. The electronic device according to claim 1, wherein: In a cross-sectional view, the thickness of the semiconductor chip is greater than the thickness from the main surface of the semiconductor chip to the upper surface of the sealing body.

4. The electronic device according to claim 1, wherein: The thickness of the sealing body is 1.40 mm or 1.00 mm.

5. The electronic device as claimed in claim 4, characterized in that: The stand-off height of each of the plurality of leads is 0.73 mm.

6. The electronic device as claimed in claim 4, characterized in that: The thickness of each of the plurality of leads is 0.125 mm or 0.15 mm.

7. The electronic device according to claim 6, wherein: The semiconductor device is a QFP (Quad Flat Package).

8. The electronic device as claimed in claim 7, characterized in that: The second semiconductor device is a QFP (quad flat package), The second semiconductor device comprises: Wafer pad; Semiconductor chips; a plurality of leads; and Sealed solid, The thickness of each of the plurality of leads of the second semiconductor device is 0.125 mm or 0.15 mm. In the cross-sectional view, the lifting height of each of the multiple leads of the second semiconductor device is greater than 0 mm and less than or equal to 0.40 mm, and the lifting height is in the thickness direction of the sealing body of the second semiconductor device, from the lower surface of the sealing body of the second semiconductor device to the top of the outer lead portion of each of the multiple leads of the second semiconductor device.

9. The electronic device as claimed in claim 8, characterized in that: The plurality of leads of the second semiconductor device each have a stand-off height of 0.10 mm or 0.40 mm.

10. The electronic device according to claim 9, wherein: The motherboard is an ECU (Electronic Control Unit) board, and the ECU board is fixed to the engine room by the plurality of metal pins.

11. An electronic device, characterized in that: include: motherboard; a plurality of metal pins inserted into the motherboard; a first semiconductor device mounted on the motherboard; as well as a second semiconductor device mounted on the motherboard, The plurality of metal pins have: a first metal pin located closest to the first semiconductor device, and a second metal pin, located closest to the second semiconductor device, wherein a first distance between the first metal pin and the first semiconductor device is smaller than a second distance between the second metal pin and the second semiconductor device, The first semiconductor device comprises: A chip pad, comprising a first surface and a second surface opposite to the first surface; a semiconductor chip having a main surface, a plurality of bonding electrodes formed on the main surface, and a back surface opposite to the main surface, wherein the semiconductor chip is mounted on the first surface of the chip pad via a die bonding material in a manner that the back surface faces the first surface of the chip pad, and the semiconductor chip is mainly composed of a first material having a first linear expansion coefficient; a plurality of leads electrically connected to the plurality of bonding electrodes respectively via a plurality of wires; a sealing body having an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface on the opposite side to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and on the opposite side to the first side surface, wherein the sealing body seals the semiconductor chip and the plurality of wires, and the sealing body is mainly composed of a second material having a second linear expansion coefficient higher than the first linear expansion coefficient, Each of the plurality of leads has an inner lead portion sealed by the sealing body and an outer lead portion exposed from the sealing body, The outer lead portion comprises: a first portion connected to the inner lead portion and extending in a horizontal direction along the upper surface of the sealing body; a second portion connected to the first portion via a first bending portion, the first bending portion being formed by bending the outer lead portion in a thickness direction of the sealing body from the upper surface toward the lower surface; and a third portion connected to the second portion via a second bending portion, the second bending portion being formed by bending the outer lead portion in a horizontal direction. wherein the plurality of leads include: a first lead, which is electrically connected to a first bonding electrode among the plurality of bonding electrodes via a first wire among the plurality of wires, and the first lead protrudes from the first side surface of the sealing body; a second lead, which is electrically connected to a second bonding electrode among the plurality of bonding electrodes via a second wire among the plurality of wires, and the second lead protrudes from the second side surface of the sealing body, wherein in cross-section, the semiconductor chip is located between the inner lead portion of the first lead and the inner lead portion of the second lead, wherein in cross-section, the first thickness of the semiconductor chip is greater than the second thickness of the sealing body from the second surface of the chip pad to the lower surface of the sealing body, and the second thickness is greater than the third thickness of the chip pad and the die bonding material, respectively; Wherein, in the cross-sectional view, each of the plurality of leads has a lift height greater than a lift height when mounted on a QFP (quad flat package) based on JEITA (Japan Electronics and Information Technology Industries Association), and less than a fourth thickness from the upper surface of the sealing body to the lower surface of the sealing body, wherein the lift height is a distance from the lower surface of the sealing body to the third portion of the outer lead portion in the thickness direction of the sealing body, In which, in the cross-sectional view, the lifting height of each of the multiple leads is greater than the fifth thickness of each of the multiple leads from the upper surface of the inner lead portion located on the same side as the main surface of the semiconductor chip to the upper surface of the sealing body, or greater than the sixth thickness of each of the multiple leads from the lower surface of the inner lead portion located on the same side as the second surface of the chip pad to the lower surface of the sealing body.

12. The electronic device according to claim 11, wherein: The first material is silicon, and the second material is epoxy resin.

13. The electronic device according to claim 11, wherein: In a cross-sectional view, the thickness of the semiconductor chip is greater than the thickness from the main surface of the semiconductor chip to the upper surface of the sealing body.

14. The electronic device according to claim 11, wherein: The thickness of the sealing body is 1.40 mm or 1.00 mm.

15. The electronic device according to claim 14, wherein: The stand-off height of each of the plurality of leads is 0.73 mm.

16. The electronic device as claimed in claim 14, characterized in that: The thickness of each of the plurality of leads is 0.125 mm or 0.15 mm.

17. The electronic device according to claim 16, wherein: The semiconductor device is a QFP (Quad Flat Package).

18. The electronic device as claimed in claim 17, wherein: The second semiconductor device is a QFP (quad flat package), The second semiconductor device comprises: Wafer pad; Semiconductor chips; a plurality of leads; and Sealed solid, The thickness of each of the plurality of leads of the second semiconductor device is 0.125 mm or 0.15 mm. In the cross-sectional view, the respective lifting heights of the multiple leads of the second semiconductor device are one of a low value of the lifting height when installed on a QFP (quad flat package) based on JEITA (Japan Electronics and Information Technology Industries Association) and a high value of the lifting height based on JEITA, and the lifting height is in the thickness direction of the sealing body of the second semiconductor device, from the lower surface of the sealing body of the second semiconductor device to the top of the outer lead portion of each of the multiple leads of the second semiconductor device.

19. The electronic device as claimed in claim 18, characterized in that: The plurality of leads of the second semiconductor device each have a stand-off height of 0.10 mm or 0.40 mm.

20. The electronic device as claimed in claim 19, wherein: The motherboard is an ECU (Electronic Control Unit) board, and the ECU board is fixed to the engine room by the plurality of metal pins.

21. A semiconductor device, characterized in that: include: A chip pad, comprising a first surface and a second surface opposite to the first surface; a semiconductor chip having a main surface, a plurality of bonding electrodes formed on the main surface, and a back surface opposite to the main surface, wherein the semiconductor chip is mounted on the first surface of the chip pad via a die bonding material in a manner that the back surface faces the first surface of the chip pad, and the semiconductor chip is mainly composed of a first material having a first linear expansion coefficient; a plurality of leads electrically connected to the plurality of bonding electrodes respectively via a plurality of wires; a sealing body having an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface on the opposite side to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and on the opposite side to the first side surface, wherein the sealing body seals the semiconductor chip and the plurality of wires, and the sealing body is mainly composed of a second material having a second linear expansion coefficient higher than the first linear expansion coefficient, Each of the plurality of leads has an inner lead portion sealed by the sealing body and an outer lead portion exposed from the sealing body. The outer lead portion comprises: a first portion connected to the inner lead portion and extending in a horizontal direction along the upper surface of the sealing body; a second portion connected to the first portion via a first bending portion, the first bending portion being formed by bending the outer lead portion in a thickness direction of the sealing body from the upper surface toward the lower surface; and a third portion connected to the second portion via a second bending portion, the second bending portion being formed by bending the outer lead portion in a horizontal direction. wherein the plurality of leads include: a first lead electrically connected to a first bonding electrode among the plurality of bonding electrodes via a first wire among the plurality of wires, and the first lead protrudes from the first side surface of the sealing body; a second lead electrically connected to a second bonding electrode among the plurality of bonding electrodes via a second wire among the plurality of wires, and the second lead protruding from the second side surface of the sealing body, wherein in cross-section, the semiconductor chip is located between the inner lead portion of the first lead and the inner lead portion of the second lead, wherein in cross-section, the thickness of the semiconductor chip is greater than the thickness of the sealing body from the second surface of the chip pad to the lower surface of the sealing body, and the thickness is greater than the thickness of the chip pad and the die bonding material, respectively; Wherein, in the cross-sectional view, the respective lifting heights of the plurality of leads are greater than the height value of the lifting height when mounted on a QFP (quad flat package) based on JEITA (Japan Electronics and Information Technology Industries Association), and are less than the thickness from the upper surface of the sealing body to the lower surface of the sealing body, and the lifting height is the distance from the lower surface of the sealing body to the third portion of the outer lead portion in the thickness direction of the sealing body, In which, in the cross-sectional view, the lifting height of each of the multiple leads is greater than the thickness of each of the multiple leads from the upper surface of the inner lead portion located on the same side as the main surface of the semiconductor chip to the upper surface of the sealing body, or greater than the thickness of each of the multiple leads from the lower surface of the inner lead portion located on the same side as the second surface of the chip pad to the lower surface of the sealing body.

22. The semiconductor device according to claim 21, wherein The first material is silicon, and the second material is epoxy resin.

23. The semiconductor device according to claim 21, wherein The thickness of the sealing body is 1.40 mm or 1.00 mm.

24. The semiconductor device according to claim 23, characterized in that The stand-off height of each of the plurality of leads is 0.73 mm.

25. The semiconductor device according to claim 23, wherein The thickness of each of the plurality of leads is 0.125 mm or 0.15 mm.

26. The semiconductor device according to claim 25, characterized in that The plurality of leads are arranged around the semiconductor chip.

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